LDMOS device and manufacturing method thereof

Abstract

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof. The LDMOS device comprises a semiconductor substrate; the body region and the drift region are formed in the semiconductor substrate, the source region is located in the body region, and the drain region is located in the drift region; the at least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the parts, higher than the surface of the semiconductor substrate, of the at least two shallow trench isolation structures; and the gate structure comprises a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, and the gate structure transversely extends to the drift region from the body region and at least partially covers the shallow trench isolation structure. The LDMOS structure has a relatively high breakdown voltage.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to an LDMOS device and a manufacturing method thereof. Background Art

[0002] The laterally diffused metal oxide semiconductor (LDMOS) adopts a double-diffusion technology, and boron and phosphorus are diffused successively in the same window twice. The channel length can be accurately determined by the difference in the lateral junction depth of the two impurity diffusions. LDMOS devices are mainly used in power integrated circuits and have the advantages of high breakdown voltage, fast switching speed, and compatibility with the process of complementary metal oxide semiconductor (CMOS) devices.

[0003] For LDMOS devices, the on-resistance (Rdson) and the breakdown voltage (BVdss) are two of the most important parameters. The smaller the on-resistance, the stronger the driving ability of the LDMOS device; the larger the breakdown voltage, the higher the reliability of the LDMOS device. Therefore, it is generally desired that the LDMOS has a smaller on-resistance and a larger breakdown voltage. Forming a shallow trench isolation (STI) structure in the drift region of the LDMOS device can optimize the electric field distribution in the drift region, reduce the electric field spikes, and avoid local breakdown caused by the electric field concentration in the drift region. However, the junction between the gate dielectric layer and the top of the sidewall of the STI is still prone to premature breakdown, resulting in a reduction in the breakdown voltage of the LDMOS device. Summary of the Invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description section. The Summary of the Invention section of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides an LDMOS device on the one hand, and the LDMOS device includes:

[0006] A semiconductor substrate;

[0007] A body region, a drift region formed in the semiconductor substrate, a source region located in the body region, and a drain region located in the drift region;

[0008] At least two shallow trench isolation structures are formed in the drift region, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the portions of the at least two shallow trench isolation structures that are higher than the surface of the semiconductor substrate; and,

[0009] A gate structure, the gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, the gate structure extends laterally from the body region to the drift region and at least partially covers the shallow trench isolation structure.

[0010] In one embodiment, the gate structure at least partially covers the dielectric layer.

[0011] In one embodiment, the shape of the gate structure is stepped, and the top of the gate structure located above the shallow trench isolation structure is higher than the top of the gate structure located above the body region and the drift region.

[0012] In one embodiment, the at least two shallow trench isolation structures have rounded top corners, and / or the shallow trench isolation structure has rounded bottom corners.

[0013] Another aspect of the embodiments of the present invention provides a method for manufacturing an LDMOS device, the method includes:

[0014] Providing a semiconductor substrate;

[0015] Forming a drift region in the semiconductor substrate;

[0016] Forming at least two shallow trenches in the drift region;

[0017] Filling the at least two shallow trenches with an isolation material to form at least two shallow trench isolation structures, the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate;

[0018] Forming a dielectric layer between the portions of the at least two shallow trench isolation structures that are higher than the surface of the semiconductor substrate, and forming a gate dielectric layer on the semiconductor substrate and the shallow trench isolation structures;

[0019] Forming a gate electrode layer on the gate dielectric layer;

[0020] Patterning the gate electrode layer and the gate dielectric layer to form a gate structure, the gate structure extends laterally from the body region to the drift region and at least partially covers the shallow trench isolation structure.

[0021] In one embodiment, the forming at least two shallow trenches in the drift region includes:

[0022] A hard mask layer and a photoresist layer are sequentially formed on the semiconductor substrate;

[0023] Based on the photoresist layer, the hard mask layer and the semiconductor substrate are sequentially etched to form openings corresponding to the at least two shallow trenches in the hard mask layer, and the at least two shallow trenches are formed in the semiconductor substrate;

[0024] Filling the at least two shallow trenches with an isolation material to form at least two shallow trench isolation structures, the tops of the at least two shallow trench isolation structures being higher than the surface of the semiconductor substrate, including:

[0025] Forming an isolation material to fill the shallow trenches and the openings;

[0026] Removing the hard mask layer to obtain the at least two shallow trench isolation structures with tops higher than the surface of the semiconductor substrate.

[0027] In one embodiment, after forming the at least two shallow trenches and before filling the at least two shallow trenches with an isolation material, the method further includes:

[0028] Rounding the top corners and / or bottom corners of the at least two shallow trenches.

[0029] In one embodiment, the rounding of the top corners and / or bottom corners of the at least two shallow trenches includes:

[0030] Laterally etching the hard mask layer to expand the openings and expose the top corners of the shallow trenches;

[0031] Performing an isotropic dry etching process to round the top corners and the bottom corners.

[0032] In one embodiment, forming a dielectric layer between portions of the at least two shallow trench isolation structures that are higher than the surface of the semiconductor substrate, and forming a gate dielectric layer on the semiconductor substrate and the shallow trench isolation structures, includes:

[0033] Performing a thermal oxidation process on the surface of the semiconductor substrate to obtain the dielectric layer and the gate dielectric layer.

[0034] Another aspect of an embodiment of the present invention provides a semiconductor device, the semiconductor device including a CMOS device and the LDMOS device as described above, the CMOS device including a shallow trench isolation structure, and the shallow trench isolation structure of the CMOS device having rounded top corners and / or rounded bottom corners.

[0035] An embodiment of the present invention further provides an electronic device, the electronic device including the semiconductor device as described above.

[0036] According to the LDMOS device provided by the present invention, at least two shallow trench isolation structures are arranged in the drift region, which can improve the breakdown voltage without increasing the on-resistance; the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, increasing the thickness of the insulating material under the gate structure, reducing the electric field strength at the junction of the gate structure and the shallow trench isolation structure, avoiding breakdown at the junction, and further improving the breakdown voltage of the LDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The following drawings of the present invention are hereby incorporated as part of the present invention for understanding the present invention. The embodiments of the present invention and their descriptions are shown in the drawings to explain the principles of the present invention.

[0038] In the drawings:

[0039] Figure 1 shows a cross-sectional schematic diagram of an LDMOS device according to the related art;

[0040] Figure 2 shows a schematic flow chart of a manufacturing method of an LDMOS device according to a specific embodiment of the present invention;

[0041] Figures 3A - 3G shows a cross-sectional schematic diagram of an LDMOS device obtained by successively implementing each step of the manufacturing method of an LDMOS device according to a specific embodiment of the present invention;

[0042] Figure 4 shows a cross-sectional schematic diagram of a CMOS device in a semiconductor device based on a specific embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid obscuring the present invention.

[0044] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Like reference numerals throughout the drawings denote like elements.

[0045] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below may be denoted as a second element, component, region, layer, or section without departing from the teachings of the present invention.

[0046] Spatial relationship terms such as “below,” “beneath,” “lower,” “under,” “above,” “upper,” etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as “below” or “beneath” or “under” another element or feature will be oriented “above” the other element or feature. Thus, the exemplary terms “below” and “beneath” can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] Currently, in order to improve the breakdown voltage of LDMOS devices, a gate field plate structure is usually adopted. There are three traditional gate field plate structures: the step-oxide structure, the local oxidation of silicon (LOCOS) structure, and the STI structure. As Figure 1 shown, the LDMOS device based on the STI structure includes a semiconductor substrate 100, a drift region 101 formed in the semiconductor substrate 100, and a body region 102 adjacent to the drift region 101; a body region contact region 103 and a source region 104 are formed in the body region 102, a shallow trench isolation structure 106 and a drain region 105 are formed in the drift region 101, and the drain region 105 is formed on the side of the shallow trench isolation structure 106 away from the source region 104. A gate structure is further formed on the semiconductor substrate 100, the gate structure includes a gate dielectric layer 107 and a gate electrode layer 108, and the gate structure partially covers the shallow trench isolation structure 106. Among them, the body region serves as a channel region to control the on and off of the LDMOS device; the drift region is used to withstand the high voltage of the LDMOS device; the trench isolation filling structure increases the effective length of the drift region, thereby improving the breakdown voltage of the LDMOS device.

[0049] Figure 1 The main disadvantage of the LDMOS device shown is that the junction between the gate dielectric layer and the top of the sidewall of the trench isolation filling structure is easily broken down in advance, resulting in a reduction in the breakdown voltage of the LDMOS device. In order to improve the breakdown voltage, one approach is to reduce the ion implantation dose in the drift region or reduce the size of the drift region surrounding the trench insulation filling structure; however, these two methods will increase the on-resistance of the LDMOS device. At the same time, increasing the width of the shallow trench isolation structure cannot further increase the breakdown voltage of the LDMOS device.

[0050] In view of the existence of the foregoing technical problems, an embodiment of the present invention provides an LDMOS device and a manufacturing method thereof. Next, refer to Figures 2 to 3G for a detailed description of the manufacturing method of the LDMOS device according to the embodiment of the present invention, where Figure 2 shows a schematic flow chart of the manufacturing method of the LDMOS device according to a specific embodiment of the present invention, Figure 3A and Figure 3G shows a device cross-sectional view obtained during the implementation of the manufacturing method of the LDMOS device according to a specific embodiment of the present invention.

[0051] First, step S201 is executed. As Figure 3A shown, a semiconductor substrate 300 is provided.

[0052] Exemplarily, the material of the semiconductor substrate 300 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, or silicon on insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon germanium-on-insulator stacked silicon (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).

[0053] Exemplarily, the semiconductor substrate 300 has doping ions of a first conductivity type, and the doping ions of the first conductivity type can be P-type doping ions or N-type doping ions. When the formed LDMOS is an N-type LDMOS device, the first conductivity type is P-type; when the formed LDMOS is a P-type LDMOS device, the first conductivity type is N-type. Hereinafter, the case where the first conductivity type is P-type is mainly taken as an example for description.

[0054] Next, step S202 is performed to form a drift region 301 in the semiconductor substrate 300.

[0055] Exemplarily, before forming the drift region 301, the semiconductor substrate 300 can also be implanted with doping ions of a second conductivity type to form a well region. Exemplarily, the well region has N-type doping ions.

[0056] Next, a drift region 301 is formed in the well region. The drift region has doping ions of a second conductivity type, such as N-type doping ions. The doping concentration of the drift region 301 is relatively low, so that the LDMOS device can withstand a higher voltage.

[0057] Next, step S203 is performed to form at least two shallow trenches in the drift region 301. Exemplarily, the at least two shallow trenches have the same width and depth. The number of shallow trenches can be two or more, and can be specifically set according to process requirements. Exemplarily, the shallow trenches can also be formed prior to the drift region 301.

[0058] Specifically, first as Figure 3B shown, a hard mask layer 302 is formed on the semiconductor substrate 300. The material of the hard mask layer 302 can include one or a combination of nitride, oxide, oxynitride, fluorine-doped silica FSG, carbon-doped silica, etc. The method for forming the hard mask layer 302 includes, but is not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. In one example, the hard mask layer includes a silica layer and a silicon nitride layer formed on the semiconductor substrate 300 in sequence.

[0059] Next, a photoresist layer 303 is formed on the hard mask layer 302. Based on the photoresist layer 303, the hard mask layer 302 and the semiconductor substrate 300 are etched in sequence to form openings in the hard mask layer 302 and shallow trenches in the semiconductor substrate 300 that are located below the openings.

[0060] Specifically, first, a layer of photoresist layer 303 is spin-coated on the hard mask layer 302, and the photoresist layer 303 is exposed and developed, thereby forming at least two windows in the photoresist layer 303, with each window corresponding to a shallow trench, as Figure 3B shown. After that, an anisotropic dry etching process is performed using the photoresist layer 303 as a mask, thereby forming at least two openings in the hard mask layer 302 that are located below the windows, and etching the semiconductor substrate 300 exposed by the openings to form at least two shallow trenches, as Figure 3C shown. Then, processes such as ashing can be used to remove the photoresist layer, and cleaning and drying treatments are performed.

[0061] The shallow trenches formed based on the above etching process have relatively sharp top corners and bottom corners, where electric field peaks are likely to form, reducing the breakdown voltage of the LDMOS device. To avoid this problem, the top corners and / or bottom corners of the shallow trenches can be rounded to optimize the electric field distribution at the corners, as Figure 3D shown.

[0062] In one example, an isotropic dry etching process can be used to round the top corners and / or bottom corners of the shallow trenches. Specifically, first, the hard mask layer 302 is etched laterally to expand the openings formed in the hard mask layer 302 and expose the top corners of the shallow trenches; then, an isotropic dry etching process is performed to round the top corners and bottom corners of the shallow trenches. During the process of performing the isotropic dry etching process, O2 and CF4 plasmas can be used and no bias voltage is applied, so that the plasmas bombard the bottom of the shallow trenches in different directions, thereby rounding the top corners and bottom corners of the shallow trenches.

[0063] When the hard mask layer 302 includes multiple stacked layers of different materials, only the hard mask material layer adjacent to the semiconductor substrate 300 can be etched laterally, thereby exposing the top corners of the shallow trenches below it without reducing the thickness of the hard mask layer, ensuring that the subsequent formed shallow trench isolation structure has the expected height. For example, when the hard mask layer 302 includes a silicon oxide layer and a silicon nitride layer formed in sequence, a dilute hydrofluoric acid solution can be used to etch the silicon oxide layer laterally to expose the semiconductor substrate 300 below the silicon oxide layer, and the process is simple and does not affect the thickness of the upper silicon nitride layer.

[0064] Next, step S204 is performed to form isolation materials in at least two shallow trenches to form at least two shallow trench isolation structures 304, and the tops of the at least two shallow trench isolation structures 304 are higher than the surface of the semiconductor substrate 300.

[0065] Specifically, first, as Figure 3E shown, isolation materials are deposited to fill at least two shallow trenches in the semiconductor substrate 300 and to fill the openings formed in the hard mask layer 302 above the shallow trenches. Among them, the isolation materials may include at least one of insulating materials such as silicon dioxide, silicon nitride, tetraethyl orthosilicate, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, silicon oxynitride, etc. The deposition process includes but is not limited to Chemical Vapor Deposition (CVD) process. Since the shallow trenches in the embodiments of the present invention are narrower in width and larger in aspect ratio compared with conventional shallow trenches, the High Density Plasma-Chemical Vapor Deposition (HDP-CVD) process can be used to deposit the isolation materials to avoid voids during filling. Next, a planarization process is performed to remove the isolation materials above the hard mask layer 302, and the planarization process may include Chemical Mechanical Polishing (CMP) process.

[0066] After that, as Figure 3F shown, the hard mask layer 302 is removed to obtain the shallow trench isolation structure 304, and the top of the shallow trench isolation structure 304 is higher than the surface of the semiconductor substrate. For example, the hard mask layer 302 can be removed by a wet etching process, and the filling materials filling the openings in the hard mask layer 302 constitute the part of the shallow trench isolation structure 304 above the semiconductor substrate 300. Thus, without adding additional processes, the shallow trench isolation structure 304 higher than the semiconductor substrate 300 can be obtained based on the existing hard mask layer.

[0067] Next, step S205 is performed. As Figure 3G shown, a dielectric layer 305 is formed between the portions of the at least two shallow trench isolation structures 304 that are higher than the surface of the semiconductor substrate 300, and a gate dielectric layer 306 is formed on the semiconductor substrate 300 and the shallow trench isolation structures 304.

[0068] Exemplarily, a thermal oxidation process can be employed to oxidize the surface of the semiconductor substrate 300, thereby simultaneously forming the dielectric layer 305 and the gate dielectric layer 306. Specifically, the semiconductor substrate 300 can be exposed to oxygen or water vapor at a high temperature of 800°C - 1100°C, causing silicon to react with oxygen to form silicon dioxide. The thermal oxidation process can generate a high-quality gate dielectric layer 306 and dielectric layer 305, and can avoid the problem of incomplete filling of the dielectric layer 305 that may occur in the deposition process. The dielectric layer 305 can connect the portions of at least two shallow trench isolation structures 304 above the surface of the semiconductor substrate 300 into a whole, jointly serving to increase the thickness of the dielectric layer and improve the breakdown voltage.

[0069] Next, step S206 is executed to form a gate electrode layer 307 on the gate dielectric layer 306. Specifically, a deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition can be performed to form the gate electrode layer 307, and the material of the gate electrode layer 307 can include conductive materials such as polysilicon or metal. Since a part of the gate electrode layer 307 is formed above the shallow trench isolation structure 304, the top of the gate electrode layer 307 above the shallow trench isolation structure 304 is higher than the top of the gate electrode layer 307 above the semiconductor substrate 300, making the gate electrode layer 307 present a stepped shape.

[0070] Next, step S207 is executed to pattern the gate electrode layer 307 and the gate dielectric layer 306 to form a gate structure. Specifically, a mask layer can be formed on the gate electrode layer 307, and the gate electrode layer 307 and the gate dielectric layer 306 are etched based on the mask layer to obtain a stepped gate structure. After that, spacer walls 308 can also be formed on both sides of the gate structure to protect the sidewalls of the gate structure.

[0071] After forming the gate structure, step S208 is executed to form a body region 309 in the semiconductor substrate 300. The body region 309 has doping ions of a first conductivity type, such as P-type doping ions. The body region 309 and the drift region 301 are arranged side by side in the semiconductor substrate 300, and the gate structure also covers a part of the body region 309 to form a channel region during operation. It should be noted that the body region 309 can also be formed prior to the gate structure, or prior to the shallow trench.

[0072] Next, step S209 is performed to form a drain region 312 in the drift region 301 and a source region 310 in the body region 309. In addition, a body contact region 311 can also be formed in the body region 309. Among them, the drain region 312 is located on the side of the shallow trench isolation structure 304 away from the body region 309, and the body contact region 311 is located on the side of the source region 310 away from the drift region 301. The body contact region 311 has doping ions of a first conductivity type, and the source region 310 and the drain region 312 have doping ions of a second conductivity type. For example, the body contact region 311 has P-type doping ions, and the source region 310 and the drain region 312 have N-type doping ions, and the source region 310, the drain region 312, and the body contact region 311 have a relatively high doping concentration. After the source region 310 and the drain region 312 are formed, a high-temperature annealing process is performed to form a graded doping profile with the previously implanted doping ions.

[0073] So far, the process steps implemented according to the manufacturing method of the LDMOS device in the first aspect embodiment of the present invention are completed. It can be understood that the manufacturing method of the LDMOS device in this embodiment not only includes the above steps, but may also include other necessary steps before, during, or after the above steps, and all of them are included in the scope of the manufacturing method of this embodiment.

[0074] According to the manufacturing method of the LDMOS device provided by the embodiments of the present invention, at least two shallow trench isolation structures are provided in the drift region, which can improve the breakdown voltage without increasing the on-resistance; the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, increasing the thickness of the insulating material under the gate structure, reducing the electric field strength at the junction of the gate structure and the shallow trench isolation structure, avoiding breakdown at the junction, and further improving the breakdown voltage of the LDMOS device.

[0075] The embodiments of the present invention also provide an LDMOS device, which can be prepared by the method in the foregoing embodiments, but is not limited thereto.

[0076] Next, a detailed introduction and description of the LDMOS device of the present invention will be given. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as those in the foregoing embodiments, and the specific explanations and descriptions can be referred to the description in Embodiment 1.

[0077] Specifically, as Figure 3GAs shown in the figure, the LDMOS device according to an embodiment of the present invention includes: a semiconductor substrate 300; a body region 309, a drift region 301 formed in the semiconductor substrate 300, a source region 310 located in the body region 309, and a drain region 312 located in the drift region 301; at least two shallow trench isolation structures 304 formed in the drift region 301, the tops of the at least two shallow trench isolation structures 304 are higher than the surface of the semiconductor substrate 300, and a dielectric layer 305 is formed between the portions of the at least two shallow trench isolation structures 304 that are higher than the surface of the semiconductor substrate 300; and a gate structure, the gate structure includes a gate dielectric layer 306 and a gate electrode layer 307 located on the gate dielectric layer 306, the gate structure extends laterally from the body region 309 to the drift region 301 and at least partially covers the shallow trench isolation structure 304.

[0078] Further, the gate structure at least partially covers the dielectric layer 305.

[0079] Further, the shape of the gate structure is stepped, and the top of the gate structure above the shallow trench isolation structure 304 is higher than the top of the gate structure above the body region 309 and the drift region 301.

[0080] Further, the shallow trench isolation structure 304 has a smooth top corner, and / or the shallow trench isolation structure 304 has a smooth bottom corner.

[0081] The LDMOS device according to an embodiment of the present invention is provided with at least two shallow trench isolation structures in the drift region, which can improve the breakdown voltage without increasing the on-resistance; the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, increasing the thickness of the insulating material under the gate structure, reducing the electric field strength at the junction of the gate structure and the shallow trench isolation structure, avoiding breakdown at the junction, and further improving the breakdown voltage of the LDMOS device.

[0082] On the other hand, an embodiment of the present invention provides a semiconductor device, including the LDMOS device and a CMOS device as described above. Among them, as Figure 4 shown, the CMOS device includes a semiconductor substrate 400, at least two transistor structures 401 formed in the semiconductor substrate, and a shallow trench isolation structure 402 located between the at least two transistor structures 401, and the shallow trench isolation structure has a smooth top corner and / or a smooth bottom corner. Each transistor structure 401 at least includes a source region, a drain region located between the semiconductor substrates 400, and a gate structure above the semiconductor substrate 400 between the source region and the drain region.

[0083] The semiconductor device can be a BCD (Bipolar-CMOS-DMOS) device, that is, a semiconductor device in which bipolar transistors, CMOS, and DMOS (double-diffused metal oxide semiconductor) transistors are combined on a single chip. Among them, CMOS is mainly used to control logic operations, and LDMOS is mainly used for voltage withstand, gain, linearity, heat dissipation, etc.

[0084] In a CMOS device, if the top corners and bottom corners of the shallow trench isolation structure are sharp corners, it is easy to cause electric field spikes, reduce the carrier mobility, thereby reducing the threshold voltage (Vth) of the CMOS device, and even cause the "Hump Effect" of the device, resulting in the dew point problem and output error of the semiconductor, and further causing terminal failure, affecting the reliability of the entire circuit. In the embodiment of the present invention, the shallow trench isolation structure of the CMOS device is set to have rounded top corners and / or rounded bottom corners, which can avoid the above problems. Exemplarily, the shallow trench isolation structure of the CMOS device and the shallow trench isolation structure of the above LDMOS device are formed synchronously, and the top corners and / or bottom corners of the two can be rounded by the same isotropic dry etching process.

[0085] In the embodiment of the present invention, an electronic device is also provided, including the aforementioned semiconductor device, and the semiconductor device can be prepared according to the aforementioned method.

[0086] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or can also be any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because it uses the above-mentioned semiconductor device.

[0087] The present invention has been described through the above embodiments, but it should be understood that the above embodiments are only for the purpose of illustration and example, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of protection required by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalent scope.

Claims

1. An LDMOS device, characterized in that: The LDMOS device comprises: Semiconductor substrate; A body region, a drift region, a source region in the body region, and a drain region in the drift region are formed in the semiconductor substrate; At least two shallow trench isolation structures are formed in the drift region, wherein the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, and a dielectric layer is formed between the portions of the at least two shallow trench isolation structures that are higher than the surface of the semiconductor substrate; and, A gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer, the gate structure extends laterally from the body region to the drift region and at least partially covers the shallow trench isolation structure.

2. The LDMOS device according to claim 1, characterized in that The gate structure at least partially covers the dielectric layer.

3. The LDMOS device according to claim 1, characterized in that: The gate structure is in a stepped shape, and a top portion of the gate structure located above the shallow trench isolation structure is higher than a top portion of the gate structure located above the body region and the drift region.

4. The LDMOS device according to claim 1, wherein: The at least two shallow trench isolation structures have rounded top angles, and / or the at least two shallow trench isolation structures have rounded bottom angles.

5. A method for manufacturing an LDMOS device, characterized in that: The method comprises: providing a semiconductor substrate; forming a drift region in the semiconductor substrate; forming at least two shallow trenches in the drift region; forming an isolation material in the at least two shallow trenches to form at least two shallow trench isolation structures, wherein tops of the at least two shallow trench isolation structures are higher than a surface of the semiconductor substrate; forming a dielectric layer between portions of the at least two shallow trench isolation structures that are higher than the surface of the semiconductor substrate, and forming a gate dielectric layer on the semiconductor substrate and the shallow trench isolation structures; forming a gate electrode layer on the gate dielectric layer; Patterning the gate electrode layer and the gate dielectric layer to form a gate structure; A body region is formed in the semiconductor substrate, wherein the gate structure extends laterally from the body region to the drift region and at least partially covers the shallow trench isolation structure; A source region is formed in the body region, and a drain region is formed in the drift region.

6. The manufacturing method according to claim 5, characterized in that: The forming of at least two shallow trenches in the drift region comprises: forming a hard mask layer and a photoresist layer in sequence on the semiconductor substrate; Sequentially etching the hard mask layer and the semiconductor substrate based on the photoresist layer to form openings corresponding to the at least two shallow trenches in the hard mask layer and to form the at least two shallow trenches in the semiconductor substrate; The step of forming an isolation material in the at least two shallow trenches to form at least two shallow trench isolation structures, wherein the tops of the at least two shallow trench isolation structures are higher than the surface of the semiconductor substrate, comprises: depositing an isolation material to fill the shallow trench and the opening; The hard mask layer is removed to obtain the at least two shallow trench isolation structures whose tops are higher than the surface of the semiconductor substrate.

7. The manufacturing method according to claim 6, characterized in that: After forming the at least two shallow trenches and before forming an isolation material in the at least two shallow trenches, the method further includes: The top angles and / or bottom angles of the at least two shallow grooves are rounded.

8. The manufacturing method according to claim 7, characterized in that: The step of rounding the top angles and / or bottom angles of the at least two shallow grooves comprises: Laterally etching the hard mask layer to expand the opening and expose the top corner of the shallow trench; An isotropic dry etching process is performed to round the top corner and the bottom corner.

9. The manufacturing method according to claim 5, characterized in that: The step of forming a dielectric layer between portions of the at least two shallow trench isolation structures that are higher than the surface of the semiconductor substrate, and forming a gate dielectric layer on the semiconductor substrate and the shallow trench isolation structures, comprises: A thermal oxidation process is performed on the surface of the semiconductor substrate to obtain the dielectric layer and the gate dielectric layer.

10. A semiconductor device, characterized in that: The semiconductor device comprises a CMOS device and an LDMOS device as claimed in any one of claims 1 to 4, wherein the CMOS device comprises a shallow trench isolation structure, and the shallow trench isolation structure of the CMOS device has a rounded top angle and / or a rounded bottom angle.

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