Display device

Abstract

An embodiment of the present disclosure relates to a display device that may include a substrate, a planarization layer disposed on the substrate, a weir spaced apart from the planarization layer, a first encapsulation layer covering the weir, and a first overcoat layer disposed on the first encapsulation layer and overlapping the weir, thereby preventing moisture penetration.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0183677, filed on December 15, 2023, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] Embodiments of the present disclosure relate to a display device. Background art

[0004] With the development of the information society, the demand for display devices that display images in various forms has increased. Therefore, in recent years, various display devices such as liquid crystal displays and organic light - emitting display devices have been used.

[0005] A display device may include a display area and a non - display area. Summary of the invention

[0006] Moisture may penetrate into the display panel through the non - display area.

[0007] Embodiments of the present disclosure may provide a display device capable of preventing moisture penetration.

[0008] Embodiments of the present disclosure may provide a display device capable of preventing the formation of seams in the display panel.

[0009] Embodiments of the present disclosure may provide a display device capable of extending the moisture penetration path.

[0010] Embodiments of the present disclosure may provide a display device capable of achieving low power consumption by preventing moisture penetration.

[0011] A display device according to an embodiment of the present disclosure may include a substrate, a planarization layer disposed on the substrate, a dam portion spaced apart from the planarization layer, a first encapsulation layer covering the dam portion, and a first outer coating layer disposed on the first encapsulation layer and overlapping the dam portion.

[0012] Embodiments of the present disclosure may provide a display device capable of preventing moisture penetration.

[0013] Embodiments of the present disclosure may provide a display device capable of preventing seams that may form on the display panel.

[0014] Embodiments of the present disclosure may provide a display device having improved encapsulation performance by forming a long moisture penetration path.

[0015] Embodiments of the present disclosure may provide a display device capable of achieving low power consumption by being able to prevent moisture penetration. Brief description of the drawings

[0016] Figure 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0017] Figure 2 Shows a display panel according to an embodiment of the present disclosure.

[0018] Figure 3 Shows a substrate of a display panel according to an embodiment of the present disclosure.

[0019] Figure 4 is a cross-sectional view of a display area of a display panel according to an embodiment of the present disclosure.

[0020] Figure 5 is a cross-sectional view of a dam portion area of a display device according to an embodiment of the present disclosure.

[0021] Figure 6 is a cross-sectional view of a dam portion area of a display device according to an embodiment of the present disclosure.

[0022] Figure 7 is a cross-sectional view of a dam portion area of a display device according to an embodiment of the present disclosure.

[0023] Figure 8 , Figure 9 and Figure 10 are diagrams for explaining a process of forming an outer coating according to an embodiment of the present disclosure. Detailed Description

[0024] In the following description of examples or embodiments of the present invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in the drawings, the same reference numerals and symbols may be used to represent the same or similar components, even if these components are shown in different drawings from each other. Further, in the following description of examples or embodiments of the present invention, when it is determined that a detailed description of well-known functions and components incorporated herein may make the subject matter in some embodiments of the present invention rather unclear, these descriptions will be omitted. Terms such as "comprising", "having", "including", "constituting", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise.

[0025] Terms such as "first", "second", "A", "B", "(A)", or "(B)" may be used herein to describe elements of the present invention. Each of these terms is not used to define the nature, order, sequence, quantity, etc. of the element, but is only used to distinguish the corresponding element from other elements.

[0026] When referring to the first element and the second element being "connected or combined", "contacted or overlapped", etc., it should be interpreted that not only can the first element be "directly connected or combined" or "directly contacted or overlapped" with the second element, but also a third element can be "interposed" between the first element and the second element, or the first element and the second element can be "connected or combined", "contacted or overlapped", etc. with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or combined", "contacted or overlapped", etc. with each other.

[0027] When time-related terms such as "after", "subsequently", "next", "before", etc. are used to describe the process or operation of an element or configuration, or the process or steps in an operation, processing, manufacturing method, these terms can be used to describe a non-continuous or non-sequential process or operation, unless used together with the terms "directly" or "immediately".

[0028] In addition, when referring to any size, relative size, etc., even if no relevant description is specified, the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature should be considered to include the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "can".

[0029] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] Figure 1 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0031] Referring to Figure 1 , a display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit is a circuit for driving the display panel 110, and may include a data driving circuit 120, a gate driving circuit 130, and a display controller 140.

[0032] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111.

[0033] The substrate 111 of the display panel 110 may include a display area DA capable of displaying an image and a non-display area NDA located outside the display area DA.

[0034] A plurality of sub-pixels SP for image display may be disposed in the display area DA, and the non-display area NDA may include a pad area PA extending from the display area DA in a first direction.

[0035] In the display panel 110 according to an embodiment of the present disclosure, the non-display area NDA can be very small. In this specification, the non-display area NDA may also be referred to as a "bezel".

[0036] For example, the non-display area NDA may include a first non-display area located outside the display area DA in a first direction, a second non-display area located outside the display area DA in a second direction intersecting the first direction, a third non-display area located outside the display area DA in a direction opposite to the first direction, and a fourth non-display area located outside the display area DA in a direction opposite to the second direction. One or two of the first non-display area to the fourth non-display area may include a pad area connected or coupled to the data driving circuit 120. Among the first non-display area to the fourth non-display area, two or three non-display areas that do not include the pad area may be very small in size.

[0037] For another example, the boundary area between the display area DA and the non-display area NDA may be curved such that the non-display area NDA may be located below the display area. In this case, when the user views the display device 100 from the front, there may be little or no non-display area NDA visible to the user.

[0038] Various types of signal lines for driving the plurality of sub-pixels SP may be provided on the substrate 111 of the display panel 110.

[0039] The display device 100 according to an embodiment of the present disclosure may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to an embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting device.

[0040] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting device is implemented as an organic light-emitting diode (OLED). For another example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting device is implemented as an inorganic-based light-emitting diode. For still another example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device in which the light-emitting device is implemented by quantum dots, which are self-luminous semiconductor crystals.

[0041] The structure of each sub-pixel among the plurality of sub-pixels SP may vary according to the type of the display device 100. For example, if the display device 100 is a self-emitting display device having self-emitting sub-pixels SP, each sub-pixel SP may include a self-emitting light-emitting device, one or more transistors, and one or more capacitors.

[0042] For example, various types of signal lines may include a plurality of data lines DL that supply data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL that transmit gate signals (also referred to as scan signals).

[0043] For example, the plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend in a first direction. Each of the plurality of gate lines GL may be arranged to extend in a second direction. Here, the first direction may be the column direction, and the second direction may be the row direction. Alternatively, the first direction may be the row direction, and the second direction may be the column direction. Hereinafter, for ease of explanation, a case where each of the plurality of data lines DL is arranged along the column direction and each of the plurality of gate lines GL is arranged along the row direction will be illustrated.

[0044] The data driving circuit 120 is a circuit for driving the plurality of data lines DL and may output data signals to the plurality of data lines DL.

[0045] The data driving circuit 120 may receive image data in digital form from the display controller 140 and convert the received image data into an analog data signal to output to the plurality of data lines DL.

[0046] For example, the data driving circuit 120 may be connected to the display panel 110 using a tape automated bonding (TAB) method, or may be connected to bonding pads of the display panel 110 using a chip on glass (COG) or chip on panel (COP) method, or may be implemented and connected to the display panel 110 using a chip on film (COF) method.

[0047] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to more than two sides of the four sides of the display panel 110.

[0048] The data driving circuit 120 may be connected to the outside of the display area DA of the display panel 110. However, alternatively, the data driving circuit 120 may be provided in the display area DA of the display panel 110.

[0049] The gate driving circuit 130 is a circuit for driving the plurality of gate lines GL and may output gate signals to the plurality of gate lines GL.

[0050] The gate driving circuit 130 may receive a first gate voltage corresponding to a conduction-level voltage, a second gate voltage corresponding to a cut-off-level voltage, and various gate driving control signals GCS, and may generate a gate signal and supply the generated gate signal to a plurality of gate lines GL.

[0051] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be built in the display panel 110 as a gate-in-panel (GIP) type. If the gate driving circuit 130 is of the gate-in-panel type, the gate driving circuit 130 may be formed on the substrate of the display panel 110 during the manufacturing process of the display panel 110.

[0052] In the display device 100 according to an embodiment of the present disclosure, the gate driving circuit 130 may be disposed in the display area DA of the display panel 110. For example, the gate driving circuit 130 may be disposed in a first partial area (e.g., the left area or the right area within the display area DA) within the display area DA. For another example, the gate driving circuit 130 may be disposed in a first partial area (e.g., the left area or the right area within the display area DA) and a second partial area (e.g., the right area or the left area within the display area DA) within the display area DA.

[0053] In the present disclosure, the gate driving circuit 130 built in the display panel 110 as a gate-in-panel type may be referred to as a "gate-in-panel circuit".

[0054] The display controller 140 may be a device for controlling the data driving circuit 120 and the gate driving circuit 130, and may control the driving timings of a plurality of data lines DL and a plurality of gate lines GL.

[0055] The display controller 140 may supply a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120, and may supply a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130.

[0056] The display controller 140 may receive input image data from the host system 150, and supply image data DATA to the data driving circuit 120 based on the input image data.

[0057] The display controller 140 may be implemented as a component separate from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0058] The display controller 140 may be a timing controller used in typical display technologies, or may be a control device including a timing controller capable of further performing other control functions, or may be a control device different from a timing controller, or may be a control device in addition to a timing controller, or may be a circuit within a control device. The display controller 140 may be implemented by various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0059] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit.

[0060] The display controller 140 may send signals to the data driving circuit 120 and receive signals from the data driving circuit 120 according to one or more predetermined interfaces. For example, the interface may include a low voltage differential signal (LVDS) interface, an embedded clock point-to-point interface (EPI) interface, or a serial peripheral interface (SPI).

[0061] In order to provide not only an image display function but also a touch sensing function, the display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit for detecting a touch generated by a touch object such as a finger or a pen or for detecting a touch position by sensing the touch sensor.

[0062] The touch sensing circuit may include a touch driving circuit for driving and sensing the touch sensor to generate and output touch sensing data, and a touch controller for detecting the occurrence of a touch or detecting a touch position using the touch sensing data.

[0063] The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch driving circuit.

[0064] The touch sensor may exist in the form of a touch panel outside the display panel 110, or may exist inside the display panel 110. If the touch sensor exists in the form of a touch panel outside the display panel 110, the touch sensor may be referred to as an external type. If the touch sensor is of the external type, the touch panel and the display panel 110 may be manufactured separately and combined during the assembly process. The external touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0065] If a touch sensor is present inside the display panel 110, during the manufacturing process of the display panel 110, the touch sensor can be formed on the substrate SUB together with signal lines and electrodes related to display driving.

[0066] The touch driving circuit can supply a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0067] The touch sensing circuit can perform touch sensing using a self - capacitance sensing method or a mutual - capacitance sensing method.

[0068] If the touch sensing circuit performs touch sensing using the self - capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self - capacitance sensing method, each of the plurality of touch electrodes can be used as a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0069] If the touch sensing circuit uses the mutual - capacitance sensing method to perform touch sensing, the touch sensing circuit can perform touch sensing based on the capacitance between touch electrodes. According to the mutual - capacitance sensing method, the plurality of touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0070] The touch driving circuit and the touch controller included in the touch sensing circuit can be implemented as separate devices or as one device. In addition, the touch driving circuit and the data driving circuit can be implemented as separate devices or one device.

[0071] The display device 100 can further include a power supply circuit that supplies various types of power to the display driving circuit and / or the touch sensing circuit.

[0072] The display device 100 according to an embodiment of the present disclosure can be a mobile terminal such as a smart phone or a tablet computer, or a display or a television of various sizes, but is not limited thereto, and can be displays of various types and sizes capable of displaying information or images.

[0073] The display device 100 according to an embodiment of the present disclosure can further include electronic devices such as a camera (e.g., an image sensor) and a detection sensor. For example, the detection sensor can be a sensor for detecting an object or a human body by receiving light such as infrared rays, ultrasonic waves, or ultraviolet rays.

[0074] Figure 2 FIG. 110 shows a display panel according to an embodiment of the present disclosure.

[0075] Referring to Figure 2 , the display panel 110 may include a substrate 111 provided with a plurality of sub-pixels SP and an encapsulation layer 200 on the substrate 111. Here, the encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0076] Referring to Figure 2 , when the display device 100 according to an embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting device ED and a sub-pixel circuit SPC for driving the light-emitting device ED.

[0077] Referring to Figure 2 , the sub-pixel circuit SPC may include a plurality of pixel driving transistors for driving the light-emitting device ED and at least one capacitor. In the present disclosure, the sub-pixel circuit SPC may drive the light-emitting device ED by supplying a driving current to the light-emitting device ED at a predetermined time. The light-emitting device ED may be driven by the driving current and emit light.

[0078] The plurality of pixel driving transistors may include a driving transistor DT for driving the light-emitting device ED and a scanning transistor ST that is turned on or off according to a scan signal SC.

[0079] The driving transistor DT may supply a driving current to the light-emitting device ED.

[0080] The scanning transistor ST may be configured to control the electrical state of a corresponding node in the sub-pixel circuit SPC, or control the state or operation of the driving transistor DT.

[0081] The at least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during a frame.

[0082] In order to drive the sub-pixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal may be applied to the sub-pixel SP. In addition, a common pixel driving voltage including a first driving voltage VDD and a second driving voltage VSS may be applied to the sub-pixel SP to drive the sub-pixel SP.

[0083] The light-emitting device ED may include an anode AND, a light-emitting device intermediate layer EL, and a cathode CAT. The light-emitting device intermediate layer EL may be a layer provided between the anode AND and the cathode CAT.

[0084] When the light-emitting device ED is an organic light-emitting device, the light-emitting device intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 between the anode AND and the light-emitting layer EML, and a second common intermediate layer COM2 between the light-emitting layer EML and the cathode CAT. The light-emitting layer EML may be disposed in each sub-pixel SP. In contrast, the first common intermediate layer COM1 and the second common intermediate layer COM2 may be commonly disposed to span multiple sub-pixels SP. The light-emitting layer EML may be disposed in each light-emitting region, and the first common intermediate layer COM1 and the second common intermediate layer COM2 may be commonly disposed to span multiple light-emitting regions and non-light-emitting regions. The first common intermediate layer COM1 and the second common intermediate layer COM2 may be collectively referred to as the common intermediate layer EL_COM.

[0085] For example, the first common intermediate layer COM1 may include a hole injection layer HIL and a hole transport layer HTL. The second common intermediate layer COM2 may include an electron transport layer ETL and an electron injection layer EIL. The hole injection layer may inject holes from the anode AND into the hole transport layer, and the hole transport layer may transport the holes to the light-emitting layer EML. The electron injection layer may inject electrons from the cathode CAT into the electron transport layer, and the electron transport layer may transport the electrons to the light-emitting layer EML.

[0086] For example, the cathode CAT may be electrically connected to the second common driving voltage line VSSL. The second common driving voltage VSS of the common pixel driving voltage type may be applied to the cathode CAT through the second common driving voltage line VSSL. The anode AND may be electrically connected to the first node N1 of the driving transistor DT of each sub-pixel SP. In the present disclosure, the second common driving voltage VSS may also be referred to as the base voltage VSS, and the second common driving voltage line VSSL may also be referred to as the base voltage line VSSL.

[0087] For example, the anode AND may be a pixel electrode disposed in each sub-pixel SP, and the cathode CAT may be a common electrode commonly disposed in multiple sub-pixels SP. For another example, the cathode CAT may be a pixel electrode disposed in each sub-pixel SP, and the anode AND may be a common electrode commonly disposed in multiple sub-pixels SP. Hereinafter, for the sake of convenience of description, it is assumed that the anode AND is a pixel electrode and the cathode CAT is a common electrode.

[0088] Each light-emitting device ED may be composed of an overlapping portion of the anode AND, the light-emitting device intermediate layer EL, and the cathode CAT. A predetermined light-emitting region may be formed by each light-emitting device ED. For example, the light-emitting region of each light-emitting device ED may include a region where the anode AND, the light-emitting device intermediate layer EL, and the cathode CAT overlap.

[0089] For example, the light-emitting device ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting device. For example, when the light-emitting device ED is an organic light-emitting diode OLED, the light-emitting device intermediate layer EL in the light-emitting device ED may include an organic light-emitting device intermediate layer EL containing an organic material.

[0090] The driving transistor DT may be a driving transistor for supplying a driving current to the light-emitting device ED. The driving transistor DT may be connected between the first common driving voltage line VDDL and the light-emitting device ED.

[0091] The driving transistor DT may include a first node N1 electrically connected to the light-emitting device ED, a second node N2 to which a data signal VDATA is applied, and a third node N3 to which a driving voltage VDD is applied from the first common driving voltage line VDDL.

[0092] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of explanation, a case where the second node N2 in the driving transistor DT is a gate node, the first node N1 is a source node, and the third node N3 is a drain node will be described.

[0093] Figure 2 The scanning transistor ST included in the sub-pixel circuit SPC shown in may be a switching transistor for transmitting a data signal VDATA, which is an image signal, to the second node N2, which is the gate node of the driving transistor DT.

[0094] The scanning transistor ST may be controlled to be turned on and off by a scanning signal SC, which is a gate signal applied through a scanning line SCL (a type of gate line GL), and may control the electrical connection between the second node N2 of the driving transistor DT and the data line DL. The drain or source of the scanning transistor ST may be electrically connected to the data line DL, and the source or drain of the scanning transistor ST may be electrically connected to the second node N2 of the driving transistor DT. The gate of the scanning transistor ST may be electrically connected to the scanning line SCL.

[0095] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DT.

[0096] The storage capacitor Cst can be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd) of an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DT.

[0097] Each of the driving transistor DT and the scanning transistor ST can be an n-type transistor or a p-type transistor.

[0098] The display panel 110 can have a top-emitting structure or a bottom-emitting structure.

[0099] If the display panel 110 has a top-emitting structure, at least a part of the sub-pixel circuit SPC can overlap at least a part of the light-emitting device ED in the vertical direction. Alternatively, if the display panel 110 has a bottom-emitting structure, the sub-pixel circuit SPC can not overlap with the light-emitting device ED in the vertical direction.

[0100] As Figure 2 shown, the sub-pixel circuit SPC can have a 2T-1C structure including two transistors T1 and T2 and one capacitor Cst. In some cases, the sub-pixel circuit SPC can also include one or more transistors or one or more capacitors.

[0101] For example, the sub-pixel circuit SPC can have an 8T-1C structure including eight transistors and a single capacitor. For another example, the sub-pixel circuit SPC can have a 6T-2C structure including six transistors and two capacitors. For yet another example, the sub-pixel circuit SPC can have a 7T-1C structure including seven transistors and one capacitor.

[0102] According to the structure of the sub-pixel circuit SPC, the type and number of gate signals and / or gate lines supplied to the sub-pixel SP can be changed.

[0103] In addition, according to the structure of the sub-pixel circuit SPC, the type and number of common pixel driving voltages supplied to the sub-pixel SP can be changed.

[0104] Since the circuit elements (specifically, the light-emitting device ED implemented by an organic light-emitting diode (OLED) containing an organic material) within each sub-pixel SP are vulnerable to external moisture or oxygen, the encapsulation layer 200 can be provided on the display panel 110 to prevent oxygen from penetrating into the circuit elements (specifically, the light-emitting device ED). The encapsulation layer 200 can be configured in various shapes to prevent the light-emitting device ED from coming into contact with moisture or oxygen.

[0105] Figure 3 The substrate 111 of the display panel 110 according to an embodiment of the present disclosure is shown.

[0106] Reference Figure 3 Referring to Figure 3 , the substrate 111 of the display panel 110 according to an embodiment of the present disclosure may include a display area DA for displaying an image and a non-display area NDA for not displaying an image.

[0107] Reference Figure 3 Referring to Figure 3 , the non-display area NDA may include a first non-display area NDA1 extending from the display area DA in a first direction, a second non-display area NDA2 extending from the display area DA in a second direction, a third non-display area NDA3 extending from the display area DA in a direction opposite to the first direction, and a fourth non-display area NDA4 extending from the display area DA in a direction opposite to the second direction. For example, the first direction may be a column direction (e.g., the Y-axis direction), and the second direction intersecting the first direction may be a row direction (e.g., the X-axis direction).

[0108] Reference Figure 3 Referring to Figure 3 , the first non-display area NDA1 may include a pad area PA provided with a plurality of pads.

[0109] A plurality of pads electrically connected to the driving circuit may be provided in the pad area PA. A plurality of driving circuits or a plurality of printed circuit boards may be electrically connected in the pad area. For example, the plurality of pads may include a plurality of display pads and a plurality of touch pads. A plurality of data lines, a first common driving voltage line VDDL, and a second common driving voltage line VSSL may be electrically connected to the plurality of display pads. A plurality of touch wirings may be electrically connected to the plurality of touch pads.

[0110] Reference Figure 3 Referring to Figure 3 , the first non-display area NDA1 may further include a bending area BA. In this case, the substrate 111 may be a flexible substrate. In some cases, the first non-display area NDA1 may not include the bending area BA.

[0111] Reference Figure 3 Referring to Figure 3 , the display panel 110 may further include a ground wire provided in the non-display area NDA of the substrate 111. The ground wire may be provided to extend from a point in the pad area PA through the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4 to another point in the pad area PA.

[0112] Reference Figure 3 Referring to Figure 3 , the display panel 110 may include an encapsulation layer area A_ENCAP and a dam area A_DAM.

[0113] Reference Figure 3, the encapsulation layer region A_ENCAP can be the region where the encapsulation layer 200 is provided. In the display panel 110 according to an embodiment of the present disclosure, the encapsulation layer 200 can have a structure in which an inorganic layer and an organic layer are stacked. In this case, the edge of the encapsulation layer 200 can be referred to as the edge of the organic layer.

[0114] Referring to Figure 3 , the dam region A_DAM can be the region surrounding the encapsulation layer region A_ENCAP. A structure for providing a dam function can be provided in the dam region A_DAM. The dam can prevent the liquid organic film from flowing outwards.

[0115] Figure 4 is a cross-sectional view of the display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0116] Referring to Figure 4 , the substrate SUB can include a first substrate SUB1, an interlayer insulating film IPD, and a second substrate SUB2. The interlayer insulating film IPD can be located between the first substrate SUB1 and the second substrate SUB2. Since the substrate SUB is composed of the first substrate SUB1, the interlayer insulating film IPD, and the second substrate SUB2, moisture penetration can be prevented. For example, the first substrate SUB1 and the second substrate SUB2 can be polyimide (PI) substrates. The first substrate SUB1 can be referred to as a primary PI substrate, and the second substrate SUB2 can be referred to as a secondary PI substrate.

[0117] Referring to Figure 4 , various patterns (e.g., ACT, SD1, and GATE) and various insulating films (e.g., MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, and PAS0) and various metal patterns (e.g., TM, GM, ML1, and ML2) can be provided on the substrate SUB.

[0118] Referring to Figure 4 , the multi-buffer layer MBUF can be provided on the second substrate SUB2, and the first active buffer layer ABUF1 can be provided on the multi-buffer layer MBUF.

[0119] The first metal layer ML1 and the second metal layer ML2 can be provided on the first active buffer layer ABUF1. Here, the first metal layer ML1 and the second metal layer ML2 can be a light-shielding layer LS for light shielding.

[0120] The second active buffer layer ABUF2 can be provided on the first metal layer ML1 and the second metal layer ML2. The first active layer ACT of the driving transistor DRT can be provided on the second active buffer layer ABUF2.

[0121] The first gate insulating film GI may be provided to cover the first active layer ACT.

[0122] The first gate GATE of the driving transistor DRT may be provided on the first gate insulating film GI. In this case, the gate material layer GM may be provided on the first gate insulating film GI together with the first gate GATE of the driving transistor DRT and may be provided at a position different from the formation position of the driving transistor DRT.

[0123] The first interlayer insulating film ILD1 may be provided to cover the first gate GATE and the gate material layer GM. The metal pattern TM may be provided on the first interlayer insulating film ILD1. The metal pattern TM may be located at a position different from the formation position of the driving transistor DRT. The second interlayer insulating film ILD2 may be provided to cover the metal pattern TM on the first interlayer insulating film ILD1.

[0124] Two first source-drain patterns SD1 may be provided on the second interlayer insulating film ILD2. One of the two first source-drain patterns SD1 may be a source node of the driving transistor DRT, and the other may be a drain node of the driving transistor DRT. The two first source-drain patterns SD1 may be electrically connected to one side and the other side of the first active layer ACT through contact holes in the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the first gate insulating film GI.

[0125] The portion of the first active layer ACT overlapping with the first gate GATE may be a channel region. One of the two first source-drain patterns SD1 may be connected to one side of the channel region in the first active layer ACT, and the other of the two first source-drain patterns SD1 may be connected to the other side of the channel region in the first active layer ACT.

[0126] The passivation layer PAS0 may be provided to cover the two first source-drain patterns SD1. The planarization layer PLN may be provided on the passivation layer PAS0. The planarization layer PLN may include a first planarization layer PLN1 and a second planarization layer PLN2.

[0127] The first planarization layer PLN1 may be provided on the passivation layer PAS0.

[0128] The second source-drain pattern SD2 may be provided on the first planarization layer PLN1. The second source-drain pattern SD2 may be connected to one of the two first source-drain patterns SD1 (corresponding to Figure 3 the second node N2 of the driving transistor DRT in the sub-pixel SP) through a contact hole in the first planarization layer PLN1.

[0129] The second planarization layer PLN2 may be set to cover the second source-drain pattern SD2. The light-emitting device ED may be disposed on the second planarization layer PLN2.

[0130] In the stacked structure of the light-emitting device ED, the anode AE may be disposed on the second planarization layer PLN2. The anode AE may be electrically connected to the second source-drain pattern SD2 through a contact hole in the second planarization layer PLN2.

[0131] The bank BANK may be set to cover a part of the anode AE. A part of the bank BANK corresponding to the light-emitting region EA of the sub-pixel SP may be open.

[0132] A part of the anode AE may be exposed to the opening (i.e., the opening part) of the bank BANK. The light-emitting layer EL may be located on the side surface of the bank BANK and the opening (i.e., the opening part) of the bank BANK. All or part of the light-emitting layer EL may be located between adjacent banks BANK.

[0133] At the opening of the bank BANK, the light-emitting layer EL may contact the anode AE. The cathode CE may be disposed on the light-emitting layer EL.

[0134] The light-emitting device ED may be formed of the anode AE, the light-emitting layer EL, and the cathode CE. The light-emitting layer EL may include an organic layer.

[0135] The encapsulation layer ENCAP may be disposed on the light-emitting device ED.

[0136] The encapsulation layer ENCAP may have a single-layer structure or a multi-layer structure. For example, as Figure 6 and Figure 7 shown, the encapsulation layer ENCAP may include a first encapsulation layer PAS1, a second encapsulation layer PCL, and a third encapsulation layer PAS2.

[0137] For example, the first encapsulation layer PAS1 and the third encapsulation layer PAS2 may be inorganic films, and the second encapsulation layer PCL may be an organic film. Among the first encapsulation layer PAS1, the second encapsulation layer PCL, and the third encapsulation layer PAS2, the second encapsulation layer PCL may be the thickest and may be used as a planarization layer.

[0138] The first encapsulation layer PAS1 may be disposed on the cathode CE and may be set to be closest to the light-emitting device ED. The first encapsulation layer PAS1 may be formed of an inorganic insulating material capable of low-temperature deposition. For example, the first encapsulation layer PAS1 may be silicon nitride (SiN x ), silicon oxide (SiO x)), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer PAS1 is deposited in a low-temperature atmosphere, the first encapsulation layer PAS1 can prevent the light-emitting layer EL containing organic materials vulnerable to high-temperature atmospheres from being damaged during the deposition process.

[0139] The second encapsulation layer PCL can be formed to have an area smaller than that of the first encapsulation layer PAS1. In this case, the second encapsulation layer PCL can be formed to expose both ends of the first encapsulation layer PAS1. The second encapsulation layer PCL can be used as a buffer to relieve the stress between layers due to the bending of the display device 100, and can also be used to enhance the planarization performance. For example, the second encapsulation layer PCL can be acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbide (SiOC), and can be formed of an organic insulating material. For example, the second encapsulation layer PCL can be formed using an inkjet method.

[0140] The third inorganic encapsulation layer PAS2 can be formed on the substrate SUB on which the second encapsulation layer PCL is formed to cover the upper surfaces and side surfaces of each of the second encapsulation layer PCL and the first encapsulation layer PAS1. The third encapsulation layer PAS2 can minimize or prevent external moisture or oxygen from penetrating into the first inorganic encapsulation layer PAS1 and the second encapsulation layer PCL which is an organic encapsulation layer. For example, the third encapsulation layer PAS2 can be formed of an inorganic insulating material such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0141] Referring to Figure 4 , when the touch sensor TS is of the type built into the display panel 110, the touch sensor TS can be provided on the encapsulation layer ENCAP. The touch sensor structure is described in detail below.

[0142] The touch buffer film T-BUF can be provided on the encapsulation layer ENCAP. The touch sensor TS can be provided on the touch buffer film T-BUF.

[0143] The touch sensor TS can include a touch sensor metal TSM and a bridging metal BRG located in different layers.

[0144] The touch interlayer insulating film T-ILD can be provided between the touch sensor metal TSM and the bridging metal BRG.

[0145] For example, the touch sensor metal TSM may include a first touch sensor metal TSM, a second touch sensor metal TSM, and a third touch sensor metal TSM arranged adjacent to each other. When the third touch sensor metal TSM is disposed between the first touch sensor metal TSM and the second touch sensor metal TSM, and the first touch sensor metal TSM and the second touch sensor metal TSM need to be electrically connected to each other, the first touch sensor metal TSM and the second touch sensor metal TSM may be electrically connected to each other through a bridging metal BRG located on different layers. The bridging metal BRG may be insulated from the third touch sensor metal TSM through a touch interlayer insulating film T-ILD.

[0146] When forming the touch sensor TS on the display panel 110, chemical solutions (such as developers or etchants) used in the process or moisture from the outside may be generated. By disposing the touch sensor TS on the touch buffer film T-BUF, it is possible to prevent the chemical solution or moisture from penetrating into the light-emitting layer EL containing organic materials during the manufacturing process of the touch sensor TS. Therefore, the touch buffer film T-BUF can prevent damage to the light-emitting layer EL that is vulnerable to chemicals or moisture.

[0147] The touch buffer film T-BUF may be formed at a low temperature below a specific temperature (e.g., 100 degrees Celsius) to prevent damage to the light-emitting layer EL containing organic materials that are vulnerable to high temperatures, and may be made of an organic insulating material having a low dielectric constant of 1-3. For example, the touch buffer film T-BUF may be formed of an acrylic-based, epoxy-based, or siloxane-based material. When the display device 100 is bent, the encapsulation layer ENCAP may be damaged, and the touch sensor metal located on the touch buffer layer T-BUF may be broken. Even when the display device 100 is bent, the touch buffer film T-BUF made of an organic insulating material and having a flat performance can prevent damage to the encapsulation layer ENCAP and / or breakage of the metal (such as TSM, BRG) constituting the touch sensor TS.

[0148] The protective layer PAC may be provided to cover the touch sensor TS. The protective layer PAC may be an organic insulating film.

[0149] Figure 5 is a cross-sectional view of the weir portion area of the display device 100 according to an embodiment of the present disclosure. In Figure 5 Among the structural features of the shown display panel 110, the description of features identical to those of the Figure 4 shown display panel 110 may be omitted.

[0150] The first substrate SUB1 may be disposed at the bottom of the display panel 110. The first substrate SUB1 may be the same as the Figure 4 shown first substrate SUB1.

[0151] The interlayer insulating film IPD can be provided on the first substrate SUB1. The interlayer insulating film IPD can be the same as the Figure 4 interlayer insulating film IPD shown.

[0152] The second substrate SUB2 can be provided on the interlayer insulating film IPD. The second substrate SUB2 can be the same as the Figure 4 second substrate SUB2 shown.

[0153] The buffer layer BUF can be provided on the second substrate SUB2. The buffer layer BUF can include the Figure 4 multi-buffer layer MBUF and the active buffer layers ABUF1 and ABUF2 shown.

[0154] The planarization layer PLN can be provided on the buffer layer BUF. The planarization layer PLN can include the Figure 4 planarization layer PLN shown. The planarization layer PLN can be composed of two or more than three planarization layers. The planarization layer can include contact holes, and the upper electrode and the lower electrode can be electrically connected through the contact holes.

[0155] The anode AE can be provided on the planarization layer PLN. The planarization layer PLN can include a plurality of transistors, and the plurality of transistors can include driving transistors. The source (or drain) of the driving transistor can be electrically connected to the anode AE. Figure 5 The anode AE shown can have the same characteristics as the Figure 4 anode AE shown. For the sake of convenience of explanation, the structure of the transistor electrically connected to the anode AE shown will be omitted. Figure 5 shown.

[0156] The bank BANK can be provided on the planarization layer PLN and the anode AE.

[0157] The outermost bank BANK_O can be provided on the planarization layer PLN and can be provided adjacent to the end of the planarization layer PLN. The outermost bank BANK_O can prevent the organic encapsulation layer from overflowing to the outside.

[0158] The dam DAM can be provided on the buffer layer BUF. The dam can prevent the organic encapsulation layer from overflowing to the outside. The dam DAM can be provided at an interval from the outermost bank BANK_O.

[0159] The light-emitting layer EL can be provided on the bank BANK. The light-emitting layer EL can be provided on the bank BANK and in contact with the anode AE. Referring to Figure 5 the light-emitting layer EL can be provided in contact with two anode AEs. The cathode (not shown) can be provided on the light-emitting layer EL.

[0160] The first encapsulation layer PAS1 can be set to cover the light-emitting layer EL, the outermost bank BANK_O, and the dam DAM. The first encapsulation layer PAS1 can be an inorganic encapsulation layer. The first encapsulation layer PAS1 can be deposited on the entire surface from the display area to the non-display area.

[0161] The second encapsulation layer PCL1 can be disposed on the first encapsulation layer PAS1. The second encapsulation layer PCL1 can be an organic encapsulation layer. The second encapsulation layer PCL1 can be thicker than the first encapsulation layer PAS1 and the third encapsulation layer PAS2.

[0162] The third encapsulation layer PAS2 can be set to cover the second encapsulation layer PCL1 and the first encapsulation layer PAS1. The third encapsulation layer PAS2 can be an inorganic encapsulation layer.

[0163] Meanwhile, when forming a specific layer, the lower part of the specific layer can be formed to be close to a right angle. This can be referred to as a "high taper form".

[0164] The region where the high taper shape is formed can be a high taper region.

[0165] When forming the high taper shape, a seam shape may be generated in other layers disposed in the high taper region.

[0166] The step coverage can represent the thickness difference between the top layer and the bottom layer of the uneven surface on which deposition is performed, or the thickness difference between the top layer and the sidewall layer. The seam shape can be a shape that reduces the step coverage during the manufacturing process of the display panel 110. For example, the display panel 110 can include a structure having a specific shape, such as a cone. Another layer can be disposed on top of the structure having a specific shape (e.g., a cone). If the cone is not formed stably, the layer deposited on top of the cone structure may be unstable. If the layer deposited on the cone structure is unstable, cracks may occur in the layer, which can be referred to as a "seam".

[0167] For example, seams may be generated in the lower layer of the high taper shape. Refer to Figure 5 , the seams are indicated by dotted lines.

[0168] Moisture may penetrate the seam shape and damage the display device 100.

[0169] Therefore, embodiments of the present disclosure can provide a display device 100 capable of preventing moisture penetration.

[0170] Embodiments of the present disclosure can provide a display device 100 capable of preventing or delaying moisture from penetrating from the outside into the display panel through seams that may be formed in the display panel 110.

[0171] Embodiments of the present disclosure may provide a display device 100 having improved encapsulation performance by forming a long moisture permeation path.

[0172] Embodiments of the present disclosure may provide a display device 100 capable of achieving low power consumption by preventing moisture permeation.

[0173] The display device 100 will be described in detail below.

[0174] Figure 6 is a cross-sectional view of a dam portion area of the display device 100 according to an embodiment of the present disclosure.

[0175] Referring to Figure 6 , the first substrate SUB1 may be disposed at the lowermost part of the display panel 110. The first substrate SUB1 may be the same as the first substrate SUB1 shown in Figure 4 .

[0176] Referring to Figure 6 , the interlayer insulating film IPD may be disposed on the first substrate SUB1. The interlayer insulating film IPD may be the same as the interlayer insulating film IPD shown in Figure 4 .

[0177] Referring to Figure 6 , the second substrate SUB2 may be disposed on the interlayer insulating film IPD. The second substrate SUB2 may be the same as the second substrate SUB2 shown in Figure 4 .

[0178] Referring to Figure 6 , the buffer layer BUF may be disposed on the second substrate SUB2. The buffer layer BUF may include the multi-buffer layer MBUF and the active buffer layers ABUF1 and ABUF2 shown in Figure 4 .

[0179] Referring to Figure 6 , the planarization layer PLN may be disposed on the buffer layer BUF. The planarization layer PLN may include the planarization layer PLN shown in Figure 4 . The planarization layer PLN may be composed of two or more than three planarization layers PLN.

[0180] The planarization layer PLN may include an end portion having a high taper. Seams may be generated in the lower layer of the high taper region of the planarization layer PLN. That is, the lower layer of the high taper region of the planarization layer PLN may include seams. For example, referring to Figure 6 , seams may be formed in the buffer layer BUF.

[0181] Referring to Figure 6 , the anode AE may be disposed on the planarization layer PLN. For ease of explanation, Figure 6Configuration of a transistor electrically connected to an anode AE. A cathode (not shown) may be provided on a light-emitting layer EL.

[0182] Referring to Figure 6 , a bank BANK may be provided on a planarization layer PLN and an anode AE.

[0183] Referring to Figure 6 , an outermost bank BANK_O may be provided on the planarization layer PLN and may be provided adjacent to an end of the planarization layer PLN. The height of an upper surface of the outermost bank BANK_O may be higher than the height of other banks BANK. The outermost bank BANK_O may prevent an organic encapsulation layer from overflowing to the outside.

[0184] The outermost bank BANK_O may include an end portion formed with a high taper. A seam may be generated in a lower layer of a high taper region of the outermost bank BANK_O. That is, a lower layer of a high taper region of the outermost bank BANK_O may include a seam. For example, referring to Figure 6 , a seam may be formed in the planarization layer.

[0185] Referring to Figure 6 , a dam DAM may be provided on a buffer layer BUF. The dam may prevent an organic encapsulation layer from overflowing to the outside.

[0186] The height of the dam DAM may be similar to the height of the planarization layer PLN. In this case, the dam DAM and the planarization layer PLN may include the same components.

[0187] The dam DAM may be provided spaced apart from the planarization layer PLN. An organic encapsulation layer may be provided between the dam DAM and the planarization layer PLN.

[0188] The dam DAM may include an end portion formed with a high taper. A seam may be generated in a lower layer of a high taper region of the dam. That is, a lower layer of a high taper region of the dam may include a seam. For example, referring to Figure 6 , a seam may be formed in the buffer layer.

[0189] Referring to Figure 6 , a light-emitting layer EL may be provided on the bank BANK. The light-emitting layer EL may be provided on the bank BANK and in contact with the anode AE.

[0190] Referring to Figure 6 , a first encapsulation layer PAS1 may be provided to cover the light-emitting layer EL, the outermost bank BANK_O, and the dam DAM. The first encapsulation layer PAS1 may be an inorganic encapsulation layer.

[0191] Referring to Figure 6, the first outer coating FCL1 can be disposed on the first encapsulation layer PAS1 and can be disposed in the weir region. Since the first outer coating FCL1 is disposed in the weir region, the first outer coating FCL1 can be arranged to cover the high taper region. The weir region may include the region where the weir DAM and the outermost bank BANK_O are provided.

[0192] Referring to Figure 6 , the first outer coating FCL1 can be arranged to cover the outermost bank BANK_O, the planarization layer PLN, the buffer layer BUF, and the weir DAM.

[0193] The first outer coating FCL1 can be disposed on the outer side of the lower part of the planarization layer PLN. The first outer coating FCL1 can be arranged to overlap with the planarization layer PLN. When the planarization layer PLN is formed with a high taper, seams may be generated in the planarization layer PLN. The first encapsulation layer PAS1 and the first outer coating FCL1 can be disposed in the region where seams may appear in the planarization layer PLN.

[0194] The first outer coating FCL1 can be disposed on the outer side of the lower part of the bank BANK. The first outer coating FCL1 can be arranged to overlap with the bank BANK. When the bank BANK is formed with a high taper, seams may be generated in the bank BANK. The first encapsulation layer PAS1 and the first outer coating FCL1 can be disposed in the region where seams may appear in the bank BANK.

[0195] The first outer coating FCL1 can be disposed on the outer side of the inner lower part of the weir DAM. The first outer coating FCL1 can be arranged to overlap with the weir DAM. If the weir DAM is formed with a high taper, seams may be generated in the weir DAM. The first encapsulation layer PAS1 and the first outer coating FCL1 can be disposed in the region where seams may appear in the weir DAM.

[0196] The display panel 110 may include four border regions at the top, bottom, left, and right. The weir DAM can be disposed in at least three border regions. The first outer coating FCL1 disposed in the weir region can also be disposed in at least three border regions.

[0197] Referring to Figure 6 , the first outer coating FCL1 can be arranged to overlap with a part of the outermost bank BANK_O, one side of the planarization layer PLN, the upper surface of the buffer layer BUF, and the inner surface of the weir DAM.

[0198] Referring to Figure 6, a first portion of the first outer coating FCL1 overlapping with the upper surface of the outermost bank BANK_O may be set higher than a second portion of the first outer coating FCL1 overlapping with the upper surface of the dam DAM. The second portion of the first outer coating FCL1 overlapping with the upper surface of the dam DAM may be set higher than a third portion of the first outer coating FCL1 overlapping with the buffer layer BUF.

[0199] The first outer coating FCL1 may include a fluorine-based component. The fluorine-based component may have the property of separating it from moisture, that is, a hydrophobic property. Therefore, the first outer coating FCL1 containing the fluorine-based component can effectively block moisture.

[0200] The first outer coating FCL1 containing the fluorine-based component can be patterned or dissolved only by a fluorine-based material and cannot be dissolved by common organic solvents. Therefore, when forming the first outer coating FCL1 containing the fluorine-based component, the display panel 110 will not deteriorate due to the fluorine-based solvent.

[0201] The fluorine-based component may be in the form of a polymer containing different amounts of fluorine (F) based on a carbon-carbon chain.

[0202] The fluorine-based solvent may be a single molecule or a complex containing a large amount of fluorine (F) based on a carbon-carbon chain.

[0203] Referring to Figure 6 , the first outer coating FCL1 may be disposed inside the dam DAM.

[0204] Referring to Figure 6 , the second outer coating FCL2 may be disposed outside the dam DAM.

[0205] Referring to Figure 6 , the second outer coating FCL2 may be disposed outside the lower outer side of the dam DAM. The second outer coating FCL2 may be disposed to overlap with the dam DAM. If the dam DAM is formed with a high taper, seams may occur in the dam DAM. The first encapsulation layer PAS1 and the first outer coating FCL1 may be disposed in the area where seams may occur in the dam DAM.

[0206] The second outer coating FCL2 may be disposed to overlap with the upper surface of the buffer layer BUF and the outer surface of the dam DAM.

[0207] The second outer coating FCL2 may include a fluorine-based component. The properties of the second outer coating FCL2 containing the fluorine-based component are the same as those of the first outer coating FCL1 containing the fluorine-based component.

[0208] The height of the first outer coating FCL1 overlapping with the buffer layer BUF may be the same as the height of the second outer coating FCL2 overlapping with the buffer layer BUF.

[0209] Since the first outer coating FCL1 and the second outer coating FCL2 are arranged to overlap with the area where seams may be formed, moisture penetration into the display panel 110 can be prevented.

[0210] Referring to Figure 6 , the first outer coating FCL1 and the second outer coating FCL2 can be arranged to be spaced apart from each other. The third encapsulation layer PAS2 can be arranged between the first outer coating FCL1 overlapping with the dam portion DAM and the second outer coating FCL2 overlapping with the dam portion DAM. However, the first outer coating FCL1 and the second outer coating FCL2 can be integrally arranged.

[0211] The first outer coating FCL1 containing a fluorine-based component can protect seams that may appear in the outermost bank portion BANK_O, the planarization layer PLN, and the buffer layer BUF from external moisture.

[0212] The second outer coating FCL2 containing a fluorine-based component can protect seams that may appear in the buffer layer BUF from external moisture.

[0213] Referring to Figure 6 , the second encapsulation layer PCL1 can be arranged on the first encapsulation layer PAS1. The second encapsulation layer PCL1 can be an organic encapsulation layer.

[0214] Referring to Figure 6 , the third encapsulation layer PAS2 can be arranged on the second encapsulation layer PCL1. The third encapsulation layer PAS2 can be an inorganic encapsulation layer.

[0215] Referring to Figure 6 , the fourth encapsulation layer PCL2 can be arranged between the first outer coating FCL1 and the third encapsulation layer PAS2. The fourth encapsulation layer PCL2 can be an organic encapsulation layer.

[0216] The fourth encapsulation layer PCL2 can be arranged between the dam portion DAM and the outermost bank portion BANK_O.

[0217] The fourth encapsulation layer PCL2 can be arranged at a position spaced apart from the second encapsulation layer PCL1.

[0218] The fourth encapsulation layer PCL2 can be formed together with the second encapsulation layer PCL1.

[0219] Referring to Figure 6 , the height of the upper surface of the fourth encapsulation layer PCL2 can be higher than the height of the upper surface of the dam portion DAM.

[0220] The height of the upper surface of the fourth encapsulation layer PCL2 can be less than the height of the outermost bank portion BANK_O.

[0221] Since the fourth encapsulation layer PCL2 is set to be spaced apart from the second encapsulation layer PCL1, the length of the moisture penetration path for external moisture to reach the second encapsulation layer PCL1 can be increased. That is, since the fourth encapsulation layer PCL2 is set to be spaced apart from the second encapsulation layer PCL1, the moisture penetration reliability can be improved.

[0222] In addition, since the fourth encapsulation layer PCL2 is disposed between the dam portion DAM and the outermost bank portion BANK_O, the area where seams may be formed can be protected more robustly. Therefore, moisture penetration into the display panel 110 can be prevented.

[0223] The fourth encapsulation layer PCL2 can be disposed between the dam portion DAM and the outermost bank portion BANK_O and can be set to cover the first outer coating layer FCL1. This will be described with reference to Figure 7 to describe.

[0224] Figure 7 is a cross-sectional view of a dam portion area of the display device 100 according to an embodiment of the present disclosure.

[0225] Referring to Figure 7 , the anode AE can be disposed on the planarization layer PLN. For ease of explanation, the description of the configuration of the transistor electrically connected to the anode AE shown in Figure 7 is omitted. The cathode (not shown) can be disposed on the light-emitting layer EL.

[0226] Referring to Figure 7 , the fourth encapsulation layer PCL2 can be disposed between the dam portion DAM and the outermost bank portion BANK_O and can be set to cover the first outer coating layer FCL1.

[0227] The fourth encapsulation layer PCL2 can be disposed at a position spaced apart from the second encapsulation layer PCL1.

[0228] The fourth encapsulation layer PCL2 can be set to contact the first encapsulation layer PAS1 that overlaps the outermost bank portion BANK_O.

[0229] The fourth encapsulation layer PCL2 can be set to contact the first encapsulation layer PAS1 that overlaps the dam portion DAM.

[0230] Referring to Figure 7 , the third encapsulation layer PAS2 can be set to cover the second encapsulation layer PCL1, and the fifth encapsulation layer PAS3 can be set to cover the fourth encapsulation layer PCL2. The third encapsulation layer PAS2 and the fifth encapsulation layer PAS3 can be inorganic encapsulation layers.

[0231] The third encapsulation layer PAS2 and the fifth encapsulation layer PAS3 can be set to be spaced apart from each other.

[0232] Referring toFigure 7 The fifth encapsulation layer PAS3 can be set to contact the first encapsulation layer PAS1 that overlaps with the outermost bank BANK_O.

[0233] The fifth encapsulation layer PAS3 can be set to contact the first encapsulation layer PAS1 that overlaps with the dam DAM.

[0234] Refer to Figure 7 The fourth encapsulation layer PCL2 and the fifth encapsulation layer PAS3 can be set between the first outer coating FCL1 that overlaps with the dam DAM and the second outer coating FCL2 that overlaps with the dam DAM.

[0235] Refer to Figure 7 The fourth encapsulation layer PCL2 and the fifth encapsulation layer PAS3 can be set outside the display area. The fourth encapsulation layer PCL2 and the fifth encapsulation layer PAS3 can be arranged to surround the display area. The fourth encapsulation layer PCL2 and the fifth encapsulation layer PAS3 can be set outside at least three sides of the display area.

[0236] Figure 8 、 Figure 9 and Figure 10 are diagrams for explaining the process of forming the outer coating according to an embodiment of the present disclosure.

[0237] Refer to Figure 8 which shows the first substrate SUB1, the interlayer insulating film IPD, the second substrate SUB2, the buffer layer BUF, the planarization layer PLN, the light-emitting layer EL, the dam DAM, the anode AE, the bank BANK, the outermost bank BANK_O, and the first encapsulation layer PAS1.

[0238] Refer to Figure 9 The first outer coating FCL1 can be set on the first encapsulation layer PAS1 that overlaps with the outermost bank BANK_O.

[0239] Refer to Figure 9 The first outer coating FCL1 can be set on the first encapsulation layer PAS1 that overlaps with the dam DAM.

[0240] Refer to Figure 9 The first outer coating FCL1 can be set on the first encapsulation layer PAS1 that overlaps with the planarization layer PLN.

[0241] Refer to Figure 9 The first outer coating FCL1 can be set on the first encapsulation layer PAS1 that overlaps with the buffer layer BUF.

[0242] Refer to Figure 9 The second outer coating FCL2 can be set on the first encapsulation layer PAS1 that overlaps with the dam DAM.

[0243] Refer to Figure 9 , the second outer coating FCL2 can be disposed on the first encapsulation layer PAS1 that overlaps with the buffer layer BUF.

[0244] Refer to Figure 9 , the first outer coating FCL1 can be disposed inside the dam portion DAM, and the second outer coating FCL2 can be disposed outside the dam portion DAM.

[0245] Refer to Figure 10 , the second encapsulation layer PCL1 can be disposed on the first encapsulation layer PAS1.

[0246] Refer to Figure 10 , the second encapsulation layer PCL1 can be disposed to overlap with the light-emitting layer EL.

[0247] Refer to Figure 10 , the second encapsulation layer PCL1 can be disposed in the display area.

[0248] Refer to Figure 10 , the second encapsulation layer PCL1 can be disposed to overlap with the outermost bank portion BANK_O.

[0249] Refer to Figure 10 , the third encapsulation layer PAS2 can be disposed on the second encapsulation layer PCL1.

[0250] Refer to Figure 10 , the third encapsulation layer PAS2 can be arranged to overlap with the outermost bank portion BANK_O.

[0251] Refer to Figure 10 , the fourth encapsulation layer PCL2 can be disposed to cover the first outer coating FCL1.

[0252] Refer to Figure 10 , the fourth encapsulation layer PCL2 can be disposed to overlap with the outermost bank portion BANK_O.

[0253] Refer to Figure 10 , the fourth encapsulation layer PCL2 can be disposed to overlap with the dam portion DAM.

[0254] Refer to Figure 10 , the fourth encapsulation layer PCL2 can be disposed to be spaced apart from the second encapsulation layer PCL1.

[0255] Refer to Figure 10 , the fifth encapsulation layer PAS3 can be disposed on the fourth encapsulation layer PCL2.

[0256] Refer to Figure 10 , the fifth encapsulation layer PAS3 can be arranged to overlap with the outermost bank portion BANK_O.

[0257] Refer to Figure 10, the fifth encapsulation layer PAS3 can be arranged to overlap with the weir portion DAM.

[0258] Referring to Figure 10 , the fifth encapsulation layer PAS3 can be set to be spaced apart from the third encapsulation layer PAS2.

[0259] A display device includes: a substrate including a display area and a weir portion area as an external area of the display area; a planarization layer provided on the substrate; a weir portion provided on the substrate and in the weir portion area; a first encapsulation layer provided to cover the planarization layer and the weir portion; and a first outer coating provided on the first encapsulation layer and in the weir portion area.

[0260] Wherein, the first outer coating is provided outside the lower part of the planarization layer.

[0261] Wherein, the first outer coating is provided outside the inner lower part of the weir portion.

[0262] A display device further includes a bank portion provided between the first encapsulation layer and the planarization layer, wherein the first outer coating is provided outside the lower part of the bank portion.

[0263] A display device further includes a second outer coating provided outside the lower part of the weir portion.

[0264] Wherein, the first outer coating is provided inside the weir portion, and the second outer coating is provided outside the weir portion.

[0265] The display device further includes:

[0266] A second encapsulation layer provided on the first encapsulation layer, a third encapsulation layer provided on the second encapsulation layer, and a fourth encapsulation layer provided between the first encapsulation layer and the third encapsulation layer.

[0267] Wherein, the fourth encapsulation layer is provided to cover the first encapsulation layer.

[0268] A display device further includes a fifth encapsulation layer provided to cover the fourth encapsulation layer and being an inorganic encapsulation layer, wherein the third encapsulation layer is provided to cover the second encapsulation layer which is an organic encapsulation layer, and the third encapsulation layer is an inorganic encapsulation layer.

[0269] Wherein, the first outer coating contains a fluorine-based material.

[0270] The above description and the drawings only provide examples of the technical idea of the present disclosure for illustrative purposes. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, the disclosed embodiments are intended to illustrate the scope of the technical idea of the present disclosure. Therefore, the scope of the present disclosure is not limited to the illustrated embodiments.

Claims

1. A display device, comprising: substrate; a planarization layer, the planarization layer being disposed on the substrate; a dam portion, the dam portion being spaced apart from the planarization layer; a first encapsulation layer, the first encapsulation layer covering the dam portion; as well as A first outer coating layer is disposed on the first encapsulation layer and overlaps the dam portion.

2. The display device according to claim 1, further comprising: a bank portion, the bank portion being disposed on the planarization layer, the outermost bank portion of the bank portion being adjacent to an end portion of the planarization layer, the dam portion being spaced apart from the outermost bank portion, The first encapsulation layer covers the outermost bank, and the first outer coating layer overlaps the outermost bank.

3. The display device according to claim 2, further comprising: a buffer layer, the buffer layer being disposed on the substrate, the planarization layer and the dam portion being disposed on the buffer layer; A first electrode, disposed on the planarization layer; as well as A light-emitting layer is disposed on the bank and in contact with the first electrode, and the first encapsulation layer covers the light-emitting layer.

4. The display device according to claim 3, wherein: The first overcoat layer overlaps an outer surface of the outermost bank, one side of the planarization layer, an upper surface of the buffer layer, and an inner surface of the dam.

5. The display device according to claim 1, wherein: The substrate includes a display area and four frame areas surrounding the display area, and the dam portion and the first overcoat layer are disposed in at least three of the frame areas.

6. The display device according to claim 2, wherein: The height of the outermost bank is higher than the heights of other banks except the outermost bank.

7. The display device according to claim 3, wherein: A height of the first outer coating layer overlapping the outermost bank is higher than a height of the first outer coating layer overlapping the weir portion, and a height of the first outer coating layer overlapping the weir portion is higher than a height of the first outer coating layer overlapping the buffer layer.

8. The display device according to claim 3, further comprising: A second outer coating layer overlaps an upper surface of the buffer layer and an outer surface of the dam portion.

9. The display device according to claim 8, wherein: A height of the first outer coating layer overlapping the buffer layer is the same as a height of the second outer coating layer overlapping the buffer layer.

10. The display device according to claim 8, wherein: The first outer coating layer and the second outer coating layer are spaced apart from each other.

11. The display device according to claim 8, wherein: The first outer coating layer and the second outer coating layer include a fluorine-based component.

12. The display device according to claim 8, further comprising: a second encapsulation layer, the second encapsulation layer being disposed on the first encapsulation layer; as well as A third encapsulation layer is disposed on the second encapsulation layer.

13. The display device according to claim 12, wherein: The third encapsulation layer is disposed between the first outer coating layer overlapping the dam portion and the second outer coating layer overlapping the dam portion.

14. The display device according to claim 12, further comprising: A fourth encapsulation layer is provided between the dam portion and the outermost bank portion.

15. The display device according to claim 14, wherein: The fourth encapsulation layer is disposed between the first outer coating layer and the third encapsulation layer.

16. The display device according to claim 14, wherein: The fourth encapsulation layer is spaced apart from the second encapsulation layer.

17. The display device according to claim 14, wherein: The height of the upper surface of the fourth encapsulation layer is higher than the height of the upper surface of the dam portion.

18. The display device according to claim 14, wherein: The fourth encapsulation layer contacts the first encapsulation layer overlapping the outermost bank portion and the first encapsulation layer overlapping the dam portion.

19. The display device according to claim 14, further comprising: A fifth encapsulation layer is disposed on the fourth encapsulation layer.

20. The display device according to claim 19, wherein: The fifth encapsulation layer is spaced apart from the third encapsulation layer.

21. The display device according to claim 19, wherein: The fifth encapsulation layer contacts the first encapsulation layer overlapping the outermost bank portion and the first encapsulation layer overlapping the dam portion.

22. The display device according to claim 19, wherein: The fourth encapsulation layer and the fifth encapsulation layer are disposed between the first outer coating layer overlapping the dam portion and the second outer coating layer overlapping the dam portion.

23. The display device according to claim 2, wherein: The planarization layer, the outermost bank portion, and a lower portion of the dam portion are formed at a right angle to a layer stacking direction.

24. A display device comprising: A substrate, comprising a display area and a frame area arranged around the display area; a weir region, the weir region being disposed in the frame region and comprising a weir; a first encapsulation layer, the first encapsulation layer being disposed on the substrate and covering the dam region; as well as A first outer coating layer covers the first encapsulation layer and overlaps the dam portion.

Images