Capacitor, memory cell, memory array, memory, and electronic device

Abstract

The invention provides a capacitor, a storage unit, a storage array, a memory and electronic equipment. The capacitor comprises a first electrode, the first electrode comprises a first sub-electrode and a second sub-electrode, and the second sub-electrode surrounds the first sub-electrode and is connected with the side face of the first sub-electrode; the second electrode surrounds the first electrode, is opposite to the surface, facing the second sub-electrode and not covered by the second sub-electrode, of the first sub-electrode, and is opposite to at least one surface of the second sub-electrode; and the dielectric structure is positioned between the first electrode and the second electrode. The area utilization rate of the capacitor can be improved, the capacitance area of the capacitor is increased, and therefore higher capacitance capacity is achieved under the same integration level.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular, to a capacitor, a storage unit, a storage array, a memory, and an electronic device. Background Art

[0002] A dynamic random access memory (DRAM) generally includes a plurality of storage units. Each storage unit includes a capacitor and a switching transistor. The switching transistor is used for address selection, and the capacitor is used for storing data. When the capacitance area of the capacitor is larger, the stored charge quantity is larger, and the read window is also larger. Therefore, it is necessary for the capacitor to have a sufficiently large capacitance area.

[0003] However, in the related art, the utilization rate of the capacitance area of the capacitor is low. To obtain a larger capacitance area, it is necessary to increase the volume of the entire storage unit, which results in a reduction in integration. Summary of the Invention

[0004] To solve the above technical problems, the present application provides a capacitor, a storage unit, a storage array, a memory, and an electronic device, which can improve the area utilization rate of the capacitor, increase the capacitance area of the capacitor, and thus achieve a higher capacitance capacity under the same integration level.

[0005] In a first aspect of the present application, a capacitor is provided, including: a first electrode, a second electrode, and a dielectric structure. The first electrode includes a first sub-electrode and a second sub-electrode. The second sub-electrode surrounds the first sub-electrode and is connected to the side surface of the first sub-electrode. The first sub-electrode is arranged along the thickness direction of the capacitor, and there is an included angle between the arrangement direction of the first sub-electrode and the arrangement direction of the second sub-electrode. Exemplarily, the arrangement direction of the second sub-electrode can be perpendicular to the thickness direction. The second electrode surrounds the first electrode, and is opposite to the surface of the first sub-electrode facing the second sub-electrode and not covered by the second sub-electrode, and is opposite to at least one surface of the second sub-electrode. The dielectric structure is located between the first electrode and the second electrode. Exemplarily, a part of the dielectric structure is located between the surface of the first sub-electrode facing the second sub-electrode and not covered by the second sub-electrode and the second electrode, and a part of the dielectric structure is also located between at least one surface of the second sub-electrode and the second electrode.

[0006] In the present application, the first sub-electrode is disposed along the thickness direction of the capacitor, the second sub-electrode surrounds the first sub-electrode, and the second electrode is opposite to the surface of the first sub-electrode that faces the second sub-electrode and is not covered by the second sub-electrode. Therefore, the second electrode can be opposite to the surface of the first sub-electrode along the thickness direction and not covered by the second sub-electrode. A part of the dielectric structure is located between the second electrode and the surface of the first sub-electrode along the thickness direction. Thus, a part of the capacitance can be formed between the second electrode and the surface of the first sub-electrode along the thickness direction and not covered by the second sub-electrode. Therefore, the capacitance area includes the surface area of the second electrode opposite to the first sub-electrode. In addition, the second electrode can also be opposite to at least one surface of the second sub-electrode, and a part of the dielectric structure is located between at least one surface of the second sub-electrode and the second electrode. Therefore, a part of the capacitance can also be formed between the second electrode and the second sub-electrode, and the capacitance area also includes the surface area of the second sub-electrode opposite to the second electrode. It can be seen that the present application can make full use of the surface areas of the first sub-electrode and the second sub-electrode, thereby improving the area utilization rate, increasing the capacitance area of the capacitor, and further achieving a higher capacitance capacity under the same integration degree.

[0007] In some embodiments, the first electrode includes at least two second sub-electrodes that are stacked and spaced apart, the second electrode includes a third sub-electrode, and the third sub-electrode is located between two adjacent second sub-electrodes; the dielectric structure includes a first dielectric part and at least two second dielectric parts that are stacked and spaced apart, the first dielectric part is located between the first sub-electrode and the third sub-electrode, and at least a part of the second dielectric parts is located between the second sub-electrode and the third sub-electrode. In this way, a part of the capacitance can be formed between the first sub-electrode and the third sub-electrode, and a part of the capacitance can be formed between each second sub-electrode and the third sub-electrode. That is to say, the capacitance area includes the surface area of the first sub-electrode opposite to the third sub-electrode and the surface area of each second sub-electrode opposite to the third sub-electrode. Thus, the capacitance area can be increased, and the area utilization rate can be further improved.

[0008] In a possible implementation, the second electrode includes at least two third sub-electrodes that are stacked and spaced apart. The top surface of the first sub-electrode is higher than the top surface of the second sub-electrode. Part of the third sub-electrodes are located between two adjacent second sub-electrodes, and part of the third sub-electrodes are opposite to the part of the first sub-electrode that is higher than the second sub-electrode. In this way, a part of the capacitance can be formed respectively between the third sub-electrode and the part of the first sub-electrode that is higher than the second sub-electrode, between the top surface of the second sub-electrode located at the top layer and the third sub-electrode, between the surface of each second sub-electrode facing other second sub-electrodes and the third sub-electrode, and between the first sub-electrode and the third sub-electrode located between two adjacent second sub-electrodes. That is to say, the capacitance area includes the surface area where the third sub-electrode is opposite to the part of the first sub-electrode that is higher than the second sub-electrode, the surface area where each second sub-electrode is opposite to the third sub-electrode, and the surface area where the first sub-electrode and the third sub-electrode are opposite to each other between two adjacent second sub-electrodes, thereby further improving the area utilization rate.

[0009] Moreover, the bottom surface of the first sub-electrode is lower than the bottom surface of the second sub-electrode, and part of the third sub-electrodes are opposite to the part of the first sub-electrode that is lower than the second sub-electrode. In this way, a part of the capacitance can be formed between the bottom surface of the second sub-electrode located at the bottom layer and the third sub-electrode, and between the part of the first sub-electrode that is lower than the second sub-electrode and the third sub-electrode. That is to say, the capacitance area also includes the surface area where the side of the second sub-electrode located at the bottom layer facing away from other second sub-electrodes is opposite to the third sub-electrode, and the surface area where the part of the first sub-electrode that is lower than the second sub-electrode is opposite to the third sub-electrode, thereby further improving the area utilization rate.

[0010] In another possible implementation, the second electrode includes at least two third sub-electrodes that are stacked and spaced apart, and a third sub-electrode is provided between every two adjacent second sub-electrodes. In this way, a part of the capacitance can be formed respectively between each second sub-electrode and the third sub-electrode, and between the third sub-electrode and the first sub-electrode located between two adjacent second sub-electrodes. That is to say, the capacitance area includes the surface area where each second sub-electrode is opposite to the third sub-electrode, and the surface area where the first sub-electrode and the third sub-electrode are opposite to each other between two adjacent second sub-electrodes, thereby further improving the area utilization rate.

[0011] Based on this, the second electrode further includes a fourth sub-electrode located on the side of the second sub-electrode facing away from the first sub-electrode; the dielectric structure further includes a third dielectric part located between the second sub-electrode and the fourth sub-electrode. Each third sub-electrode can be connected to the fourth sub-electrode. In this way, a part of the capacitance can be formed respectively between the fourth sub-electrode and each second sub-electrode. That is to say, the capacitance area includes the surface area where each second sub-electrode is opposite to the fourth sub-electrode, thereby further improving the area utilization rate.

[0012] In some embodiments, the first electrode further includes a fifth sub-electrode connected to a side of the second sub-electrode facing away from the first sub-electrode, and the third sub-electrode is also located between the first sub-electrode and the fifth sub-electrode; the dielectric structure further includes a fourth dielectric portion located between the fifth sub-electrode and the third sub-electrode. In this way, a part of the capacitance can also be formed between the fifth sub-electrode and the third sub-electrode, that is to say, the capacitance area also includes the surface area of the fifth sub-electrode and the third sub-electrode facing each other, thereby further improving the area utilization rate.

[0013] Moreover, the fifth sub-electrode is connected to two adjacent second sub-electrodes, and an accommodation space is formed by enclosing between the two adjacent second sub-electrodes, the first sub-electrode and the fifth sub-electrode, and the third sub-electrode is located in the accommodation space. In this way, the dimension of the fifth sub-electrode in the thickness direction is at least the same as the dimension of the first sub-electrode located between the two adjacent second sub-electrodes in the thickness direction, thereby increasing the dimension of the fifth sub-electrode in the thickness direction, and further increasing the capacitance area.

[0014] Based on this, the second electrode further includes a sixth sub-electrode located on a side of the fifth sub-electrode facing away from the first sub-electrode; the dielectric structure further includes a fifth dielectric portion located between the fifth sub-electrode and the sixth sub-electrode. In this way, a part of the capacitance can also be formed between the sixth sub-electrode and the fifth sub-electrode, that is to say, the capacitance area also includes the surface area of the sixth sub-electrode and the fifth sub-electrode facing each other, thereby further increasing the area utilization rate.

[0015] Further, the dimension of the fifth dielectric portion in the thickness direction and the dimension of the fifth sub-electrode in the thickness direction are both the same as the dimension of the first sub-electrode in the thickness direction. In this way, the dimension of the fifth sub-electrode in the thickness direction is larger, thereby increasing the size of the capacitance area formed between the fifth sub-electrode and the third sub-electrode.

[0016] In the second aspect of the present application, a storage unit is further provided, including a switching transistor and the capacitor according to any one of the above embodiments, and the switching transistor is electrically connected to the capacitor. The storage unit can achieve all the effects of the capacitor.

[0017] In some embodiments, the first sub-electrode of the capacitor surrounds the switching transistor; the switching transistor includes a channel and at least two stacked and spaced first electrodes, a part of the channel is located between the two first electrodes in the thickness direction, and the channel is connected to the first sub-electrode. In this way, the first sub-electrode can be used as the drain of the switching transistor.

[0018] Further, a part of the first sub-electrode and a part of at least one third sub-electrode are arranged on the same layer as the first electrode. In this way, the area outside the first electrode can also be fully utilized to form a capacitance, thereby further improving the area utilization rate.

[0019] In a third aspect of the present application, a storage array is further provided, which includes a plurality of the above-mentioned storage units arranged in an array. The storage array can achieve all the effects of the storage units.

[0020] In some embodiments, the storage array includes multiple layers of storage units, and each layer of storage units includes a plurality of storage units arranged in an array. The storage array includes word lines, bit lines, and plate lines. The word lines are connected to the first pole of the switching transistors, the bit lines are located inside the switching transistors and penetrate from the top to the bottom of the storage units, and the plate lines are connected to the second electrodes of the capacitors. Each of the storage units stacked in the thickness direction shares the bit lines, multiple storage units arranged in the width direction of the storage array share the word lines, and multiple storage units arranged in the length direction of the storage array share the plate lines.

[0021] In a fourth aspect of the present application, a memory is further provided, which includes a controller and the above-mentioned storage array, and the controller is electrically connected to the storage array. The memory can achieve all the effects of the storage array.

[0022] In a fifth aspect of the present application, an electronic device is further provided, which includes a circuit board and the above-mentioned memory, and the circuit board is electrically connected to the memory. The electronic device can achieve all the effects of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0024] Figure 1 It is a schematic structural diagram of a storage unit in the first embodiment of the present application;

[0025] Figure 2 It is Figure 1 a cross-sectional view taken along the A-A direction in

[0026] Figure 3 It is a schematic structural diagram of a storage unit in the second embodiment of the present application;

[0027] Figure 4 It is a storage array including Figure 3 the storage unit shown in

[0028] Figure 5 It is a schematic structural diagram of a storage unit in the third embodiment of the present application;

[0029] Figure 6 It is a storage array including Figure 5Schematic structural diagram of the memory array of the memory cell shown

[0030] Figure 7 Schematic structural diagram of the memory cell in the fourth embodiment of the present application

[0031] Figure 8 Schematic structural diagram of the memory cell in the fifth embodiment of the present application

[0032] Figure 9 Schematic structural diagram of the memory cell in the sixth embodiment of the present application

[0033] Icon: 1 - Memory array; 100 - Memory cell; 200 - Word line; 300 - Bit line; 400 - Plate line; 10 - Capacitor; 11 - First electrode; 111 - First sub - electrode; 112 - Second sub - electrode; 113 - Fifth sub - electrode; 12 - Second electrode; 121 - Third sub - electrode; 122 - Fourth sub - electrode; 123 - Sixth sub - electrode; 13 - Dielectric structure; 131 - First dielectric part; 132 - Second dielectric part; 133 - Third dielectric part; 134 - Fourth dielectric part; 135 - Fifth dielectric part; 136 - Sixth dielectric part; 20 - Switching transistor; 21 - Metal column; 22 - Source electrode; 23 - Channel; 24 - First pole; 25 - Dielectric layer; 26 - Gate dielectric layer; 30 - Insulating dielectric layer Detailed implementation manners

[0034] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application

[0035] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Here, A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" means one or more, and "multiple" means two or more. "At least one (piece) of the following" or its similar expression means any combination of these items, including any combination of single item (piece) or plural items (pieces). For example, at least one (piece) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple

[0036] In the description of the embodiments of this application, the terms "first", "second", etc. in the specification and claims are used to distinguish different objects, rather than to describe a specific order of the objects. For example, the first target object, the second target object, etc. are used to distinguish different target objects, rather than to describe a specific order of the target objects.

[0037] Words such as "connected" and "linked" are used to express the interconnection or interaction between different components, and may include direct connection or indirect connection through other components. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a method, system, product, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices. The terms "upper", "lower", "left", "right", etc. are only relative to the orientation of the components in the drawings. These directional terms are relative concepts, and they are used for relative description and clarification, and they can change accordingly with the change of the orientation of the components placed in the drawings.

[0038] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0039] In the description of the embodiments of this application, unless otherwise specified, the meaning of "a plurality" refers to two or more. For example, a plurality of processing units refers to two or more processing units; a plurality of systems refers to two or more systems.

[0040] For convenience of description, three directions can be defined, namely the first direction (X direction), which represents the length direction of the memory; the second direction (Y direction), which represents the width direction of the memory; and the third direction (Z direction), which represents the height direction of the memory. The X direction, Y direction, and Z direction are perpendicular to each other pairwise.

[0041] Currently, most electronic devices are equipped with a circuit board and a memory, and the circuit board is electrically connected to the memory. The memory can be used to perform write or read operations. When the memory performs a write operation, data can be stored; when the memory performs a read operation, the data stored in the memory can be read. The electronic device can be a mobile phone, a tablet computer, a wearable device, an augmented reality (AR) device, a laptop computer, a personal digital assistant (PDA), etc. The memory can be a ferroelectric random access memory (FeRAM), or a DRAM.

[0042] The memory can include a controller and a storage array, and the controller is electrically connected to the storage array. The controller can be used to send instructions to the storage array so that the storage array performs write or read operations according to the instructions. The storage array can include a plurality of storage cells. The plurality of storage cells are arranged in an array. The plurality of storage cells can be arranged in one layer or multiple layers.

[0043] The storage cell can be of a 1T1C structure. Specifically, the storage cell can include a capacitor and a switching transistor. The switching transistor is used for address selection, and the capacitor is used for storing data. When the capacitance area of the capacitor is larger, the stored charge amount is larger, and the read window is also larger. Therefore, it is necessary for the capacitor to have a sufficiently large capacitance area.

[0044] However, in the related art, the utilization rate of the capacitance area of the capacitor is low. To obtain a larger capacitance area, it is necessary to increase the volume of the entire storage cell, resulting in a decrease in integration.

[0045] Based on this, as Figure 1 shown, an embodiment of the present application provides a storage cell 100, and the storage cell 100 includes a capacitor 10, an insulating dielectric layer 30, and a switching transistor 20.

[0046] For the convenience of describing the storage cell 100 of this embodiment, three directions are first defined, which are the X direction, the Y direction, and the Z direction respectively. Among them, the X direction represents the length direction of the storage cell 100, the Y direction represents the width direction of the storage cell 100, and the Z direction represents the thickness direction of the storage cell 100. And, the X direction, the Y direction, and the Z direction are perpendicular to each other pairwise.

[0047] The switching transistor 20 can be a transistor, specifically a single-gate transistor or a double-gate transistor. This embodiment will be described by taking the double-gate transistor as an example.

[0048] As Figure 1As shown, the switching transistor 20 includes a metal column 21, a source electrode 22, a channel 23, two first electrodes 24, a dielectric layer 25, and a gate dielectric layer 26. The metal column 21 is arranged along the Z direction. The source electrode 22 is arranged along the Z direction and surrounds the metal column 21. The channel 23 surrounds the source electrode 22, and the channel 23 is located at the middle position of the source electrode 22 along the Z direction. Exemplarily, the bottom surface of the channel 23 is higher than the bottom surface of the source electrode 22, and the top surface of the channel 23 is lower than the top surface of the source electrode 22. The inside of the channel 23 is filled with the dielectric layer 25.

[0049] In this embodiment, as Figure 1 shown, one of the two first electrodes 24 is located below the channel 23 and surrounds the source electrode 22. That is, this first electrode 24 corresponds to the part of the source electrode 22 that is lower than the channel 23. The other first electrode 24 is located above the channel 23 and surrounds the source electrode 22. That is, this first electrode 24 corresponds to the part of the source electrode 22 that is higher than the channel 23.

[0050] As Figure 1 shown, the number of the gate dielectric layers 26 can be two, and the two gate dielectric layers 26 respectively wrap the two first electrodes 24. And, the top surface of the top gate dielectric layer 26 is lower than the top surface of the source electrode 22. The bottom surface of the bottom gate dielectric layer 26 is higher than the bottom surface of the channel 23.

[0051] Both of the two first electrodes 24 can be gates. The material of the dielectric layer 25 can include SiO x or SiN x and other materials and their dopants. Wherein, x is greater than 0 and less than or equal to 10.

[0052] As Figure 1 shown, the number of the insulating dielectric layers 30 is two, and the two insulating dielectric layers 30 are stacked and arranged at intervals. The bottom insulating dielectric layer 30 is located below the bottom gate dielectric layer 26, that is, this insulating dielectric layer 30 surrounds the part of the source electrode 22 that is lower than the bottom gate dielectric layer 26. And, the bottom surface of this insulating dielectric layer 30 is flush with the bottom surface of the source electrode 22. The top insulating dielectric layer 30 is located above the top gate dielectric layer 26, that is, this insulating dielectric layer 30 surrounds the part of the source electrode 22 that is higher than the top gate dielectric layer 26. And, the top surface of this insulating dielectric layer 30 is flush with the top surface of the source electrode 22.

[0053] As Figure 2 shown, the capacitor 10 is arranged to surround the switching transistor 20. As Figure 1 shown, the capacitor 10 can include: a first electrode 11, a second electrode 12, and a dielectric structure 13.

[0054] As Figure 1As shown, the first electrode 11 may include a first sub - electrode 111, a second sub - electrode 112, and a fifth sub - electrode 113. Among them, the first sub - electrode 111 may be arranged along the Z - direction. It can be understood that the first sub - electrode 111 being arranged along the Z - direction means that the dimension of the first sub - electrode 111 along the Z - direction is greater than the thicknesses of the first sub - electrode 111 along the X - direction and the Y - direction.

[0055] As Figure 2 shown, the first sub - electrode 111 surrounds the switching transistor 20. As Figure 1 shown, the dimension of the first sub - electrode 111 along the Z - direction may be the same as the distance between the top surface and the bottom surface of the dielectric layer 25. The first sub - electrode 111 is in contact with the channel 23. In this way, the first sub - electrode 111 can serve as the drain of the switching transistor 20.

[0056] There is an included angle between the setting direction of the second sub - electrode 112 and the setting direction of the first sub - electrode 111. Exemplarily, the setting direction of the second sub - electrode 112 may be perpendicular to the Z - direction, that is, the second sub - electrode 112 may be arranged along the X - direction and / or the Y - direction. It can be understood that the second sub - electrode 112 being arranged along the X - direction means that the dimension of the second sub - electrode 112 along the X - direction is greater than the dimension along the Z - direction.

[0057] In this embodiment, as Figure 1 shown, the number of the second sub - electrodes 112 may be two. The two second sub - electrodes 112 are stacked and arranged at intervals. The two second sub - electrodes 112 both surround the first sub - electrode 111 and are connected to the first sub - electrode 111. Exemplarily, the two second sub - electrodes 112 are both arranged outside the first sub - electrode 111 and are in contact with the first sub - electrode 111. In other embodiments, the number of the second sub - electrodes 112 may also be greater than two. Exemplarily, the number of the second sub - electrodes 112 is three, four, or more.

[0058] In this embodiment, as Figure 1 shown, the bottom surface of the first sub - electrode 111 is lower than the bottom surface of the bottom - layer second sub - electrode 112 and is in contact with the bottom - layer insulating dielectric layer 30. The top surface of the first sub - electrode 111 is higher than the top surface of the top - layer second sub - electrode 112 and is in contact with the top - layer insulating dielectric layer 30. In other embodiments, as Figure 3 shown, the two second sub - electrodes 112 may be located at both ends of the first sub - electrode 111. Exemplarily, the bottom surface of one of the second sub - electrodes 112 is flush with the bottom surface of the first sub - electrode 111, and the top surface of the other second sub - electrode 112 is flush with the bottom surface of the first sub - electrode 111.

[0059] The fifth sub - electrode 113 surrounds and is connected to the side of the second sub - electrode 112 facing away from the first sub - electrode 111. In one example, as Figure 1As shown, the fifth sub-electrode 113 is connected to both second sub-electrodes 112, and the top surface of the fifth sub-electrode 113 is flush with the top surface of the second sub-electrode 112 of the top layer, and the bottom surface of the fifth sub-electrode 113 is flush with the bottom surface of the second sub-electrode 112 of the bottom layer. In this way, the fifth sub-electrode 113, the two second sub-electrodes 112 and the first sub-electrode 111 are all connected to form the first electrode 11. Moreover, the fifth sub-electrode 113, the two second sub-electrodes 112 and the first sub-electrode 111 can be surrounded to form a receiving space. In another example, the fifth sub-electrode 113 is connected to one of the second sub-electrodes 112, and is not connected to the other second sub-electrode 112.

[0060] like Figure 1 As shown, the second electrode 12 is disposed around the first electrode 11, and the dielectric structure 13 is located between the first electrode 11 and the second electrode 12. The second electrode 12 includes a third sub-electrode 121 and a sixth sub-electrode 123.

[0061] Among them, Figure 1 As shown, in this embodiment, the number of the third sub-electrodes 121 can be three, and the three third sub-electrodes 121 are stacked and arranged at intervals. The third sub-electrode 121 of the bottom layer is located below the second sub-electrode 112 of the bottom layer, that is, the third sub-electrode 121 corresponds to the first sub-electrode 111 lower than the second sub-electrode 112. In other embodiments, the number of the third sub-electrodes 121 can be two or four, etc.

[0062] The third sub-electrode 121 of the top layer is located above the second sub-electrode 112 of the top layer, that is, the third sub-electrode 121 corresponds to the first sub-electrode 111 which is higher than the second sub-electrode 112. The third sub-electrode 121 in the middle position is located in the accommodation space formed by the fifth sub-electrode 113, the two second sub-electrodes 112 and the first sub-electrode 111.

[0063] like Figure 1 As shown, the sixth sub-electrode 123 is located on the side of the fifth sub-electrode 113 away from the first sub-electrode 111, and the sixth sub-electrode 123 surrounds the fifth sub-electrode 113. Both sides of the sixth sub-electrode 123 are respectively connected to the third sub-electrodes 121 on the top and bottom layers to form the second electrode 12.

[0064] like Figure 1 As shown, the dielectric structure 13 may include a first dielectric portion 131 , a second dielectric portion 132 , a fourth dielectric portion 134 , a fifth dielectric portion 135 and a sixth dielectric portion 136 .

[0065] The first dielectric portion 131 is located between the first sub-electrode 111 and the third sub-electrode 121. Figure 1As shown, the surface of the first sub-electrode 111 facing the second sub-electrode 112 is separated into three regions by two second sub-electrodes 112, and the number of the third sub-electrodes 121 is also three. Therefore, correspondingly, the number of the first dielectric parts 131 is three, and each first dielectric part 131 is respectively located between each region of the first sub-electrode 111 and each third sub-electrode 121. Specifically, one of the first dielectric parts 131 is located between the part of the first sub-electrode 111 lower than the second sub-electrode 112 and the bottom third sub-electrode 121, whereby a part of the capacitance can be formed; the first dielectric part 131 at the middle position is located between the first sub-electrode 111 and the middle third sub-electrode 121, whereby a part of the capacitance can be formed; the first dielectric part 131 is located between the part of the first sub-electrode 111 higher than the second sub-electrode 112 and the top third sub-electrode 121, whereby a part of the capacitance can be formed. It can be seen that the first dielectric part 131, the first sub-electrode 111 and the third sub-electrode 121 can provide three parts of capacitance area for the capacitor 10. That is to say, the capacitance area also includes the surface area of the first sub-electrode 111 opposite to the third sub-electrode 121.

[0066] The second dielectric part 132 can be located between the second sub-electrode 112 and the third sub-electrode 121. As Figure 1 shown, the capacitor 10 includes two second sub-electrodes 112, and second dielectric parts 132 are provided between the two opposite surfaces of each second sub-electrode 112 and the third sub-electrode 121. That is to say, the number of the second dielectric parts 132 can be four. One of the second dielectric parts 132 is located between the top surface of the bottom third sub-electrode 121 and the bottom surface of the bottom second sub-electrode 112, whereby a part of the capacitance can be formed; one of the second dielectric parts 132 is located between the top surface of the bottom second sub-electrode 112 and the bottom surface of the middle third sub-electrode 121, whereby a part of the capacitance can be formed; one of the second dielectric parts 132 is located between the bottom surface of the top second sub-electrode 112 and the top surface of the middle third sub-electrode 121, whereby a part of the capacitance can be formed; the last second dielectric part 132 is located between the top surface of the top second sub-electrode 112 and the bottom surface of the top third sub-electrode 121, whereby a part of the capacitance can be formed. It can be seen that the second dielectric part 132, the second sub-electrode 112 and the third sub-electrode 121 can provide four parts of capacitance area for the capacitor 10. That is to say, the capacitance area of the capacitor 10 also includes the surface areas of the two opposite surfaces of each second sub-electrode 112 opposite to the corresponding third sub-electrode 121.

[0067] As Figure 1As shown, the fourth dielectric portion 134 is located between the fifth sub-electrode 113 and the third sub-electrode 121. In this way, a part of the capacitance can also be formed between the fifth sub-electrode 113, the fourth dielectric portion 134 and the third sub-electrode 121. It can be seen that the fifth sub-electrode 113, the fourth dielectric portion 134 and the third sub-electrode 121 can provide a part of the capacitance area for the capacitor 10. That is to say, the capacitance area also includes the surface area of the fifth sub-electrode 113 opposite to the third sub-electrode 121, thereby further improving the area utilization rate.

[0068] Moreover, the fifth sub-electrode 113 is connected to two adjacent second sub-electrodes 112, and an accommodation space is formed by enclosing between the two adjacent second sub-electrodes 112, the first sub-electrode 111 and the fifth sub-electrode 113, and the third sub-electrode 121 is located in the accommodation space. In this way, the dimension of the fifth sub-electrode 113 in the thickness direction is at least the same as the dimension of the first sub-electrode 111 in the thickness direction located between the two adjacent second sub-electrodes 112, thereby increasing the dimension of the fifth sub-electrode 113 in the thickness direction, and further increasing the capacitance area.

[0069] As Figure 1 shown, the fifth dielectric portion 135 is located between the fifth sub-electrode 113 and the sixth sub-electrode 123. In this way, a part of the capacitance can also be formed between the sixth sub-electrode 123, the fifth dielectric portion 135 and the fifth sub-electrode 113. It can be seen that the fifth dielectric portion 135, the fifth sub-electrode 113 and the sixth sub-electrode 123 can provide a part of the capacitance area for the capacitor 10. That is to say, the capacitance area also includes the surface area of the sixth sub-electrode 123 opposite to the fifth sub-electrode 113, thereby further increasing the area utilization rate. It can be seen that the present application can make full use of the surface areas of the first sub-electrode 111 and the second sub-electrode 112, thereby improving the area utilization rate, increasing the capacitance area of the capacitor 10, and further realizing a higher capacitance capacity under the same integration degree.

[0070] As Figure 1 shown, the sixth dielectric portion 136 can be located between the third sub-electrode 121 and the insulating dielectric layer 30. Exemplarily, the number of the sixth dielectric portions 136 is two, and the two sixth dielectric portions 136 are stacked and spaced apart. The top sixth dielectric portion 136 is located between the top insulating dielectric layer 30 and the top third sub-electrode 121, and the bottom sixth dielectric portion 136 is located between the bottom insulating dielectric layer 30 and the bottom third sub-electrode 121.

[0071] The material of the dielectric structure 13 may include ZrO x , HfO x , ZrHfO x , ZrAlO x or AlO xMaterials such as and their dopants or laminated combinations. Among them, x is greater than 0 and less than or equal to 10.

[0072] Such as Figure 1 As shown, a part of the first sub-electrode 111 and a part of at least one third sub-electrode 121 are arranged on the same layer as the first pole 24. Exemplarily, the part of the first sub-electrode 111 below the second sub-electrode 112 surrounds the first pole 24 at the bottom layer, and the part of the first sub-electrode 111 above the second sub-electrode 112 surrounds the second pole 112 at the top layer. The part of the third sub-electrode 121 at the bottom layer is arranged on the same layer as the first pole 24 at the bottom layer, that is, the third sub-electrode 121 at the bottom layer surrounds the first pole 24 at the bottom layer; the part of the third sub-electrode 121 at the top layer is arranged on the same layer as the first pole 24 at the top layer, that is, the third sub-electrode 121 at the top layer surrounds the first pole 24 at the top layer. In this way, the area outside the first pole 24 can also be fully utilized to form partial capacitance, thereby further improving the area utilization rate.

[0073] For the structure of the storage array 1, in one example, such as Figure 4 As shown, the storage array 1 includes two layers of storage cells 100, and each layer of storage cells 100 includes a plurality of storage cells 100 arranged in an array. The storage array 1 includes word lines 200 (word line, WL), bit lines 300 (bit line, BL), and plate lines 400 (plate line, PL). The word lines 200 are connected to the first poles 24 of the switching transistors 20, the metal pillars 21 serve as the bit lines 300, and penetrate from the top surface to the bottom surface of the storage cells 100. The plate lines 400 are connected to the second electrodes 12 of the capacitors 10. Each storage cell 100 stacked in the thickness direction shares the bit line 300, a plurality of storage cells 100 arranged in the width direction of the storage array 1 share the word line 200, and a plurality of storage cells 100 arranged in the length direction of the storage array 1 share the plate line 400. In other examples, the storage array 1 may include one layer of storage cells 100, or three layers of storage cells 100, etc.

[0074] In other embodiments of the present application, the difference from the Figure 1 shown embodiment lies in the number of the second sub-electrodes 112, the number of the second dielectric parts 132, the number of the fourth dielectric parts 134, the dimension of the fifth sub-electrode 113 in the Z direction, the dimension of the sixth sub-electrode 123 in the Z direction, and the dimension of the fifth dielectric part 135 in the Z direction.

[0075] Specifically, in this embodiment, such as Figure 5 As shown, the number of the second sub-electrodes 112 is four. The four second sub-electrodes 112 are stacked and arranged at intervals. The second sub-electrode 112 at the top layer is in contact with the insulating dielectric layer 30 at the top layer, and the second sub-electrode 112 at the bottom layer is in contact with the insulating dielectric layer 30 at the bottom layer.

[0076] The number of the second dielectric portions 132 is six, and the six second dielectric portions 132 are stacked and arranged at intervals. The arrangement positions of the four second dielectric portions 132 at the middle position are the same as those in the Figure 1 illustrated embodiment, and will not be described herein again. The second dielectric portion 132 at the top layer is located between the top surface of the third sub-electrode 121 at the top layer and the bottom surface of the second sub-electrode 112 at the top layer, whereby a part of the capacitance can be formed. The second dielectric portion 132 at the bottom layer is located between the bottom surface of the third sub-electrode 121 at the bottom layer and the top surface of the second sub-electrode 112 at the bottom layer, whereby a part of the capacitance can be formed. That is to say, the capacitance area of the capacitor 10 further includes the opposite surfaces of the third sub-electrode 121 at the top layer and the second sub-electrode 112 at the top layer, and the opposite surfaces of the third sub-electrode 121 at the bottom layer and the second sub-electrode 112 at the bottom layer.

[0077] As Figure 5 illustrated, the dimension of the fifth sub-electrode 113 in the Z direction is the same as the dimension of the first sub-electrode 111 in the Z direction. In this way, three accommodation spaces can be formed between the fifth sub-electrode 113, the first sub-electrode 111 and the four second sub-electrodes 112. Correspondingly, the number of the fourth dielectric portions 134 can also be three, and each fourth dielectric is respectively located in each accommodation space and between each third sub-electrode 121 and the fifth sub-electrode 113. Thus, the dimension of the fifth sub-electrode 113 in the thickness direction is larger, and further the capacitance area formed between the fifth sub-electrode 113 and the third sub-electrode 121 can be increased.

[0078] As Figure 5 illustrated, the dimension of the sixth sub-electrode 123 in the Z direction is the difference between the dimension of the fifth sub-electrode 113 in the Z direction and the sum of the dimensions of the two sixth dielectric portions 136 in the Z direction. That is to say, the top surface of the sixth sub-electrode 123 contacts the sixth dielectric portion 136 at the top layer, and the bottom surface of the sixth sub-electrode 123 contacts the sixth dielectric portion 136 at the bottom layer. Correspondingly, the dimension of the fifth dielectric portion 135 in the Z direction can be the same as the dimension of the fifth sub-electrode 113 in the Z direction, whereby the capacitance area of the capacitance formed among the fifth sub-electrode 113, the fifth dielectric portion 135 and the sixth sub-electrode 123 can be increased.

[0079] As Figure 6 illustrated, the memory array 1 may include two layers of memory cells 100, and each layer of memory cells 100 may include a plurality of memory cells 100 arranged in an array.

[0080] In other embodiments of the present application, the difference from the Figure 1 illustrated embodiment lies in the number of the second sub-electrodes 112 and the number of the second dielectric portions 132. Specifically, as Figure 7As shown, the number of the second sub - electrodes 112 is four. The four second sub - electrodes 112 are stacked and spaced apart. The top - layer second sub - electrode 112 is in contact with the top - layer insulating dielectric layer 30, and the bottom - layer second sub - electrode 112 is in contact with the bottom - layer insulating dielectric layer 30. Correspondingly, the number of the second dielectric parts 132 is six. The six second dielectric parts 132 are stacked and spaced apart. The settings of the four second dielectric parts 132 at the middle position are the same as those in the Figure 1 embodiment shown, which will not be elaborated here. The top - layer second dielectric part 132 is located between the top surface of the top - layer third sub - electrode 121 and the bottom surface of the top - layer second sub - electrode 112, whereby a part of the capacitance can be formed. The bottom - layer second dielectric part 132 is located between the bottom surface of the bottom - layer third sub - electrode 121 and the top surface of the bottom - layer second sub - electrode 112, whereby a part of the capacitance can be formed. That is to say, the capacitance area of the capacitor 10 also includes the opposite surfaces of the top - layer third sub - electrode 121 and the top - layer second sub - electrode 112, and the opposite surfaces of the bottom - layer third sub - electrode 121 and the bottom - layer second sub - electrode 112.

[0081] In other embodiments of the present application, the difference from the Figure 7 embodiment shown is that, on the basis of the Figure 7 embodiment shown, the sixth sub - electrode 123, the fifth sub - electrode 113, the fourth dielectric part 134 and the fifth dielectric part 135 are removed, and the fourth sub - electrode 122 and the third dielectric part 133 are added. That is to say, in this embodiment, as Figure 8 shown, the first electrode 11 includes the first sub - electrode 111 and the second sub - electrode 112. The second electrode 12 includes the third sub - electrode 121 and the fourth sub - electrode 122. The dielectric structure 13 includes the first dielectric part 131, the second dielectric part 132, the third dielectric part 133 and the sixth dielectric part 136.

[0082] As Figure 8 shown, the fourth sub - electrode 122 is located on the side of the second sub - electrode 112 away from the first sub - electrode 111. Each third sub - electrode 121 can be connected to the fourth sub - electrode 122. The number of the third dielectric parts 133 is two, and one of the third dielectric parts 133 is located between the third second sub - electrode 112 along the Z - direction and the fourth sub - electrode 122, and the other third dielectric part 133 is located between the second second sub - electrode 112 along the Z - direction and the fourth sub - electrode 122. Thus, a part of the capacitance can be formed between the two third dielectric parts 133, the two second sub - electrodes 112 and the fourth sub - electrode 122 respectively. The capacitance area includes the surface area of each second sub - electrode 112 opposite to the fourth sub - electrode 122, thereby further improving the area utilization rate.

[0083] It can be understood that in the above embodiments, the second sub-electrode 112 is taken as an example of at least two. In other embodiments, the number of the second sub-electrodes 112 can also be one.

[0084] In other embodiments of the present application, such as Figure 9 shown, the difference from the Figure 8 embodiment shown lies in the number of the second sub-electrodes 112, and the fourth sub-electrode 122 and the third dielectric part 133 are removed on the basis of the Figure 8 embodiment shown. That is to say, in this embodiment, the number of the second sub-electrodes 112 is two, and the two second sub-electrodes 112 are located at both ends of the first sub-electrode 111. That is, the top surface of one of the second sub-electrodes 112 is flush with the top surface of the first sub-electrode 111, and the bottom surface of the other second sub-electrode 112 is flush with the bottom surface of the first sub-electrode 111.

[0085] The second electrode 12 includes a third sub-electrode 121. The dielectric structure 13 includes a first dielectric part 131, a second dielectric part 132, and a sixth dielectric part 136.

[0086] The number of the sixth dielectric parts 136 is two, and the two sixth dielectric parts 136 are respectively connected to the two second dielectric parts 132.

[0087] The embodiments of the present application have been described above with reference to the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

Claims

1. A capacitor, characterized in that, Comprising: A first electrode, the first electrode comprising a first sub-electrode and a second sub-electrode, the second sub-electrode surrounding the first sub-electrode and connected to a side surface of the first sub-electrode; A second electrode, the second electrode surrounding the first electrode, and opposite to a surface of the first sub-electrode facing the second sub-electrode and not covered by the second sub-electrode, and opposite to at least one surface of the second sub-electrode; A dielectric structure, the dielectric structure being located between the first electrode and the second electrode.

2. The capacitor according to claim 1, characterized in that, The first electrode comprises at least two of the second sub-electrodes that are stacked and spaced apart, the second electrode comprises a third sub-electrode, and the third sub-electrode is located between two adjacent ones of the second sub-electrodes; The dielectric structure comprises a first dielectric portion and at least two second dielectric portions that are stacked and spaced apart, the first dielectric portion is located between the first sub-electrode and the third sub-electrode, and at least a part of the second dielectric portions is located between the second sub-electrode and the third sub-electrode.

3. The capacitor according to claim 2, characterized in that, The second electrode comprises at least two of the third sub-electrodes that are stacked and spaced apart, a top surface of the first sub-electrode is higher than a top surface of the second sub-electrode, a part of the third sub-electrodes is located between two adjacent ones of the second sub-electrodes, and a part of the third sub-electrodes is opposite to a part of the first sub-electrode that is higher than the second sub-electrode.

4. The capacitor according to claim 2 or 3, characterized in that, A bottom surface of the first sub-electrode is lower than a bottom surface of the second sub-electrode, and a part of the third sub-electrodes is opposite to a part of the first sub-electrode that is lower than the second sub-electrode.

5. The capacitor according to claim 2, characterized in that, The second electrode comprises at least two of the third sub-electrodes that are stacked and spaced apart, and the third sub-electrode is provided between every two adjacent ones of the second sub-electrodes.

6. The capacitor according to any one of claims 2 - 5, characterized in that, The second electrode further comprises a fourth sub-electrode located on a side of the second sub-electrode facing away from the first sub-electrode; The dielectric structure further comprises a third dielectric portion, and the third dielectric portion is located between the second sub-electrode and the fourth sub-electrode.

7. The capacitor according to any one of claims 2 - 6, characterized in that, The first electrode further comprises a fifth sub-electrode connected to a side of the second sub-electrode facing away from the first sub-electrode, and the third sub-electrode is further located between the first sub-electrode and the fifth sub-electrode; The dielectric structure further comprises a fourth dielectric portion, and the fourth dielectric portion is located between the fifth sub-electrode and the third sub-electrode.

8. The capacitor according to claim 7, characterized in that, The fifth sub-electrode is connected to two adjacent ones of the second sub-electrodes, and an accommodation space is formed by enclosing between two adjacent ones of the second sub-electrodes, the first sub-electrode and the fifth sub-electrode, and the third sub-electrode is located within the accommodation space.

9. The capacitor according to claim 7 or 8, characterized in that, The second electrode further comprises a sixth sub-electrode located on a side of the fifth sub-electrode facing away from the first sub-electrode; The dielectric structure further comprises a fifth dielectric portion, and the fifth dielectric portion is located between the fifth sub-electrode and the sixth sub-electrode.

10. The capacitor according to claim 9, characterized in that, A dimension of the fifth dielectric portion in a thickness direction and a dimension of the fifth sub-electrode in the thickness direction are both the same as a dimension of the first sub-electrode in the thickness direction, and the thickness direction is a stacking direction of at least two of the second sub-electrodes.

11. A storage unit, characterized in that, Comprising a switching tube and the capacitor according to any one of claims 1-10, the switching tube being electrically connected to the capacitor.

12. The storage unit according to claim 11, characterized in that, The first sub - electrode of the capacitor surrounds the switching transistor. The switching transistor includes a channel and at least two stacked and spaced first electrodes. A part of the channel is located between the two first electrodes, and the channel is connected to the first sub - electrode.

13. The storage unit according to claim 12, characterized in that, A part of the first sub - electrode and a part of at least one third sub - electrode are arranged on the same layer as the first electrode.

14. A storage array, characterized in that, It includes a plurality of storage units as described in claim 13, and the plurality of storage units are arranged in an array.

15. The storage array according to claim 14, characterized in that, The storage array includes multiple layers of the storage units, and each layer of the storage units includes a plurality of the storage units arranged in an array.

16. A memory, characterized in that, It includes a controller and the storage array as described in claim 14 or 15, and the controller is electrically connected to the storage array.

17. An electronic device, characterized in that, It includes a circuit board and the memory as described in claim 16, and the circuit board is electrically connected to the memory.

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