Light-emitting element inspection method, display device manufacturing method, and light-emitting element inspection device

Abstract

The invention relates to a light-emitting element inspection method, a display device manufacturing method and a light-emitting element inspection device. The light emitting element inspection method includes: forming a plurality of light emitting element rods by etching a plurality of semiconductor material layers stacked on a growth substrate; forming a protective layer covering a portion of a top surface and a portion of a side surface of the plurality of light emitting element rods and forming a contact electrode on the protective layer; forming a metal layer on side surfaces of the plurality of light emitting element bars and on portions of the growth substrate where the plurality of light emitting element bars are not provided; forming a contact pad connected to the metal layer on the growth substrate; and applying a test power to the contact electrode and the contact pad.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0187489, filed with the Korean Intellectual Property Office on December 20, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a method for inspecting a light - emitting element, a method for manufacturing a display device, and a light - emitting element inspection apparatus. Background art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. The display device may be a flat - panel display device, such as a liquid - crystal display, a field - emission display, or a light - emitting display.

[0005] The light - emitting display device may be implemented as an organic light - emitting display device including an organic light - emitting diode element as a light - emitting element, an inorganic light - emitting display device including an inorganic semiconductor element as a light - emitting element, or a micro - light - emitting diode display device including an ultra - small light - emitting diode element (or micro - light - emitting diode element) as a light - emitting element.

[0006] In a display device manufactured by a process of bonding micro - light - emitting elements to a display panel, after the display device process is completed, a defect inspection of the micro - light - emitting elements is performed. If a defect is found in the micro - light - emitting elements after the display device process is completed, it is not easy to replace the defective micro - light - emitting elements with high - quality light - emitting elements, so that the conventional lighting inspection method has problems of reducing process efficiency and reducing productivity. Summary of the invention

[0007] Aspects and features of embodiments of the present disclosure provide a method and an inspection apparatus for performing a lighting inspection of a light - emitting element on a growth substrate.

[0008] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the following detailed description of the present disclosure.

[0009] According to one or more embodiments, a light-emitting element inspection method includes: forming a plurality of light-emitting element rods by etching a plurality of semiconductor material layers stacked on a growth substrate; forming a protective layer covering a part of the top surface and a part of the side surface of the plurality of light-emitting element rods and forming a contact electrode on the protective layer; forming a metal layer on the side surfaces of the plurality of light-emitting element rods and on a portion of the growth substrate where the plurality of light-emitting element rods are not provided; forming a contact pad connected to the metal layer on the growth substrate; and applying a test power to the contact electrode and the contact pad.

[0010] According to one or more embodiments, forming a plurality of light-emitting element rods includes: sequentially forming a third semiconductor material layer, a second semiconductor material layer, an active material layer, and a first semiconductor material layer on a growth substrate; and patterning the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer to form a plurality of light-emitting element rods.

[0011] According to one or more embodiments, forming a protective layer covering a part of the top surface and a part of the side surface of the plurality of light-emitting element rods and forming a contact electrode on the protective layer includes: forming a photoresist covering at least a part of the second semiconductor material layer on the entire surface of the growth substrate; applying a protective material layer covering the plurality of light-emitting element rods and the photoresist; forming a protective layer covering the top surface of the plurality of light-emitting element rods and the side surfaces of the first semiconductor material layer and the active material layer; and forming a through hole in a part of the protective layer on the top surface of each of the plurality of light-emitting element rods, and forming a contact electrode covering the through hole.

[0012] According to one or more embodiments, forming a metal layer on the side surfaces of the plurality of light-emitting element rods and on a portion of the growth substrate where the plurality of light-emitting element rods are not provided includes: forming a metal layer on the entire surface of the growth substrate except for the top surface of the plurality of light-emitting element rods using a mask, the metal layer being in direct contact with the second semiconductor material layer of the plurality of light-emitting element rods and connected to the plurality of light-emitting element rods.

[0013] According to one or more embodiments, applying a test power to the contact electrode and the contact pad includes: providing a test power to at least a part of the plurality of light-emitting element rods using a probe on one side of the plurality of light-emitting element rods; acquiring an image of light emitted from the plurality of light-emitting element rods through an image sensor, the test power being provided to the other side of the plurality of light-emitting element rods; and determining whether the plurality of light-emitting element rods are defective by comparing the acquired image with a pre-stored reference image through a control part.

[0014] According to one or more embodiments, a method of manufacturing a display device includes: forming a plurality of light-emitting element rods by etching a plurality of semiconductor material layers stacked on a growth substrate; forming a protective layer covering a part of a top surface and a part of a side surface of the plurality of light-emitting element rods and forming a contact electrode on the protective layer; forming a metal layer on side surfaces of the plurality of light-emitting element rods and on a portion of the growth substrate where the plurality of light-emitting element rods are not provided; forming a contact pad connected to the metal layer on the growth substrate; applying a test power to the contact electrode and the contact pad; transferring the plurality of light-emitting elements including the plurality of light-emitting element rods, the protective layer, and the metal layer to a circuit board; and forming a common electrode in contact with the metal layer on side surfaces of the plurality of light-emitting elements.

[0015] According to one or more embodiments, forming the plurality of light-emitting element rods includes: sequentially forming a third semiconductor material layer, a second semiconductor material layer, an active material layer, and a first semiconductor material layer on the growth substrate; and forming the plurality of light-emitting element rods by patterning the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer.

[0016] According to one or more embodiments, forming a protective layer covering a part of a top surface and a part of a side surface of the plurality of light-emitting element rods and forming a contact electrode on the protective layer includes: forming a photoresist covering at least a part of the second semiconductor material layer on the entire surface of the growth substrate; applying a protective material layer covering the plurality of light-emitting element rods and the photoresist; forming a protective layer covering a top surface of the plurality of light-emitting element rods and side surfaces of the first semiconductor material layer and the active material layer; and forming a through hole in a portion of the protective layer on a top surface of each of the plurality of light-emitting element rods, and forming a contact electrode covering the through hole.

[0017] According to one or more embodiments, forming a metal layer on side surfaces of the plurality of light-emitting element rods and on a portion of the growth substrate where the plurality of light-emitting element rods are not provided includes: forming a metal layer on the entire surface of the growth substrate except for a top surface of the plurality of light-emitting element rods using a mask, the metal layer being in direct contact with a second semiconductor material layer of the plurality of light-emitting element rods and connected to the plurality of light-emitting element rods.

[0018] According to one or more embodiments, forming a metal layer on side surfaces of the plurality of light-emitting element rods and on a portion of the growth substrate where the plurality of light-emitting element rods are not provided includes: forming a photoresist covering at least a part of the third semiconductor material layer on the entire surface of the growth substrate; and forming a metal layer covering the plurality of light-emitting element rods and the photoresist.

[0019] According to one or more embodiments, between applying test power and transferring a plurality of light-emitting elements to a circuit board, the method further includes: removing a photoresist; forming a covering protective layer around side surfaces and top surfaces of the plurality of light-emitting element rods; and forming an opening exposing a contact electrode in the covering protective layer.

[0020] According to one or more embodiments, a plurality of pixel circuit portions are on the circuit board, wherein each of the plurality of pixel circuit portions includes a pixel electrode located at a top surface of the plurality of pixel circuit portions, and wherein transferring the plurality of light-emitting elements including the plurality of light-emitting element rods, a protective layer, and a metal layer to the circuit board includes: placing a contact electrode of the light-emitting element on the pixel electrode, and electrically connecting and bonding the contact electrode on the circuit board.

[0021] According to one or more embodiments, the circuit board further includes a bank around the pixel electrode, and wherein the method further includes: forming a light-blocking layer on a common electrode overlapping the bank; in a region divided by the light-blocking layer, forming a first wavelength conversion layer in a region corresponding to a first sub-pixel of the display device, forming a second wavelength conversion layer in a region corresponding to a second sub-pixel of the display device, and forming a light-transmissive layer in a region corresponding to a third sub-pixel of the display device; and forming a first color filter on the first wavelength conversion layer, forming a second color filter on the second wavelength conversion layer, and forming a third color filter on the light-transmissive layer.

[0022] According to one or more embodiments, the common electrode does not overlap with a top surface of the light-emitting element.

[0023] According to one or more embodiments, applying test power to the contact electrode and the contact pad includes: using a probe on one side of the plurality of light-emitting element rods to provide test power to at least a portion of the plurality of light-emitting element rods; acquiring an image of light emitted from the plurality of light-emitting element rods through an image sensor, the test power being provided to the other side of the plurality of light-emitting element rods; and determining whether the plurality of light-emitting element rods are defective by comparing the image acquired by the image sensor with a reference image through a control portion.

[0024] According to one or more embodiments, a light-emitting element inspection device for inspecting illumination of a plurality of light-emitting elements on a growth substrate, the light-emitting element inspection device includes: a contact pad on the growth substrate and electrically connected to a metal layer on side surfaces of the plurality of light-emitting elements and a portion of the growth substrate where the plurality of light-emitting elements are not provided; and a probe and a power application portion configured to apply test power to the contact electrode and the contact pad of the plurality of light-emitting elements through the probe.

[0025] According to one or more embodiments, the light-emitting element inspection apparatus further includes: an image sensor on one side of a plurality of light-emitting elements to obtain an image of light emitted from the plurality of light-emitting elements; and a control section for determining whether the plurality of light-emitting elements are defective by comparing the image obtained by the image sensor with a reference image.

[0026] According to one or more embodiments, one of the plurality of light-emitting elements includes a second semiconductor layer, a first semiconductor layer, and an active layer between the second semiconductor layer and the first semiconductor layer, and wherein a metal layer is in direct contact with the second semiconductor layer and spaced apart from a contact electrode.

[0027] According to one or more embodiments, one light-emitting element further includes a protective layer around a top surface and a side surface of the first semiconductor layer and a side surface of the active layer, wherein the protective layer includes a through hole in a portion of the protective layer on the top surface of the first semiconductor layer, and wherein the contact electrode is electrically connected to the first semiconductor layer through the through hole.

[0028] According to one or more embodiments, the metal layer extends over the protective layer and around a side surface of the first semiconductor layer and a side surface of the active layer.

[0029] However, the effects of the present disclosure are not limited to the above effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0031] Figure 2 is a layout view showing a display device according to one or more embodiments.

[0032] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0033] Figure 4 is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments.

[0034] Figure 5 is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments.

[0035] Figure 6 is a layout view showing a plurality of pixels in a display area according to one or more embodiments.

[0036] Figure 7 is a cross-sectional view showing a display device taken along line I1-I1' according to one or more embodiments Figure 6 of

[0037] Figure 8 is Figure 7 an enlarged view of region A of

[0038] Figure 9 and Figure 10 is an enlarged view of region A of Figure 7 according to one or more embodiments.

[0039] Figure 11 is a flowchart showing a method of manufacturing a display device according to one or more embodiments.

[0040] Figures 12 to 18 and Figures 20 to 24 is a cross-sectional view of each stage of an inspection process of a display device according to one or more embodiments, and Figure 19 is a top view of a growth substrate according to one or more embodiments.

[0041] Figure 25 is a cross-sectional view showing steps of an inspection process of a light-emitting element inspection method according to one or more embodiments.

[0042] Figures 26 to 28 is a cross-sectional view of each step of an inspection process of a light-emitting element inspection method according to one or more embodiments. Detailed Description

[0043] Aspects and features of embodiments of the present disclosure and methods for implementing them will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein and will be implemented in various different forms. The presented embodiments are provided only to make the present disclosure complete and to give a full picture of the scope of the present disclosure to those of ordinary skill in the art to which the present disclosure pertains, and the present disclosure may be defined by the scope of the claims and their equivalents.

[0044] An element or layer is referred to as being "on" another element or layer including that the element or layer is directly above the other element or layer or that the element or layer is on the other element or layer and other elements are interposed therebetween. Throughout the present disclosure, the same reference numerals denote the same components. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments are examples and do not limit the present disclosure to those shown.

[0045] Although terms such as first, second, etc. are used to describe various components, these components are not limited by these terms. Thus, within the technical concept of the present disclosure, the first component mentioned herein may also be the second component.

[0046] Taking into account the entire disclosure, those of ordinary skill in the art will understand that each suitable feature of the various embodiments of the present disclosure can be combined or partially or fully combined with each other, and can be technically interlocked and operated in various suitable ways, and each embodiment can be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0047] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0048] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0049] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0050] Reference Figure 1 , the display device 10 is a device for displaying videos or still images, such as mobile phones, smart phones, tablet personal computers, and portable electronic devices such as smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs), and display screens for various products such as televisions, laptop computers, monitors, billboards, and / or Internet of Things (IoT) devices.

[0051] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a miniaturized light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, the description focuses on the fact that the display device 10 is a micro light-emitting display device, but the present disclosure is not limited thereto. On the other hand, for ease of explanation, micro light-emitting diodes are hereinafter referred to as light-emitting diodes.

[0052] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply circuit 500.

[0053] The display panel 100 can be formed as a flat surface in a rectangular shape, having a short side in the first direction DR1 and a long side in the second direction DR2 intersecting the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be rounded to have an appropriate curvature (e.g., a predetermined curvature), or can be formed as right angles. The planar shape of the display panel 100 is not limited to a rectangle and can be formed as other polygonal shapes, circular shapes, or oval shapes. The display panel 100 can be formed flat, but is not limited thereto. For example, the display panel 100 can include curved portions formed at the left and right ends having a constant curvature or a varying curvature. Additionally, the display panel 100 can be formed flexible to be able to bend, curve, fold, and / or curl.

[0054] The display panel 100 can include a main area MA and a sub-area SBA.

[0055] The main area MA can include a display area DA for displaying an image and a non-display area NDA that is a peripheral area of the display area DA and surrounds the display area DA along the edge or periphery of the display area DA (e.g., around the display area DA). The display area DA can include a plurality of pixels for displaying an image. For example, a pixel can include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0056] The sub-area SBA can protrude from one side in the second direction DR2 of the main area MA. Although Figure 1 the unfolded sub-area SBA is shown, the sub-area SBA can be bent, and in this case, the sub-area SBA can be disposed on the bottom surface of the display panel 100. When the sub-area SBA is bent, it can overlap the main area MA in the third direction DR3 that is the thickness direction of the display panel 100. The display driving circuit 250 can be disposed in the sub-area SBA.

[0057] The display driving circuit 250 can generate signals and voltages for driving the display panel 100. The display driving circuit 250 can be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 can be attached to the circuit board 300 using a chip on film (COF) method.

[0058] The circuit board 300 may be attached to one end of the sub-region SBA of the display panel 100. In this way, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0059] The power supply circuit 500 (e.g., a power supply unit) may generate and / or supply a plurality of panel driving voltages according to an external power supply voltage. The power supply circuit 500 may be formed as an integrated circuit (IC) and attached to the circuit board 300 using the COF method.

[0060] Figure 2 is a layout diagram showing a display device according to one or more embodiments. Figure 2 shows the sub-region SBA unfolded and not bent.

[0061] Reference Figure 2 , the display panel 100 may include a main region MA and a sub-region SBA.

[0062] The main region MA may include a display region DA for displaying an image and a non-display region NDA as a peripheral region of the display region DA. The display region DA may occupy most of the main region MA. The display region DA may be located in the center of the main region MA.

[0063] The display region DA may include a plurality of pixels PX for displaying an image, and each of the plurality of pixels PX may include a plurality of sub-pixels SPX. A pixel PX may be defined as a group of sub-pixels that is the smallest unit capable of presenting a white gray level.

[0064] The non-display region NDA may be placed adjacent to the display region DA. The non-display region NDA may be an area outside the display region DA. The non-display region NDA may be arranged around the display region DA (e.g., surrounding the display region DA). The non-display region NDA may be an edge region of the display panel 100.

[0065] The first scan driving unit (or first scan driving part) SDC1 and the second scan driving unit (or second scan driving part) SDC2 may be disposed in the non-display area NDA. The first scan driving unit SDC1 is disposed on one side (e.g., the left side) of the display panel 100, and the second scan driving unit SDC2 is disposed on the other side (e.g., the right side) of the display panel 100. However, it is not limited thereto. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may receive a scan control signal from the display driving circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan line.

[0066] The sub-region SBA may protrude from one side in the second direction DR2 of the main region MA. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 is less than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be disposed at the lower part of the display panel 100. In this case, the sub-region SBA may overlap the main region MA in the third direction DR3.

[0067] The sub-region SBA may include a connection region CA, a pad region PA, and a bending region BA.

[0068] The connection region CA is a region that protrudes from one side in the second direction DR2 of the main region MA. One side of the connection region CA may be in contact with the non-display area NDA of the main region MA, and the other side of the connection region CA may be in contact with the bending region BA.

[0069] The pad region PA is a region where the pad PD and the display driving circuit 250 are disposed. The display driving circuit 250 may be attached to the driving pad of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad region PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad region PA may be in contact with the bending region BA.

[0070] The bent region BA is a bent area. When the bent region BA is bent, the pad region PA can be disposed (e.g., in the thickness direction (e.g., the third direction DR3)) below the connection region CA and below the main region MA. The bent region BA can be disposed between the connection region CA and the pad region PA. One side of the bent region BA can be in contact with the connection region CA, and the other side of the bent region BA can be in contact with the pad region PA.

[0071] The non-display power supply line NVSL can be disposed in the non-display region NDA, the connection region CA, the bent region BA, and the pad region PA.

[0072] The non-display power supply line NVSL can be disposed on four sides of the display region DA in the non-display region NDA. The non-display power supply line NVSL can be arranged to surround at least three sides of the display region DA (e.g., around at least three sides of the display region DA). For example, the non-display power supply line NVSL can be around the left side, the top side, and the right side of the display region DA (e.g., can surround the left side, the top side, and the right side of the display region DA), and can be disposed on at least a part of the lower side. In addition, the non-display power supply line NVSL can be disposed outside the first scan driving unit SDC1 and the second scan driving unit SDC2. For example, the non-display power supply line NVSL can be disposed on the left side of the first scan driving unit SDC1 and on the right side of the second scan driving unit SDC2. The non-display power supply line NVSL can be disposed at the edges of the first scan driving unit SDC1 and the substrate SUB (e.g., see Figure 7 ) and at the edges of the second scan driving unit SDC2 and the substrate SUB. Alternatively, the non-display power supply line NVSL can overlap with the first scan driving unit SDC1 and the second scan driving unit SDC2.

[0073] The non-display power supply line NVSL can be disposed at the left and right edges of the connection region CA and the bent region BA. The non-display power supply line NVSL can be connected to the pad PD adjacent to one side edge and the pad PD adjacent to the other side edge in the pad region PA. The second driving voltage ( Figure 1 of 300) on the circuit board ( Figure 1 of 500) can be supplied to the non-display power supply line NVSL. Figure 3 of VSS).

[0074] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0075] Refer to Figure 3 , the display region DA includes a plurality of pixels PX (see Figure 2) Multiple scan lines SL, multiple emission control lines EL, and multiple data lines DL. According to one or more embodiments, each of the multiple pixels PX includes multiple sub-pixels SPX.

[0076] The multiple pixels PX can be arranged in a matrix form in a first direction DR1 and a second direction DR2. For example, the multiple pixels PX can be arranged along the rows and columns of the matrix along the first direction DR1 and the second direction DR2. The multiple scan lines SL and the multiple emission control lines EL can extend in the first direction DR1 and can be arranged along the second direction DR2. The multiple data lines DL can extend in the second direction DR2 and can be arranged along the first direction DR1. The multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, multiple initialization scan lines GIL, and multiple bias scan lines GBL.

[0077] Each of the multiple sub-pixels SPX can be connected to one write scan line GWL among the multiple write scan lines GWL, one control scan line GCL among the multiple control scan lines GCL, one initialization scan line GIL among the multiple initialization scan lines GIL, one bias scan line GBL among the multiple bias scan lines GBL, one emission control line EL among the multiple emission control lines EL, and one data line DL among the multiple data lines DL. A data voltage of the data line DL can be provided to each of the multiple sub-pixels SPX according to a write scan signal of the write scan line GWL, and each of the multiple sub-pixels SPX can emit light according to the data voltage.

[0078] The non-display area NDA includes a first scan driving unit SDC1, a second scan driving unit SDC2, and a display driving circuit 250.

[0079] Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may include a write scan signal output unit 611, a control scan signal output unit 612, an initialization scan signal output unit 613, a bias scan signal output unit 614, and a light emission signal output unit 615. Each of the write scan signal output unit 611, the control scan signal output unit 612, the initialization scan signal output unit 613, the bias scan signal output unit 614, and the light emission signal output unit 615 may receive a scan timing control signal SCS from the timing control circuit 251. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS of the timing control circuit 251, and output them sequentially to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals according to the scan timing control signal SCS, and output them sequentially to the control scan lines GCL. The initialization scan signal output unit 613 may generate initialization scan signals according to the scan timing control signal SCS, and output them sequentially to the initialization scan lines GIL. The bias scan signal output unit 614 may generate bias scan signals according to the scan timing control signal SCS, and output them sequentially to the bias scan lines GBL. The light emission signal output unit 615 may generate light emission control signals according to the scan timing control signal SCS, and output them sequentially to the emission control lines EL.

[0080] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit 252.

[0081] The data driving circuit 252 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into analog data voltages according to the data timing control signal DCS, and outputs them to the data lines DL. In this case, the sub-pixels SPX are selected by the write scan signals of the first scan driving unit SDC1 and the second scan driving unit SDC2, and the data voltages may be provided to the selected sub-pixels SPX.

[0082] The timing control circuit 251 may receive digital video data DATA and a timing signal from an external source. The timing control circuit 251 may generate a scan timing control signal SCS and a data timing control signal DCS according to the timing signal to control the display panel 100. The timing control circuit 251 may output the scan timing control signal SCS to the first scan driving unit SDC1 and the second scan driving unit SDC2. The timing control circuit 251 may output the digital video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0083] The data driving circuit 252 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 251.

[0084] The data driving circuit 252 may provide corresponding data signals (e.g., analog data voltages) to the sub-pixels SPX. For example, the data driving circuit 252 may convert the digital video data DATA into analog data voltages according to the data timing control signal DCS and output them to the data lines DL. The sub-pixels SPX may be selected by the write scan signals of the first scan driving unit SDC1 and the second scan driving unit SDC2, and the data signals may be provided to the selected sub-pixels SPX.

[0085] The power supply circuit 500 may generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit 500 may generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT, and may provide the first driving voltage VDD, the second driving voltage VSS, and the third driving voltage VINT to the display panel 100.

[0086] Figure 4 is an equivalent circuit diagram showing a sub-pixel according to one or more embodiments.

[0087] Reference Figure 4 , the sub-pixel SPX according to one or more embodiments may be connected to the scan lines GWL, GIL, GCL, and GBL, the emission control line EL, and the data line DL. For example, the sub-pixel SPX may be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission control line EL, and the data line DL.

[0088] The sub-pixel SPX according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1, and a light-emitting element LE. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6. The driving transistor DT, the switching element, and the capacitor C1 may be referred to as a pixel circuit PXC. The pixel circuit PXC may include a driving transistor DT, at least one switching transistor ST (e.g., transistors ST1, ST2, ST3, ST4, ST5, and ST6), and a capacitor C1. In one or more embodiments, the pixel circuit PXC may include the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 as the switching transistor ST. The configuration of the pixel circuit PXC is not limited to Figure 4 and Figure 5 the embodiments, and may be changed in various ways.

[0089] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current (e.g., hereinafter referred to as "driving current Ids") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0090] The light-emitting element LE may be a micro light-emitting diode.

[0091] The light-emitting element LE emits light according to the driving current Ids. The amount of light emitted from the light-emitting element LE may be proportional to the driving current Ids. The anode electrode of the light-emitting element LE is connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to the second power supply line VSL to which the second power supply voltage is applied. A parasitic capacitance Cel may be formed between the anode electrode and the cathode electrode of the light-emitting element LE.

[0092] A capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power supply line VDL to which the first power supply voltage is applied. The level of the first power supply voltage may be higher than the level of the second power supply voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first power supply line VDL.

[0093] As Figure 4 shown, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6, and the driving transistor DT may all be formed as P-type metal-oxide-semiconductor field-effect transistors (P-type MOSFETs). In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT may be formed of polysilicon.

[0094] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. The gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission control line EL. Since the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as P-type MOSFETs, they can be turned on when a scan signal with a low gate voltage and an emission signal with a low voltage are respectively applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission control line EL. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0095] For example, the first transistor ST1 may be connected between the second electrode and the gate electrode of the driving transistor DT. The second transistor ST2 may be connected between the data line DL and the first electrode of the driving transistor DT. The third transistor ST3 may be connected between the initialization voltage line VIL and the gate electrode of the driving transistor DT. The fourth transistor ST4 may be connected between the initialization voltage line VIL and the light-emitting element LE. The fifth transistor ST5 may be connected between the first power supply line VDL and the first electrode of the driving transistor DT. The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the light-emitting element LE.

[0096] Figure 5 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0097] Reference Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of P-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed as N-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as P-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as N-type MOSFETs may be formed of an oxide semiconductor. In this case, the transistors formed of polysilicon and the transistors formed of an oxide semiconductor may be arranged in different layers.

[0098] Since the first transistor ST1 and the third transistor ST3 are formed as N-type MOSFETs, when a control scan signal having a high gate voltage is applied to the control scan line GCL, the first transistor ST1 can be turned on, and when an initialization scan signal having a high gate voltage is applied to the initialization scan line GIL, the third transistor ST3 can be turned on. In comparison, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as P-type MOSFETs, and thus they can be turned on when scan signals having a low gate voltage and an emission signal (e.g., having a low voltage) are applied to the write scan line GWL, the bias scan line GBL, and the emission control line EL, respectively.

[0099] Alternatively, Figure 4 the fourth transistor ST4 in can be formed of an N-type MOSFET. In this case, the active layer of each fourth transistor ST4 can be formed of an oxide semiconductor. When the fourth transistor ST4 is formed of an N-type MOSFET, it can be turned on when a bias scan signal having a high gate voltage is applied to the bias scan line GBL.

[0100] In one or more embodiments, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can all be formed as N-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can be formed of an oxide semiconductor.

[0101] Figure 6 is a layout diagram showing a plurality of pixels in a display area according to one or more embodiments.

[0102] Referring to Figure 6 , each of the plurality of pixels PX in the display area DA can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0103] The plurality of pixels PX can be arranged in a matrix form. In each of the plurality of pixels PX, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged along a first direction DR1.

[0104] The first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 can emit light of a third color. Here, the first color light can be light in the red wavelength band, the second color light can be light in the green wavelength band, and the third color light can be light in the blue wavelength band. For example, the blue wavelength band can represent that the main peak wavelength of the light is included in the wavelength band of about 370 nm to 460 nm, the green wavelength band can represent that the main peak wavelength of the light is included in the wavelength band of about 480 nm to 560 nm, and the red wavelength band can represent that the main peak wavelength of the light is included in the wavelength band of about 600 nm to 750 nm.

[0105] Each of the first sub-pixel SPX1 to the third sub-pixel SPX3 may include a pixel electrode PXE and one or more light-emitting elements LE.

[0106] The pixel electrode PXE may have a rectangular planar shape having a short side in a first direction DR1 and a long side in a second direction DR2, but the present disclosure is not limited thereto.

[0107] The pixel electrode PXE may include a first pixel electrode PXE1, a second pixel electrode PXE2, and a third pixel electrode PXE3. The first pixel electrode PXE1 may be electrically connected to the second electrode of the fourth transistor ( Figure 4 and Figure 5 in ST4) of the first sub-pixel SPX1 and the second electrode of the sixth transistor ( Figure 4 and Figure 5 in ST6) through a first connection hole CT1. The second pixel electrode PXE2 may be electrically connected to the second electrode of the fourth transistor ( Figure 4 and Figure 5 in ST4) of the second sub-pixel SPX2 and the second electrode of the sixth transistor ( Figure 4 and Figure 5 in ST6) through a second connection hole CT2. The third pixel electrode PXE3 may be electrically connected to the second electrode of the fourth transistor ( Figure 4 and Figure 5 in ST4) of the third sub-pixel SPX3 and the second electrode of the sixth transistor ( Figure 4 and Figure 5 in ST6) through a third connection hole CT3.

[0108] Multiple light-emitting elements LE can be disposed on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. The same number of light-emitting elements LE can be disposed on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. For example, two light-emitting elements LE can be disposed on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. Alternatively, one light-emitting element LE can be disposed on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3.

[0109] Multiple light-emitting elements LE can emit third light, that is, light in the blue wavelength band, but is not limited thereto. For example, the light-emitting element LE disposed on the first pixel electrode PXE1 emits light in the blue wavelength band, the light-emitting element LE disposed on the second pixel electrode PXE2 emits light in the green wavelength band, and the light-emitting element LE disposed on the third pixel electrode PXE3 emits light in the red wavelength band.

[0110] Figure 7 is a cross-sectional view of the display device taken along Figure 6 the line I1-I1'. Figure 8 is Figure 7 an enlarged view of the region A of Figure 9 and Figure 10 is an enlarged view of the region A of Figure 7 according to one or more embodiments.

[0111] Refer to Figure 7 and Figure 8 , the substrate SUB can be made of an insulating material such as glass, polymer resin, etc. If the substrate SUB is made of a polymer resin, it can be a flexible substrate that can be stretched. The polymer resin can be acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0112] The barrier film BR can be disposed on the substrate SUB. The barrier film BR is a film for protecting the transistors of the thin film transistor layer TFTL and the light-emitting elements LE of the light-emitting element layer EML from moisture that penetrates through the substrate SUB (which is easily permeated by moisture). The barrier film BR can be composed of multiple inorganic films stacked alternately. For example, the barrier film BR can be formed as a multi-layer of an alternating inorganic film of one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0113] The first thin film transistor TFT1 can be disposed on the barrier film BR. The first thin film transistor TFT1 can be Figure 5The fourth transistor ST4 or the sixth transistor ST6 shown in []. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0114] The first active layer ACT1 of the first thin film transistor TFT1 may be disposed on the barrier film BR. The first active layer ACT1 of the first thin film transistor TFT1 may include polysilicon, single crystal silicon, low temperature polysilicon, and / or amorphous silicon.

[0115] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region overlapping with the first gate electrode G1 in a third direction DR3 in the thickness direction of the substrate SUB. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions in which the silicon semiconductor is doped with ions to make it conductive.

[0116] The first gate insulating film 131 may be disposed on the first channel region CHA1, the first source region S1, the first drain region D1 of the first thin film transistor TFT1, and the barrier film BR. The first gate insulating film 131 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0117] The first gate metal layer GTL1 may be disposed on the first gate insulating film 131. The first gate metal layer GTL1 may include the first gate electrode G1 and the first capacitor electrode CAE1 of the first thin film transistor TFT1. The first gate electrode G1 may overlap with the first active layer ACT1 in the third direction DR3. In Figure 7 [], the first gate electrode G1 and the first capacitor electrode CAE1 are shown to be separated from each other (for example, arranged to be spaced apart from each other), but the first gate electrode G1 and the first capacitor electrode CAE1 may be connected to each other. The first gate metal layer GTL1 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or its alloy.

[0118] The second gate insulating film 132 may be disposed on the first gate electrode G1, the first capacitor electrode CAE1, and the first gate insulating film 131 of the first thin film transistor TFT1. The second gate insulating film 132 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0119] The second gate metal layer GTL2 may be disposed on the second gate insulating film 132. The second gate metal layer GTL2 may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 of the capacitor C1 in the third direction DR3. Since the second gate insulating film 132 has a suitable dielectric constant (e.g., a predetermined dielectric constant), the capacitor ( Figure 5 C1) may be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the second gate insulating film 132 disposed therebetween. The second gate metal layer GTL2 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys.

[0120] The first interlayer insulating film 141 may be disposed on the second capacitor electrode CAE2 and the second gate insulating film 132. The first interlayer insulating film 141 may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0121] The second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second thin film transistor TFT2 may be Figure 5 the first transistor ST1 or the third transistor ST3 shown in. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2.

[0122] The second active layer ACT2 of the second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), and / or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0123] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region overlapping with the second gate electrode G2 in the third direction DR3. The second source region S2 may be disposed on one side of the second channel region CHA2, and the second drain region D2 may be disposed on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that do not overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 may be regions in which the oxide semiconductor is doped with ions to make it conductive.

[0124] The third gate insulating film 133 may be disposed on the second active layer ACT2 of the second thin film transistor TFT2 and the first interlayer insulating film 141. The third gate insulating film 133 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0125] The third gate metal layer GTL3 may be disposed on the third gate insulating film 133. The third gate metal layer GTL3 may include the second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap the second active layer ACT2 in the third direction DR3. The third gate metal layer GTL3 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or its alloy.

[0126] The second interlayer insulating film 142 may be disposed on the second gate electrode G2 of the second thin film transistor TFT2 and the third gate insulating film 133. The second interlayer insulating film 142 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0127] The first data metal layer DTL1 may be disposed on the second interlayer insulating film 142. The first data metal layer DTL1 may include a first source connection electrode SBE3, a second source connection electrode SBE1, and a third source connection electrode SBE2. The first source connection electrode SBE3 may be connected to the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 passing through the first gate insulating film 131, the second gate insulating film 132, the first interlayer insulating film 141, the third gate insulating film 133, and the second interlayer insulating film 142. The second source connection electrode SBE1 may be connected to the second source region S2 of the second active layer ACT2 through a second source connection contact hole BCT1 passing through the second interlayer insulating film 142 and the third gate insulating film 133. The third source connection electrode SBE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third source connection contact hole BCT2 passing through the second interlayer insulating film 142 and the third gate insulating film 133. The first data metal layer DTL1 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or its alloy. For example, the first data metal layer DTL1 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0128] The first organic layer 160 may be provided to planarize the steps caused by the first thin-film transistor TFT1, the second thin-film transistor TFT2, and the first source connection electrode SBE3, the second source connection electrode SBE1, and the third source connection electrode SBE2 on the second interlayer insulating film 142. The first organic layer 160 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0129] The second data metal layer DTL2 may be provided on the first organic layer 160. The second data metal layer DTL2 may include a fourth source connection electrode SBE4. The fourth source connection electrode SBE4 may be connected to the first source connection electrode SBE3 through a second pixel contact hole PCT2 passing through the first organic layer 160. The second data metal layer DTL2 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or its alloys. For example, the second data metal layer DTL2 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0130] The second organic layer 180 may be provided on the fourth source connection electrode SBE4 and the first organic layer 160. The second organic layer 180 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0131] The light-emitting element layer EML may be provided on the second organic layer 180. The light-emitting element layer EML may include pixel electrodes PXE1, PXE2, and PXE3, a light-emitting element LE, a common electrode CE, and a contact electrode CTE.

[0132] The pixel electrode layer PXL may be provided on the second organic layer 180. The pixel electrode layer PXL may include a first pixel electrode PXE1, a second pixel electrode PXE2, and a third pixel electrode PXE3. In the first sub-pixel SPX1, the first pixel electrode PXE1 may be connected to the fourth source connection electrode SBE4 through a first connection hole ( Figure 6 CT1 therein) passing through the second organic layer 180. In the second sub-pixel SPX2, the second pixel electrode PXE2 may be connected to the fourth source connection electrode SBE4 through a second connection hole ( Figure 6 CT2 therein) passing through the second organic layer 180. In the third sub-pixel SPX3, the third pixel electrode PXE3 may be connected to the fourth source connection electrode SBE4 through a third connection hole ( Figure 6 CT3 therein) passing through the second organic layer 180.

[0133] In the first sub-pixel SPX1, the first pixel electrode PXE1 can be connected to the first source region S1 or the first drain region D1 of the first thin-film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Accordingly, the voltage controlled by the first thin-film transistor TFT1 in the first sub-pixel SPX1 can be applied to the first pixel electrode PXE1.

[0134] In addition, in the second sub-pixel SPX2, the second pixel electrode PXE2 can be connected to the first source region S1 or the first drain region D1 of the first thin-film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Accordingly, the voltage controlled by the first thin-film transistor TFT1 in the second sub-pixel SPX2 can be applied to the second pixel electrode PXE2.

[0135] In addition, in the third sub-pixel SPX3, the third pixel electrode PXE3 can be connected to the first source region S1 or the first drain region D1 of the first thin-film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Accordingly, the voltage controlled by the first thin-film transistor TFT1 in the third sub-pixel SPX3 can be applied to the third pixel electrode PXE3.

[0136] The pixel electrode PXE (e.g., pixel electrodes PXE1, PXE2, PXE3) can be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys. Since the pixel electrode PXE is used to connect the first light-emitting element LE1, the second light-emitting element LE2, or the third light-emitting element LE3, it is desirable to reduce the surface resistance of the pixel electrode PXE to reduce the contact resistance between the pixel electrode PXE and the first light-emitting element LE1, the second light-emitting element LE2, or the third light-emitting element LE3. For example, the pixel electrode layer PXL can be made of copper (Cu) having a low sheet resistance.

[0137] The bank layer 190 can be provided to cover the edges of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. The bank layer 190 can be formed of an organic layer, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. The bank layer 190 can include a light-blocking material to prevent light from the light-emitting element LE of one sub-pixel SPX from traveling to an adjacent sub-pixel SPX. For example, the bank layer 190 can include an inorganic black pigment such as carbon black and / or an organic black pigment.

[0138] The light-emitting element LE may be disposed on the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 that are exposed and not covered by the bank layer 190. One or more light-emitting elements LE may be disposed on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3.

[0139] As Figure 7 shown, the light-emitting element LE (e.g., light-emitting elements LE1, LE2, LE3) may be disposed in each of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. The light-emitting element LE may be a vertical light-emitting diode element extending in the third direction DR3. That is, the length of the light-emitting element LE in the third direction DR3 may be greater than the length in the horizontal direction. The length in the horizontal direction represents the length in the first direction DR1 and / or the length in the second direction DR2. For example, the length of the light-emitting element LE in the third direction DR3 may be about 1 μm to 5 μm. However, the present disclosure is not limited thereto, and the length of the light-emitting element LE in the third direction DR3 may be equal to or less than the length in the horizontal direction.

[0140] The light-emitting element LE may be a micro light-emitting diode element. Referring to Figure 8 , the light-emitting element LE may include a current spreading layer CSL, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a third semiconductor layer SEM3 sequentially stacked in the thickness direction of the substrate SUB (i.e., in the third direction DR3). In one or more embodiments, an electron blocking layer may be disposed between the first semiconductor layer SEM1 and the active layer MQW. In addition, a superlattice layer may be disposed between the active layer MQW and the second semiconductor layer SEM2. In addition, the current spreading layer CSL and / or the third semiconductor layer SEM3 may be omitted.

[0141] In addition, the light-emitting element LE may further include a protective layer INS and a metal layer ML.

[0142] The light-emitting element LE may have a cylindrical shape, a disk shape, or a rod shape, where the height is longer than the width. However, it is not limited thereto, and the light-emitting element LE may be shaped as a rod, a wire, a tube, etc., or may have a polygonal shape such as a cube, a cuboid, a hexagon, and / or a hexagonal column, or may have a shape that extends in one direction but has a partially inclined outer surface (e.g., an outer peripheral surface or an outer circumferential surface).

[0143] The current spreading layer CSL is a layer that improves the light extraction efficiency and may be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO) to transmit light, but is not limited thereto.

[0144] The first semiconductor layer SEM1 may be disposed on the current spreading layer CSL. The length in the first direction DR1 or the second direction DR2 of the bottom surface of the first semiconductor layer SEM1 may be less than the length in the first direction DR1 or the second direction DR2 of the contact electrode CTE. The first semiconductor layer SEM1 may be made of GaN doped with a dopant of the first conductivity type such as Mg, Zn, Ca, Ba, etc.

[0145] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0146] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer MQW may have a structure in which a semiconductor material having a high energy bandgap and a semiconductor material having a low energy bandgap are alternately stacked with each other, and may include other group III-V semiconductor materials according to the wavelength range of the emitted light.

[0147] When the active layer MQW includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer MQW may shift to the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer MQW may shift to the blue wavelength band. For example, the content of indium (In) in the active layer MQW of the light emitting element LE that emits the third light (for example, light in the blue wavelength band) may be about 10 wt% to 20 wt%.

[0148] The second semiconductor layer SEM2 may be disposed on the active layer MQW. The second semiconductor layer SEM2 may be doped with a dopant of the second conductivity type such as Si, Ge, Se, Sn, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si.

[0149] An electron blocking layer may be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer that inhibits or prevents too many electrons from flowing into the active layer MQW. For example, the electron blocking layer may be AlGaN and / or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0150] The superlattice layer may be provided between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer may be formed of InGaN and / or GaN. The superlattice layer may be omitted.

[0151] The protective layer INS may be a film for protecting the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the light-emitting element LE.

[0152] The protective layer INS may be around the side surfaces of the current spreading layer CSL, the first semiconductor layer SEM1, and the active layer MQW (e.g., may surround them), and may be around a part of the side surface of the second semiconductor layer SEM2 (e.g., may surround a part of the side surface of the second semiconductor layer SEM2). The protective layer INS may expose at least a part of the side surface of the second semiconductor layer SEM2. In addition, the protective layer INS may expose the side surface of the third semiconductor layer SEM3. The protective layer INS may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0153] The metal layer ML may directly contact at least a part of the side surface of the second semiconductor layer SEM2 where the protective layer INS is not provided and the third semiconductor layer SEM3 and may be around at least a part of the side surface of the second semiconductor layer SEM2 where the protective layer INS is not provided and the third semiconductor layer SEM3 (e.g., may surround them). The metal layer ML may extend over the protective layer INS and may be around at least a part of the side surface of the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1, and the current spreading layer CSL above the protective layer INS (e.g., may surround them). Thus, the metal layer ML does not directly contact the active layer MQW, the first semiconductor layer SEM1, the current spreading layer CSL, and the contact electrode CTE.

[0154] The metal layer ML may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu).

[0155] In one or more embodiments, referring to Figure 9 , the metal layer ML may be around at least a part of the side surface of the second semiconductor layer SEM2 and the side surface of the third semiconductor layer SEM3 (e.g., may surround them). The metal layer ML may not be provided on the side surfaces of the current spreading layer CSL, the first semiconductor layer SEM1, and the active layer MQW.

[0156] In one or more embodiments, referring to Figure 9, the side surface of the contact electrode CTE and the side surface of the light-emitting element LE can be aligned with each other and placed in a straight line.

[0157] In one or more embodiments, referring to Figure 10 , the metal layer ML can be around at least a portion of the side surface of the second semiconductor layer SEM2 (e.g., can surround at least a portion of the side surface of the second semiconductor layer SEM2). The metal layer ML may not be around at least a portion of the side surface of the third semiconductor layer SEM3 (e.g., may not surround at least a portion of the side surface of the third semiconductor layer SEM3). The metal layer ML can be in direct contact with at least a portion of the side surface of the second semiconductor layer SEM2. In one or more embodiments, the metal layer ML can be around at least a portion of the side surface of the third semiconductor layer SEM3 (e.g., can surround at least a portion of the side surface of the third semiconductor layer SEM3).

[0158] The light-emitting element LE may further include a covering protective layer CINS around the side surfaces of the plurality of semiconductor layers, the side surfaces and the top surface of the current spreading layer CSL, and on the metal layer ML and the protective layer INS (e.g., surrounding them). The covering protective layer CINS can have an opening on the top surface of the light-emitting element LE. The contact electrode CTE can be exposed through the opening.

[0159] Referring to Figures 8 to 10 , the metal layer ML can be around at least a portion of the side surface of the second semiconductor layer SEM2 (e.g., can surround at least a portion of the side surface of the second semiconductor layer SEM2). The metal layer ML can be in direct contact with the second semiconductor layer SEM2.

[0160] The contact electrode CTE can be disposed between the pixel electrode PXE and the light-emitting element LE. The contact electrode CTE connects the light-emitting element LE and the pixel electrode PXE that overlap in the thickness direction of the light-emitting element LE.

[0161] The contact electrode CTE can be disposed on the pixel electrode PXE. The contact electrode CTE can be used as a bonding metal for bonding the pixel electrode PXE and the light-emitting element LE. Alternatively, the contact electrode CTE can further include a separate connection electrode between the pixel electrodes PXE.

[0162] The contact electrode CTE can be formed in multiple layers. The contact electrode CTE can include a connection part and a reflective part spaced apart (e.g., separated) from the pixel electrode PXE, and the connection part is disposed on the pixel electrode PXE to bond the pixel electrode PXE and the light-emitting element LE. The reflective part can be disposed closer to the first semiconductor layer SEM1 (or current spreading layer CSL) than the connection part. The reflective part is used to reflect the light emitted from the light-emitting element LE that travels in the downward direction rather than the upward direction, thereby improving the light-emitting efficiency of the light-emitting element LE. The reflective part can include a metal material with higher reflectivity than the connection part, such as Al.

[0163] The contact electrode CTE can be in contact with the pixel electrodes PXE1, PXE2, and PXE3. The contact electrode CTE can be in direct contact with the current spreading layer CSL of the light-emitting element LE. The protective layer INS can have a through hole such that the contact electrode CTE is in direct contact with the current spreading layer CSL. The current spreading layer CSL can be exposed through the through hole. The current spreading layer CSL exposed through the through hole and the contact electrode CTE can be in direct contact.

[0164] The through hole overlaps with the contact electrode CTE in the thickness direction of the light-emitting element LE, and the width of the through hole can be equal to or less than the width of the contact electrode CTE.

[0165] The contact electrode CTE can include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu).

[0166] The third organic layer 191 can be disposed to cover a part of the side surfaces of the bank layer 190 and the plurality of light-emitting elements LE. The third organic layer 191 can be formed of an organic layer, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0167] The third organic layer 191 can be disposed to cover a part of the side surface of each of the plurality of light-emitting elements LE. The third organic layer 191 can be disposed lower than the plurality of light-emitting elements LE to expose the upper part of the light-emitting element LE.

[0168] The third organic layer 191 is a layer for planarizing the steps caused by the plurality of light-emitting elements LE. In one or more embodiments, the third organic layer 191 can be formed as a single layer, but can also be formed as multiple layers.

[0169] The common electrode CE can be disposed on the side surfaces of each of the plurality of light-emitting elements LE and on the top surface of the third organic layer 191. The common electrode CE can be a common layer commonly formed in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. Since the common electrode CE contacts the side surfaces of the light-emitting elements LE and is not disposed on the top surfaces of the light-emitting elements LE, the common electrode CE can be a light-impermeable conductive material, but is not limited thereto. The common electrode CE can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO) that can transmit light. The common electrode CE can be disposed on the top surface of each of the plurality of light-emitting elements LE.

[0170] In one or more embodiments, the pixel electrode PXE can be referred to as an anode electrode or a first electrode, and the common electrode CE can be referred to as a cathode electrode or a second electrode.

[0171] The first capping layer CAP1 can be disposed on the common electrode CE. The first capping layer CAP1 can be formed of an inorganic layer film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0172] The light-blocking layer BM, the first light-converting layer QDL1, the second light-converting layer QDL2, and the light-transmitting layer TPL can be disposed on the first capping layer CAP1. The first light-converting layer QDL1, the second light-converting layer QDL2, and the light-transmitting layer TPL can be formed by partitioning the light-blocking layer BM. Accordingly, the first light-converting layer QDL1 is disposed on the first capping layer CAP1 in the first sub-pixel SPX1, and the second light-converting layer QDL2 is disposed on the first capping layer CAP1 in the second sub-pixel SPX2, and the light-transmitting layer TPL can be disposed on the first capping layer CAP1 in the third sub-pixel SPX3. The light-blocking layer BM can overlap the bank layer 190 in the third direction DR3 and can not overlap the plurality of light-emitting elements LE.

[0173] The first light-converting layer QDL1 can convert a part of the third light (for example, light in the blue wavelength band) incident from the light-emitting element LE into the first light (for example, light in the red wavelength band). The first light-converting layer QDL1 can include a first base resin BRS1 and a first wavelength-converting particle WCP1. The first base resin BRS1 can include a light-transmitting organic material. For example, the first base resin BRS1 can include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, and / or an imide-based resin. The first wavelength-converting particle WCP1 can convert a part of the third light (for example, light in the blue wavelength band) incident from the light-emitting element LE into the first light (for example, light in the red wavelength band). The first wavelength-converting particle WCP1 can be a quantum dot (QD), a quantum rod, a fluorescent material, and / or a phosphorescent material.

[0174] The second light conversion layer QDL2 can convert a part of the third light (e.g., light in a blue wavelength band) incident from the light-emitting element LE into the second light (e.g., light in a green wavelength band). It can include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 can include a light-transmissive organic material. For example, the second base resin BRS2 can include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, and / or an imide-based resin. The second wavelength conversion particles WCP2 can convert a part of the third light (e.g., light in a blue wavelength band) incident from the light-emitting element LE into the second light (e.g., light in a green wavelength band). The second wavelength conversion particles WCP2 can be quantum dots (QDs), quantum rods, fluorescent materials, and / or phosphorescent materials.

[0175] The light-transmissive layer TPL can include a light-transmissive organic material. For example, the light-transmissive layer TPL can include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, and / or an imide-based resin.

[0176] The light-blocking layer BM can include a first light-blocking layer BM1 and a second light-blocking layer BM2 stacked in sequence. The length of the first direction DR1 or the second direction DR2 of the first light-blocking layer BM1 can be wider than the length of the first direction DR1 or the second direction DR2 of the second light-blocking layer BM2. The first light-blocking layer BM1 and the second light-blocking layer BM2 can be formed of an organic layer, such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The first light-blocking layer BM1 and the second light-blocking layer BM2 can include a light-blocking material to prevent the light from the light-emitting element LE of one sub-pixel SPX from traveling to an adjacent sub-pixel SPX. For example, the first light-blocking layer BM1 and the second light-blocking layer BM2 can include an inorganic black pigment such as carbon black or an organic black pigment.

[0177] The second capping layer CAP2 can be disposed on the first capping layer CAP1 and the light-blocking layer BM. The second capping layer CAP2 can be disposed on the side surface and the top surface of the light-blocking layer BM. That is, the second capping layer CAP2 can be disposed on the side surfaces of the first light-blocking layer BM1 and the second light-blocking layer BM2 and the top surface of the second light-blocking layer BM2.

[0178] The reflective layer RF can be disposed between the light-blocking layer BM and the first light conversion layer QDL1, between the light-blocking layer BM and the second light conversion layer QDL2, and between the light-blocking layer BM and the light-transmitting layer TPL. The reflective layer RF can be disposed on the second capping layer CAP2 provided on the sides of the first light-blocking layer BM1 and the second light-blocking layer BM2. The reflective layer RF is used to reflect the light traveling in the lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL.

[0179] The reflective layer RF can include a highly reflective metal material such as aluminum (Al). The thickness of the reflective layer RF can be about 0.1 μm.

[0180] Alternatively, the reflective layer RF can include M (where M is an integer greater than or equal to 2) pairs of a first layer and a second layer having different refractive indices to serve as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers can be alternately arranged. The first layer and the second layer can be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0181] The third capping layer CAP3 can be disposed on the second capping layer CAP2, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL. The third capping layer CAP3 can be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL can be encapsulated by the first capping layer CAP1, the second capping layer CAP2, and the third capping layer CAP3.

[0182] The fourth organic layer 193 can be disposed on the second capping layer CAP2. The fourth organic layer 193 can be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0183] A plurality of color filters CF1, CF2, and CF3 can be disposed on the fourth organic layer 193. The plurality of color filters CF1, CF2, and CF3 can include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0184] The first color filter CF1 disposed in the first sub-pixel SPX1 can transmit first light (e.g., light in the red wavelength band) and absorb or block third light (e.g., light in the blue wavelength band). Thus, the first color filter CF1 can transmit the first light (e.g., light in the red wavelength band) converted from the third light (e.g., light in the blue wavelength band) emitted by the light-emitting element LE by the first light conversion layer QDL1, and absorb or block the third light (e.g., light in the blue wavelength band) not converted by the first light conversion layer QDL1. Therefore, the first sub-pixel SPX1 can emit first light (e.g., light in the red wavelength band).

[0185] The second color filter CF2 disposed in the second sub-pixel SPX2 can transmit second light (e.g., light in the green wavelength band) and absorb or block third light (e.g., light in the blue wavelength band). Thus, the second color filter CF2 can transmit the second light (e.g., light in the green wavelength band) converted from the third light (e.g., light in the blue wavelength band) emitted by the light-emitting element LE by the second light conversion layer QDL2, and absorb or block the third light (e.g., light in the blue wavelength band) not converted by the second light conversion layer QDL2. Therefore, the second sub-pixel SPX2 can emit second light (e.g., light in the green wavelength band).

[0186] The third color filter CF3 disposed in the third sub-pixel SPX3 can transmit third light (e.g., light in the blue wavelength band). Thus, the third color filter CF3 can transmit the third light (e.g., light in the blue wavelength band) emitted from the light-emitting element LE through the light-transmitting layer TPL. Therefore, the third sub-pixel SPX3 can emit third light (e.g., light in the blue wavelength band).

[0187] The first color filter CF1, the second color filter CF2, and the third color filter CF3 overlapping in the third direction DR3 can overlap with the bank layer 190 and the light-blocking layer BM in the third direction DR3.

[0188] The fifth organic layer 194 for planarization can be disposed on the plurality of color filters CF1, CF2, and CF3. The fifth organic layer 194 can be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0189] Reference Figure 7 and Figure 8 , the light-emitting element LE includes a metal layer ML around at least a part of the side surface of the second semiconductor layer SEM2 (e.g., around at least a part of the side surface of the second semiconductor layer SEM2), and the metal layer ML can be in contact with the common electrode CE and the side surface of the second semiconductor layer SEM2. Thus, the common electrode CE may not cover the top surface of the light-emitting element LE. The common electrode CE can also be formed of a non-transparent conductive material.

[0190] Figure 11 is a flowchart showing a method of manufacturing a display device according to one or more embodiments. Figures 12 to 18 and Figures 20 to 24 is a cross-sectional view of each stage of an inspection process of a display device according to one or more embodiments, and Figure 19 is a top view of a growth substrate according to one or more embodiments. Additionally, as described above, Figure 20 is a cross-sectional view of each stage of an inspection process of a display device according to one or more embodiments and is a diagram for schematically explaining a light-emitting element inspection device.

[0191] Hereinafter, reference will be made to Figures 11 to 24 to describe a method of manufacturing a display device.

[0192] Referring to Figure 11 , according to one or more embodiments, a method of manufacturing a display device includes: forming a light-emitting element bar LED on a growth substrate (e.g., a base substrate) BSUB (S110); forming a protective layer INS and a contact electrode CTE covering the top surface of the light-emitting element bar LED (S120); forming a metal layer ML provided on the side surface of the light-emitting element bar LED and on the growth substrate BSUB where the light-emitting element bar LED is not provided (S130); forming a contact pad CPD connected to the metal layer ML on the growth substrate BSUB (S140); applying a test power to the contact electrode CTE and the contact pad CPD (S150); transferring the light-emitting element LE to a circuit board (S160); and forming a common electrode CE to contact the metal layer ML side of the light-emitting element LE (S170). Here, the steps from step S110 to step S150 can be referred to as a light-emitting element inspection step S10.

[0193] Hereinafter, a method of manufacturing the Figure 11 display device shown in Figures 12 to 24 will be described in combination with

[0194] Referring to Figure 12 and Figure 13 , a light-emitting element bar LED is formed on the growth substrate BSUB ( Figure 11 S110 in

[0195] First, a growth substrate BSUB is prepared. The growth substrate BSUB may be a sapphire substrate (Al2O3) and / or a silicon wafer containing silicon. However, it is not limited thereto, and one or more embodiments will be described by way of an example when the growth substrate BSUB is a sapphire substrate.

[0196] A plurality of semiconductor material layers are formed on a growth substrate BSUB. The plurality of semiconductor material layers grown by an epitaxial method can be formed by growing a seed crystal. Here, the method of forming the semiconductor material layer can be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-mode thermal evaporation, sputtering, metalorganic chemical vapor deposition (MOCVD), etc., and can preferably be formed by metalorganic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0197] The precursor material for forming the plurality of semiconductor material layers is not particularly limited within the range that can be conventionally selected to form the target material. In one example, the precursor material can be a metal precursor containing an alkyl group (such as a methyl group and / or an ethyl group). For example, it can be a compound such as trimethylgallium (Ga(CH3)3), trimethylaluminum (Al(CH3)3), and / or triethyl phosphate ((C2H5)3PO4), but is not limited thereto.

[0198] A third semiconductor material layer SEM3L is formed on the growth substrate BSUB. In the drawings, the third semiconductor material layer SEM3L is shown as one layer, but the present disclosure is not limited thereto, and a plurality of layers can be formed. The third semiconductor material layer SEM3L can be provided to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the growth substrate BSUB. In one or more embodiments, the third semiconductor material layer SEM3L can include an undoped semiconductor and can be a material that is not doped as an N-type or a P-type. In one or more embodiments, the third semiconductor material layer SEM3L can be undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and / or InN, but is not limited thereto.

[0199] The second semiconductor material layer SEM2L, the active material layer MQWL, and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer SEM3L using the above method. In one or more embodiments, a superlattice material layer can be formed between the second semiconductor material layer SEM2L and the active material layer MQWL. In addition, an electron blocking material layer can be formed between the active material layer MQWL and the first semiconductor material layer SEM1L. In one or more embodiments, a current spreading material layer CSLL can further be included on the first semiconductor material layer SEM1L. The current spreading material layer CSLL can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO) that can transmit light.

[0200] Next, refer to Figure 13 , and the plurality of semiconductor material layers are etched through an etching process using a mask to form a light-emitting element bar LED.

[0201] Specifically, a mask pattern is formed on the first semiconductor material layer SEM1L and the current spreading material layer CSLL. The mask pattern can be a hard mask containing an inorganic material and / or a photoresist mask containing an organic material. The mask pattern prevents the underlying plurality of semiconductor material layers from being etched. Next, a part of the plurality of semiconductor material layers is etched using the plurality of mask patterns as a mask to form a plurality of light-emitting element rods LED.

[0202] The semiconductor material layer can be etched by a conventional method. For example, the process of etching the semiconductor material layer can be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), etc. In the case of the dry etching method, anisotropic etching is possible and can be suitable for vertical etching. When using the above etching methods, the etchant for etching can be Cl2 and / or O2. However, it is not limited thereto.

[0203] The plurality of semiconductor material layers overlapping with the mask pattern are not etched but are formed into the light-emitting element rods LED. Therefore, the light-emitting element rods LED are formed to include the third semiconductor layer SEM3, the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1, and the current spreading layer CSL.

[0204] Next, a protective layer INS and a contact electrode CTE covering the top surface of the light-emitting element rods LED are formed. (S120)

[0205] For example, referring to Figure 14 , a photoresist PR is formed up to the side surfaces of the light-emitting element rods LED. The photoresist PR can be formed to a height lower than that of the light-emitting element rods LED in the third direction DR3. For example, the photoresist PR can be formed to a height lower than that of the first semiconductor layer SEM1 and the active layer MQW of the light-emitting element rods LED and higher than the boundary between the third semiconductor layer SEM3 and the second semiconductor layer SEM2.

[0206] A protective material layer INSL is completely applied to the growth substrate BSUB on which the photoresist PR is formed. The protective material layer INSL can be provided on the top and some side surfaces of the light-emitting element rods LED. Then, the photoresist PR is removed to form a protective layer INS on the top surface and some side surfaces of the light-emitting element rods LED.

[0207] Next, as Figure 15 and Figure 16As shown, a through hole h1 is formed in the protective layer INS on the top surface of the light-emitting element bar LED. Then, an electrode material layer is applied to cover the through hole h1, and then the electrode material layer is etched using a mask to form a contact electrode CTE. The contact electrode CTE can be formed wider than the width of the through hole h1 and narrower than the width of one side of the light-emitting element bar LED.

[0208] Next, referring to Figure 17 , a metal layer ML is formed on the entire surface of the growth substrate BSUB except for the top surface of the light-emitting element bar LED. ( Figure 11 S130 in

[0209] The metal layer ML is a conductive metal and can be provided on the side surface of the light-emitting element bar LED and on the growth substrate BSUB where the light-emitting element bar LED is not provided. In one or more other embodiments, the metal layer ML can be provided on the side surface of the light-emitting element bar LED and on the growth substrate BSUB where there are no multiple light-emitting element bars LED.

[0210] The metal layer ML is around the side surfaces of the multiple light-emitting element bars LED (e.g., surrounding the side surfaces of the multiple light-emitting element bars LED), and can be a common layer provided on the entire surface of the growth substrate BSUB. Thus, the metal layer ML and the multiple light-emitting element bars LED can be electrically connected.

[0211] Thereafter, referring to Figure 18 and Figure 19 , one or more contact pads CPD connected to the metal layer ML can be formed on the growth substrate BSUB. ( Figure 11 S140 in

[0212] Referring to Figure 18 , the contact pad CPD is provided on the metal layer ML, but is not limited thereto. In addition, in one or more embodiments, the contact pad CPD can be omitted.

[0213] One or more contact pads CPD can be formed on the growth substrate BSUB. Referring to Figure 19 , one contact pad CPD is respectively formed on the top side, bottom side, left side, and right side of the growth substrate BSUB, but is not limited thereto. The position, size, or number of the contact pads CPD can be changed according to convenience.

[0214] Referring to Figure 20 , test power can be applied to the contact electrode CTE and the contact pad CPD of the light-emitting element bar LED. ( Figure 11 S150 in

[0215] Before describing the application of the test power, the light-emitting element inspection device will be described with reference to Figure 20 .

[0216] The light-emitting element inspection device may include a contact pad CPD, a power application unit 50, an image sensor 30, and a control unit 60.

[0217] The power application unit 50 includes a plurality of probes 51 and 52, and applies test power to the light-emitting element bars LED to be inspected using the plurality of probes 51 and 52.

[0218] For example, after the first probe 51 of the power application unit 50 contacts the contact electrode CTE and the second probe 52 of the power application unit 50 contacts the contact pad CPD, the power application unit 50 applies test power to the plurality of light-emitting element bars LED through the first probe 51 and the second probe 52. The power application unit 50 can be driven by a signal applied from the outside, and when power is applied, the test power is applied to the plurality of light-emitting element bars LED to be inspected to check whether the plurality of light-emitting element bars LED are defective. When the test power is applied, the normal light-emitting element bars LED can be lit.

[0219] One or more image sensors 30 are provided on one side of the light-emitting element bars LED to acquire an image of the light emitted from the light-emitting element bars LED. The image sensor 30 can be, for example, a camera. Here, the camera can include, but is not limited to, an area scan camera or a line scan camera, and any device that can photograph an object other than a camera can be used.

[0220] The control unit 60 is electrically connected to the image sensor 30 and the power application unit 50 to transmit and receive information. The control unit 60 can control the operations of the image sensor 30 and the power application unit 50. The information transmitted and received by the control unit 60 can include, for example, a reference image for determining defects in the light-emitting element bars LED. Before the inspection, the reference image can be stored in the control unit 60. The control unit 60 can determine lighting defects through the image acquired via the image sensor 30.

[0221] For example, the control unit 60 can determine whether the light-emitting element bars LED are defective by comparing one or more of the brightness and illuminance on the acquired image with a preset standard. For example, if one or more of the brightness and illuminance of any of the light-emitting element bars LED in the acquired image are significantly lower than those of other light-emitting element bars LED, that light-emitting element bar LED can be determined to be defective.

[0222] For example, when a failure is detected in some of the light-emitting element bars LED, a process for removing the corresponding light-emitting element bars LED can be performed separately.

[0223] According to one or more embodiments, a metal layer ML formed on a growth substrate BSUB and a light-emitting element bar LED are electrically connected to check whether the light-emitting element bar LED is defective before being transferred to a circuit board.

[0224] Next, referring to Figure 21 and Figure 22 , the light-emitting element LE on the growth substrate BSUB to be inspected is transferred to a circuit board (e.g., a substrate SUB) ( Figure 11 in S160).

[0225] A pixel circuit PXC and a pixel electrode PXE electrically connected to the pixel circuit PXC may be provided on the circuit board (e.g., the substrate SUB).

[0226] For example, the light-emitting element LE on the growth substrate BSUB to be inspected may be aligned on each pixel electrode PXE. Although the pixel electrode PXE and the light-emitting element LE are shown to have a one-to-one correspondence, this is only an example for explanation, and multiple light-emitting elements LE may be provided on one pixel electrode PXE.

[0227] Thereafter, the contact electrode CTE of the light-emitting element LE is bonded by contacting the pixel electrode PXE of the circuit board (e.g., the substrate SUB).

[0228] For example, by irradiating the contact electrode CTE with a laser to heat the contact electrode CTE to the melting temperature of the contact electrode CTE, the circuit board (e.g., the substrate SUB) and the contact electrode CTE may be pressure-melted and bonded. Here, in the pressure-melting bond, the contact electrode CTE is heated and melted by the irradiation of the laser, and the light-emitting element LE and the pixel electrode PXE are melted and mixed, and are cooled to a solid state when the laser supply is terminated. Although the melted and mixed state is cooled and solidified, the conductivity of the light-emitting element LE and the pixel electrode PXE is maintained, so that the pixel electrode PXE and the light-emitting element LE can be electrically connected and physically connected, respectively. In one or more embodiments, an example of irradiating the contact electrode CTE with a laser has been described, but the bonding may be performed by adding a separate connection electrode between the contact electrode CTE and the pixel electrode PXE.

[0229] After that, a laser is irradiated onto the growth substrate BSUB to separate the growth substrate BSUB from the plurality of light-emitting elements LE. The growth substrate BSUB may be separated by a laser lift-off (LLO) process. The laser lift-off process uses a laser, and a KrF excimer laser (248 nm wavelength) may be used as a source. The energy density of the excimer laser is in the range of about 550 mJ / cm 2 to 950 mJ / cm 2 and the incident area may be 50×50 μm 2in the range of 1×1 cm or less, but not limited thereto. By irradiating a laser to the growth substrate BSUB, the growth substrate BSUB can be separated from the light-emitting element LE. In one or more embodiments, the light-emitting element LE on the growth substrate BSUB is directly transferred to a circuit board (e.g., the substrate SUB), but the present disclosure is not limited thereto. For example, the light-emitting element LE on the growth substrate BSUB can be transferred to a separate relay substrate and then transferred to the circuit board (e.g., the substrate SUB). 2 The light-emitting element LE transferred to the circuit board (e.g., the substrate SUB) can be arranged on the circuit board (e.g., the substrate SUB) in the reverse order of its growth on the growth substrate BSUB. For example, the current spreading layer CSL, the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3 can be sequentially stacked on the pixel electrode PXE.

[0230] Next, referring to

[0231] Next, referring to Figure 23 , a common electrode CE is formed to contact the metal layer ML side of the light-emitting element LE ( Figure 11 S170 in

[0232] For example, a third organic layer 191 is formed on the side surface of the light-emitting element LE. The third organic layer 191 can be referred to as a planarization film because it planarizes the steps between the light-emitting elements LE. The third organic layer 191 can be formed of an inorganic film such as silicon oxide (SiO2), aluminum oxide (Al2O3), and / or hafnium oxide (HfO x ), but not limited thereto. The third organic layer 191 is formed to have a thickness lower than the height of the light-emitting element LE so that one end of the light-emitting element LE is exposed. For example, it can be formed by applying a coating to cover all of the plurality of light-emitting elements LE and then patterning them using a mask pattern to expose the upper layer of the plurality of light-emitting elements LE.

[0233] Next, a common electrode CE is formed on the third organic layer 191. The common electrode CE can be in direct contact with the metal layer ML of the light-emitting element LE on the side surface of the light-emitting element LE. The common electrode CE can have an opening on the light-emitting element LE. The common electrode CE can include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu). In addition, the common electrode CE can be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO), but the common electrode CE can be non-transparent because it has an opening on the top surface of the light-emitting element LE.

[0234] Then, referring to Figure 24, a light blocking layer BM, a first light conversion layer QDL1, a second light conversion layer QDL2, a light transmissive layer TPL, and color filters CF1, CF2, and CF3 are formed.

[0235] For example, a first capping layer CAP1 is formed on a common electrode CE, a first light blocking layer BM1 is formed on the first capping layer CAP1, and a second light blocking layer BM2 is formed on the first light blocking layer BM1. The first light blocking layer BM1 and the second light blocking layer BM2 may overlap with the bank layer 190 in a third direction DR3 and may not overlap with the plurality of light emitting elements LE. The length of the first light blocking layer BM1 in a first direction DR1 or a second direction DR2 may be wider than the length of the second light blocking layer BM2 in the first direction DR1 or the second direction DR2.

[0236] Then, a second capping layer CAP2 is formed on the first capping layer CAP1 and the light blocking layer BM, and a reflective layer RF is formed on the second capping layer CAP2 provided on side surfaces of the first light blocking layer BM1 and the second light blocking layer BM2.

[0237] Then, in a region separated from the first light blocking layer BM1 and the second light blocking layer BM2, a first light conversion layer QDL1 is formed in a region corresponding to the first sub-pixel SPX1, a second light conversion layer QDL2 is formed in a region corresponding to the second sub-pixel SPX2, and a light transmissive layer TPL is formed in a region corresponding to the third sub-pixel SPX3.

[0238] Then, a third capping layer CAP3 is formed on the second capping layer CAP2, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmissive layer TPL, and a fourth organic layer 193 is formed on the third capping layer CAP3.

[0239] Then, a plurality of color filters CF1, CF2, and CF3 are formed on the fourth organic layer 193, and a fifth organic layer 194 is formed on the plurality of color filters CF1, CF2, and CF3.

[0240] Figure 25 is a cross-sectional view showing steps of an inspection process of a light emitting element inspection method according to one or more embodiments. Figure 25 corresponds to Figure 9 of the light emitting element inspection method for the light emitting element LE.

[0241] Refer to Figure 25, a metal layer ML can be disposed on the entire surface of a growth substrate BSUB, around at least a portion of the third semiconductor layer SEM3 and the second semiconductor layer SEM2 (e.g., surrounding them), and in direct contact with some portions of the side surfaces of the light-emitting element LE. A contact pad CPD can be formed to be in direct contact with the metal layer ML. Defects in the light-emitting element LE can be inspected by applying a test voltage to one or more contact pads CPD and contact electrodes CTE.

[0242] Figures 26 to 28 is a cross-sectional view showing each step of an inspection process of a method for inspecting a light-emitting element according to one or more embodiments. Figures 26 to 28 corresponds to Figure 10 of the light-emitting element inspection method for the light-emitting element LE.

[0243] Refer to Figure 26 , a photoresist PR can be formed on the growth substrate BSUB at a height in a third direction DR3 below the boundary between the second semiconductor layer SEM2 and the third semiconductor layer SEM3 of the light-emitting element LE.

[0244] The photoresist PR can be disposed on the formed growth substrate BSUB, in direct contact with at least a portion of the third semiconductor layer SEM3 of the light-emitting element LE and around at least a portion of the third semiconductor layer SEM3 of the light-emitting element LE (e.g., surrounding at least a portion of the third semiconductor layer SEM3 of the light-emitting element LE), and can be disposed on the entire surface of the growth substrate BSUB. Next, the metal layer ML and the base pad CPD can be formed, and then defects in the light-emitting element LE can be inspected by applying a test voltage to one or more contact pads CPD and contact electrodes CTE.

[0245] Then, as Figure 27 shown, the photoresist PR can be removed. At this time, as the photoresist PR is removed, the metal layer ML formed on the photoresist PR is removed, and only the metal layer ML disposed on the side surface of the light-emitting element LE remains. Thus, the metal layers ML disposed on the side surfaces of each light-emitting element LE are electrically separated from each other.

[0246] As Figure 28 shown, a cover protective layer CINS can be formed on the metal layer ML and the protective layer INS around the side surfaces of the plurality of semiconductor layers and the side surfaces and top surface of the current spreading layer CSL (e.g., surrounding them). For example, the cover protective layer CINS can be entirely applied to the growth substrate BSUB on which the metal layer ML is formed.

[0247] However, aspects of the present disclosure are not limited to those set forth herein. By reference to the claims and their functional equivalents included therein, the above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

Claims

1. Light-emitting component inspection method, including: forming a plurality of light emitting element rods by etching a plurality of semiconductor material layers stacked on a growth substrate; forming a protective layer covering a portion of the top surface and a portion of the side surface of the plurality of light emitting element rods and forming a contact electrode on the protective layer; forming a metal layer on the side surfaces of the plurality of light emitting element rods and on a portion of the growth substrate where the plurality of light emitting element rods are not provided; forming a contact pad connected to the metal layer on the growth substrate; as well as A test power is applied to the contact electrode and the contact pad.

2. The light emitting element inspection method according to claim 1, wherein forming the plurality of light emitting element rods comprises: sequentially forming a third semiconductor material layer, a second semiconductor material layer, an active material layer and a first semiconductor material layer on the growth substrate; as well as The third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer are patterned to form the plurality of light emitting element rods.

3. The light emitting element inspection method according to claim 2, wherein: Forming the protective layer covering the portion of the top surface and the portion of the side surface of the plurality of light emitting element rods and forming the contact electrode on the protective layer includes: forming a photoresist covering at least a portion of the second semiconductor material layer on the entire surface of the growth substrate; applying a layer of protective material covering the plurality of light emitting element rods and the photoresist; forming the protective layer covering the top surfaces of the plurality of light emitting element rods and the side surfaces of the first semiconductor material layer and the active material layer; and A through hole is formed in a portion of the protective layer on the top surface of each of the plurality of light emitting element rods, and the contact electrode is formed covering the through hole.

4. The light emitting element inspection method according to claim 3, wherein: Forming the metal layer on the side surfaces of the plurality of light emitting element bars and on the portion of the growth substrate where the plurality of light emitting element bars are not disposed comprises: The metal layer is formed on the entire surface of the growth substrate except the top surface of the plurality of light emitting element bars using a mask, the metal layer directly contacts the second semiconductor material layer of the plurality of light emitting element bars and is connected to the plurality of light emitting element bars.

5. The light emitting element inspection method according to claim 1, wherein: Applying the test power to the contact electrode and the contact pad includes: supplying the test power to at least a portion of the plurality of light emitting element rods using a probe on one side of the plurality of light emitting element rods; acquiring an image of light emitted from the plurality of light emitting element bars by an image sensor, the test power being supplied to the other side of the plurality of light emitting element bars; and Whether the plurality of light emitting element rods are defective is determined by comparing the acquired image with a pre-stored reference image through the control portion.

6. A method for manufacturing a display device, comprising: forming a plurality of light emitting element rods by etching a plurality of semiconductor material layers stacked on a growth substrate; forming a protective layer covering a portion of the top surface and a portion of the side surface of the plurality of light emitting element rods and forming a contact electrode on the protective layer; forming a metal layer on the side surfaces of the plurality of light emitting element rods and on a portion of the growth substrate where the plurality of light emitting element rods are not provided; forming a contact pad connected to the metal layer on the growth substrate; applying a test power to the contact electrode and the contact pad; transferring a plurality of light emitting elements including the plurality of light emitting element rods, the protective layer and the metal layer to a circuit board; as well as A common electrode is formed on side surfaces of the plurality of light emitting elements to contact the metal layer of the plurality of light emitting elements.

7. The method for manufacturing a display device according to claim 6, wherein: Forming the plurality of light emitting element bars comprises: sequentially forming a third semiconductor material layer, a second semiconductor material layer, an active material layer and a first semiconductor material layer on the growth substrate; and The plurality of light emitting element rods are formed by patterning the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer.

8. The method for manufacturing a display device according to claim 7, wherein: Forming the protective layer covering the portion of the top surface and the portion of the side surface of the plurality of light emitting element rods and forming the contact electrode on the protective layer includes: forming a photoresist covering at least a portion of the second semiconductor material layer on the entire surface of the growth substrate; applying a layer of protective material covering the plurality of light emitting element rods and the photoresist; forming the protective layer covering the top surfaces of the plurality of light emitting element rods and the side surfaces of the first semiconductor material layer and the active material layer; and A through hole is formed in a portion of the protective layer on the top surface of each of the plurality of light emitting element rods, and the contact electrode is formed covering the through hole.

9. The method for manufacturing a display device according to claim 8, wherein: Forming the metal layer on the side surfaces of the plurality of light emitting element bars and on the portion of the growth substrate where the plurality of light emitting element bars are not disposed comprises: The metal layer is formed on the entire surface of the growth substrate except the top surface of the plurality of light emitting element bars using a mask, the metal layer directly contacts the second semiconductor material layer of the plurality of light emitting element bars and is connected to the plurality of light emitting element bars.

10. The method for manufacturing a display device according to claim 8, wherein: Forming the metal layer on the side surfaces of the plurality of light emitting element bars and on the portion of the growth substrate where the plurality of light emitting element bars are not disposed comprises: forming the photoresist covering at least a portion of the third semiconductor material layer on the entire surface of the growth substrate; and The metal layer is formed to cover the plurality of light emitting element rods and the photoresist.

11. The method for manufacturing a display device according to claim 10, wherein: Between applying the test power and transferring the plurality of light emitting elements to the circuit board, the method further includes: removing the photoresist; forming a covering protective layer around the side surfaces and the top surfaces of the plurality of light emitting element rods; and An opening exposing the contact electrode is formed in the cover protection layer.

12. The method for manufacturing a display device according to claim 6, wherein: A plurality of pixel circuit parts are on the circuit board, wherein each of the plurality of pixel circuit parts comprises a pixel electrode located at a top surface of the plurality of pixel circuit parts, and Wherein, transferring the plurality of light emitting elements including the plurality of light emitting element rods, the protective layer and the metal layer to the circuit board comprises: The contact electrode of the light emitting element is placed on the pixel electrode, and the contact electrode is electrically connected and bonded to the circuit board.

13. The method for manufacturing a display device according to claim 12, wherein: The circuit board further comprises a bank around the pixel electrode, wherein the method further comprises: forming a light blocking layer on the common electrode overlapping the bank; In the area divided by the light blocking layer, a first wavelength conversion layer is formed in an area corresponding to a first sub-pixel of the display device, a second wavelength conversion layer is formed in an area corresponding to a second sub-pixel of the display device, and a light-transmitting layer is formed in an area corresponding to a third sub-pixel of the display device; and A first color filter is formed on the first wavelength conversion layer, a second color filter is formed on the second wavelength conversion layer, and a third color filter is formed on the light-transmitting layer.

14. The method for manufacturing a display device according to claim 6, wherein: The common electrode does not overlap with a top surface of the light emitting element.

15. The method for manufacturing a display device according to claim 6, wherein applying the test power to the contact electrode and the contact pad comprises: supplying the test power to at least a portion of the plurality of light emitting element rods using a probe on one side of the plurality of light emitting element rods; acquiring an image of light emitted from the plurality of light emitting element rods by an image sensor, the test power being supplied to the other side of the plurality of light emitting element rods; as well as Whether the plurality of light emitting element rods are defective is determined by comparing the image acquired by the image sensor with a reference image through a control portion.

16. A light emitting element inspection apparatus for inspecting illumination of a plurality of light emitting elements on a growth substrate, the light emitting element inspection apparatus comprising: a contact pad on the growth substrate and electrically connected to the metal layer on the side surfaces of the plurality of light emitting elements and a portion of the growth substrate where the plurality of light emitting elements are not disposed; as well as A probe and power applying section is configured to apply a test power to the contact electrodes of the plurality of light emitting elements and the contact pads through the probe.

17. The light emitting element inspection device according to claim 16, further comprising: an image sensor on one side of the plurality of light emitting elements to acquire an image of light emitted from the plurality of light emitting elements; as well as A control section is configured to determine whether the plurality of light emitting elements are defective by comparing the image acquired by the image sensor with a reference image.

18. The light emitting element inspection device according to claim 16, in, A light emitting element among the plurality of light emitting elements includes a second semiconductor layer, a first semiconductor layer, and an active layer between the second semiconductor layer and the first semiconductor layer, and The metal layer is in direct contact with the second semiconductor layer and is spaced apart from the contact electrode.

19. The light emitting element inspection device according to claim 18, in, The one light emitting element further includes a protective layer around a top surface and a side surface of the first semiconductor layer and a side surface of the active layer, wherein the protective layer comprises a through hole in a portion of the protective layer on the top surface of the first semiconductor layer, and The contact electrode is electrically connected to the first semiconductor layer through the through hole.

20. The light emitting element inspection device according to claim 19, in, The metal layer extends over the protection layer and around the side surfaces of the first semiconductor layer and the active layer.

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