Memory device and operating method for generating checkpoints based on write data pattern

Abstract

The invention relates to a memory system. A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks. The controller identifies a change in a mode of the plurality of write data, delays a checkpoint operation associated with a write operation with respect to the plurality of write data entries when a size of operational data with respect to the plurality of write data entries is within a range that can be stored in the buffer, and delays a checkpoint operation associated with a write operation with respect to the plurality of write data entries when the size of the operational data exceeds the range. And executing check point operation.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10 - 2023 - 0185748, filed on December 19, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of the present disclosure described herein relate to a memory system and an operating method thereof, and more particularly, to an apparatus and method for generating a checkpoint based on a write data pattern. Background Art

[0004] A data processing system includes a memory system or a data storage device. The data processing system can be developed to store a larger amount of data in the data storage device, store data in the data storage device faster, and read data stored in the data storage device faster. The memory system or the data storage device can include non - volatile memory cells and / or volatile memory cells for storing data.

[0005] The memory system can generate checkpoint data during a data input / output operation. The memory system may abnormally terminate its operation due to a sudden power - off (SPO). In this case, when the power supply is restored, the memory system can resume its operation state before the sudden power - off (SPO) based on the checkpoint data. Summary of the Invention

[0006] Embodiments of the present disclosure can provide a memory system including a memory device, a data processing system including the memory system, and an operation process or method that can quickly and reliably process data into the memory device by reducing the operation complexity and performance degradation of the memory system, thereby improving the usage efficiency of the memory device.

[0007] Embodiments of the present disclosure can provide an apparatus or method for improving the data input / output performance of a memory system by delaying mapping data update operations or checkpoint operations based on patterns of multiple write data entries.

[0008] In addition, embodiments of the present invention can provide an apparatus or method for avoiding or reducing problems such as buffer overflow or overrun that may occur during a recovery operation, even when there is a size difference between a first buffer for data input or output operations and a second buffer for sudden - power - off recovery (SPOR) performed when power is supplied after a sudden power - off (SPO). In an embodiment, an operation for storing operation data regarding multiple write data entries before a sudden power - off (SPO) can be performed based on the size of the second buffer.

[0009] Embodiments of the present invention may provide a memory system, including: a memory device including a plurality of memory blocks; and a controller configured to identify a pattern change of a plurality of write data entries, delay a checkpoint operation associated with a write operation on the plurality of write data entries when a size of operation data on the plurality of write data entries is within a range that can be stored in a buffer, and perform a checkpoint operation when the size of the operation data exceeds the range.

[0010] The checkpoint operation may include an operation of adding operation data on at least one write entry that has been stored in the memory device among the plurality of write data entries to log data.

[0011] The pattern may change from sequential data entries to random data entries.

[0012] The operation data may include information on a logical address and a physical address associated with the random data entries.

[0013] The operation data may include count information on how many sequential data entries have been stored in the memory device.

[0014] The range may be determined based on a size of the buffer established for a recovery operation performed after a sudden power outage (SPO), a size of mapping data on sequential data entries existing before the sudden power outage, and a size of mapping data for the recovery operation.

[0015] In the memory system, a first number of maximum sequential data entries and a second number of maximum random data entries programmed in the memory device during a continuous write operation are determined based on the size of the buffer. The first number may be greater than the second number.

[0016] The controller may be further configured to: store checkpoint information in the log data through a checkpoint operation; and restore a plurality of write data entries based on the checkpoint information when power is supplied after a sudden power outage (SPO).

[0017] The controller may be configured to, after power is supplied, when a pattern change is identified through the checkpoint information, add operation data corresponding to the random data entries to mapping data of the sequential data entries.

[0018] The controller may be configured to record the random data entries as the first entry of new sequential data entries in a spare area of the mapping data based on the operation data corresponding to the random data entries.

[0019] The controller may be configured to skip a data scan for an open memory block based on the count information on the sequential data entries included in the checkpoint information.

[0020] Another embodiment of the present invention may provide a method for operating a memory system, including: identifying a change in a pattern of a plurality of write data entries input from an external device and programmed in a memory device, the memory device including a plurality of memory blocks; determining whether a size of operation data regarding the plurality of write data entries is within a range that can be stored in a buffer; when the size of the operation data is within the range, delaying a checkpoint operation associated with a write operation regarding the plurality of write data entries; and when the size of the operation data exceeds the range, performing the checkpoint operation.

[0021] The checkpoint operation may include an operation of adding operation data regarding at least one write entry already stored in the memory device among the plurality of write data entries to log data.

[0022] The pattern may change from sequential data entries to random data entries.

[0023] The operation data may include information regarding a logical address and a physical address associated with the random data entries, and count information on how many sequential data entries have been stored in the memory device.

[0024] The range may be determined based on a size of the buffer established for a recovery operation performed after a sudden power outage (SPO), a size of mapping data regarding sequential data entries existing before the sudden power outage, and a size of mapping data for the recovery operation. The first number of the maximum sequential data entries programmed in the memory device and the second number of the maximum random data entries during continuous write operations may be determined based on the size of the buffer. The first number may be greater than the second number.

[0025] The method may further include: storing checkpoint information in the log data through the checkpoint operation; and when power is supplied after a sudden power outage (SPO), restoring the plurality of write data entries based on the checkpoint information.

[0026] Restoring the plurality of write data entries may include: after power is supplied, when a pattern change is identified through the checkpoint information, adding operation data corresponding to the random data entries to mapping data of the sequential data entries.

[0027] Adding the operation data may include: based on the operation data corresponding to the random data entries, recording the random data entries as the first entry of new sequential data entries in a spare area of the mapping data.

[0028] Restoring the plurality of write data entries may include: skipping a data scan for open memory blocks based on the count information regarding the sequential data entries included in the checkpoint information. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The description herein refers to the accompanying drawings, in which like reference numerals indicate like parts in the drawings.

[0030] Figure 1 A memory system according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A checkpoint operation and a recovery operation according to an embodiment of the present disclosure are shown.

[0032] Figure 3 Operations performed in a memory system according to another embodiment of the present disclosure are shown.

[0033] Figure 4 A recovery operation performed in a memory system according to another embodiment of the present disclosure is shown.

[0034] Figure 5 Operations performed in a memory system according to another embodiment of the present disclosure are shown.

[0035] Figure 6 A recovery operation performed in a memory system according to another embodiment of the present disclosure is shown.

[0036] Figure 7 Operations of a memory system according to an embodiment of the present disclosure are shown.

[0037] Figure 8 A data processing system according to another embodiment of the present disclosure is shown.

[0038] Figure 9 A memory system according to another embodiment of the present disclosure is shown. Detailed Description

[0039] Various embodiments of the present disclosure will be described below with reference to the accompanying drawings. However, the elements and features of the present disclosure can be configured or arranged differently to form other embodiments, which can be any variation of the disclosed embodiments.

[0040] In the present disclosure, various features (e.g., elements, structures, modules, components, steps, operations, features, etc.) included in "one embodiment", "example embodiment", "embodiment", "another embodiment", "some embodiments", "various embodiments", "other embodiments", "optional embodiments", etc. are intended to indicate that any such feature is included in one or more embodiments of the present disclosure, but can be combined in the same embodiment or not necessarily combined in the same embodiment.

[0041] In the present disclosure, the terms "comprising", "comprises", "including", and "includes" are open-ended. As used in the appended claims, these terms specify the presence of the stated elements and do not preclude the presence or addition of one or more other elements. The terms in the claims do not prohibit the device from including other components, such as interface units, circuits, etc.

[0042] In the present disclosure, various units, circuits, or other components may be described or claimed as "configured to" perform one or more tasks. In such cases, "configured to" is used to imply structure by indicating that the block / unit / circuit / component includes the structure (e.g., circuitry) that performs one or more tasks during operation. Thus, even if the specified block / unit / circuit / component is not currently operational, such as being turned on or activated, it can be said that the block / unit / circuit / component is configured to perform the task. Examples of blocks / units / circuits / components using the "configured to" language include hardware, circuitry, memory storing program instructions executable to implement the operations, etc. Additionally, "configured to" may include general structures, such as general-purpose circuitry, manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the relevant tasks. "Configured to" may also include adjusting a manufacturing process, such as a semiconductor manufacturing device, to fabricate a device suitable for implementing or performing one or more tasks, such as an integrated circuit.

[0043] In the present disclosure, the terms "machine", "circuit", or "logic" refer to all of the following: (a) pure hardware circuit implementations, such as those implemented only in analog and / or digital circuitry; and (b) combinations of circuitry with software and / or firmware, such as (where applicable): (i) combinations of processors or (ii) portions of processors / software, including digital signal processors, software, and memory, that together cause a device such as a mobile phone or a server to perform various functions; (c) circuitry that requires software or firmware for operation, such as a microprocessor or a portion of a microprocessor, even if the software or firmware is not actually present. This definition of "machine", "circuit", or "logic" applies to all uses of the term in this application, including its use in any claims. As a further example, as used in this application, the terms "machine", "circuit", or "logic" also encompass implementations consisting solely of one processor or multiple processors or portions of processors and their (or their) attendant software and / or firmware. For example, in the case of a particular claim element, the terms "machine", "circuit", or "logic" also encompass an integrated circuit for a storage device.

[0044] As used herein, the terms "first", "second", "third", etc. are used as labels for the nouns preceding them and do not imply any type of ordering, such as spatial, temporal, logical, etc. The terms "first" and "second" do not necessarily imply that the first value must be written before the second value. Additionally, although terms are used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that otherwise has the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0045] Furthermore, the term "based on" is used to describe one or more factors that affect a determination. This term does not exclude other factors that may affect the determination. That is, the determination can be based entirely on those factors, or at least partially on those factors. Consider the phrase "determine A based on B". Although in this case, B is a factor that affects the determination of A, such a phrase does not exclude the determination of A also being based on C. In other cases, A can be determined based only on B.

[0046] Herein, a data entry, an entry of data, an item of data, or a data item can be a sequence of bits. For example, a data entry can include the content of a file, a part of a file, a page in a memory, an object in an object-oriented program, digital information, a part of a digital scanned image, a video or audio signal, metadata, or any other entity that can be represented by a sequence of bits. According to an embodiment, a data entry can include discrete objects. According to another embodiment, a data entry can include an information unit that is processed or disposed of for a data input / output operation. According to another embodiment, a data entry can include an information unit within a data packet transmitted between two different components.

[0047] Embodiments will now be described with reference to the accompanying drawings, where like reference numerals refer to like elements.

[0048] Figure 1 A memory system according to an embodiment of the present disclosure is shown.

[0049] Referring Figure 1 , the memory system 110 can include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 can be regarded as physically separate components or elements. The memory device 150 and the controller 130 can be connected by at least one data path. For example, the data path can include a channel and / or a passageway.

[0050] According to an embodiment, the memory device 150 and the controller 130 may be functionally separate components or elements. In addition, according to an embodiment, the memory device 150 and the controller 130 may be implemented using a single chip or multiple chips. The memory device 150 may include a plurality of memory blocks. A memory block may be understood as a group of non-volatile memory cells that remove data together through a single erase operation. A memory block may include a plurality of pages. According to an embodiment, each page may be understood as a group of non-volatile memory cells that store data together during a single programming operation or output data together during a single read operation.

[0051] The memory device 150 may include a plurality of memory planes or a plurality of memory dies. According to an embodiment, a memory plane may be regarded as a logical partition or a physical partition, including at least one memory block, a driving circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells.

[0052] In addition, according to an embodiment, a memory die may include at least one memory plane. A memory die may be understood as a group of components implemented on a physically distinguishable substrate. Each memory die may be connected to the controller 130 through a data path. Each memory die may include an interface for exchanging data entries and signals with the controller 130.

[0053] According to an embodiment, the memory device 150 may include at least one memory block, at least one memory plane, or at least one memory die. Figure 1 The internal configuration of the memory device 150 shown may vary according to the performance of the memory system 110. Embodiments of the present disclosure are not limited to Figure 1 the internal configuration shown.

[0054] To an external device (e.g., see Figures 8 - 9The write data entry requested by the host 102 is stored in the memory device 150 (e.g., a storage space including non-volatile memory cells), and the memory system 110 can perform address translation between the file system used by the host 102 and the physical location of the storage space including non-volatile memory cells. For example, the data address determined according to the file system used by the host 102 can be referred to as a logical address or a logical block address, while the address of the physical location where the data entry is stored in the storage space can be referred to as a physical address or a physical block address. When the host 102 transmits a logical address together with a read request or a read command to the memory system 110, the memory system 110 searches for the physical address associated with the logical address, reads the data entry stored at the location identified by the physical address, and outputs the read data entry to the host 102. During this process, address translation can be performed in the memory system 110 to search for the physical address associated with the logical address input from the host 102.

[0055] The controller 130 can perform data input / output operations in response to a request or command input from an external device. For example, when the controller 130 performs a read operation in response to a read request or a read command input from an external device, the data entry stored in the plurality of non-volatile memory cells included in the memory device 150 is transmitted to the controller 130. For the read operation, the input / output controller 192 can perform address translation on the logical address input from the external device to obtain the physical address, and then transmit a read command to the memory device 150 corresponding to the physical address through the transceiver 198. The transceiver 198 can transmit the read command to the memory device 150 and receive the data entry corresponding to the physical address output from the memory device 150. The transceiver 198 can store the data entry transmitted from the memory device 150 in the memory 144. The input / output controller 192 can output the data entry stored in the memory 144 to the external device in response to the read request or the read command.

[0056] In addition, the input / output controller 192 can transmit the write data entry and the write request or write command from the external device to the memory device 150 through the transceiver 198. After the data is stored in the memory device 150, the input / output controller 192 can transmit a response corresponding to the write request or write command to the external device. The input / output controller 192 can update the mapping data that associates the physical address with the logical address input together with the write request or write command, and the physical address indicates the location in the memory device 150 where the write data entry is stored.

[0057] When the input / output controller 192 performs a data input / output operation, the write operation checker 194 can determine an operation mode regarding a write request (or write command) input from an external device and a plurality of write data entries. For example, the write operation checker 194 can determine whether a plurality of write requests transmitted by the external device are associated with sequential data entries or random data entries. When the write operation checker 194 determines a mode regarding an operation performed in the memory system 110, the input / output controller 192 can arrange operations corresponding to a plurality of requests or commands received from the external device based on the mode. For example, when a mixed request or command of sequential data entries and random data entries is input, the input / output controller 192 can classify or arrange each of the mixed requests or commands based on the mode determined by the write operation checker 194 so as to adjust or change an order of operations to be performed corresponding to the mixed requests or commands. In one embodiment, when a plurality of requests or commands for sequential data entries are mixed with random data entries, the input / output controller 192 can perform operations associated with at least some of the plurality of requests or commands for sequential data entries earlier than an operation corresponding to another one of the plurality of requests or commands for random data entries, so as to improve data input / output performance of the memory system 110.

[0058] The operation data controller 196 can perform a checkpoint operation at a preset period or preset operation conditions. Herein, the checkpoint operation can be used to ensure consistency and stability of data entries stored in the memory device 150. The checkpoint operation can save a current working or operation state to avoid or prevent data loss in the case of problems such as system failure or crash when performing a long task such as a continuous programming operation on a large number of write data entries. For example, if the memory system 110 crashes while writing a specific data entry to the memory device 150, all operations completed so far may be lost. To avoid such a problem, the current operation state can be saved at a specific time interval or specific operation conditions through the checkpoint operation. When checkpoint information is saved through the checkpoint operation, even if the memory system 110 fails, only the data entries after the most recently saved checkpoint need to be reprocessed, thereby greatly reducing data loss in the memory system 110.

[0059] The checkpoint operation can be used to maintain data consistency. For example, in the case where a plurality of storage blocks should be updated simultaneously, it is difficult to confirm whether the update task is completed before all storage blocks are updated. In this case, the checkpoint operation can be used to set a checkpoint before or after the update for all storage blocks. Even if a problem occurs after the checkpoint is set, the memory system can roll back to any one of the operation states corresponding to the checkpoint to maintain data consistency in the memory system 110.

[0060] According to an embodiment, based on a pattern regarding a plurality of commands (CMD) and a plurality of write data entries (WD) identified or determined by the write operation checker 194, the data controller 196 may determine whether to perform a checkpoint operation. Herein, the checkpoint operation may include an operation of updating mapping data regarding data entries stored in the memory device 150. The checkpoint operation and the mapping data may be used to support data stability and consistency. The mapping data is a kind of information for the controller 130 to track the physical locations of data entries stored in the memory device 150. Through the checkpoint operation performed at any point, the memory system 110 may store the state (or operation state) of the data entries in a timely manner. The checkpoint information generated and stored during the checkpoint operation may include the mapping data, which may indicate the physical location or state of the data entries. Since the mapping data may be stored together when the checkpoint information is generated or updated, even if the memory system 110 suddenly becomes inoperable, data consistency may be maintained through a rollback operation based on the checkpoint information. In addition, when a situation such as a sudden power failure occurs in the memory system 110, the memory system 110 may, after restarting (i.e., after power is supplied), based on the mapping data stored through the checkpoint operation, find the physical locations of the data entries stored before the sudden power failure. The stored data entries may be repaired or restored, thereby avoiding data loss.

[0061] The mapping data may include a plurality of mapping entries regarding mapping information, and each mapping entry may associate a logical address with a physical address, or may associate a physical address with a logical address. The mapping information is used as operation information for data input / output operations performed by the controller 130. For example, the input / output controller 192 may use the mapping entries for address translation, and the mapping entries may be updated or generated after data corresponding to a write request or a write command is programmed in the memory device 150. According to an embodiment, the mapping data may be classified into first mapping data (e.g., logical-to-physical (L2P) table) for associating a logical address with a physical address and second mapping data (e.g., physical-to-logical (P2L) table) for associating a physical address with a logical address. The mapping data controller 196 may determine or change the data structure of the first mapping data or the second mapping data loaded or generated in the memory 144.

[0062] According to an embodiment, mapping entries included in the first mapping data or the second mapping data stored in the memory device 150 may be stored to associate a single logical address with a single physical address. A plurality of mapping entries may constitute a single mapping segment. A mapping segment may be regarded as a unit composed of the mapping data stored in the memory device 150. After the controller 130 loads at least some portions of the first mapping data or the second mapping data from the memory device 150 and stores them in the memory 144, the controller 130 may utilize the loaded information to perform data input / output operations. When sufficient space is temporarily allocated in the memory 144 for the first mapping data and the second mapping data, a process of changing the data structure or shape of the first mapping data or the second mapping data may cause unnecessary overhead. However, the storage capacity of the memory 144 in the memory system 110 may be limited. When the space allocated for temporarily storing the first mapping data and the second mapping data including a plurality of mapping entries decreases, more space in the memory 144 may be allocated and used for other purposes, such as data input / output operations.

[0063] According to an embodiment, first mapping data (e.g., an L2P table) including a plurality of first mapping entries (e.g., logical-to-physical (L2P) information) for associating logical addresses with physical addresses may be stored in the memory device 150. However, the controller 130 may generate second mapping data (a P2L table) that includes a plurality of second mapping entries (e.g., physical-to-logical (P2L) information) generated through a plurality of data input / output operations for associating physical addresses with logical addresses.

[0064] For example, after the controller 130 programs a new user data entry into the memory device 150, the controller 130 may generate a second mapping entry (P2L) for linking a physical address (indicating the location where the new user data entry is programmed) to a logical address input from the host 102 and corresponding to the new user data entry. The second mapping entry P2L in the memory 144 may provide an indication of the most recent location of the data stored in the memory device 150. In one case, it may be assumed that a first mapping entry L2P indicates that a specific logical address (e.g., "0A0") and a first physical address (e.g., "123") in the first mapping data (L2P table) loaded into the memory 144 are associated with each other.

[0065] After the controller 130 performs a subsequent programming operation on new data corresponding to the same logical address (e.g., "0A0"), the controller 130 may generate a second mapping entry (P2L) in the memory 144. The second mapping entry (P2L) may associate the logical address (e.g., "0A0") with a second physical address (e.g., "876"), where the second physical address indicates the location where the new data is stored by the programming operation. In this case, the controller 130 may identify that the first mapping entry L2P stored in the first mapping data (L2P table) is old and the second mapping entry P2L is the latest, i.e., the most recent mapping entry. The controller 130 may update the first mapping data (L2P table) stored in the memory device 150 based on the second mapping entry P2L.

[0066] As described above, the controller 130 may perform a mapping flush (e.g., an operation for updating the first mapping data (L2P table) stored in the memory device 150) periodically, intermittently, or as needed. After performing the mapping flush, the second mapping data P2L table including the second mapping entry P2L in the memory 144 may be deleted or destroyed. When an operation for programming data is performed in the memory device 150 after performing the mapping flush, the controller 130 may generate new second mapping data (P2L table).

[0067] The timing for performing a checkpoint operation including mapping data update may be determined differently according to embodiments. For example, when the controller 130 performs 10 programming operations, the controller 130 may determine that mapping data update (or mapping flush) should be performed. For example, when the space allocated for the second mapping data (P2L table) is full and a new second mapping entry P2L cannot be added to the space, the controller 130 may determine that mapping data update should be performed. For example, according to an embodiment, the controller 130 may determine to perform mapping data update every predetermined time period (e.g., 1 hour, 10 minutes, 1 minute, etc.).

[0068] For example, when the memory system 110 has an independent address system (e.g., a physical address distinguishable from the logical address) not adopted by an external device such as the host 102, a checkpoint operation including mapping data update is an operation that can be performed in the memory system 110. The external device does not have to request mapping data update at the memory system 110. The memory system 110 independently performs mapping data update, so data input / output operations may be delayed during mapping data update. From the perspective of the external device, mapping data update in the memory system 110 may be recognized as overhead. Therefore, when mapping data update is too frequent, data input / output performance may degrade.

[0069] The size of the memory 144 can be restricted. The memory 144 includes a buffer established for storing checkpoint information and mapping data. According to an embodiment, the performance of the checkpoint operation can be determined based on the buffer size limit. The buffer set in the memory 144 is generally a space for temporarily storing data. When the space becomes full, the memory system 110 should move the completed data to the memory device 150 which is a non-volatile storage device. The period of the checkpoint operation can be determined based on the size of the buffer. If the period of the checkpoint operation is set too long, there may not be enough space in the buffer. This may increase the risk of data loss, or in some severe cases, may lead to a decline in the performance of the memory system 110. On the contrary, if the period of the checkpoint operation is set too short, the overhead may increase, which may have a negative impact on the operation performance of the memory system 110. Therefore, when the period of the checkpoint operation is appropriately adjusted according to the size of the buffer, the usage pattern of the buffer, and the requirements of the memory system 110, the performance of the memory system 110 can be optimized while ensuring data stability.

[0070] According to an embodiment, the checkpoint operation can store or add checkpoint information in the logged data. The checkpoint operation and logging can be performed in the memory system 110 to ensure data consistency and stability. Logging can involve recording the upcoming changes in a log called "logging" first before changing the state or storing a data entry in the memory device 150. After that, the data entry can be stored or the state can be changed. If an error occurs during the process of changing or storing a data entry in the memory system 110, the memory system 110 can be restored to the most recently completed consistent state based on the log recorded in the logging. The checkpoint operation and logging can be in a complementary relationship and are mechanisms for ensuring data stability and consistency. The checkpoint operation can store the operation state of the memory system 110 at a specific point in time, and logging can be used to safely perform the changes without losing data by recording the changes.

[0071] Refer to Figure 1, the operation data controller 196 may determine when to perform a checkpoint operation based on a command (CMD) transmitted from an external device or a mode of writing data entries (WD). For example, unlike the case of inputting a plurality of commands with random data entries, when a plurality of commands with sequential data entries transmitted from an external device are input, the operation data controller 196 may compress mapping data related to the sequential data entries. In this case, when a plurality of commands with sequential data entries are input, the time to perform a checkpoint operation may be delayed compared to when a plurality of commands with random data entries are input. When the controller 130 can use more resources to process a plurality of commands with sequential data entries, the data input / output performance of the memory system 110 may be improved.

[0072] Figure 2 FIG. shows a checkpoint operation and a recovery operation according to an embodiment of the present disclosure.

[0073] Referring to Figure 1 and Figure 2 , the memory system 110 may perform a data input / output operation in response to a plurality of commands (CMD) transmitted from an external device. The plurality of commands (CMD) input from the external device may include a write command or a programming command accompanied by write data entries (WD). The operation data controller 196 may manage and store information associated with operations performed within the memory system 110. According to an embodiment, the memory system 110 may perform a checkpoint operation and logging. Examples of the resulting operation data may include checkpoint information CP1 and CP2 and logging data (e.g., log (journal) data).

[0074] As time passes, the memory system 110 may perform a plurality of different operations. During the various operations of the memory system 110, information required for data stability and consistency in the memory system 110 may be stored in log data (e.g., log (journal) data) together with the checkpoint information CP1 and CP2. Referring to Figure 2 , the memory system 110 may add the checkpoint information CP1 and CP2 to the logging data. According to another embodiment, the memory system 110 may store the checkpoint information CP1 and CP2 and the logging data in different regions, respectively.

[0075] The checkpoint information CP1 and CP2 may be generated based on a preset period of the checkpoint operation. That is, a first checkpoint period (CP1 CYCLE) for generating the first checkpoint information (CP1) and a second checkpoint period (CP2 CYCLE) for generating the second checkpoint information (CP2) may be substantially the same.

[0076] However, regardless of whether the time of the checkpoint period is the same, the operations performed in the memory system 110 during the checkpoint period may not be substantially the same. For example, the data input / output operations performed by the memory system 110 during the first checkpoint period (CP1 CYCLE) and the second checkpoint period (CP2 CYCLE) may be different. Although 10M bytes of data entries may be stored in the memory device 150 during the first checkpoint period (CP1 CYCLE), 5M bytes of data entries may be stored in the memory device 150 during the second checkpoint period (CP2 CYCLE). In some cases, although a large number of random data entries may be stored in the memory device 150 during the first checkpoint period (CP1 CYCLE), only sequential data entries (no random data entries) may be stored in the memory device 150 during the second checkpoint period (CP2 CYCLE). When the operations performed in the memory system 110 during each checkpoint period may be different, the amount of operation data maintained and managed by the memory system 110 during each checkpoint period may be different. Therefore, it is more efficient for the memory system 110 to perform the checkpoint operations for generating the checkpoint information CP1 and CP2 when a preset operation condition is satisfied, rather than at each preset period set for performing the checkpoint operations.

[0077] When a sudden power outage (SPO) occurs while the memory system 110 is operating, the memory system 110 can no longer perform normal operations. In this case, the memory system 110 can use an auxiliary power source to store the checkpoint information CP1 and CP2 and log data (e.g., log (journal) data) into a non-volatile memory.

[0078] When power is supplied (Power-On) after a sudden power outage (SPO), the memory system 110 can perform a recovery operation based on the checkpoint information CP1 and CP2. For example, the recovery operation can include updating the mapping data of the data entries that were stored in the memory device 150 before the sudden power outage (SPO) occurred. Through the recovery operation, the memory system 110 can return to the operation state (rollback) before the sudden power outage (SPO) occurred.

[0079] Figure 3 Operations performed in a memory system according to another embodiment of the present disclosure are illustrated. In particular, the operation method of the memory system may include an operation for determining when to perform mapping data update or checkpoint operations during a process of performing a plurality of programming operations for storing a plurality of write data entries in the memory device 150.

[0080] Refer to Figure 3, when there is a write data entry that is the target of a write operation to be performed in the memory device 150, the write operation can be started (step 502).

[0081] An indicator or flag regarding whether the operation data is expanded (fExpansion) is set to "not expanded" (FALSE) (step 504). Here, whether the operation data is expanded indicates whether there is a data entry for which the mapping data stored in the memory device 150 but associated with the stored data entry has not been updated.

[0082] For example, the memory device 150 may store first mapping data (L2P table), and the L2P table includes first mapping entries (logical to physical, L2P) for associating logical addresses with physical addresses. The controller 130 may generate second mapping data (P2L table), and the P2L table includes second mapping entries (physical to logical, P2L) for associating physical addresses with logical addresses during data input / output operations. Mapping data update (step 518) includes the operation of updating the first mapping data (L2P table) or the first mapping entry (L2P) based on the second mapping data (P2L table).

[0083] When the indicator or flag regarding the expansion of the operation data is set to "expanded" (TRUE), the indicator or flag indicates that there is a data entry for which the mapping data needs to be updated. That is, this indicates that second mapping data (P2L table) has been generated for the write data entry during the write operation, but the first mapping data (L2P table) has not been updated based on the second mapping data (P2L table).

[0084] On the other hand, when the indicator or flag regarding the expansion of the operation information is set to "not expanded" (FALSE), the indicator or flag indicates that the first mapping data has been updated for the data entries stored in the memory device 150. That is, this indicates that the first mapping entry (L2P) in the first mapping data (L2P table) has been updated for the corresponding data entries stored in the memory device 150.

[0085] Since the first mapping entry (L2P) is stored in the memory device 150, the corresponding data entry can be retained even without power supply. However, the second mapping data (P2L table) is temporarily stored in the memory 144 and may be lost or corrupted when power is not supplied. Restoring the second mapping data (P2L table) for the data entries stored in the memory device 150 before a power interruption based on the checkpoint information CP1 and CP2 and the log record data (e.g., log record (log) data) is necessary for the memory system 110 to maintain data security and consistency.

[0086] Thereafter, the written data entry is stored in the memory device 150 (step 506).

[0087] After storing the written data entry in the memory device 150 (step 506), the memory system 110 may check whether a second mapping table (e.g., a random P2L table) for the random data entry is available (step 508). Here, when the corresponding random data entry does not affect the continuous write / program operation performed within the memory system 110, the second mapping table (e.g., the random P2L table) for the random data entry may be available. When the memory system 110 holds the continuous write / program operation due to the corresponding random data entry, the controller 130 may determine that the second mapping table (e.g., the random P2L table) for the random data entry will not be available. When the second mapping table (e.g., the random P2L table) for the random data entry is not available (No in step 508), the memory system 110 updates the mapping data before performing the next programming operation (step 518). According to an embodiment, the memory system 110 may perform a checkpoint operation together with updating the mapping data (step 518).

[0088] When the second mapping table (e.g., the random P2L table) for the random data entry is available (Yes in step 508), the memory system 110 may determine whether the operation data can be extended (step 510). When the operation data cannot be extended (No in step 510), the memory system 110 may update the mapping data corresponding to the performed write operation to check whether the size of the mapping data is less than a first reference value (M) (step 524). Here, the first reference value (M) may determine the range repaired or restored by a recovery operation (e.g., a sudden power-off recovery (SPOR) operation) performed when power is supplied (Power-On) after a sudden power-off (SPO). During the process of updating the mapping data, when the size of the mapping data is not less than the first reference value (M) (No in step 524), the memory system 110 may update the mapping data before performing the next programming operation (step 518).

[0089] When the operation data is extensible (Yes in step 510), the memory system 110 may check whether the write operation is for sequential data entries (step 512). Here, checking whether the written data entry is a sequential data entry may include checking whether the written data entry is sequential with the previously programmed data entry. For example, the change in the pattern of the written data entry may be confirmed based on checking whether the written data entry is sequential with the previously programmed data entry. When the write operation is not for sequential data entries (No in step 512), the memory system 110 may update the mapping data corresponding to the write operation to check whether the size of the mapping data is less than a first reference value (M) (step 524). Here, the first reference value (M) may be the range recovered by a recovery operation (e.g., a sudden power-off recovery (SPOR) operation) when power is supplied (Power-On) after a sudden power-off (SPO). When updating the mapping data, when the size of the mapping data is not less than the first reference value (M) (No in step 524), the memory system 110 may update the mapping data before performing the next programming operation (step 518).

[0090] When the write operation is for sequential data entries (Yes in step 512), the memory system 110 may determine whether the size of the data that can be programmed after updating the mapping data is less than a second reference value (step 514). According to an embodiment, the second reference value may correspond to the amount of data that can be stored in the memory device 150 using an auxiliary power source when a sudden power-off (SPO) occurs. When a sudden power-off (SPO) occurs, the memory system 110 needs to perform a minimum amount of operations to maintain data security and consistency. In this case, it may be difficult to store data entries in multiple open storage blocks within the memory device 150. Therefore, for example, the second reference value may correspond to the size of one storage block allocated in the memory device 150 for use during a sudden power-off (SPO).

[0091] When the size of the data that can be programmed after updating the mapping data is not less than the second reference value (No in step 514), the memory system 110 may update the mapping data before performing the next programming operation (step 518).

[0092] When the size of the programmable data after updating the mapping data is less than a second reference value (Yes in step 514), or when the mapping data is less than a first reference value (M) during the update of the mapping data (Yes in step 524), the memory system 110 may check whether the first mapping data (e.g., P2L table) of the sequential data entries is available (step 516). At this time, the available mapping entries (e.g., P2L) for the sequential data entries may change according to the maximum number (N) of programmable sequential data entries in the memory system 110. The maximum number (N) of programmable sequential data entries may correspond to the period of the checkpoint operation that the memory system 110 performs as late as possible to maintain data security and consistency. When the mapping entries (e.g., P2L) of the sequential data entries are not available (No in step 516), the memory system 110 may update the mapping data before performing the next programming operation (step 518).

[0093] When the mapping entries (e.g., P2L) of the sequential data entries are available (Yes in step 516), the memory system 110 may check whether the write operation is for the sequential data entries (step 520). Here, checking whether the corresponding write data entry is a sequential data entry may include checking whether it is a random data entry or a sequential data entry based on the relationship with the previously programmed data entries. For example, it may be checked whether the corresponding write data entry is a random data entry or a new sequential data entry. When the write operation is not for the sequential data entries (No in step 520), the memory system 110 may add the mapping entry corresponding to the write operation to the mapping data of the random data entries (e.g., random P2L table) (step 522). When the write operation is for the sequential data entries (Yes in step 520), the memory system 110 may add the mapping entry corresponding to the write operation to the mapping data of the sequential data entries (e.g., sequential P2L table) (step 526).

[0094] After adding the mapping entry corresponding to the write operation to the mapping data of the sequential data entries (e.g., sequential P2L table), the memory system 110 may check whether the size of the mapping data of the sequential data entries (e.g., sequential P2L table) is greater than or equal to the first reference value (M) (step 528). When the size of the mapping data of the sequential data entries (e.g., sequential P2L table) is greater than or equal to the first reference value (M) (Yes in step 528), the memory system 110 may perform a checkpoint operation (step 532).

[0095] According to an embodiment, the checkpoint operation may include an operation for updating the mapping data. For example, the processes of performing the checkpoint operation (step 532) and performing the mapping data update (step 518) may substantially include the same operations.

[0096] When the size of the mapped data of sequential data entries (e.g., sequential P2L table) is not greater than the first reference value (M) (No in step 528), the memory system 110 may change an indication or flag indicating whether the operation data is expanded (fExpansion) to "expanded" (TRUE) (step 530). Thereafter, the memory system 110 may perform a programming operation to store the next write data entry in the memory device 150 (step 506).

[0097] Figure 4 A recovery operation performed in a memory system according to another embodiment of the present disclosure is shown. Figure 4 Shown according to Figure 3 The recovery operation (e.g., sudden power-off recovery (SPOR) operation) when storing checkpoint information according to the operation method of the memory system described in. The recovery operation (SPOR) may be performed when power is supplied (Power-On) after a sudden power-off (SPO) (step 602).

[0098] Referring to Figure 4 , the memory system 110 may scan the data most recently stored in the memory device 150 (step 604). The memory system 110 may check the most recently stored data by scanning the open storage blocks used in the memory device 150 before the sudden power-off (SPO).

[0099] Then, the memory system 110 performs a recovery operation based on the mapped data of random data entries (e.g., random P2L table) (step 606). Generally, the memory system 110 stores more sequential data entries in the memory device 150 than random data entries stored therein. Since each random data entry is not continuously connected to each other, each random data entry can be recovered based on the mapped data of the random data entries (e.g., random P2L table).

[0100] Then, the memory system 110 may check whether the operation data has been expanded using the checkpoint information stored in the memory device 150 (step 608). Referring to Figure 3 , when the operation data is indicated as not expanded (FALSE) (No in step 608), the memory system 110 does not have to recover the mapped data (e.g., P2L table) of the data entries stored in the memory device 150 (step 614). The memory system 110 may check the mapped data (e.g., P2L table) ensured by the checkpoint information CP1 and CP2 and the log data (e.g., log record (log) data), and perform a recovery operation based on the corresponding mapped data (e.g., P2L table) (step 614).

[0101] When the operation data is indicated as extended (TRUE), the memory system 110 needs to recover the mapping data (e.g., P2L table) of the data entries stored in the memory device 150. First, the memory system 110 can calculate the area of sequential data entries based on the mapping data (e.g., P2L table) ensured by the checkpoint information CP1 and CP2 and the log record data. The memory system 110 can determine the length (Seq Length) of the sequential data entries based on the difference between the most recently stored data position (the most recent programmed NOP) and the most recent position (the current NOP) of the mapping data (e.g., P2L table) (step 610).

[0102] The memory system 110 can insert the data or information that is not recorded in the mapping data (e.g., P2L table) but stored in the memory device 150 into the mapping data (e.g., sequential P2L table) of the sequential data entries (step 612). Thereafter, the memory system 110 can perform a recovery operation based on the updated mapping data of the sequential data entries (e.g., sequential P2L table) (step 614).

[0103] Refer to Figure 3 and Figure 4 Even when the mode of the written data entries changes, the memory system 110 can continue to perform the write operation without delaying the checkpoint operation or the mapping data update operation in response to the state of the buffer set for storing the operation data. The state of the buffer set for storing the operation data can be determined based on a plurality of preset reference values corresponding to the performance of the memory system 110.

[0104] Figure 5 Illustrates operations performed in a memory system according to another embodiment of the present disclosure. Specifically, the operation method of the memory system can include operations for determining when to perform mapping data update or checkpoint operations during the execution of a plurality of programming operations to store a plurality of written data entries in the memory device 150.

[0105] Refer to Figure 5 When there is a written data entry that is the target of the write operation to be performed in the memory device 150, the write operation can be started (step 702).

[0106] First, an indicator of whether the operation data is extended (fExpansion) is set to not extended (FALSE) (step 704). Here, whether the operation data is extended is generally equivalent to Figure 3 the operation data being extended as described.

[0107] After that, the written data entry is stored in the memory device 150 (step 706).

[0108] After storing the write data entry in the memory device 150 (step 706), the memory system 110 may check whether mapping data (e.g., a random P2L table) of the random data entry is available (step 708). When the mapping data (e.g., the random P2L table) of the random data entry is not available (No in step 708), the memory system 110 updates the mapping data (e.g., the L2P table) before performing the next programming operation (step 722). According to an embodiment, the memory system 110 may perform a checkpoint operation together with updating the mapping data (e.g., the L2P table) (step 722).

[0109] When the mapping data (e.g., the random P2L table) of the random data entry is available (Yes in step 708), the memory system 110 may determine whether the operation data can be extended (step 710). When the operation data cannot be extended (No in step 710), the memory system 110 may update the mapping data corresponding to the write operation to check whether the size of the mapping data is less than a first reference value (M) (step 730). Here, the first reference value (M) may be a range that can be repaired or restored by a recovery operation (e.g., a sudden power-off recovery (SPOR) operation) performed when power is supplied (Power-On) after a sudden power-off (SPO). When updating the mapping data, when the size of the mapping data is not less than the first reference value (M) (No in step 730), the memory system 110 may update the mapping data before performing the next programming operation (step 722).

[0110] When the operation data can be extended (Yes in step 710), the memory system 110 may check whether the write operation is for sequential data input (step 712). Here, checking whether the write data is sequential data entries may include checking whether the write data entries are sequential with respect to the previously programmed data entries. For example, it may be confirmed whether there is a change in the pattern of the write data entries based on checking whether the write data entries are sequential data programmed previously. When the write operation is not for sequential data entries (No in step 712), the write operation may be for random data entries, such that the memory system 110 may increase the number (e.g., the length) of the random data entries (step 728). When the write operation is for sequential data entries (Yes in step 712), the memory system 110 may increase the number of the sequential data entries by "1" (step 714).

[0111] The memory system 110 may determine whether the size of the data that can be programmed after updating the mapping data is less than a second reference value (step 716). According to an embodiment, the second reference value may correspond to the amount of data that can be stored in the memory device 150 using an auxiliary power supply when a sudden power outage (SPO) occurs. When a sudden power outage (SPO) occurs, the memory system 110 needs to perform a minimum amount of operations to maintain data security and consistency. In this case, it may be difficult to store data entries in multiple open storage blocks within the memory device 150. Thus, for example, the second reference value may correspond to the size of one storage block allocated in the memory device 150 for use during a sudden power outage (SPO).

[0112] When the size of the data that can be programmed after updating the mapping data is not less than the second reference value (No in step 716), the memory system 110 may update the mapping data (e.g., the L2P table) before performing the next programming operation (step 722).

[0113] When the size of the data that can be programmed after updating the mapping data is less than the second reference value (Yes in step 716), the memory system 110 may check whether there is available mapping data (e.g., available space in the mapping data) for a sudden power outage recovery (SPOR) operation to be performed when power is supplied (power-on) after a sudden power outage (SPO). For example, the memory system 110 may determine whether the value obtained by adding the number of random data entries (from step 728) or the increment of sequential data entries (e.g., "1") to the number of data entries currently used (stored) in the mapping data of sequential data entries is less than the maximum number (N) of programmable sequential data entries. The maximum number (N) of programmable sequential data entries may correspond to the period of the checkpoint operation that the memory system 110 can perform as late as possible to maintain data security and consistency. When there is no available space in the mapping data (No in step 718), the memory system 110 may update the mapping data (e.g., the L2P table) before performing the next programming operation (step 722).

[0114] When there is available space in the mapping data (Yes in step 718), or when updating the mapping data and the mapping data is less than the first reference value (M) (Yes in step 730), the memory system 110 may check whether the mapping data of sequential data entries (e.g., sequential P2L table) is available (step 720). At this time, the availability of the mapping data of sequential data entries (e.g., sequential P2L table) may change according to the maximum number (N) of programmable sequential data entries in the memory system 110. If the mapping data of sequential data entries (e.g., sequential P2L table) is not available (No in step 720), the memory system 110 may update the mapping data (e.g., L2P table) before performing the next programming operation (step 722).

[0115] When the mapping data of sequential data entries (e.g., sequential P2L table) is available (Yes in step 720), the memory system 110 may check whether the write operation is for sequential data entries (step 724). Here, checking whether the corresponding write data entry is a sequential data entry may include checking whether it is a random data entry or a sequential data entry based on its relationship with the previously programmed data entries. For example, it may be checked whether the corresponding write data entry is a random data entry or a new sequential data entry. When the write operation is not for sequential data entries (No in step 724), the memory system 110 may add the mapping entry corresponding to the write operation to the mapping data of random data entries (e.g., random P2L table) (step 726). When the write operation is for sequential data entries (Yes in step 724), the memory system 110 may add the mapping entry corresponding to the write operation to the mapping data of sequential data entries (e.g., sequential P2L table) (step 732).

[0116] After adding the mapping entry corresponding to the write operation to the mapping data of sequential data entries (e.g., sequential P2L table), the memory system 110 may check whether the size of the mapping data of sequential data entries (e.g., sequential P2L table) is greater than or equal to the first reference value (M) (step 734). When the size of the mapping data of sequential data entries (e.g., sequential P2L table) is greater than or equal to the first reference value (M) (Yes in step 734), the memory system 110 may perform a checkpoint operation (step 740).

[0117] According to an embodiment, the checkpoint operation may include an operation for updating the mapping data. For example, the respective processes for performing the checkpoint operation (step 740) and for performing the mapping data update (step 722) may substantially include the same operations.

[0118] When the mapped data of sequential data entries (e.g., sequential P2L table) is less than the first reference value (M) (No in step 734), the memory system 110 may change an indication or flag indicating whether the operation data is expanded (fExpansion) to "expanded" (TRUE) (step 736). The memory system may insert additional information into the mapped data of the sequential data entries (e.g., sequential P2L table) (step 738). For example, the memory system 110 may store the physical address of the corresponding data entry and another piece of information pointing to the start of the new sequential data entry in a spare area of the mapped data of the sequential data entries (e.g., sequential P2L table). Thereafter, the memory system 110 may perform a programming operation to store the next write data entry into the memory device 150 (step 706).

[0119] Figure 6 A recovery operation performed in a memory system according to another embodiment of the present disclosure is shown. Figure 6 A recovery operation (e.g., a sudden power-off recovery (SPOR) operation) when storing checkpoint information according to the operation method of the memory system described in Figure 5 is shown. The recovery operation (SPOR) may be performed when power is supplied (Power-On) after a sudden power-off (SPO) (step 802).

[0120] Referring to Figure 6 , the memory system 110 may scan the data most recently stored in the memory device 150 (step 804). The memory system 110 may determine the data most recently stored by scanning the open storage blocks used in the memory device 150 before the sudden power-off (SPO).

[0121] The memory system 110 performs a recovery operation based on the mapped data of random data entries (e.g., random P2L table) (step 806). Generally, the memory system 110 stores more sequential data entries in the memory device 150 than random data entries stored therein. Since each random data entry is not connected to each other continuously, each random data entry can be recovered based on the mapped data of the random data entries (e.g., random P2L table).

[0122] Then, the memory system 110 may check whether the operation data is expanded using the checkpoint information stored in the memory device 150 (step 808). Referring to Figure 5, when the operation data is indicated as not extended (FALSE) (No in step 808), the memory system 110 does not have to restore the mapping data (such as the P2L table) of the data entries stored in the memory device 150 (step 816). The memory system 110 can check the mapping data (such as the P2L table) ensured by the checkpoint information CP1 and CP2 and the log data (such as the log (journal) data), and perform a recovery operation based on the corresponding mapping data (such as the P2L table) (step 816).

[0123] When the operation data is indicated as extended (TRUE), the memory system 110 needs to restore the mapping data (such as the P2L table) of the data entries stored in the memory device 150. First, the memory system 110 can check whether there is additional information in the mapping data (such as P2L) obtained through the checkpoint information CP1 and CP2 and the log data (such as the log (journal) data) (step 812). At this time, based on the additional information included in the mapping data (such as P2L), the memory system 110 can check whether the data entry corresponding to the mapping entry included in the mapping data is a sequential data entry or a random data entry during the recovery operation.

[0124] For example, when the mapping data includes additional information (Yes in step 812), the memory system 110 can identify that the data entry corresponding to the mapping data of the sequential data entry (such as the sequential P2L table) is a sequential data entry (step 814). When the mapping data does not include additional information (No in step 812), the memory system 110 can identify that the data entry corresponding to the mapping data of the sequential data entry (such as the sequential P2L table) is a random data entry (step 818).

[0125] After that, the memory system 110 can check whether there is another additional information in the mapping data (such as the sequential P2L table) of the sequential data entry (step 810). When the scan of the additional information in the mapping data (such as the sequential P2L table) of the sequential data entry is completed (Completed in step 810), the memory system 110 can perform a recovery operation based on the updated mapping data (such as the sequential P2L table) of the sequential data entry (step 816).

[0126] Refer to Figure 5 and Figure 6, even when the mode of writing data entries changes, the memory system 110 can continue to perform the write operation without delaying the checkpoint operation or the mapping data update operation in response to the state of the buffer for storing the operation data settings. The state of the buffer for storing the operation data settings can be determined based on a plurality of preset reference values corresponding to the performance of the memory system 110. In particular, the size of the mapping data that can be used in the sudden power-off recovery (SPOR) operation performed when power is supplied (Power-On) after a sudden power-off (SPO) can be considered before the sudden power-off (SPO), so that the memory system 110 can avoid buffer overflow or overrun that may occur in the later recovery operation. In addition, by storing additional information about the change in the mode of the written data in the mapping data, it is possible for the memory system 110 to more easily check whether the data entries stored in the open storage block are sequential data entries or random data entries during the recovery operation.

[0127] Figure 7 Illustrates the operation of a memory system according to an embodiment of the present disclosure.

[0128] Referring to Figures 1 to 7 , the memory system 110 can perform a checkpoint operation according to a first operation method (e.g., the first embodiment) based on the change in the mode of the written data entries, a second operation method corresponding to the state of the buffer (e.g., the second embodiment), or a combination thereof.

[0129] A plurality of written data entries WD can be transmitted to the memory system 110. The plurality of written data entries (WD) can include sequential data entries SWD1, SWD2, SWD3, SWD4, SWD5, and SWD6 and random data entries RWD1 and RWD2. The memory system 110 can sequentially perform a plurality of programming operations to store the plurality of written data entries WD in the memory device 150.

[0130] Referring to the first embodiment, the memory system 110 can perform a plurality of programming operations SWO1, SWO2, SWO3, and SWO4 corresponding to the sequential data entries SWD1, SWD2, SWD3, and SWD4, respectively. When the first random data entry RWD1 is transmitted after the fourth sequential data entry SWD4, the memory system 110 can recognize that the mode of the written data entries has changed. In response to the change in the mode of the written data entries, the memory system 110 can perform a first checkpoint operation CPO1 before performing the programming operation RWO1 corresponding to the first random data entry RWD1. After performing the first checkpoint operation CPO1, the memory system 110 can perform the programming operation RWO1 corresponding to the first random data entry RWD1.

[0131] Referring to the second embodiment, the memory system 110 may delay the first checkpoint operation CPO1 under the same conditions. That is, the first checkpoint period (CP1 period) for executing the first checkpoint operation CPO1 may be delayed. The memory system 110 may perform a plurality of programming operations SWO1, SWO2, SWO3, and SWO4 corresponding to sequential data entries SWD1, SWD2, SWD3, and SWD4, respectively. When the first random data entry RWD1 is transmitted after the fourth sequential data entry SWD4, the memory system 110 may recognize that the pattern of the written data entries has changed. However, the memory system 110 may determine whether the operation data regarding the first random data RWD1 falls within the range that can be stored in the buffer within the memory 144. When it is determined that the operation data regarding the first random data entry RWD1 falls within the range, the memory system 110 may perform the programming operation RWO1 corresponding to the first random data entry RWD1 and delay the first checkpoint operation CPO1.

[0132] In the second embodiment, although the change in the pattern of the written data entries is detected twice, the memory system 110 may still delay the first checkpoint operation CPO1. Even when the first pattern change occurs between the fourth sequential data entry SWD4 and the first random data entry RWD1 and the second pattern change occurs between the second random data entry RWD2 and the fifth sequential data entry SWD5, the operation data regarding the plurality of written data entries including the sequential data entries SWD1, SWD2, SWD3, SWD4, SWD5, and SWD6 and the random data entries RWD1 and RWD2 may be stored in the buffer within the memory 144, such that the memory system 110 may continue to perform the programming operation SWO6 corresponding to the sixth sequential data entry SWD6. After performing the programming operation SWO6, the memory system 110 may perform the first checkpoint operation CPO1.

[0133] Comparing the first embodiment and the second embodiment, at least to the extent that the first checkpoint period (CP1 period) for executing the first checkpoint operation CPO1 is delayed, the data input / output performance of the memory system 110 can be expected to be improved. For example, the memory system 110 may delay the timing for performing the checkpoint operation, thereby reducing the number of times the checkpoint operation is performed.

[0134] Figure 8 A data processing system according to an embodiment of the present disclosure is shown.

[0135] Referring to Figure 8, the data processing system 100 may include a host 102 coupled or connected to a memory system such as the memory system 110. For example, the host 102 and the memory system 110 may be connected to each other via a data bus, a host cable, etc. to perform data communication.

[0136] The memory system 110 may include memory devices 150 and a controller 130. The memory devices 150 and the controller 130 in the memory system 110 may be regarded as physically separate components or elements. The memory devices 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a passageway.

[0137] According to an embodiment, the memory devices 150 and the controller 130 may be functionally separate components or elements. Further, according to an embodiment, the memory devices 150 and the controller 130 may be implemented with a single chip or multiple chips.

[0138] The controller 130 may perform data input / output operations (such as read operations, programming operations, erase operations, etc.) in response to requests or commands input from an external device such as the host 102. For example, when the controller 130 performs a read operation in response to a read request input from an external device, the data stored in a plurality of non-volatile memory cells included in the memory device 150 is transmitted to the controller 130. In addition, the controller 130 may perform operations independently regardless of requests or commands input from the host 102. Regarding the operation state of the memory device 150, the controller 130 may perform operations such as garbage collection (GC), wear leveling (WL), and bad block management (BBM) for checking whether a storage block is bad and handling bad blocks.

[0139] The memory device 150 may include a plurality of storage blocks 152, 154, 156. The storage blocks 152, 154, 156 may be understood as a group of non-volatile memory cells, and the data therein is removed together by a single erase operation. Although not shown, the storage blocks 152, 154, 156 may include pages, which are a group of non-volatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, the storage blocks 152, 154, 156 may include a plurality of pages. The memory device 150 may include a voltage supply circuit 170 capable of supplying at least one voltage to the storage blocks 152, 154, 156. The voltage supply circuit 170 may supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the storage blocks 152, 154, 156.

[0140] The host 102 that interoperates with the memory system 110 or the data processing system 100 including the memory system 110 and the host 102 is a mobile electronic device (such as a vehicle), a portable electronic device (such as a mobile phone, an MP3 player, a laptop computer, etc.), and a non-portable electronic device (such as a desktop computer, a game console, a television, a projector, etc.). The host 102 can provide an interaction between the host 102 and a user who uses the data processing system 100 or the memory system 110 through at least one operating system (OS). The host 102 transmits a plurality of commands corresponding to a user request to the memory system 110, and the memory system 110 performs data input / output operations corresponding to the plurality of commands (e.g., operations corresponding to the user request).

[0141] The memory system 110 can be implemented using any one of various types of storage devices. Non-limiting examples of the storage device include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced-size MMC (RS-MMC), a micro MMC, a secure digital (SD) card, a mini SD, a micro SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, etc. According to an embodiment, the controller 130 can include a host interface 132, a processor 134, a power management unit (PMU) 140, a memory interface 142, and a memory 144. Components can be added or omitted in the controller 130 according to the structure, function, operation performance, etc. of the memory system 110.

[0142] The host 102 and the memory system 110 can each include a controller or an interface for transmitting and receiving signals, data, etc. according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 can include a device or a circuit capable of transmitting signals, data, etc. to the host 102 or receiving signals, data, etc. from the host 102. According to an embodiment, the host interface 132 is a layer for exchanging data with the host 102 and is implemented or driven by firmware called a host interface layer (HIL). According to an embodiment, the host interface 132 can include a command queue.

[0143] The host 102 and the memory system 110 can send and receive data therebetween using a set of predetermined data communication rules or programs or a preset interface. Examples of the set of rules or programs of the data communication standards or interfaces for sending and receiving data supported by the host 102 and the memory system 110 include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Peripheral Component Interconnect Express (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to an embodiment, the host 102 and the memory system 110 can be interconnected via the Universal Serial Bus (USB). The Universal Serial Bus (USB) is a highly scalable, hot-pluggable, plug-and-play serial interface that ensures cost-effective standard connection to peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, video conferencing cameras, etc.

[0144] The memory system 110 can support Non-Volatile Memory Express (NVMe). Non-Volatile Memory Express (NVMe) is an interface type based at least on Peripheral Component Interconnect Express (PCIe), designed to improve the performance and design flexibility of the host 102, server, computing device, etc. equipped with the memory system 110. PCIe can use a slot or a specific cable to connect a computing device (e.g., the host 102) and a peripheral device (e.g., the memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of megabytes per second or more (e.g., 250MB / s, 500MB / s, 984.6250MB / s, or 1969MB / s). According to an embodiment, the PCIe scheme can achieve a bandwidth of dozens to hundreds of gigabits per second.

[0145] The Power Management Unit (PMU) 140 can control the power supplied to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110, e.g., the voltage supplied to the controller 130, and supply power to the components included in the controller 130. The PMU 140 can not only detect power-on or power-off, but also generate a trigger signal to enable the memory system 110 to perform an emergency backup of the current state when the electrical energy supplied to the memory system 110 is unstable. According to an embodiment, the PMU 140 can include a device or component (such as an auxiliary power supply) capable of accumulating electrical energy that can be used in an emergency.

[0146] The memory interface 142 can be used as an interface for processing commands and data transmitted between the controller 130 and the memory device 150, enabling the controller 130 to control the memory device 150 in response to commands or requests input from the host 102. In the case where the memory device 150 includes a NAND flash memory, the memory interface 142 includes a NAND flash controller (NFC). According to an embodiment, the memory interface 142 can be implemented by firmware called a flash interface layer (FIL) or driven by firmware called FIL for exchanging data with the memory device 150. In addition, according to an embodiment, the memory interface 142 can support an open NAND flash interface (ONFi), a switching mode, etc. for data input / output with the memory device 150. For example, ONFi can use a data path (e.g., a channel, a lane, etc.) that includes at least one signal line capable of supporting bi-directional transmission and reception in units of 8-bit or 16-bit data. Data communication between the controller 130 and the memory device 150 can be achieved through at least one interface regarding asynchronous single data rate (SDR), synchronous double data rate (DDR), switched double data rate (DDR), etc.

[0147] The memory 144 can be used as a working memory of the memory system 110 or the controller 130 when temporarily storing transaction data for operations to be performed in the memory system 110 and the controller 130. According to an embodiment, the memory 144 can be implemented using a volatile memory. For example, the memory 144 can be implemented using a static random access memory (SRAM), a dynamic random access memory (DRAM), or both. The memory 144 can be provided within the controller 130, but the embodiment is not limited thereto. The memory 144 can be located inside or outside the controller 130. For example, the memory 144 can be embodied by an external volatile memory having a memory interface for transmitting data and / or signals between the memory 144 and the controller 130.

[0148] The processor 134 can control all operations of the memory system 110. For example, the processor 134 can control a programming operation or a read operation of the memory device 150 in response to a write request or a read request input from the host 102. According to an embodiment, the processor 134 can run firmware to control a programming operation or a read operation in the memory system 110. Here, the firmware can be called a flash translation layer (FTL). Examples of the FTL will be described in detail with reference to Figure 9 According to an embodiment, the processor 134 can be implemented by a microprocessor, a central processing unit (CPU), etc. According to an embodiment, the memory system 110 can be implemented using at least one multi-core processor, a coprocessor, etc.

[0149] The multiple memory blocks 152, 154, 156 included in the memory device 150 can be classified according to the number of bits that can be stored in or represented by each memory cell. The memory blocks included in the memory device 150 can include single-level cell (SLC) memory blocks, dual-level cells (DLC), triple-level cells (TLC), and quad-level cells (QLC), or include multi-level cells of multiple pages implemented by memory cells, where each page can store data of 5 bits or more in one memory cell.

[0150] According to an embodiment, the controller 130 can use the MLC memory blocks included in the memory device 150 as SLC memory blocks that store one bit of data in each memory cell. The data input / output speed of the multi-level cell (MLC) memory blocks may be slower than that of the SLC memory blocks. That is, when the MLC memory blocks are used as SLC memory blocks, the margin of the read or program operation may be reduced. For example, when the MLC memory blocks are used as SLC memory blocks, the controller 130 can perform data input / output operations at a higher speed. The controller 130 can use the MLC memory blocks as SLC buffers to temporarily store data because the SLC buffer or write boost buffer for writing data can provide a higher data input / output speed, thereby improving the performance of the memory system 110.

[0151] In addition, according to an embodiment, the controller 130 can program the data in the MLC multiple times without performing an erase operation on a specific MLC memory block included in the memory device 150. Generally, non-volatile memory cells do not support data overwriting. However, the controller 130 can utilize the characteristic that the MLC can store multiple bits of data to program 1-bit data in the MLC multiple times. For the MLC overwrite operation, when programming 1-bit data in the MLC, the controller 130 can store the number of program times as separate operation information. According to an embodiment, before programming another 1-bit data in the same MLC, an operation of evenly leveling the threshold voltage of the MLC can be performed, where each MLC stores 1-bit data.

[0152] According to an embodiment, the memory device 150 is implemented as a non-volatile memory, such as a flash memory, for example, a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a magnetic RAM (MRAM), a NAND flash memory, a NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of a phase change random access memory (PCRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), and a spin transfer torque magnetic random access memory (STT-MRAM), etc.

[0153] Figure 9 A memory system according to an embodiment of the present disclosure is shown.

[0154] Referring to Figure 9 , the controller 130 in the memory system operates together with the host 102 and the memory device 150. As shown, the controller 130 may have a hierarchical structure, including a host interface layer (HIL) 220, a flash translation layer (FTL) 240, and a memory interface layer (flash interface layer, FIL) 260.

[0155] The memory device 150 may include a plurality of memory chips 252 coupled to the controller 130 through a plurality of channels CH0, CH1,..., CH1_n and paths W0,..., W_k. The memory chips 252 may include a plurality of memory planes or a plurality of memory dies. According to an embodiment, a memory plane may be regarded as a logical partition or a physical partition, including at least one storage block, a driving circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells. Each memory plane or each memory die may support an interleaved mode, in which a plurality of data input / output operations are performed in parallel or simultaneously. According to an embodiment, the storage blocks included in each memory plane or each memory die included in the memory device 150 may be grouped to input / output a plurality of data entries as a super storage block.

[0156] Figure 8 and Figure 9 The internal configuration of the memory device 150 shown may be changed based on the operating performance of the memory system 110. Embodiments of the present disclosure may not be limited to Figure 8 and Figure 9 the internal configuration described therein.

[0157] Figure 9The host interface layer (HIL) 220, flash translation layer (FTL) 240, and memory interface layer (FIL) 260 described in are shown as one embodiment. The host interface layer (HIL) 220, flash translation layer (FTL) 240, and memory interface layer (FIL) 260 may be implemented in various forms according to the operating performance of the memory system 110. According to an embodiment, the host interface layer 220 may be included in Figure 8 the host interface 132 shown, and the memory interface layer 260 may be included in Figure 8 the memory interface 142 shown.

[0158] The buffer manager 280 in the controller 130 may control the input / output of data or operation information in combination with the host interface layer (HIL) 220, flash translation layer (FTL) 240, and memory interface layer (FIL) 260. To this end, the buffer manager 280 may set up or establish various buffers, caches, or queues in the Figure 8 memory 144 described, and control the data input / output of the buffers, caches, or queues, or the data transfer between the buffers, caches, or queues in response to requests or commands generated by the host interface layer (HIL) 220, flash translation layer (FTL) 240, and memory interface layer (FIL) 260. For example, the controller 130 may temporarily store the read data provided from the memory device 150 in response to a request from the host 102 before providing the read data to the host 102. Also, the controller 130 may temporarily store the write data provided from the host 102 in the memory 144 before storing the write data in the memory device 150. When controlling operations such as read operations, programming operations, and erase operations performed within the memory device 150, the read data or write data transferred or generated between the controller 130 and the memory device 150 in the memory system 110 may be stored and managed in buffers, queues, etc. established by the buffer manager 280 in the memory 144. In addition to read data or write data, the buffer manager 280 may also store signals or information (e.g., mapping data, read commands, programming commands, etc. for performing operations such as programming and reading data between the host 102 and the memory device 150) in buffers, caches, queues, etc. established in the memory 144. The buffer manager 280 may set up or manage command queues, program memories, data memories, write buffers / caches, read buffers / caches, data buffers / caches, mapping buffers / caches, etc.

[0159] The host interface layer (HIL) 220 can process commands, data, etc. transmitted from the host 102. By way of example and not limitation, the host interface layer 220 may include a command queue manager 222 and an event queue manager 224. The command queue manager 222 can store the commands, data, etc. received from the host 102 in order in the command queue and output them to the event queue manager 224, for example, in the order in which they are stored in the command queue manager 222. The event queue manager 224 can sequentially transmit events for processing the commands, data, etc. received from the command queue. According to an embodiment, the event queue manager 224 can classify, manage, or adjust the commands, data, etc. received from the command queue. In addition, according to an embodiment, the host interface layer 220 may include an encryption manager 226, which is configured to encrypt the response or output data to be transmitted to the host 102, or decrypt the encrypted portion of the commands or data transmitted from the host 102.

[0160] Multiple commands or data having the same characteristics may be transmitted from the host 102, or multiple commands and data having different characteristics may be mixed or scrambled by the host 102 and then transmitted to the memory system 110. For example, multiple commands for reading data, i.e., read commands, may be transmitted, or commands for reading data, i.e., read commands, and commands for programming / writing data, i.e., write commands, may be alternately transmitted to the memory system 110. The command queue manager 222 of the host interface layer 220 can store the commands, data transmitted from the host 102 in order in the command queue. Thereafter, the host interface layer 220 can estimate or predict the type of internal operation that the controller 130 will perform based on the characteristics of the commands, data, etc. transmitted from the host 102. The host interface layer 220 can determine its processing order and priority based on the characteristics of the commands, data, etc. According to the characteristics of the commands, data, etc. transmitted from the host 102, the event queue manager 224 in the host interface layer 220 is configured to receive an event from the buffer manager 280, and the event should be processed or disposed of inside the memory system 110 or the controller 130 according to the commands, data, etc. input from the host 102. Then, the event queue manager 224 can transmit the event including the commands, data, etc. to the flash translation layer (FTL) 240.

[0161] According to an embodiment, the flash translation layer (FTL) 240 may include a host request manager (HRM) 242, a mapping manager (MM) 244, a state manager 246, and a block manager 248. In addition, according to an embodiment, the flash translation layer (FTL) 240 may implement a multi-threaded scheme to perform data input / output (I / O) operations. The multi-threaded FTL may be implemented by using a multi-core processor with multi-threading included in the controller 130. For example, the host request manager (HRM) 242 may manage events transmitted from the event queue. The mapping manager (MM) 244 may process or control mapping data. The state manager 246 may perform operations such as garbage collection (GC) or wear leveling (WL) after checking the operation state of the memory device 150. The block manager 248 may execute commands or instructions on the blocks in the memory device 150.

[0162] The host request manager (HRM) 242 may use the mapping manager (MM) 244 and the block manager 248 to process requests according to read and program commands and events sent from the host interface layer 220. The host request manager (HRM) 242 may send a query request to the mapping manager (MM) 244 to determine the physical address corresponding to the logical address of the event input. The host request manager (HRM) 242 may send a read request with the physical address to the memory interface layer 260 to process the read request, that is, to process the event. In one embodiment, the host request manager (HRM) 242 may send a program request (or write request) to the block manager 248 to program data to a specific empty page in the memory device 150 where no data is stored, and then may send a mapping update request corresponding to the program request to the mapping manager (MM) 244 to update the item related to the program data in the information that maps the logical address and the physical address to each other.

[0163] The block manager 248 may convert the program requests transmitted from the host request manager (HRM) 242, the mapping manager (MM) 244, and / or the state manager 246 into flash program requests for the memory device 150 to manage the flash blocks in the memory device 150. To maximize or enhance the programming or writing performance of the memory system 110, the block manager 248 may collect program requests and send the flash program requests for multi-plane and single programming operations to the memory interface layer 260. In an embodiment, the block manager 248 sends multiple flash program requests to the memory interface layer 260 to enhance or maximize the parallel processing of the multi-channel and multi-direction flash controller.

[0164] In an embodiment, the block manager 248 may manage the blocks in the memory device 150 according to the number of valid pages, select and erase a block without valid pages when an idle block is needed, and select a block including the smallest number of valid pages when it is determined that garbage collection will be performed. The state manager 246 may perform garbage collection to move the valid data stored in the selected block to an empty block and erase the data stored in the selected block so that the memory device 150 may have sufficient idle blocks (i.e., empty blocks without data).

[0165] When the block manager 248 provides information about the block to be erased to the state manager 246, the state manager 246 may check all the flash pages of the block to be erased to determine whether each page of the block is valid. For example, to determine the validity of each page, the state manager 246 may identify the logical address recorded in the out-of-band (OOB) area of each page. To determine whether each page is valid, the state manager 246 may compare the physical address of the page with the physical address mapped from the logical address obtained from the query request. The state manager 246 sends a programming request to the block manager 248 for each valid page. When the programming operation is completed, the mapping table may be updated by the mapping manager 244.

[0166] The mapping manager 244 may manage mapping data, such as a logical-physical mapping table. The mapping manager 244 may process various requests generated by the host request manager (HRM) 242 or the state manager 246, such as queries, updates, etc. The mapping manager 244 may store the entire mapping table in the memory device 150, such as flash / non-volatile memory, and cache mapping entries according to the storage capacity of the memory 144. When a mapping cache miss occurs in the case of processing a query or update request, the mapping manager 244 may send a read request to the memory interface layer 260 to load the relevant mapping table stored in the memory device 150. When the number of dirty cache blocks in the mapping manager 244 exceeds a certain threshold, a programming request may be sent to the block manager 246 to generate clean cache blocks, and the dirty mapping table may be stored in the memory device 150.

[0167] When garbage collection is performed, the status manager 246 copies valid pages into free blocks, and the host request manager (HRM) 242 can program the data of the most recent version of the same logical address of the pages and issue an update request simultaneously. When the status manager 246 requests a mapping update in a state where the copying of valid pages is not completed normally, the mapping manager 244 may not perform the mapping table update. This is because when the status manager 246 requests a mapping update, the mapping request is issued with old physical information, and the copying of valid pages is completed later. The mapping manager 244 can perform the mapping update operation to ensure accuracy when or only when the most recent mapping table still points to the old physical address.

[0168] The memory interface layer 260 can exchange data, commands, status information, etc. with a plurality of memory chips 252 in the memory device 150 through a data communication method. According to an embodiment, the memory interface layer 260 can include a status check schedule manager 262 and a data path manager 264. The status check schedule manager 262 can check and determine the operation status of the plurality of memory chips 252 connected to the controller 130, the operation status of the plurality of channels CH0, CH1,..., CH1_n, and the plurality of paths W0,..., W_k, etc. The sending and receiving of data or commands can be arranged in response to the operation status of the plurality of memory chips 252 and the plurality of channels CH0, CH1,..., CH1_n. The data path manager 264 can control the sending and receiving of data, commands, etc. through the plurality of channels CH0, CH1,..., CH1_n and the paths W0,..., W_k based on the information sent from the status check schedule manager 262. According to an embodiment, the data path manager 264 can include a plurality of transceivers, each transceiver corresponding to each of the plurality of channels CH0, CH1,..., CH1_n.

[0169] According to an embodiment, the memory interface layer 260 can further include an ECC (error correction code) module 266 configured to perform error checking and correction on the data transmitted between the controller 130 and the memory device 150. The ECC module 266 can be implemented as a separate module, circuit, or firmware in the controller 130, but according to an embodiment, it can also be implemented in each memory chip 252 included in the memory device 150. The ECC module 266 can include a program, circuit, module, system, or device for detecting and correcting error bits of the data processed by the memory device 150.

[0170] To find and correct any errors in data transmitted from the memory device 150, the ECC module 266 may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder may perform error correction encoding on data to be programmed in the memory device 150 to generate encoded data with added parity bits and store the encoded data in the memory device 150. When the controller 130 reads data stored in the memory device 150, the ECC decoder may detect and correct error bits included in the data read from the memory device 150. For example, after performing error correction decoding on the data read from the memory device 150, the ECC module 266 may determine whether the error correction decoding is successful and output an instruction signal, such as a correction success signal or a correction failure signal, based on the result of the error correction decoding. The ECC module 266 may use the parity bits generated during the ECC encoding process of the data stored in the memory device 150 to correct the error bits of the read data entry. When the number of error bits is greater than or equal to the number of correctable error bits, the ECC circuit 138 may not correct the error bits but may output a correction failure signal indicating a failure to correct the error bits.

[0171] According to an embodiment, the ECC circuit 138 may perform error correction operations based on coding modulations such as: low density parity check (LDPC) code, Bose-Chaudhuri-Hocquenghem (BCH) code, Turbo code, Reed-Solomon (RS) code, convolutional code, recursive systematic code (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc. The ECC circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the above-mentioned codes.

[0172] According to an embodiment, the managers included in the host interface layer 220, the flash translation layer (FTL) 240, and the memory interface layer 260 may be implemented with a general-purpose processor, an accelerator, a dedicated processor, a coprocessor, a multi-core processor, etc. According to an embodiment, the manager may be implemented by firmware that works in cooperation with the processor.

[0173] As described above, the memory device or the memory system according to an embodiment of the present disclosure may prevent a decrease in data input / output performance due to frequent mapping data updates or checkpoint operations.

[0174] In addition, a memory device or a memory system according to an embodiment of the present disclosure can continuously perform a programming operation of a plurality of write data entries without updating mapping data or performing a checkpoint operation even when sequential data entries and random data entries are mixed in the plurality of write data entries, thereby improving the speed of data input / output operations in the memory device or the memory system.

[0175] The methods, processes, and / or operations described herein can be performed by code or instructions executed by a computer, a processor, a controller, or other signal processing device. The computer, the processor, the controller, or other signal processing device can be those described herein or additional devices outside those described herein. Since the algorithms underlying the methods or operations constituting the computer, the processor, the controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, the processor, the controller, or other signal processing device into a dedicated processor for performing the methods herein.

[0176] In addition, another embodiment can include a computer-readable medium for storing the above code or instructions, such as a non-transitory computer-readable medium. The computer-readable medium can be a volatile or non-volatile memory or other storage device, which can be removably or fixedly coupled to a computer, a processor, a controller, or other signal processing device that will implement the code or instructions for performing the operations of the method embodiments or device embodiments herein.

[0177] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logics, interfaces, decoders, drivers, generators, and other signal generation and signal processing features of the embodiments disclosed herein can be implemented, for example, in non-transitory logic, which can include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logics, interfaces, decoders, drivers, generators, and other signal generation and signal processing functions can be, for example, any of various integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, systems-on-a-chip, microprocessors, or other types of processing or control circuits.

[0178] When implemented at least in part in software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logics, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing code or instructions, such as those executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or additional devices outside of the elements described herein. Since the algorithms underlying the methods or operations that make up a computer, processor, microprocessor, controller, or other signal processing device have been described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0179] While the teachings of the present disclosure have been shown and described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made in accordance with the present disclosure without departing from the scope of the invention as defined by the appended claims. Additionally, the disclosed embodiments may be combined to form additional embodiments.

Claims

1. A memory system, comprising: A memory device including a plurality of memory blocks; as well as A controller is configured to recognize a change in a pattern of a plurality of write data entries, delay a checkpoint operation associated with a write operation on the plurality of write data entries when a size of operation data on the plurality of write data entries is within a range that can be stored in a buffer, and perform the checkpoint operation when the size of the operation data exceeds the range.

2. The memory system according to claim 1, wherein: The checkpoint operation includes an operation of adding operation data about at least one write entry among the plurality of write data entries, which has been stored in the memory device, to log data.

3. The memory system according to claim 2, wherein: The change in pattern is a change from sequential data entries to random data entries.

4. The memory system according to claim 3, wherein: The operation data includes information about logical addresses and physical addresses associated with the random data entries.

5. The memory system according to claim 3, wherein: The operational data includes count information regarding how many of the sequential data entries have been stored in the memory device.

6. The memory system according to claim 1, wherein: The range is determined based on the size of a buffer established for a recovery operation performed after a sudden power outage (SPO), the size of map data regarding sequential data entries existing before the sudden power outage, and the size of map data used for the recovery operation.

7. The memory system according to claim 1, wherein: determining a first maximum number of sequential data entries and a second maximum number of random data entries to be programmed in the memory device during consecutive write operations based on the size of the buffer, and The first number is greater than the second number.

8. The memory system according to claim 1, wherein: The controller further: storing the checkpoint information in the log data through the checkpoint operation; and When power is supplied after a sudden power outage (SPO), the plurality of written data entries are restored based on the checkpoint information.

9. The memory system according to claim 8, wherein: The controller, when power is supplied and when recognizing through the checkpoint information that the change of the mode has occurred, adds operation data corresponding to the random data entry to the map data of the sequential data entry.

10. The memory system according to claim 9, wherein: The controller records the random data entry as a first entry of new sequential data entries in a spare area of ​​the map data based on operation data corresponding to the random data entry.

11. The memory system according to claim 8, wherein: The controller skips data scanning for an open memory block based on count information about sequential data entries included in the checkpoint information.

12. A method of operating a memory system, comprising: identifying a change in a pattern of a plurality of write data entries input from an external device and programmed in a memory device, the memory device comprising a plurality of memory blocks; determining whether the size of the operation data regarding the plurality of write data entries is within a range that can be stored in the buffer; When the size of the operation data is within the range, delaying a checkpoint operation associated with a write operation on the plurality of write data entries; as well as When the size of the operation data exceeds the range, the checkpoint operation is performed.

13. The method according to claim 12, wherein: The checkpoint operation includes an operation of adding operation data about at least one write entry among the plurality of write data entries, which has been stored in the memory device, to log data.

14. The method according to claim 12, wherein: The change in pattern is from sequential data entry to random data entry.

15. The method of claim 14, the operation data comprising information about logical addresses and physical addresses associated with the random data entries and count information about how many of the sequential data entries have been stored in the memory device.

16. The method according to claim 12, wherein: The range is determined based on the size of a buffer established for a recovery operation performed after a sudden power outage (SPO), the size of mapping data about sequential data entries existing before the sudden power outage, and the size of mapping data used for the recovery operation, and determining a first maximum number of sequential data entries and a second maximum number of random data entries to be programmed in the memory device during consecutive write operations based on the size of the buffer, and The first number is greater than the second number.

17. The method according to claim 12, further comprising: Storing the checkpoint information in the log data through the checkpoint operation; as well as When power is supplied after a sudden power outage (SPO), the plurality of written data entries are restored based on the checkpoint information.

18. The method of claim 17, wherein restoring the plurality of written data entries comprises: After power is supplied, when it is recognized through the checkpoint information that the change of the mode has occurred, operation data corresponding to the random data entry is added to the map data of the sequential data entry.

19. The method according to claim 18, wherein: Adding the operation data includes: The random data entry is recorded as a first entry of new sequential data entries in a spare area of ​​the map data based on operation data corresponding to the random data entry.

20. The method according to claim 17, wherein: Restoring the plurality of written data entries comprises: Based on the count information about the sequential data entries included in the checkpoint information, data scanning for the open storage block is skipped.

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