Storage device for storing data and method of operating storage device

Abstract

The invention provides a storage device and a method of operating the storage device. The storage device includes a memory device including a plurality of memory blocks, each memory block including a plurality of memory cells configured to store data; and a memory controller, and a processor in communication with the memory device and configured to 1) determine whether a write mode of a memory block of the memory device is a first write mode or a second write mode based on a temperature of the memory device and a number of read recovery operations that have been performed in the memory block, one data bit is stored in a memory cell of the memory block, and a second write mode in which a plurality of data bits are stored in the memory cell, and 2) controlling the memory device to perform a write operation in the determined write mode.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0186052, filed on December 19, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, to a storage device for storing data and a method of operating the storage device. Background Art

[0004] A storage device may be a device that stores data under the control of a host such as any one of a mobile phone, a smartphone, an MP3 player, a laptop computer, a server computer, a desktop computer, a game console, a television (TV), a tablet PC, an automobile, an in - vehicle infotainment system, or various types of electronic devices. Such a storage device may include a memory device that stores data and a memory controller that controls the memory device. Summary of the Invention

[0005] Various embodiments of the present disclosure relate to a storage device having improved reliability and a method of operating the storage device.

[0006] Embodiments of the present disclosure may provide a storage device. The storage device may include a memory device including a plurality of memory blocks, each memory block including a plurality of memory cells configured to store data; and a memory controller communicatively coupled to the memory device and configured to 1) determine a write mode of the memory block as a first write mode or a second write mode based on the temperature of the storage device and the number of read - recovery operations that have been performed on the memory blocks of the memory device, wherein in the first write mode, one data bit is stored in the memory cells of the memory block, and in the second write mode, a plurality of data bits are stored in the memory cells, and 2) control the memory device to perform a write operation in the determined write mode.

[0007] Embodiments of the present disclosure provide a method of operating a storage device. The storage device includes a memory device and a memory controller. The memory device includes a plurality of memory blocks, each memory block including a plurality of memory cells configured to store data. The memory controller communicates with the memory device and is configured to control the memory device. The method includes measuring the temperature of the storage device; obtaining the number of read recovery operations; based on the temperature and the number of read recovery operations, selecting a write mode of the memory block as a first write mode or a second write mode. In the first write mode, one data bit is stored in the memory cells of the memory block, and in the second write mode, a plurality of data bits are stored in the memory cells; and performing a write operation in the selected write mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing a storage device according to an embodiment of the present disclosure.

[0009] Figure 2A and 2B is a diagram showing write mode determination conditions based on the temperature of a storage device according to an embodiment of the present disclosure.

[0010] Figure 3 is a diagram showing write mode determination conditions based on the number of read recovery operations according to an embodiment of the present disclosure.

[0011] Figure 4 is a diagram showing an example of performing a write operation in response to a write request from a host according to an embodiment of the present disclosure.

[0012] Figure 5 is a diagram showing an example of performing a write operation in response to a garbage collection operation according to an embodiment of the present disclosure.

[0013] Figure 6 is a diagram showing an example of performing an operation of migrating data according to an embodiment of the present disclosure.

[0014] Figure 7 is a diagram showing an example of performing an operation of migrating data according to an embodiment of the present disclosure.

[0015] Figure 8 is a flowchart showing a method of operating a storage device according to an embodiment of the present disclosure.

[0016] Figure 9 is a flowchart showing a method of performing a write operation according to an embodiment of the present disclosure.

[0017] Figure 10 is a flowchart showing a method of performing an operation of migrating data according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] Specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or this application are provided to describe the embodiments as examples of the disclosed technology. The various embodiments of the present disclosure can be practiced in various forms and should not be construed as limited to the embodiments described in the specification or the application.

[0019] Figure 1 is a diagram showing a storage device according to an embodiment of the present disclosure.

[0020] Referring to Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device 100.

[0021] According to the method for communicating with the host 300, the storage device 50 may be implemented as any one of the following storage devices: a solid state drive (SSD), a multimedia card of MMC or eMMC type, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a peripheral component interconnect (PCI) or a fast PCI (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0022] The storage device 50 may be manufactured in any one of a variety of package forms. For example, the storage device 50 may be manufactured in any one of a variety of package forms such as: a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer level package (WFP), and a wafer level stack package (WSP).

[0023] The memory device 100 may store data. The memory device 100 may include a plurality of storage blocks that store data. Each storage block may include a plurality of memory cells.

[0024] Each of the memory cells may be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits. According to the write operation, the single-level cell may have a threshold voltage corresponding to either the erased state or one of the programmed states. According to the write operation, each of the multi-level cell, the three-level cell, and the four-level cell may have a threshold voltage corresponding to the erased state and one of the multiple programmed states.

[0025] In an embodiment, the plurality of memory blocks may include a plurality of single memory blocks (SLC BLK) and a plurality of multi-memory blocks (XLC BLK). For example, based on a preset policy, the plurality of memory blocks may include memory blocks operating as single memory blocks SLC BLK and memory blocks operating as multi-memory blocks XLC BLK. Herein, each single memory block SLC BLK may be a memory block including a plurality of memory cells implemented as single-level cells. Each multi-memory block XLC BLK may be a memory block including a plurality of memory cells, and each memory cell stores a plurality of data bits, such as multi-level cells, triple-level cells, or quadruple-level cells.

[0026] In an embodiment, regardless of the preset policy, each of the plurality of memory blocks may store one data bit or a plurality of data bits in the memory cells. For example, the memory device 100 may control each memory block by controlling the threshold voltage of the memory cells, such that one data bit is stored in each of the memory cells included in the corresponding memory block, thereby enabling the corresponding memory block to operate as a single memory block SLC BLK. In some embodiments, the memory device 100 may control each memory block by controlling the threshold voltage of the memory cells, such that a plurality of data bits are stored in each of the memory cells included in the corresponding memory block, thereby enabling the corresponding memory block to operate as a multi-memory block XLC BLK.

[0027] In an embodiment, the memory device 100 may be a non-volatile memory that retains data even when the power supply is interrupted. In this specification, for ease of description, it will be assumed that the memory device 100 is a NAND flash memory for description. Those skilled in the art will understand that this description can be applied to various memory devices, not limited to NAND flash memories.

[0028] In an embodiment, the memory device 100 may receive commands and addresses from the memory controller 200. The memory device 100 may perform the operations indicated by the commands on the area selected by the addresses. For example, the memory device 100 may perform write operations (or programming operations), read operations, and erase operations.

[0029] The memory controller 200 may control the overall operation of the storage device 50. In the storage device, the reliability of the stored data may decrease according to changes in the internal temperature. For example, when the internal temperature changes from room temperature to a high temperature or a low temperature, many error bits may be included in the data read from the memory device. In this case, read recovery operations for reliability maintenance may occur frequently, and the performance of the storage device may also deteriorate due to the frequent read recovery operations. Therefore, in order to prevent the deterioration of the storage device and ensure proper operation even in a wide temperature range of the storage device, the memory controller 200 is configured to incorporate a scheme capable of improving the reliability of the storage device in response to various temperature changes.

[0030] In an embodiment, the memory controller 200 may include a processor 210, a memory 220, an interface 230, an error correction circuit 240, a temperature measuring instrument 250, a storage block manager 260, a host request operation controller 270, and a background operation controller 280. The processor 210, the memory 220, the interface 230, the error correction circuit 240, the temperature measuring instrument 250, the storage block manager 260, the host request operation controller 270, and the background operation controller 280 may communicate with each other through a communication bus 290.

[0031] The processor 210 may execute firmware, code, or one or more instructions that include various types of information required for the operation of the memory controller 200.

[0032] When power is applied to the storage device 50, the processor 210 may run firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300, a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100, and a flash interface layer (FIL) that controls communication with the memory device 100.

[0033] In an embodiment, the processor 210 may receive data and a logical block address (LBA) from the host 300, and may convert the logical block address (LBA) into a physical block address (PBA), which indicates the address of the memory cells included in the memory device 100 and in which the data to be stored is located. In this specification, the logical block address and the "logical address" may be used interchangeably with each other. In this specification, the physical block address and the "physical address" may be used interchangeably with each other.

[0034] The memory 220 may be used as a buffer memory, a cache memory, a working memory, etc.

[0035] Further, the memory 220 may store firmware, code, or one or more instructions including various types of information required for the operation of the memory controller 200.

[0036] The interface 230 may include a host interface for communicating with the host 300 and a memory interface for communicating with the memory device 100.

[0037] The error correction circuit 240 may perform error correction. The error correction circuit 240 may perform error correction code (ECC) encoding on data written to the memory device 100 through the interface 230. The encoded data may be transmitted to the memory device 100 through the interface 230. The error correction circuit 240 may perform error correction code (ECC) decoding on data received from the memory device 100 through the interface 230.

[0038] In an embodiment, the error correction circuit 240 may obtain the number of error bits in the read data read from the memory device. For example, the error correction circuit 240 may obtain the number of error bits by calculating the number of error correction bits in the read data while performing error correction. The error correction circuit 240 may provide information about the number of error bits to the storage block manager 260 and the background operation controller 280.

[0039] The temperature measuring instrument 250 may measure the internal temperature that is the temperature of the storage device 50.

[0040] In an embodiment, the temperature measuring instrument 250 may determine the temperature change of the storage device 50 during a preset period. The temperature measuring instrument 250 may provide information about the measured temperature or the temperature change to the storage block manager 260.

[0041] The storage block manager 260 may manage a plurality of storage blocks included in the memory device as a group. For example, the storage block manager 260 may generate a super block including at least two of the plurality of storage blocks. The storage block manager 260 may manage the plurality of storage blocks based on the super block.

[0042] In an embodiment, the storage block manager 260 may determine a write mode to be used in a write operation among a plurality of write modes. The plurality of write modes may be distinguished according to the number of data bits stored in each of the plurality of memory cells. In an example, the first write mode may be a scheme for storing one data bit in each of the plurality of memory cells. When operating a storage block in the first write mode, the memory device 100 may control each storage block by controlling the corresponding storage block to operate as a single storage block, such that data is stored using a single storage block SLC BLK determined based on a preset policy, or such that one data bit is stored in each of the memory cells included in the storage block, regardless of the preset policy. In an example, the second write mode may be a scheme for storing a plurality of data bits in each of the plurality of memory cells. When operating a storage block in the second write mode, the memory device 100 may control each storage block by controlling the corresponding storage block to operate as a multi-storage block, such that data is stored using a multi-storage block XLC BLK determined based on a preset policy, or such that a plurality of data bits are stored in each of the memory cells included in the storage block, regardless of the preset policy.

[0043] In an embodiment, the storage block manager 260 may determine the write mode to be used for a write operation based on the temperature of the storage device 50 and the number of read recovery operations indicating the number of times a read recovery operation is performed (i.e., the read recovery operation count). In this example, the number of read recovery operations for each storage block may be counted. A read recovery operation refers to a process of migrating data from a degraded storage block to another storage block when the count of read operations on the degraded storage block exceeds a preset threshold. In an example, when it is determined that the reliability of the memory device 100 has decreased based on the temperature and the number of read recovery operations, the storage block manager 260 may determine to perform the write operation in the first write mode. In an example, when it is determined that the reliability of the memory device 100 is not low based on the temperature and the number of read recovery operations, the storage block manager 260 may determine that the memory device 100 is in a stable state. In this case, the storage block manager 260 may determine to perform the write operation in the second write mode. Therefore, in an embodiment, based on the temperature of the storage device 50 and the number of read recovery operations, the write operation is performed in different modes, such as the first write mode or the second write mode.

[0044] The host request operation controller 270 may control operations requested by the host 300.

[0045] In an embodiment, the memory controller 200 may provide commands, addresses, or data corresponding to a programming operation, a read operation, or an erase operation to the memory device 100 to perform the corresponding operation in response to a request from the host 300.

[0046] In an embodiment, the host request operation controller 270 may control the memory device 100 to perform a write operation according to the write mode determined by the storage block manager 260. For example, when receiving a request for a write operation from the host 300, the host request operation controller 270 may control the memory device 100 to store write data corresponding to the request according to the determined write mode.

[0047] The background operation controller 280 may control background operations that are executed independently of requests from the host 300. Background operations may refer to operations that are performed within the memory device 100 by sending commands from the memory controller to the memory device without intervention from the host and without receiving and executing one or more commands from the host. Some examples of such background operations include copying and processing data stored in one part of the memory device to another part, such as wear leveling, read recovery, and / or garbage collection.

[0048] In an embodiment, the background operation controller 280 may generate commands, addresses, and data indicating background operations and may transmit them to the memory device 100. For example, the background operation controller 280 may provide the memory device 100 with the commands, addresses, and data required to perform write operations, read operations, and erase operations associated with background operations such as wear leveling operations, read recovery operations, and / or garbage collection operations.

[0049] In an embodiment, the background operation controller 280 may determine whether to perform a read recovery operation based on the number of error bits. For example, a read failure may occur when the number of error bits in the read data exceeds the level that can be corrected by the error correction circuit 240. Therefore, when the number of error bits reaches a specific number, the background operation controller 280 may perform a read recovery operation. The specific number may be predetermined and may be changed.

[0050] In an embodiment, the background operation controller 280 may perform a garbage collection operation according to the write mode determined by the storage block manager 260. For example, the garbage collection operation may include a read operation of reading valid data from a sacrificial storage block, a write operation of storing the read valid data in a new storage block, and an erase operation of erasing the data stored in the sacrificial storage block. Here, the background operation controller 280 may control the memory device 100 to store valid data according to the determined write mode during the write operation included in the garbage collection.

[0051] When the memory device 100 is in a stable state after determining to perform a write operation in the first write mode based on the temperature and the number of read recovery operations, the background operation controller 280 may perform a data migration operation of migrating data stored in a first memory block operating in the first write mode to a memory block operating in the second write mode. The background operation controller 280 may perform the data migration operation during an idle period of the memory device 100. Here, the idle period may indicate a state in which no separate operation is performed due to not receiving a request from the host 300 or not triggering a background operation. In addition, the background operation controller 280 may perform the data migration operation at a preset time such as dawn time based on the real-time clock (RTC) received from the host 300, or perform the data migration operation when the battery of the host 300 is charged, etc.

[0052] Figure 2A and 2B is a diagram showing write mode determination conditions based on the temperature of a storage device according to an embodiment of the present disclosure. As described above, in an embodiment, write operations are performed in different modes based on the temperature of the storage device and the number of read recovery operations. Figure 2A and Figure 2B shows an example of determining whether a first condition is satisfied based on the temperature of the storage device. In an embodiment, the storage block manager 260 may determine whether the first condition is satisfied based on the temperature of the storage device in order to determine the write mode. Figure 2A and 2B shows different embodiments of determining whether the first condition is satisfied.

[0053] Referring to Figure 2A when the internal temperature is lower than a first reference temperature TEMP_REF1 corresponding to a low temperature TEMP_LOW or higher than a second reference temperature TEMP_REF2 corresponding to a high temperature TEMP_HIGH, the storage block manager 260 may determine that the first condition is satisfied.

[0054] For example, the low temperature TEMP_LOW may indicate a temperature lower than the first reference temperature TEMP_REF1. The room temperature TEMP_ROOM may indicate a temperature higher than the first reference temperature TEMP_REF1 or lower than the second reference temperature TEMP_REF2. The high temperature TEMP_HIGH may indicate a temperature higher than the second reference temperature TEMP_REF2. When the internal temperature corresponds to the room temperature TEMP_ROOM, the first condition may not be satisfied. On the contrary, when the internal temperature is the low temperature TEMP_LOW or the high temperature TEMP_HIGH, as shown in the shaded area in Figure 2A the first condition may be satisfied.

[0055] Referring to Figure 2BWhen the change in the internal temperature during a preset period is greater than a reference value, the storage block manager 260 may determine that the first condition is satisfied.

[0056] For example, depending on the situation, the internal temperature may change from room temperature to a high temperature (①), from room temperature to a low temperature (②), or from a low temperature to a high temperature (③). When the current situation corresponds to any one of the above situations, the first condition may be satisfied. Therefore, when the change in the internal temperature during a preset period is greater than a reference value, the storage block manager 260 may determine that the current situation corresponds to each of the above situations.

[0057] Figure 3 is a diagram showing the write mode determination conditions based on the number of read recovery operations according to an embodiment of the present disclosure. Figure 3 Shows an example of determining whether the second condition is satisfied based on the number of read recovery operations. In an embodiment, the storage block manager 260 may determine whether the second condition is satisfied based on the number of read recovery operations (i.e., the read recovery operation count) in order to determine the write mode.

[0058] Reference Figure 3 , the background operation controller 280 may check the period of the read recovery operation based on the number of read recovery operations. When the period of executing the read recovery operation is shorter than the reference period RRC_REF, the background operation controller 280 may determine that the second condition is satisfied.

[0059] For example, the reference period RRC_REF of the read recovery operation may indicate the period of executing M read recovery operations RRC1 to RRCm during a preset period (M is a natural number).

[0060] In an embodiment, when the background operation controller 280 executes N read recovery operations RRC1 to RRCn during a preset period and N is greater than M, the current execution period RRC_TARG of the read recovery operation may be shorter than the reference period RRC_REF. In this case, the storage block manager 260 may determine that the second condition is satisfied.

[0061] In an embodiment, when it is determined that the first condition and the second condition described above are satisfied as referenced Figure 2A , Figure 2B and Figure 3 , the memory controller 200 may control the memory device 100 to perform a write operation in the first write mode. Examples of performing a write operation in the first write mode will be described in detail later with reference to Figure 4 and Figure 5 .

[0062] In an embodiment, when the above-referenced Figure 2A , Figure 2B and Figure 3When at least one of the described first condition and second condition is satisfied, the memory controller 200 may control the memory device 100 to perform a write operation in a second write mode. For example, when the internal temperature is higher than a first reference temperature TEMP_REF1 and lower than a second reference temperature TEMP_REF2, the memory controller 200 may control the memory device 100 to perform a write operation in a second write mode. For example, when the change in the internal temperature during a preset period is less than or equal to a reference value, the memory controller 200 may control the memory device 100 to perform a write operation in a second write mode. For example, when the execution period of a read recovery operation is equal to or longer than a reference period RRC_REF, the memory controller 200 may control the memory device 100 to perform a write operation in a second write mode.

[0063] The scheme for determining whether the second condition is satisfied is not limited to Figure 3 the scheme shown. For example, the storage block manager 260 may determine whether the second condition is satisfied based on various schemes capable of determining whether the reliability of the memory device 100 is low. For example, the storage block manager 260 may determine that the second condition is satisfied when the number of error bits is greater than a reference number of error bits based on the comparison result of the number of error bits and the reference number of error bits.

[0064] Figure 4 is a diagram showing an example of performing a write operation in response to a write request from a host according to an embodiment of the present disclosure. Figure 4 shows an example of performing a write operation in response to a request from the host 300 when the first condition and the second condition are satisfied.

[0065] In an embodiment, when the internal temperature of the storage device is lower than a first reference temperature corresponding to a low temperature or higher than a second reference temperature corresponding to a high temperature, and when the execution period of a read recovery operation is shorter than a reference period, the memory controller 200 may control the memory device 100 to perform a write operation in a first write mode. In another example, when the change in the internal temperature of the storage device during a preset period is greater than a reference value and the execution period of the read recovery operation is less than a reference period, the memory controller 200 may control the memory device 100 to perform a write operation in a first write mode.

[0066] See Figure 4 , when receiving a write operation request WRITE_REQ from the host 300, the memory controller 200 may control the memory device 100 to store write data DATA corresponding to the request WRITE_REQ in a first write mode.

[0067] For example, the host request operation controller 270 may receive a write request WRITE_REQ from the host 300. Here, since the first condition and the second condition are satisfied, the storage block manager 260 may select the first write mode and may provide information about the storage block type BLK_TYPE to be used in the write operation determined based on the first write mode to the host request operation controller 270. For example, the information about the storage block type BLK_TYPE may include information indicating a single storage block SLC BLK determined based on the first write mode.

[0068] In an embodiment, the host request operation controller 270 may provide a write command, an address of a single storage block SLC BLK indicating the write data DATA to be stored, and the write data DATA to the memory device 100 based on the information about the storage block type BLK_TYPE. In addition, the host request operation controller 270 may provide a write command, an address of the storage block indicating the write data DATA to be stored, a signal for controlling the corresponding storage block to operate as a single storage block SLC BLK, and the write data DATA to the memory device 100 based on the information about the storage block type BLK_TYPE.

[0069] The memory device 100 may store the write data DATA in the single storage block SLC BLK indicated by the address in response to the write command, or store one data bit in each of the memory cells included in the storage block indicated by the address.

[0070] Figure 5 is a diagram showing an example of performing a write operation in response to a garbage collection operation according to an embodiment of the present disclosure. Figure 5 Shows an example of performing a write operation included in a garbage collection operation when the first condition and the second condition are satisfied.

[0071] Reference Figure 5 , the memory controller 200 may control the memory device 100 to store the valid data DATA of the sacrifice storage block in the first write mode during a garbage collection operation including a write operation.

[0072] For example, when the conditions for the garbage collection operation are triggered, the background operation controller 280 may receive the valid data DATA stored in the sacrifice storage block in the memory device 100. Here, although the sacrifice storage block is shown as a multi-storage block XLC BLK, the present disclosure is not limited thereto. For example, in an embodiment, the sacrifice storage block may be a single storage block SLC BLK.

[0073] Here, since the first condition and the second condition are satisfied, the storage block manager 260 may select the first write mode and may provide information about the storage block type BLK_TYPE to be used in the write operation determined based on the first write mode to the background operation controller 280. The information about the storage block type BLK_TYPE may include information indicating the single storage block SLC BLK determined based on the first write mode.

[0074] In an embodiment, the background operation controller 280 may provide a write command, an address of the single storage block SLC BLK indicating the valid data DATA to be stored, and the valid data DATA to the memory device 100 based on the information about the storage block type BLK_TYPE. In addition, the background operation controller 280 may provide a write command, an address of the storage block indicating the valid data DATA to be stored, a signal for controlling the corresponding storage block to operate as a single storage block SLC BLK, and the valid data DATA to the memory device 100 based on the information about the storage block type BLK_TYPE.

[0075] The memory device 100 may store the valid data DATA in the single storage block SLC BLK indicated by the address in response to the write command, or store one data bit in each of the memory cells included in the storage block indicated by the address.

[0076] In an embodiment, the background operation controller 280 may control the memory device 100 to perform the write operation included in the garbage collection operation according to the determined write mode during the idle period. For example, the background operation controller 280 may determine whether the current state is an idle state, and when it is determined that the current state is an idle state, it may control the memory device 100 to perform the write operation included in the garbage collection operation based on the first write mode. On the other hand, when it is determined that the current state is not an idle state, the background operation controller 280 may wait for the idle state and then control the memory device 100 to perform the write operation included in the garbage collection operation based on the first write mode when the current state becomes an idle state. In some embodiments, when it is determined that the current state is not an idle state and in a specific case corresponding to the need to ensure an area for data storage in the memory device 100, the background operation controller 280 may control the memory device 100 to perform the write operation included in the garbage collection operation using the multi-storage block TLCBLK regardless of the determined write mode.

[0077] In an embodiment, the background operation controller 280 may control the memory device 100 to perform the write operation included in the garbage collection operation according to the determined write mode at a preset time such as dawn or when the battery of the host 300 is being charged.

[0078] In some implementations, when the memory device enters a stable state that does not meet the first condition and the second condition after performing a write operation according to the first write mode, the memory controller 200 may perform a data migration operation. The data migration operation may be an operation of controlling the memory device 100 to store data stored in some of the plurality of single memory blocks SLC BLK in a plurality of multi-memory blocks XLC BLK, and will be described and explained in detail below with reference to Figure 6 and Figure 7 will be described in detail and explained.

[0079] Figure 6 is a diagram showing an example of an operation of migrating data according to an embodiment of the present disclosure. Figure 6 An example of migrating data DATA stored in a single memory block SLC BLK based on the first write mode to a multi-memory block XLC BLK can be explained.

[0080] In an embodiment, after performing a write operation according to the first write mode, when the internal temperature is higher than a first reference temperature corresponding to a low temperature and lower than a second reference temperature corresponding to a high temperature and the execution period of the read recovery operation is equal to or longer than a reference period, the memory controller 200 may control the memory device 100 to migrate the data stored in the single memory block SLC BLK in the first write mode to the multi-memory block XLC BLK in the second write mode. In another example, after performing a write operation according to the first write mode, when the change in the internal temperature during a preset period is less than or equal to a reference value and the execution period of the read recovery operation is equal to or longer than a reference period, the memory controller 200 may control the memory device 100 to migrate the data stored in the single memory block SLC BLK in the first write mode to the multi-memory block XLC BLK in the second write mode.

[0081] Referring to Figure 6 , the storage block manager 260 may store a flag FLAG indicating at least one single memory block SLC BLK storing data DATA in the first write mode. For example, the storage block manager 260 may store a super block table for managing super blocks and may include the flag FLAG in the super block table. The background operation controller 280 may read the data DATA stored in the single memory block SLC BLK indicated by the received flag FLAG based on the flag FLAG. Thereafter, the background operation controller 280 may control the memory device 100 to store the read data DATA by migrating the read data DATA to the multi-memory block XLC BLK or storing a plurality of data bits in the memory cells included in the storage block.

[0082] In an embodiment, the background operation controller 280 may perform Figure 6The data migration operation shown in

[0083] Figure 7 is a diagram illustrating an example of an operation of migrating data according to an embodiment of the present disclosure. Figure 7 An example of migrating data stored in a single storage block SLC BLK to a multi - storage block XLC BLK can be explained. Here, the data stored in the single storage block SLC BLK may include all data stored based on the first write mode and data stored regardless of how the first write mode is.

[0084] Referring to Figure 7 , the storage block manager 260 may measure the data migration operation execution time MIG_TIME during which the data stored in each of the multiple single storage blocks SLC BLK is stored in another storage block. Here, the respective data migration operation execution times MIG_TIME of the multiple single storage blocks SLC BLK can be measured by recording the time required for individual test operations, normal write operations, read operations, or other operations.

[0085] In an embodiment, the background operation controller 280 may determine a target storage block based on the data migration operation execution times MIG_TIME of the received multiple single storage blocks SLC BLK.

[0086] In an embodiment, the background operation controller 280 may determine the target storage block in the order of shorter data migration operation execution times MIG_TIME among the multiple single storage blocks SLC BLK. In Figure 7 , although the single storage block SLC BLK having the shortest time required for the data migration operation is determined as the target storage block, the background operation controller 280 may be configured to determine the multiple single storage blocks SLC BLK as the target storage block in the order of shorter data migration operation execution times when the multiple single storage blocks SLC BLK are determined as the target storage block.

[0087] The background operation controller 280 may control the memory device 100 to read the data DATA stored in the determined single storage block SLC BLK and store the read data DATA in the multi - storage block XLC BLK.

[0088] In an embodiment, the background operation controller 280 may perform the Figure 7 data migration operation shown in

[0089] Figure 8 is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure. Figure 8 The method shown inFigure 1 is performed by the storage device 50 shown in

[0090] Reference Figure 8 , at step S801, the storage device 50 may measure the temperature of the storage device 50.

[0091] At step S803, the storage device 50 may calculate the number of read recovery operations.

[0092] At step S805, the storage device 50 may select a first write mode or a second write mode based on the temperature and the number of read recovery operations, where in the first write mode one data bit is stored in a memory cell and in the second write mode multiple data bits are stored in a memory cell.

[0093] In an embodiment, the storage device 50 may select a write mode according to whether a first condition based on temperature and a second condition based on the number of read recovery operations are satisfied. In an example, the storage device 50 may select the first write mode in response to the first condition and the second condition being satisfied. In an example, the storage device 50 may select the second write mode in response to at least one of the first condition and the second condition not being satisfied.

[0094] At step S807, the storage device 50 may perform a write operation according to the selected write mode. Here, the write operation may include at least one of a write operation corresponding to a request from the host 300 and a write operation included in a background operation.

[0095] Figure 9 is a flowchart showing a method of performing a write operation according to an embodiment of the present disclosure. Figure 9 The method shown in Figure 1 may be performed by the storage device 50 shown in Figure 9 is illustrative of Figure 8 steps S805 and S807 of

[0096] Reference Figure 9 , in step S901, the storage device 50 may determine whether a first condition based on temperature is satisfied. For example, when the temperature falls within a preset temperature range or when the temperature change within a preset period is greater than a reference value, the storage device 50 may determine that the first condition is satisfied. Here, the preset temperature range may include a range below a first reference temperature corresponding to a low temperature or above a second reference temperature corresponding to a high temperature.

[0097] Based on the determination result of step S901, when the first condition is satisfied, the storage device 50 may perform step S903.

[0098] At step S903, the storage device 50 may determine whether a second condition based on the number of read recovery operations is satisfied. For example, when the execution period of the read recovery operation based on the number of read recovery operations is shorter than a reference period, the storage device 50 may determine that the second condition is satisfied.

[0099] Based on the determination result of step S903, when the second condition is satisfied, the storage device 50 may execute step S905.

[0100] At step S905, the storage device 50 may perform a write operation according to the first write mode.

[0101] When the first condition or the second condition is not satisfied based on the determination results of steps S901 and S903, the storage device 50 may execute step S907. For example, when the temperature exceeds a preset temperature range while the temperature change during a preset period is less than or equal to a reference value, the storage device 50 may determine that the first condition is not satisfied. When the execution period of the read recovery operation is equal to or longer than the reference period, the storage device 50 may determine that the second condition is not satisfied. In this case, the storage device 50 may select a second write mode in response to the situation that at least one of the first condition and the second condition is not satisfied.

[0102] At step S907, the storage device 50 may perform a write operation according to the second write mode.

[0103] Figure 10 is a flowchart showing a method of performing an operation of migrating data according to an embodiment of the present disclosure. Figure 10 The method shown in Figure 1 may be executed by the storage device 50 shown in Figure 10 is for explaining the method executed after step S807 in Figure 8 and step S1001 may indicate Figure 8 step S807 of

[0104] Refer to Figure 10 , at step S1001, the storage device 50 may perform a write operation according to the first write mode.

[0105] At step S1003, the storage device 50 may determine whether a first condition based on temperature is satisfied. For example, when the temperature exceeds a preset temperature range while the temperature change during a preset period is less than or equal to a reference value, the storage device 50 may determine that the first condition is not satisfied. Based on the determination result of step S1003, when the first condition is not satisfied, the storage device 50 may execute step S1005.

[0106] At step S1005, the storage device 50 may determine whether a second condition based on the number of error bits is satisfied. For example, when the execution period of the read recycling operation is equal to or longer than a reference period, the storage device 50 may determine that the second condition is not satisfied. Based on the determination result of step S1005, when the second condition is not satisfied, the storage device 50 may execute step S1007.

[0107] In an embodiment, the storage device 50 may migrate data stored in a first storage block in a first write mode to a second storage block in a second write mode in response to a situation where the first condition and the second condition are not satisfied.

[0108] For example, at step S1007, the storage device 50 may determine whether the current state is an idle state. Based on the determination result of step S1007, when the current state is an idle state, the storage device 50 may execute step S1009.

[0109] At step S1009, the storage device 50 may migrate data stored in the first storage block to the second storage block in response to the current state being an idle state.

[0110] On the other hand, when the first condition or the second condition is satisfied based on the determination results of steps S1003 and S1005, or when the current state is not an idle state based on the determination result of step S1007, the storage device 50 may execute step S1003 by returning to step S1003.

[0111] According to the present disclosure, a storage device with improved reliability and a method of operating the storage device are provided.

Claims

1. A storage device, comprising: A memory device including a plurality of memory blocks, each memory block including a plurality of memory cells storing data; as well as A memory controller communicates with the memory device and 1) determines a write mode of the memory block to be a first write mode or a second write mode based on a temperature of the memory device and a number of read reclaim operations that have been performed in a memory block of the memory device, wherein one data bit is stored in a memory cell of the memory block, and wherein a plurality of data bits are stored in the memory cell, and 2) controls the memory device to perform a write operation in the determined write mode.

2. The storage device according to claim 1, wherein: The memory controller controls the memory device to perform the write operation based on the first write mode in response to a first condition that the temperature is lower than a first reference temperature corresponding to a low temperature or higher than a second reference temperature corresponding to a high temperature and a second condition that an execution cycle of the read recovery operation based on the number of the read recovery operations is shorter than a reference cycle.

3. The storage device according to claim 1, wherein: The memory controller controls the memory device to perform the write operation based on the first write mode in response to satisfying a first condition that the change in the temperature during a preset period is greater than a reference value and satisfying a second condition that an execution cycle of the read recovery operation based on the number of the read recovery operations is shorter than a reference cycle.

4. The storage device according to claim 1, wherein: The memory controller controls the memory device to perform the write operation based on the second write mode in response to the temperature being higher than a first reference temperature corresponding to a low temperature and lower than a second reference temperature corresponding to a high temperature.

5. The storage device according to claim 1, wherein: The memory controller controls the memory device to perform the write operation based on the second write mode in response to the change in the temperature during a preset period being less than or equal to a reference value.

6. The storage device according to claim 1, wherein: The memory controller controls the memory device to perform the write operation based on the second write mode in response to an execution cycle of the read reclaim operation obtained based on the number of the read reclaim operations being equal to or longer than a reference cycle.

7. The storage device according to claim 1, wherein: The memory controller controls the memory device to store data corresponding to the write operation based on the write mode in response to receiving a request for the write operation from a host or during a garbage collection operation including the write operation.

8. The storage device according to claim 1, wherein: The memory controller controls the memory device to perform the write operation based on the write mode during an idle period in which no request for any operation is received from a host or no background operation is triggered.

9. The storage device according to claim 1, wherein: After performing the write operation according to the first write mode, the memory controller controls the memory device to migrate the data stored in the first storage block of the first write mode among the multiple storage blocks to the second storage block of the second write mode in response to satisfying a first condition that the temperature is higher than a first reference temperature corresponding to a low temperature and lower than a second reference temperature corresponding to a high temperature and satisfying a second condition that an execution cycle of the read recovery operation based on the number of read recovery operations is equal to or longer than a reference cycle.

10. The storage device according to claim 9, wherein: The memory controller controls the memory device to store a flag indicating the first memory block and migrates data stored in the first memory block to the second memory block based on the flag.

11. The storage device according to claim 9, wherein: The memory controller determines a target memory block storing data to be migrated to the second memory block among the plurality of first memory blocks based on a data migration operation execution time of the plurality of first memory blocks.

12. The storage device according to claim 11, wherein: The memory controller determines the target storage block, and a data migration operation execution time of the target storage block is shorter than a data migration operation execution time of other first storage blocks.

13. The storage device according to claim 9, wherein: The memory controller controls the memory device to migrate data stored in the first memory block to the second memory block during an idle time when no request for any operation is received from a host or no background operation is triggered.

14. The storage device according to claim 1, wherein: After the memory controller performs the write operation on the storage block based on the first write mode, in response to satisfying a first condition that the temperature change during a preset period is less than or equal to a reference value and satisfying a second condition that an execution cycle of the read recovery operation obtained based on the number of read recovery operations is equal to or longer than a reference cycle, the memory controller controls the memory device to migrate the data stored in the storage block of the first write mode to another storage block of the second write mode.

15. A method of operating a storage device, comprising: measuring a temperature of a memory device including a memory device including a plurality of memory blocks, each memory block including a plurality of memory cells storing data, and a memory controller communicating with and controlling the memory device; Count the number of read reclaim operations; Based on the temperature and the number of read reclaim operations, selecting a write mode of a memory block as a first write mode in which one data bit is stored in a memory cell of the memory block or a second write mode in which multiple data bits are stored in the memory cell; as well as The write operation is performed in the selected write mode.

16. The method according to claim 15, wherein: Selecting the write mode includes: The first write mode is selected in response to satisfying a first condition that the temperature is within a preset temperature range or the change in the temperature during a preset period is greater than a reference value and satisfying a second condition that an execution cycle of the read recovery operation obtained based on the number of the read recovery operations is shorter than a reference cycle.

17. The method of claim 15, further comprising after performing the write operation: In response to a first condition that the temperature exceeds the preset temperature range and the change in temperature during the preset period is less than or equal to a reference value and a second condition that the execution cycle of the read recovery operation is equal to or longer than the reference cycle, data stored in a first storage block in the first write mode among multiple storage blocks is migrated to a second storage block in the second write mode.

18. The method according to claim 17, wherein: Migrating said data includes: determining whether the current state is an idle state in which no request for any operation is received from the host or no background operation is triggered; and In response to the current state being the idle state, data stored in the first storage block is migrated to the second storage block.

19. The method according to claim 15, wherein: Selecting one of the write modes further comprises: The second writing mode is selected in response to satisfying a first condition that the temperature exceeds a preset temperature range and a change in the temperature during a preset period is less than or equal to a reference value, or satisfying a second condition that an execution period of the read recovery operation is equal to or longer than a reference period.

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