Computer system and method for performing random access to bits in memory

Abstract

The disclosure relates to computer systems and methods for performing random access to bits in memory. According to one aspect, there is provided a computer system comprising: a data memory configured to store an array of bytes; a digital signal processor configured to execute a computer program stored in a program memory, the computer program including instructions to allow access to bits in the byte array, the digital signal processor configured to access each byte of the byte array; dedicated circuitry configured to read and / or write bits of bytes accessing the byte array using: a bit position pointer pointing to a bit to be accessed in the byte array; and the byte including a bit to be accessed.

Description

Technical Field

[0001] Embodiments and implementations relate to random reading and writing of bits in a data memory of a computer system. Background Art

[0002] A computer system may include a data memory configured to store an array of bytes and a central processing unit configured to perform read and / or write access to the data memory to read or write words in the array of bytes.

[0003] Generally, the central processing unit is configured to perform read and / or write access to the data memory to read 8-bit, 16-bit or 32-bit words.

[0004] Some applications require random reading and / or writing of bits in an array of bytes stored in the data memory of a computer system. Random reading and / or writing means performing the reading and / or writing at unpredictable times. Specifically, read and / or write access may be performed to read and / or write each bit of the array of bytes. For example, a known application that requires random reading or writing of bits in a data memory is the encoding and decoding of audio signals.

[0005] In these applications, memory access on 8 bits, 16 bits or 32 bits does not allow direct reading or writing of bits in the data memory.

[0006] To access only one bit in an array of bytes of a data memory, generally the byte of the array of bytes including the bit to be accessed is accessed, and then a mask associated with the position of the bit to be accessed in the byte is used to select the bit in the byte. This access to the bit is performed by the central processing unit in a software manner.

[0007] This method requires performing several tests and updates to access a single bit. Specifically, the mask should be updated for each bit to be accessed. These tests and updates performed in a software manner may require several cycles of the central processing unit. Therefore, this access to the bit is relatively long to perform. In addition, due to the need for many cycles of the central processing unit, this access to the bit consumes a relatively large amount of energy. However, for some applications, especially for low energy Bluetooth (also known by the acronym "BLE" which stands for "Bluetooth Low Energy" in English), it is necessary to minimize the energy consumption and the number of computations for performing a given task.

[0008] Therefore, there is a need to provide a technical solution that allows simpler and faster access to bits in an array of bytes. Summary of the Invention

[0009] In some embodiments, a computer system is provided, including: a data memory configured to store a byte array; a program memory configured to store a computer program; a digital signal processor configured to execute the computer program, the computer program including instructions to allow access to bits in the byte array, the digital signal processor being configured to access each byte of the byte array; and a special circuit, particularly integrated in the digital signal processor, configured to read and / or write bits of a byte accessing the byte array using: a bit position pointer pointing to the bit to be accessed in the byte array, and the byte including the bit to be accessed.

[0010] In some embodiments, the computer system uses a bit position pointer in combination with a mask instead of a byte position pointer.

[0011] In some embodiments, the computer system is configured to use a special circuit to randomly access bits in a memory to execute some instructions. The special circuit occupies very little space in the computer system and greatly improves the latency for accessing bits in the memory.

[0012] In some embodiments, the computer system is configured to simply and quickly randomly access bits in a memory. Such a special circuit requires several execution cycles of the digital signal processor to randomly access bits in the memory.

[0013] In some embodiments, the special circuit also allows reducing the energy consumption for randomly accessing bits in a memory because such access is performed by executing several operations and within several cycles.

[0014] In some embodiments, the special circuit includes a first block configured to calculate a byte shift value based on the value of the bit position pointer.

[0015] In some embodiments, the first block of the special circuit includes:

[0016] An "AND"-type logic gate configured to perform an "AND"-type logic operation between the value of the bit position pointer and the hexadecimal value 0x7 to obtain an index value,

[0017] A comparison circuit configured to calculate the byte shift value by comparing the index value with 0, where the byte shift value is equal to -1 when the index value is equal to 0, and otherwise equal to 0.

[0018] In some embodiments, the special circuit includes a second block configured to determine the value of the bit to be read from the bit position pointer and the byte including the bit to be read.

[0019] In some embodiments, the second block of the dedicated circuit includes: an adder circuit configured to increment the value of the bit position pointer by 1; a first "AND" type logic gate configured to perform a "AND" type logical operation between the incremented value of the bit position pointer and a hexadecimal value equal to 0x7; a subtractor circuit configured to calculate a shift value by subtracting a value equal to 7 from the value at the output of the first "AND" type logic gate; a shift circuit configured to shift the value of the byte including the bit to be accessed to the right by a number of bits corresponding to the shift value; a second "AND" type logic gate configured to perform a "AND" type logical operation between a value equal to 1 and the shifted value of the byte, thereby obtaining the value of the bit to be read.

[0020] In some embodiments, the dedicated circuit uses two blocks for reading bits in a byte array. In some embodiments, all tests for reading bits are performed by the dedicated circuit, rather than by the central processing unit of the computer system. In this way, random read access to bits in the byte array of the data memory can be performed more quickly.

[0021] In some embodiments, a computer program includes instructions that, when implemented by a digital signal processor, cause the digital signal processor to perform at least one invocation of a function to read bits in a byte array, each invocation of the function taking as inputs the bit position pointer and the byte pointer as attributes and causing: calculating a byte shift value by the first block, then updating the byte pointer with the byte shift value, and then determining the value of the bit to be read by the second block of the dedicated circuit.

[0022] In some embodiments, to program such a read of bits in the byte array of the data memory, intrinsic functions that allow the use of the dedicated circuit can be used. The intrinsic functions are integrated into the compiler. This allows for simplification of the programming of such random access to bits in the data memory.

[0023] In some embodiments, the dedicated circuit includes a third block configured to write the value of the bit in the byte to be written rather than writing the value of the bit at the bit pointed to by the bit position pointer.

[0024] In some embodiments, the third block of the dedicated circuit includes: an adder circuit configured to increment the value of the bit position pointer by 1; a first logic gate of the "AND" type configured to perform a logical operation of the "ADD" type between the incremented value of the bit position pointer and a hexadecimal value equal to 0x7; a subtractor circuit configured to calculate a shift value by subtracting a value equal to 7 from the value at the output of the first logic gate of the "AND" type; a shift circuit configured to shift the value 1 to the left by a number of bits corresponding to the shift value to create a mask; an inverter logic gate configured to create a complementary mask based on the mask obtained at the output of the shift circuit; a second logic circuit of the "AND" type configured to apply the complementary mask to the byte to be written to obtain a first byte B0; a logic circuit of the "OR" type configured to apply the mask to the byte to be written to obtain a second byte; and a selection circuit configured to: generate a byte corresponding to the first byte if the value of the bit to be written is equal to 1, and otherwise generate a byte corresponding to the second byte.

[0025] In some embodiments, the computer program includes instructions that, when implemented by a digital signal processor, cause the digital signal processor to perform at least one call of a function to write a bit in a byte array, each call of the function taking as inputs the bit position pointer and the byte pointer as attributes and causing: calculating a byte shift value by the first block, then updating the byte pointer with the byte shift value, and then writing the bit to be written by the third block of the dedicated circuit. To program such a write of a bit in the byte array of the data memory, it is also possible to use the intrinsic functions of the dedicated circuit.

[0026] In some embodiments, the computer program includes instructions that, when implemented by a digital signal processor, cause the digital signal processor to start the bit position pointer such that it points to the position of the last bit of the byte array and decrement the bit position pointer at each read and / or write access.

[0027] In some embodiments, a method implemented by a computer system for reading and / or writing access to bits of a byte in a byte array stored in the data memory of the computer system is provided, the method including updating instructions of a computer program by a digital signal processor of the computer system such that: accessing the byte stored in the data memory by the digital signal processor, updating a dedicated circuit of the computer system, in particular a dedicated circuit integrated in the digital signal processor, to read and / or write access the bits of the byte accessed by the digital signal processor using: a bit position pointer pointing to the bit to be accessed in the byte array, and the byte including the bit to be accessed.

[0028] In some embodiments, the method includes: implementing a first block of a dedicated circuit to calculate a byte shift value based on the value of a bit position pointer.

[0029] In some embodiments, the implementation of the first block of the dedicated circuit causes: implementing an "AND"-type logic gate of the first block to perform an "AND"-type logic operation between the value of the bit position pointer and the hexadecimal value 0x7 to obtain an index value, implementing a comparison circuit of the first block to calculate the byte shift value by comparing the index value with 0, and when the index value is equal to 0, the byte shift value is equal to -1, otherwise it is equal to 0.

[0030] In some embodiments, the method further includes: implementing a second block of the dedicated circuit to determine the value of the bit to be read from the bit position pointer and the byte including the bit to be read.

[0031] In some embodiments, the implementation of the second block of the dedicated circuit causes: implementing an adder circuit of the second block to increment the value of the bit position pointer by 1, implementing an "AND"-type first logic gate of the second block to perform an "AND"-type logic operation between the incremented value of the bit position pointer and the hexadecimal value equal to 0x7, implementing a subtractor circuit of the second block to calculate a shift value by subtracting a value equal to 7 from the value at the output of the "AND"-type first logic gate, implementing a shift circuit of the second block to shift the value of the byte including the bit to be accessed to the right by a number of bits corresponding to the shift value, and implementing an "AND"-type second logic gate of the second block to perform an "AND"-type logic operation between a value equal to 1 and the shifted value of the byte to obtain the value of the bit to be read.

[0032] In some embodiments, the method includes: implementing instructions of a computer program via a digital signal processor, causing at least one call of a function to read bits in a byte array, each call of the function taking the bit position pointer and the byte pointer as attributes as inputs and causing: calculating the byte shift value via the first block, then updating the byte pointer with the byte shift value, and then determining the value of the bit to be read by the second block of the dedicated circuit.

[0033] In some embodiments, the method further includes: implementing a third block of the dedicated circuit to write the value of the bit in the byte to be written instead of writing the value of the bit at the bit pointed to by the bit position pointer.

[0034] In some embodiments, the implementation of the third block of the dedicated circuit results in: implementing an adder circuit of the third block to increment the value of the bit position pointer by 1, implementing a first logic gate of the "AND" type of the third block to perform a logic operation of the "AND" type between the incremented value of the bit position pointer and a hexadecimal value equal to 0x7, implementing a subtractor circuit of the third block to calculate a shift value by subtracting a value equal to 7 from the value at the output of the first logic gate of the "AND" type, implementing a shift circuit of the third block to shift the value 1 to the left by a number of bits corresponding to the shift value to create a mask, implementing an inverter logic gate of the third block to create a complementary mask based on the mask obtained through the implementation of the shift circuit, implementing a second logic circuit of the "AND" type of the third block to apply the complementary mask to the byte to be written to obtain a first byte, implementing a logic circuit of the "OR" type of the third block to apply the mask to the byte to be written to obtain a second byte, and implementing a selection circuit to: generate a byte BTE_OUT corresponding to the first byte if the value of the bit to be written is equal to 0, otherwise generate a byte BTE_OUT corresponding to the second byte.

[0035] In some embodiments, implementing the instructions of a computer program by a digital signal processor includes: causing at least one call of a function to write a bit in a byte array, each call of the function taking as input a bit position pointer and a byte pointer as attributes and causing: calculating a byte shift value by the first block, then updating the byte pointer with the byte shift value, and then writing the bit to be written by the third block of the dedicated circuit.

[0036] In some embodiments, the method includes: implementing the instructions of a computer program by a digital signal processor, such that a bit position pointer is initiated to point to the position of the last bit of a byte array, and the bit position pointer is decremented at each read and / or write access. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Other advantages and features of the present disclosure will become apparent upon examination of the detailed description of non-limiting embodiments and in accordance with the drawings, in which:

[0038] Figure 1 illustrates a computer system for bits in a random access memory in some embodiments;

[0039] Figure 2 is a block diagram illustrating the logic that can be used to determine the next value of a byte shift OFFST in some embodiments;

[0040] Figure 3 is a logic circuit diagram illustrating the logic for reading a selected bit;

[0041] Figure 4 is a logic flow diagram illustrating the process of reading a selected bit in some embodiments;

[0042] Figure 5 is a logic circuit diagram illustrating the logic for writing selected bits in some embodiments; and

[0043] Figure 6 is a logic flow diagram illustrating the process for writing selected bits in some embodiments. Detailed Description

[0044] Figure 1 Illustrates an embodiment of a computer system SYS. The computer system SYS includes a central processing unit CPU and a central memory MMEM. The computer system also includes a digital signal processor (i.e., "DSP") and a data memory MEM, a program memory MEMP, and a circuit HWC dedicated to reading and / or writing access to bits in bytes. The latter is integrated into the arithmetic and logic unit (i.e., "ALU") of the digital signal processor DSP. The digital signal processor DSP also includes a control unit (i.e., "CU"), an address generation unit (i.e., "AGU"), and a register bank. The computer system SYS can be a system-on-chip.

[0045] The data memory MEM is configured to store an array of bytes BTAB. The memory MEM can be read or written accessed by the digital signal processor DSP. Each access by the digital signal processor DSP to the memory is performed on a word having a size of at least one byte. Thus, the digital signal processor DSP can access each byte of the array of bytes BTAB in the memory MEM. The digital signal processor DSP can place the loaded byte in its register, which acts as a buffer between the data memory MEM and the ALU of the digital signal processor DSP. However, the digital signal processor DSP cannot directly read or write the bits in the array of bytes.

[0046] The data of the array of bytes BTAB can correspond to compressed data of an audio data stream. Specifically, the audio data stream includes a series of audio samples. These samples can be compressed to reduce their size. For example, the samples can be independently compressed to one bit, two bits, three bits, or four bits. Each bit of the audio data stream can have its own meaning. For example, the value of each bit of the data stream may affect the actions to be taken during the decompression process. This is why it is important to be able to access the bits of the compressed audio data stream. Therefore, it is important to be able to access each bit of the array of bytes stored in the memory.

[0047] The digital signal processor DSP is configured to execute a computer program PRG that includes instructions which, when implemented in the digital signal processor DSP, cause the digital signal processor DSP to perform read and / or write access to the bits of the bytes of a byte array stored in a memory. The computer program PRG can be stored in the program memory MEMP of the computer system SYS.

[0048] The digital signal processor DSP can allocate a first register R1 to store the read byte BTE_IN from the byte array BTAB stored in the memory MEM. The digital signal processor DSP can also allocate a second register R2 to store the position pointer BITP of the bit to be accessed in the byte array BTAB. The digital signal processor DSP can also allocate a third register R3 to store the byte shift value OFFST. The digital signal processor DSP can also allocate a fourth register R4 to store the value BIT_OUT of the bit to be accessed. For writing a bit, the digital signal processor DSP uses the register R4 to store the bit BIT_IN to be written in the byte BTE_IN contained in the register R1. The digital signal processor DSP re-uses the register R1 to store the resulting byte BTE_OUT with the written bit at the output.

[0049] Specifically, the circuit HWC can be obtained from the code “Register Transfer Level” (i.e., “RTL”).

[0050] The dedicated circuit HWC includes a first block NXTBBW that is configured to determine the next value of the byte shift OFFST. Such a first block NXTBBW is illustrated in Figure 2 which.

[0051] Specifically, the first block NXTBBW is configured to receive the value of the bit position pointer BITP stored in the second register R2 as an input.

[0052] The first block NXTBBW includes an “AND”-type logic gate AND1. The logic gate AND1 is configured to receive the value of the bit position pointer BITP and a mask with the value “0x7” (in hexadecimal) as inputs. The “AND”-type logic gate is configured to apply the mask with the value “0x7” to the value of the bit position pointer BITP. Thus, the “AND”-type logic gate allows knowing whether the byte pointer should be pre-adjusted via the byte shift OFFST from the three least significant bits of the bit position pointer BITP.

[0053] The logic gate AND1 is configured to generate an index value INDX as an output. Specifically, the index value INDX on a byte is included between 0 and 7. Thus, the index value INDX can be known by observing only the three least significant bits of the bit position pointer.

[0054] The first NXTBBW also includes a comparison circuit CMPC that takes the index value INDX as an input. The comparison circuit CMPC allows verification of whether the index value is 0. If the index value is 0, this means that only a single bit of the byte remains to be read, since the other bits have been read previously. In this case, after the last bit of the current byte has been read, the byte shift value should be modified to handle the next byte in the byte array.

[0055] Specifically, the comparison circuit CMPC also takes as inputs two parameters with values “-1” and “0”.

[0056] Thus, the comparison circuit CMPC is configured to compare the index value INDX with the value “0” and generate the next value of the byte shift based on the result of this comparison. Specifically, the comparison circuit CMPC is configured to: when the index value is equal to “0”, generate the next value of the byte shift OFFST at “-1”; and when the index value is different from “0”, generate the next value of the byte shift OFFST at “0”. Thereafter, this next value of the byte shift OFFST is stored in the third register R3.

[0057] Then, the first NXTBBW is configured to determine the byte shift value OFFST within a single cycle in the digital signal processor DSP.

[0058] The dedicated circuit HWC includes a second READBIT block that is configured to determine the value BIT_OUT of a given bit in the byte BTE_IN. Such a second READBIT block is illustrated in Figure 3 . The second READBIT block is configured to receive as inputs the value of the bit position pointer BITP stored in the second register R2 and the byte BTE_IN stored in the first register R1.

[0059] The second READBIT block includes an adder circuit ADD1 that is configured to receive as inputs the value of the bit position pointer BITP and a value equal to “1”. Thus, the adder circuit ADD1 is configured to add “1” to the value of the bit position pointer BITP.

[0060] The second READBIT block also includes a first “AND” type logic gate AND2 that is configured to receive as inputs the value of the bit position pointer BITP plus “1” and a mask with a hexadecimal value “0x7”.

[0061] The second READBIT also includes a subtractor circuit SUB1, which is configured to receive a value equal to "7" and the value generated at the output of the logic gate AND2 as inputs. The subtractor circuit SUB1 is configured to generate a value SL, which corresponds to the difference between the value "7" and the value generated at the output of the logic gate AND2.

[0062] Therefore, the value SL is calculated by the following formula: SL = 7 - (BITP + 1) & 0x7.

[0063] The second READBIT also includes a shift register SFT1, which is configured to receive the byte BTE_IN stored in the first register R1 and shift the byte BTE_IN to the right by a number of bits corresponding to the value SL.

[0064] The second READBIT also includes a second "AND" logic gate AND3, which is configured to receive a value equal to "1" and the shifted byte generated at the output of the shift register SFT1 as inputs. Therefore, the logic gate AND3 allows the generation of the value BIT_OUT of the least significant bit of the shifted byte as the output. This value corresponds to the value of the bit of the byte BTE_IN stored in the first register at the position pointed to by the bit position pointer BITP. Thereafter, this value BIT_OUT of the bit of the byte BTE_IN is stored in the fourth register R4.

[0065] Therefore, the second READBIT allows the determination of the value BIT_OUT of the bit of the byte BTE_IN stored in the first register R1 at the position pointed to by the bit position pointer BITP. Specifically, the second READBIT is configured to determine the value BIT_OUT within a single cycle of the digital signal processor DSP.

[0066] The third WRITEBIT is configured to write the bit BIT_IN to the position BITP in the byte BTE_IN stored in the first register R1. In Figure 5 such a third WRITEBIT is illustrated.

[0067] The third WRITEBIT is configured to receive the value of the bit BIT_IN stored in the fourth register R4, the value of the bit position pointer BITP stored in the second register R2, and the byte BTE_IN stored in the first register R1 as inputs.

[0068] The third WRITEBIT includes an adder circuit ADD1, which is configured to receive the value of the bit position pointer BITP and a value equal to "1" as inputs. Therefore, the adder circuit ADD1 is configured to add "1" to the value of the bit position pointer BITP.

[0069] The third WRITEBIT also includes a first "AND" logic gate AND2 configured to receive as inputs the value of the bit position pointer BITP incremented by "1" and a mask having a hexadecimal value of "0x7".

[0070] The third WRITEBIT also includes a subtractor circuit SUB1 configured to receive as inputs a value equal to "7" and the value generated at the output of the logic gate AND2. The subtractor circuit SUB1 is configured to generate a value SL corresponding to the difference between the value "7" and the value generated at the output of the logic gate AND2.

[0071] Thus, the value SL is calculated by the formula: SL = 7 - (BITP + 1) & 0x7.

[0072] The third WRITEBIT also includes a shift register SFT2 configured to calculate a mask MSK. The mask MSK is intended to insert the input bit BIT_IN into the byte BTE_IN. Specifically, the shift register SFT2 is configured to shift the value 1 to the left by the number of bits corresponding to the value SL to obtain the mask MSK.

[0073] The third WRITEBIT also includes an inverter gate NOT1 configured to invert the mask MSK to obtain a complementary mask INVMSK.

[0074] The third WRITEBIT also includes a second "AND" logic gate AND4 configured to apply the complementary mask INVMSK to the byte BTE_IN. Thus, this logic gate AND4 allows a first byte B0 to be generated as an output.

[0075] The third WRITEBIT also includes a logic gate OR1 of the "OR" type configured to perform a logical operation of the "OR" type between the mask MSK and the byte BTE_IN. Thus, this logic gate OR1 allows a second byte B1 to be generated at the output.

[0076] The third WRITEBIT also includes a selection circuit MUX1 configured to receive the bytes B0 and B1 and generate a byte BTE_OUT corresponding to the byte B0 or corresponding to the byte B1 according to the value of the bit BIT_IN. Specifically, if the value of the bit BIT_IN is equal to 0, the byte BTE_OUT corresponds to the byte B0. Otherwise, the byte BTE_OUT corresponds to the byte B1. Specifically, the selection circuit MUX1 can be a multiplexer.

[0077] The byte BTE_OUT obtained at the output of the selection circuit MUX1 corresponds to the byte BTE_IN, where the bit pointed to by the bit position pointer BITP has been modified by the value of the bit BIT_IN.

[0078] Thus, the third WRITEBIT block allows the value of bit BIT_IN to be written to the position in byte BTE_IN pointed to by bit position pointer BITP. Specifically, the third WRITEBIT block is configured to write the bit into byte BTE_IN within a single cycle of the digital signal processor DSP. The resulting byte BTE_OUT with the written bit is stored in register R1 at the output.

[0079] The third WRITEBIT block may share circuits ADD1, AND2, and SUB1 with the second READBIT block. Alternatively, the circuits ADD1, AND2, and SUB1 of the second READBIT block and the third WRITEBIT block may be different.

[0080] As previously seen, the digital signal processor DSP is configured to execute a computer program including instructions that, when executed, cause the digital signal processor DSP to perform read and / or write accesses to the bits of bytes of an array of bytes stored in a memory. Specifically, the execution of the instructions causes the digital signal processor DSP to execute function RD_BIT_NW or function WRT_BIT_NW.

[0081] Function RD_BIT_NW is configured to perform a random read access to a bit in an array of bytes stored in memory MEM. Specifically, the function RD_BIT_NW is called a number of times to read all the bits of byte array BTAB.

[0082] Specifically, computer program PRG is configured to implement Figure 4 the method for read access to bits stored in byte array BTAB illustrated in

[0083] More specifically, computer program PRG includes instructions that allow the execution of start step 40. This step 40 allows the bit position pointer BITP to be started at a value that is one less than the length of the sequence of bits of byte array BTAB. This step 40 also allows the byte pointer to be started at the address of the last byte in byte array BTAB stored in memory MEM.

[0084] Thereafter, the function RD_BIT_NW may be called a number of times to read different bits of byte array BTAB. The call of function RD_BIT_NW allows the execution of steps 41, 42, 43, 44, and 45 described below. Thus, at each call of function RD_BIT_NW, these steps 41, 42, 43, 44, and 45 are executed.

[0085] Specifically, the function RD_BIT_NW is configured to pre-compute the next value of the byte shift. To this end, in step 41, the function RD_BIT_NW uses the instruction NXTBBW implemented by the first block NXTBBW of the dedicated circuit. Pre-computing the next value of the byte shift allows knowing the next byte to be used for the next read access to be performed for the next implementation of the function RD_BIT_NW. The instruction NXTBBW allows predicting the calculation of the next value of the byte shift before reading the bits in the current byte. This allows reducing the execution time of the function RD_BIT_NW by reducing the number of execution cycles of the digital signal processor DSP.

[0086] After that, in step 42, the function RD_BIT_NW is configured to decrement the bit position pointer BITP. Thus, the decremented bit position pointer BITP points to the position of the next bit in the byte array BTAB.

[0087] After that, in step 43, the function RD_BIT_NW is configured to read the current byte in the byte array pointed to by the byte pointer BPTR.

[0088] After that, in step 44, the function RD_BIT_NW is configured to update the byte pointer BPTR by adding the value of the byte shift to the byte pointer BPTR.

[0089] After that, in step 45, the function RD_BIT_NW is configured to read the current bit and then return the current bit. To this end, the function RD_BIT_NW uses the instruction READBIT implemented by the second block READBIT of the dedicated circuit.

[0090] In a processor of the "multiple issue" or "multi-threaded" type (i.e., which can execute several instructions in parallel, taking into account the data dependencies between them), these steps 41, 42, 43, 44, and 45 can be executed sequentially or in parallel.

[0091] The function RD_BIT_NW reads the bits in the byte array using only the bit position pointer BITP instead of the byte pointer BPTR and the mask. Thus, the function RB_BIT_NW uses only one variable instead of two variables. Starting from the bit position pointer BITP, using the first block NXTBBW of the dedicated circuit, the index value of the bit to be read in the current byte of the byte array can be determined, and the shift value of the byte containing the next bit to be read can be calculated. The first block NXTBBW and the second block READBIT of the dedicated circuit HWC are configured to perform all the calculations and tests to extract the bits to be read from the bytes of the byte array. This allows for a faster execution of the bit reading. For example, using the dedicated circuit allows for a reading access that is twice as fast as that performed by software using only the byte pointer and the mask.

[0092] This function RD_BIT_NW can be used in all applications that require random read access to bits in a byte array of a memory. Specifically, the function RD_BIT_NW can be used in any audio encoder-decoder that requires random read access to bits in a byte array of a memory. More specifically, the function RD_BIT_NW can be implemented in the "LC3 (Low Complexity Communication Codec in English)" audio encoder-decoder. For example, the function RD_BIT_NW can be implemented during the decoding of an audio data stream.

[0093] The computer program may also include instructions that, when executed by a digital signal processor DSP, cause the latter to execute the function WRT_BIT_NW. This function WRT_BIT_NW allows random write access to bits in a byte array stored in a memory.

[0094] The function WRT_BIT_NW is configured to perform random write access to bits in a byte array stored in the memory MEM. Specifically, the function WRT_BIT_NW is called a number of times to write to all bits of the byte array BTAB.

[0095] Specifically, the computer program PRG is configured to implement Figure 6 the process of writing access to bits in the byte array BTAB illustrated in

[0096] More specifically, the computer program PRG includes instructions that allow the execution of a start step 60. This step 60 allows starting a bit position pointer BITP at a value that is one less than the length of a sequence of bits in the byte array BTAB. This step 60 also allows starting a byte pointer at the address of the last byte in the byte array BTAB stored in the memory MEM.

[0097] Thereafter, the function WRT_BIT_NW can be called a number of times to write to different bits of the byte array BTAB. The call of the function WRT_BIT_NW allows the execution of steps 61, 62, 63, 64, and 65 described below. Thus, these steps 61, 62, 63, 64, and 65 are executed each time the function WRT_BIT_NW is called.

[0098] Specifically, the function WRT_BIT_NW is configured to pre-compute the next value of the byte shift. To this end, in step 61, the function WRT_BIT_NW uses the instruction NXTBBW implemented by the first block NXTBBW of the dedicated circuit. Pre-computing the next value of the byte shift allows knowing the next byte for the next write access to be performed for the next implementation of the function WRT_BIT_NW. The instruction NXTBBW allows predicting the calculation of the next value of the byte shift before performing the write of the bits in the current byte. This allows reducing the execution time of the function WRT_BIT_NW by reducing the number of execution cycles of the digital signal processor DSP.

[0099] After that, in step 62, the function WRT_BIT_NW is configured to decrement the bit position pointer. Thus, the decremented bit position pointer points to the position of the next bit in the byte array BTAB.

[0100] Subsequently, in step 63, the function WRT_BIT_NW is configured to read the current byte in the byte array pointed to by the byte pointer.

[0101] Subsequently, in step 64, the function WRT_BIT_NW is configured to update the byte pointer by adding the value of the byte shift to the byte pointer.

[0102] After that, in step 65, the function WRT_BIT_NW is configured to write the bit BIT_IN into the current bit. To this end, the function WRT_BIT_NW uses the instruction WRITEBIT implemented by the third block WRITEBIT of the dedicated circuit.

[0103] In a "multiple issue" or "multi-threaded" type of processor, these steps 61, 62, 63, 64, and 65 can be executed sequentially or in parallel.

[0104] The function WRT_BIT_NW writes bits into the byte array using only the bit position pointer instead of the byte pointer and the mask. Thus, the function WRT_BIT_NW uses only one variable instead of two variables. Starting from the bit position pointer, using the first block NXTBBW of the dedicated circuit, the index value of the bit to be written in the current byte of the byte array can be determined, and the shift value of the byte containing the next bit to be written can be calculated. The first block NXTBBW and the third block WRITEBIT of the dedicated circuit HWC are configured to perform all the calculations and tests for writing the bits of the byte array. This allows for a faster execution of the bit write. For example, using the dedicated circuit allows for a write access that is twice as fast as that performed by software using only the byte pointer and the mask.

[0105] Such a function WRT_BIT_NW can be used in all applications that require random write access to bits in a byte array of a memory. Specifically, the function WRT_BIT_NW can be used in any audio encoder-decoder that requires random read access to bits in a byte array of a memory. More specifically, the function WRT_BIT_NW can be implemented in the "LC3 (stands for 'Low Complexity Communication Codec' in English)" audio encoder-decoder.

[0106] In addition, the dedicated circuit HWC of the computer system SYS has the advantages of low cost and small space occupancy in the computer system. Using such a dedicated circuit does not affect the maximum frequency of the digital signal processor. Using such a dedicated circuit also allows reducing the energy consumption of reading bits in a byte array of a memory.

[0107] The computer system can be generally summarized as including: a data memory (MEM) configured to store a byte array (BTAB); and a program memory (MEMP) configured to store a computer program (PRG); a digital signal processor (DSP) configured to execute the computer program (PRG), the computer program including instructions that allow access to bits in the byte array (BTAB), the digital signal processor (DSP) being configured to access each byte of the byte array; a dedicated circuit (HWC) configured to perform read and / or write access to bits of bytes of the byte array using: a bit position pointer (BITP) pointing to the bit to be accessed in the byte array, and the byte (BTE_IN) including the bit to be accessed.

[0108] The dedicated circuit (HWC) can include a first block (NXTBBW) configured to calculate a byte shift value based on the value of the bit position pointer.

[0109] The first block (NXTBBW) of the dedicated circuit (HWC) can include: an "AND" type logic gate (AND1) configured to perform an "AND" type logic operation between the value of the bit position pointer (BITP) and the hexadecimal value 0x7 to obtain an index value (INDX); and a comparison circuit (COMPC) configured to calculate the byte shift value by comparing the index value (INDX) with 0, when the index value is equal to 0, the byte shift value is equal to -1, otherwise equal to 0.

[0110] The dedicated circuit (HWC) can include a second block (READBIT) configured to determine the value of the bit to be read from the bit position pointer (BITP), and the byte (BTE_IN) can include the bit to be read.

[0111] The second block (READBIT) of the dedicated circuit (HWC) may include: an adder circuit (ADD1) configured to increment the value of the bit position pointer by 1; a first "AND" type logic gate (AND2) configured to perform a "AND" type logical operation between the incremented value of the bit position pointer and a hexadecimal value equal to 0x7; a subtractor circuit (SUB1) configured to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the first "AND" type logic gate (AND2); a shift circuit (SFT1) configured to shift the value of the byte that may include the bit to be accessed to the right by a number of bits corresponding to the shift value (SL); and a second "AND" type logic gate (AND3) configured to perform a "AND" type logical operation between a value equal to 1 and the shifted value of the byte, thereby obtaining the value of the bit to be read (BIT_OUT).

[0112] A computer program (PRG) may include instructions that, when implemented by a digital signal processor, cause the digital signal processor to perform at least one invocation of a function (RD_BIT_NW) to read a bit in a byte array (BTAB), each invocation of the function taking the bit position pointer and the byte pointer as attributes as inputs and causing: calculating a byte shift value by means of the first block (OFFST), then updating the byte pointer with the byte shift value, and then determining the value of the bit to be read by the second block (READBIT) of the dedicated circuit (HWC).

[0113] The dedicated circuit (HWC) may include a third block (WRITEBIT) configured to write the value of the bit in the byte to be written (BTE_IN) rather than in the bit pointed to by the bit position pointer (BITP).

[0114] The third block (WRITEBIT) of the dedicated circuit (HWC) may include: an adder circuit (ADD1) configured to increment the value of a bit position pointer by 1; a first "AND" type logic gate (AND2) configured to perform an "AND" type logic operation between the incremented value of the bit position pointer and a hexadecimal value equal to 0x7; a subtractor circuit (SUB1) configured to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the first "AND" type logic gate (AND2); a shift circuit (SFT2) configured to shift the value 1 to the left by a number of bits corresponding to the shift value (SL) to create a mask (MSK); an inverter logic gate (NOT1) configured to create a complementary mask (INVMSK) based on the mask (MSK) obtained at the output of the shift circuit (SFT2); a second "AND" type logic circuit (AND4) configured to apply the complementary mask (INVMSK) to a byte to be written (BTE_IN) to obtain a first byte (B0); an "OR" type logic circuit (OR1) configured to apply the mask (MSK) to the byte to be written (BTE_IN) to obtain a second byte (B1); and a selection circuit (MUX1) configured to: generate a byte (BTE_OUT) corresponding to the first byte (B0) if the value of the bit to be written is equal to 0, or otherwise generate a byte (BTE_OUT) corresponding to the second byte (B1).

[0115] A computer program (PRG) may include instructions that, when implemented by a digital signal processor, cause the digital signal processor to perform at least one invocation of a function (WRT_BIT_NW) to write a bit in a byte array (BTAB), each invocation of the function taking as inputs a bit position pointer and a byte pointer as attributes and causing: calculating a byte shift value by the first block (OFFST), then updating the byte pointer with the byte shift value, and then writing the bit to be written by the third block (WRITEBIT) of the dedicated circuit (HWC).

[0116] A computer program (PRG) may include instructions that, when implemented by a digital signal processor (DSP), cause the digital signal processor to initiate a bit position pointer such that it points to the position of the last bit of a byte array (BTAB) and decrement the bit position pointer (BITP) on each read and / or write access.

[0117] A method implemented by a computer system (SYS) for reading and / or writing access to bits of a byte in a byte array (BTAB) stored in the data memory (MEM) of the computer system, the method can be generally summarized as including: updating instructions of a computer program (PRG) stored in a program memory (MEMP) by a digital signal processor (DSP) of the computer system (SYS), such that: accessing the byte stored in the data memory (MEM) by the digital signal processor (DSP), and updating a dedicated circuit (HWC) of the computer system (SYS) to read and / or write access to the bits of the byte accessed by the digital signal processor (DSP) using: a bit position pointer (BITP) pointing to the bit to be accessed in the byte array, and the byte (BTE_IN) including the bit to be accessed.

[0118] The method can include: implementing a first block (NXTBBW) of the dedicated circuit (HWC) to calculate a byte shift value (OFFST) according to the value of the bit position pointer (BITP).

[0119] The implementation of the first block (NXTBBW) of the dedicated circuit (HWC) can be such that: implementing an "AND" type logic gate (AND1) of the first block (NXTBBW) to perform an "AND" type logic operation between the value of the bit position pointer (BITP) and the hexadecimal value 0x7 to obtain an index value (INDX); implementing a comparison circuit (COMPC) of the first block (NXTBBW) to calculate the byte shift value by comparing the index value (INDX) with 0, when the index value is equal to 0, the byte shift value is equal to -1, otherwise equal to 0.

[0120] The method can further include: implementing a second block (READBIT) of the dedicated circuit (HWC) to determine the value of the bit to be read from the bit position pointer (BITP), and the byte (BTE_IN) can include the bit to be read.

[0121] The implementation of the second block (READBIT) of the dedicated circuit (HWC) can enable: implementing an adder circuit (ADD1) of the second block (READBIT) to increment the value of the bit position pointer by 1; implementing a first "AND" type logic gate (AND2) of the second block (READBIT) to perform a "AND" type logical operation between the incremented value of the bit position pointer and a hexadecimal value equal to 0x7; implementing a subtractor circuit (SUB1) of the second block (READBIT) to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the first "AND" type logic gate (AND2); implementing a shift circuit (SFT1) of the second block (READBIT) to shift the value of the byte that may include the bit to be accessed to the right by a number of bits corresponding to the shift value (SL); and implementing a second "AND" type logic gate (AND3) of the second block (READBIT) to perform a "AND" type logical operation between a value equal to 1 and the shifted value of the byte to obtain the value of the bit to be read (BIT_OUT).

[0122] The method may include: at least one call of a function (RD_BIT_NW) to read a bit in a byte array (BTAB) is caused by executing an instruction of a computer program (PRG) by a digital signal processor (DSP), each call of the function takes a bit position pointer and a byte pointer as attributes as inputs and enables: calculating a byte shift value by the first block (OFFST), then updating the byte pointer with the byte shift value, and then determining the value of the bit to be read by the second block (READBIT) of the dedicated circuit (HWC).

[0123] The method may further include: implementing a third block (WRITEBIT) of the dedicated circuit (HWC) to write the value of the bit in the byte to be written (BTE_IN) instead of writing the value of the bit at the bit pointed to by the bit position pointer (BITP).

[0124] The implementation of the third block (WRITEBIT) of the dedicated circuit (HWC) enables: implementing an adder circuit (ADD1) of the third block (WRITEBIT) to increment the value of the bit position pointer by 1; implementing a first logic gate (AND2) of the "AND" type of the third block (WRITEBIT) to perform a logic operation of the "AND" type between the incremented value of the bit position pointer and a hexadecimal value equal to 0x7; implementing a subtractor circuit (SUB1) of the third block (WRITEBIT) to calculate a shift value (SL) by subtracting a value equal to 7 from the value at the output of the first logic gate (AND2) of the "AND" type; implementing a shift circuit (SFT2) of the third block (WRITEBIT) to shift the value 1 to the left by a number of bits corresponding to the shift value (SL) to create a mask (MSK); implementing an inverter logic gate (NOT1) of the third block (WRITEBIT) to create a complementary mask (INVMSK) based on the mask (MSK) obtained through the implementation of the shift circuit (SFT2); implementing a second logic circuit (AND4) of the "AND" type of the third block (WRITEBIT) to apply the complementary mask (INVMSK) to the byte to be written (BTE_IN) to obtain a first byte (B0); implementing a logic circuit (OR1) of the "OR" type of the third block (WRITEBIT) to apply the mask (MSK) to the byte to be written (BTE_IN) to obtain a second byte (B1); and implementing a selection circuit (MUX1) to generate a byte (BTE_OUT) corresponding to the first byte (B0) if the value of the bit to be written is equal to 0, or otherwise generate a byte (BTE_OUT) corresponding to the second byte (B1).

[0125] The method may include: causing at least one call of a function (WRT_BIT_NW) that writes a bit in a byte array (BTAB) by implementing an instruction of a computer program (PRG) by a digital signal processor (DSP), each call of the function taking a bit position pointer and a byte pointer as attributes as inputs and enabling: calculating a byte shift value by the first block (OFFST), then updating the byte pointer with the byte shift value, and then writing the bit to be written by the third block (WRITEBIT) of the dedicated circuit (HWC).

[0126] The method may include: causing the initiation of a bit position pointer by implementing an instruction of a computer program (PRG) by a digital signal processor (DSP) such that it points to the position of the last bit of a byte array (BTAB), and decrementing the bit position pointer (BITP) at each read and / or write access.

[0127] The various embodiments described above can be combined to provide additional embodiments. In light of the foregoing detailed description, these and other changes can be made to the embodiments. Generally, in the appended claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to such claims. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A computer system comprising: a data memory configured to store a byte array; a program memory configured to store a computer program; a digital signal processor configured to execute the computer program to access each byte of the byte array; as well as The circuit is configured to perform the following operations to access the bits of the bytes of the byte array: obtaining a bit position pointer to the bit to be accessed in the byte array; and Get the byte that includes the bit to be accessed.

2. The system of claim 1, wherein the circuit is further configured to calculate a byte shift value based on the value of the bit position pointer.

3. The system of claim 2, wherein the circuit comprises: a first logic AND gate configured to perform a first logic AND on the value of the bit position pointer and a hexadecimal value 0x7 to obtain an index value; as well as The comparison circuit is configured as: comparing the index value to 0; When the index value is equal to 0, the byte shift value is set to -1; as well as When the index value is not equal to 0, the byte shift value is set to 0.

4. The system of claim 2, wherein the circuit is further configured to determine a value of the bit to be read from the bit position pointer and the byte.

5. The system of claim 4, wherein the circuit comprises: an adder circuit configured to increase the value of the bit position pointer by 1; a second logic AND gate configured to perform a second logic AND of the incremented value of the bit position pointer and a hexadecimal value equal to 0x7; a subtractor circuit configured to calculate a shift value by subtracting a value equal to 7 from the output of the second logical AND; a shift circuit configured to shift the value of the byte rightward by a number of bits corresponding to the shift value; as well as A third logic AND gate is configured to perform a third logic AND on a value equal to 1 and the value of the shift of the byte to obtain the value of the bit to be read.

6. The system of claim 5, wherein the computer program comprises instructions which, when executed by the digital signal processor, cause the digital signal processor to perform at least one call of a read bit function to read a bit in the byte array, wherein each call of the read bit function has the bit position pointer and the byte pointer as input, wherein the instructions cause the digital signal processor to: Calculate the byte shift value; updating the byte pointer based on the byte shift value; and The value of the bit to be read is determined based on the updated byte pointer.

7. The system of claim 1, wherein the circuit is configured to write the value of a bit in a byte to be written instead of writing the value of the bit at the bit pointed to by the bit position pointer.

8. The system of claim 7, wherein the circuit further comprises: an adder circuit configured to increase the value of the bit position pointer by 1; a second logic AND gate configured to perform a second logic AND of the incremented value of the bit position pointer and a hexadecimal value equal to 0x7; a subtractor circuit configured to calculate a shift value by subtracting a value equal to 7 from the value at the output of said second "AND" type logic gate; a shift circuit configured to shift the value 1 left by a number of bits corresponding to the shift value to create a mask; an inverter logic gate configured to create a complementary mask from said mask obtained at the output of said shift circuit; a fourth logic AND gate configured to apply the complementary mask to the byte to be written to obtain a first byte; a logical OR gate configured to apply the mask to the byte to be written to obtain a second byte; as well as The selection circuit is configured as follows: If the value of the bit to be written is equal to 0, outputting a byte corresponding to the first byte; and If the value of the bit to be read is not equal to 0, the byte corresponding to the second byte is output.

9. The system of claim 7, wherein the computer program includes instructions that, when executed by the digital signal processor, cause the digital signal processor to execute at least one call of a write bit function to write a bit in the byte array, wherein each call of the write bit function has the bit position pointer and the byte pointer as input, wherein the instructions cause the digital signal processor to: Calculate the byte shift value; updating the byte pointer based on the byte shift value; and The value of the bit is written based on the byte pointer being updated.

10. The system of claim 1 , wherein the computer program includes instructions that, when executed by the digital signal processor, cause the digital signal processor to start the bit position pointer to point to the position of the last bit of the byte array and decrement the bit position pointer upon each read or write access.

11. A method implemented by a computer system for accessing bits of a byte stored in a byte array, the method comprising: accessing the bytes via a digital signal processor; causing the circuit to access the bit of the byte accessed by the digital signal processor by: obtaining a bit position pointer pointing to the bit to be accessed in the byte array; obtaining the byte including the bit to be accessed; and The bit of the byte is accessed based on the byte and the bit position pointer.

12. The method according to claim 11, further comprising: A byte shift value is calculated by the circuit based on the bit position pointer.

13. The method of claim 12, wherein the circuit accesses the bits of the byte accessed by the digital signal processor by: Performing a first logical AND on the bit position pointer and the hexadecimal value 0x7 through a first logical AND gate to obtain an index value; Comparing the index value with 0 by a comparison circuit; When the index value is equal to 0, the byte shift value is set to -1 by the comparison circuit; as well as When the index value is not equal to 0, the byte shift value is set to 0 by the comparison circuit.

14. The method of claim 11 , wherein accessing the bits of the byte comprises: A value of the bit to be read is determined based on the bit position pointer and the byte including the bit to be read.

15. The method of claim 14, wherein determining the value of the bit to be read based on the bit position pointer and the byte comprises: Increasing the value of the bit position pointer by 1 via an adder circuit; performing a second logical AND of the incremented value of the bit position pointer and a hexadecimal value equal to 0x7 via a second logical AND gate; subtracting a value equal to 7 from the output of the second logical AND by a subtractor circuit to obtain a shift value; shifting the value of the byte rightward based on the shift value by a shift circuit; and A third logical AND is performed by a third logical AND gate on the value equal to 1 and the value of the shift of the byte to obtain the value of the bit to be read.

16. The method of claim 14, wherein determining the value of the bit to be read is based on the bit position pointer and a byte pointer and comprises: Calculate the byte shift value; updating the byte pointer based on the byte shift value; The value of the bit to be read is determined based on the byte pointer being updated.

17. The method according to claim 11, further comprising: The value of the bit is written in the byte to be written instead of writing the value of the bit at the bit pointed to by the bit position pointer.

18. The method of claim 17, wherein writing the value of the bit comprises: increasing the value of the bit position pointer by 1 via an adder circuit; performing a second logical AND of the incremented value of the bit position pointer and a hexadecimal value equal to 0x7 via a second logical AND gate; subtracting a value equal to 7 from the output of the second logical AND by a subtractor circuit to obtain a shift value; Shifting the value 1 left by a number of bits corresponding to the shift value through a shift circuit to create a mask; creating a complementary mask based on the mask via inverter logic gates; applying the complementary mask to the byte through a fourth logical AND gate to obtain a first byte; applying the mask to the byte through a first logical OR gate to obtain a second byte; selecting, by a selection circuit, a byte corresponding to the first byte based on the value of the bit being equal to zero; as well as The byte corresponding to the second byte is selected by the selection circuit based on the value of the bit not being equal to zero.

19. The method of claim 17, wherein the value written to the bit is based on the bit position pointer and byte pointer, and comprises: Calculate the byte shift value; updating the byte pointer based on the byte shift value; as well as The bit is written based on the byte pointer being updated.

20. The method according to claim 11, further comprising: Starting the bit position pointer to point to the position of the last bit of the byte array; as well as The bit position pointer is decremented on each access.

Images