Data storage method and device, electronic equipment and storage medium

Abstract

The invention discloses a data storage method and device, electronic equipment and a storage medium, and relates to the technical field of data storage, and the data storage method comprises the steps of determining a to-be-stored queue and a to-be-refreshed queue according to state information of a first memory, storing a received write command to the to-be-stored queue, and storing the to-be-refreshed queue into the to-be-stored queue based on the write command. Storing the to-be-written data of the second memory to the first memory; and when the first memory is subjected to state switching and the to-be-refreshed queue has a write command, determining to-be-refreshed data in the first memory and target refreshed data in the second memory based on the write command in the to-be-refreshed queue, and refreshing the to-be-refreshed data by using the target refreshed data. The technical problems that reading errors are introduced, the overall data error rate is increased and the data reliability is reduced in the mode of reducing the holding errors in the related technology are solved, and the technical effects that the overall data error rate is reduced while the holding errors are reduced, and the data reliability is improved are achieved.

Description

Technical Field

[0001] This application relates to the field of data storage technologies, and in particular, to a data storage method, apparatus, electronic device, and storage medium. Background Art

[0002] With the development of storage technologies, non-volatile memories have emerged, which can be used as caches to overcome the drawback that data in volatile memories is easily lost when power is off. Among them, Magnetoresistive Random Access Memory (MRAM for short) has become a popular choice for storing data due to its non-volatility, high durability, and low latency.

[0003] When MRAM stores data, the probability of retention errors is relatively high, resulting in low reliability of the stored data. In related technologies, data in MRAM is periodically read for data verification to determine whether there are retention errors in the data stored in MRAM, so as to recover the error data and reduce retention errors. This method will introduce read errors, increase the overall data error rate, and reduce data reliability. Summary of the Invention

[0004] This application provides a data storage method, apparatus, electronic device, and storage medium to at least solve the problem that the method of reducing retention errors in related technologies will introduce read errors, increase the overall data error rate, and reduce data reliability.

[0005] This application provides a data storage method applied to a first controller, where the first controller is used to control data writing and data reading of a first memory, and includes:

[0006] Obtain the status information of the first memory, where the first memory cyclically switches between multiple states;

[0007] Based on the status information, determine the storage queue and refresh queue to be stored in the first memory;

[0008] Store the write command sent by the second controller into the storage queue to be stored, and based on the write command, obtain the data to be written from the second memory, and store the data to be written into the first memory. The second controller is used to control data writing and data reading of the second memory;

[0009] When the first memory undergoes a status switch and there is a write command in the refresh queue to be stored, based on the write command in the refresh queue to be stored, determine the data to be refreshed in the first memory and the target refresh data in the second memory, and based on the target refresh data, refresh the data to be refreshed. The first memory is a non-volatile memory.

[0010] The present application also provides a data storage device, which is applied to a first controller. The first controller is used to control data writing and data reading of a first memory, and includes:

[0011] An acquisition module, configured to acquire status information of the first memory, where the first memory cyclically switches between multiple states;

[0012] A determination module, configured to determine a storage queue to be stored and a refresh queue to be refreshed of the first memory based on the status information;

[0013] A storage module, configured to store a write command sent by a second controller into the storage queue to be stored, and based on the write command, acquire data to be written from a second memory and store the data to be written into the first memory. The second controller is used to control data writing and data reading of the second memory;

[0014] A refresh module, configured to, when the first memory undergoes a status switch and there is a write command in the refresh queue to be refreshed, determine data to be refreshed in the first memory and target refresh data in the second memory based on the write command in the refresh queue to be refreshed, and refresh the data to be refreshed based on the target refresh data. The first memory is a non-volatile memory.

[0015] The present application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above data storage methods when executing the computer program.

[0016] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above data storage methods are implemented.

[0017] The present application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any one of the above data storage methods are implemented.

[0018] Through this application, by obtaining the status information of the first memory, determining the storage queue to be stored and the refresh queue to be refreshed according to the status information of the first memory, storing the write commands sent by the second controller received in the storage queue to be stored, and based on the write commands, obtaining the data to be written from the second memory and storing the data to be written in the first memory, the second controller is used to control the data writing and data reading of the second memory; when the first memory undergoes a status switch and there are write commands in the refresh queue to be refreshed, based on the write commands in the refresh queue to be refreshed, determining the data to be refreshed in the first memory and the target refresh data in the second memory, and refreshing the data to be refreshed based on the target refresh data. By cyclically switching different states of the first memory and refreshing the stored data in the first memory based on the stored data in the second memory, the technical problem in the related art that while reducing the retention error, a read error is introduced, increasing the overall data error rate and reducing the data reliability can be solved, and the technical effect of reducing the retention error while reducing the overall data error rate and improving the data reliability can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 It is an architecture diagram of a data storage system provided by an embodiment of the present application;

[0021] Figure 2 It is a structural block diagram of an MRAM controller provided by an embodiment of the present application;

[0022] Figure 3 It is a schematic flowchart of a data storage method provided by an embodiment of the present application;

[0023] Figure 4 It is a schematic flowchart of another data storage method provided by an embodiment of the present application;

[0024] Figure 5 It is a structural block diagram of a data storage device provided by an embodiment of the present application;

[0025] Figure 6 It is a schematic hardware structure diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0027] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] To enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0029] Dynamic Random Access Memory (DRAM) is a volatile memory, which means that in the case of abnormal power-off, the data in it will be lost. To solve this problem, a capacitor can be added to maintain the power supply state to ensure that the DRAM has enough time to transfer its internal data to a non-volatile memory, such as NAND Flash or a disk.

[0030] With the continuous progress of storage technologies and materials, new non-volatile memories such as Resistive Random Access Memory (RRAM), MRAM, and Ferroelectric Random Access Memory (FeRAM) have gradually emerged and can be used as caches to overcome the problem of data loss in DRAM after power-off. In particular, MARM has become one of the popular candidate technologies to replace DRAM for storing critical data due to its advantages such as non-volatility, high durability, and low latency. These characteristics make MRAM very suitable for application scenarios that require high reliability and fast response.

[0031] Among them, the core storage unit of MRAM is composed of two magnetic layers and an insulating layer. The magnetization states of these two magnetic layers can be arranged in parallel or anti-parallel, corresponding to the low-resistance state and the high-resistance state respectively, thus representing "0" or "1" in binary data. Data errors in MRAM are mainly divided into three categories: write errors, read errors, and retention errors.

[0032] With the progress of manufacturing processes, the size of MRAM has been continuously reduced, resulting in a decrease in the energy barrier that needs to be overcome when switching the magnetization state of the magnetic layer. Although this reduces the write power consumption and the incidence of write errors, it also makes retention errors more prominent, becoming one of the main problems affecting the performance of MRAM. The probability of occurrence of retention errors when MRAM stores data is relatively high, resulting in lower reliability of the stored data and lower system stability.

[0033] In related technologies, data stored in MRAM is periodically read for data verification to determine whether there are retention errors in the data stored in MRAM, so as to recover the error data and reduce retention errors. Among them, if the data can be corrected, it means that the data has not erred; if the verification fails, the data stored in MRAM has erred, and data recovery methods need to be used, such as requesting a rewrite from the upper level or issuing a data error interrupt for software processing.

[0034] In some scenarios, data is rarely read. For example, some log data. If it is necessary to read the data in MRAM to judge the correctness of the data to recover the error data and reduce retention errors, read errors will be introduced, increasing the overall data error rate and reducing data reliability.

[0035] In view of the above problems, an embodiment of the present application provides a data storage method, apparatus, electronic device, and storage medium. The method is applied to a first controller, and the first controller is used to control data writing and data reading of a first memory. By obtaining the status information of the first memory, where the first memory cyclically switches between multiple states, based on the status information, a to-be-stored queue and a to-be-refreshed queue of the first memory are determined; the write command sent by the second controller is stored in the to-be-stored queue, and based on the write command, the to-be-written data is obtained from the second memory and stored in the first memory. The second controller is used to control data writing and data reading of the second memory; when the first memory undergoes a status switch and there is a write command in the to-be-refreshed queue, based on the write command in the to-be-refreshed queue, the to-be-refreshed data in the first memory and the target refresh data in the second memory are determined, and based on the target refresh data, the to-be-refreshed data is refreshed. The first memory is a non-volatile memory. This solves the technical problem in the related art that the method of reducing retention errors will introduce read errors, increase the overall data error rate, and reduce data reliability, achieving the technical effect of reducing retention errors while reducing the overall data error rate and improving data reliability.

[0036] The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present invention will be described below with reference to the accompanying drawings. First, the system architecture on which the present application is based will be described:

[0037] The data storage method, apparatus, electronic device, and storage device provided by the embodiments of the present application are applicable to reducing retention errors of non-volatile memories, reducing the introduction of read errors, reducing the overall data error rate, and improving the stability of the storage system. As Figure 1As shown in the figure, it is a schematic diagram of the architecture of the data storage system based on the embodiments of the present application. The data storage system includes a central processing unit (CPU), a DRAM memory, a DRAM controller, a Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) memory, an MRAM controller, a NAND controller, and a NAND Flash memory. Among them, the central processing unit in this embodiment consists of 2 cores, which are divided into a level 1 cache, a level 2 cache, and a level 3 cache. The level 1 cache is divided into an instruction cache and a data cache. The size of the instruction cache is 64KB, and the size of the data cache is 64KB. The level 2 cache is a cache exclusive to a single core, with a size of 256KB. The level 3 cache is a cache shared by multiple cores, with a size of 16MB. The DRAM memory is connected to the DRAM controller through a double data rate interface (DDR). The capacity of the DRAM memory is 8GB, and the DDR interface can be DDR4. The STT-MRAM memory is connected to the MRAM controller through an STT-DDR interface. Among them, this STT-DDR interface combines the characteristics of DDR and spin transfer torque. The capacity of the STT-MRAM memory is 512MB. The NAND controller and the NAND Flash memory are connected through an Open NAND Flash Interface (ONFI). The capacity of the NAND Flash memory is 512G, and this ONFI interface can be an ONFI5.1 interface.

[0038] Figure 2 It is a structural block diagram of the MRAM controller according to the embodiments of the present application. As Figure 2 shown, the MRAM controller includes a queue management unit, a status management unit, a refresh management unit, and other units. Among them, the queue management unit of the MRAM controller is responsible for dividing the number of queues for receiving write commands in the MRAM memory and managing the requests written to the MARM controller, and storing the metadata and addresses of the written data into the corresponding queues. The status management unit of the MRAM controller is responsible for managing the status of the MRAM memory and the transitions between states, and notifying the queue management unit to process the data in the corresponding queues. The refresh management unit is responsible for refreshing the corresponding stored data in the queue according to the state of the MRAM memory, and re-reading the data from the DRAM memory according to the metadata stored in the queue and storing it into the MRAM memory to complete the refresh operation of the data in the corresponding queue.

[0039] The central processing unit is used to generate log data and allocate a storage space in the DRAM memory for storing the log data. The DRAM controller controls the log data to enter the DRAM memory through the DDR interface. The DRAM controller sends a write request to the MRAM controller to write the log data in the DRAM into the MRAM memory, which can prevent data loss in case of abnormal power-off. And because the read and write speed of MRAM is relatively fast, it takes less time than directly writing data from DRAM to the NAND Flash memory. The MRAM controller performs a refresh operation on the log data in the MRAM controller by configuring different queues and states to reduce the retention error of the log data in the MRAM memory, and finally stores the log data in the NAND Flash memory.

[0040] An embodiment of the present application provides a data storage method, which is applied to a first controller. The first controller can be the above-mentioned MRAM controller, and the first controller is used to control the data writing and data reading of the first memory. Among them, the first memory can be the above-mentioned STT-MRAM memory. Figure 3 The flowchart of the data storage method provided by the embodiment of the present application is as Figure 3 shown, and the process includes the following steps:

[0041] Step S301, obtain the status information of the first memory, where the first memory cyclically switches between multiple states.

[0042] Among them, the status management unit of the first controller is responsible for managing the status of the first memory and setting the retention time of the status. In this embodiment, the retention time of the first memory in each state is a preset retention time. It should be noted that the retention time of the first memory in each state can also be different, that is, the retention time of each state can be controlled separately. The preset retention time can be set by technicians and is not specifically limited here. The preset retention time can be a fixed time or can change in real time according to functions of external parameters such as temperature and magnetic field strength.

[0043] Use a counter to detect in real time the retention time of the current state of the first memory, and when the retention time of the current state reaches the preset retention time, notify the status management unit to perform a status conversion.

[0044] Step S302, based on the status information, determine the storage queue and refresh queue of the first memory.

[0045] Among them, different status information corresponds to different storage queues and refresh queues. After obtaining the status information of the first memory, determine the storage queue and refresh queue of the first memory according to the status information of the first memory.

[0046] Step S303: Store the write command sent by the second controller into the queue to be stored, and based on the write command, obtain the data to be written from the second memory and store the data to be written into the first memory. The second controller is used to control the data writing and data reading of the second memory.

[0047] Among them, the queue to be stored is used to store the write commands sent by the second controller. The second controller may be the above-mentioned DRAM controller, and the second memory may be the above-mentioned DRAM memory.

[0048] The write command includes the metadata of the data to be written and the address information of the data to be written in the first memory.

[0049] Step S304: When the first memory undergoes a state transition and there is a write command in the queue to be refreshed, determine the data to be refreshed in the first memory and the target refresh data in the second memory based on the write command in the queue to be refreshed, and refresh the data to be refreshed based on the target refresh data. The first memory is a non-volatile memory.

[0050] Among them, after the state transition, the queue to be stored may be switched to the queue to be refreshed, and there may be a write command in the queue to be refreshed. When the first memory undergoes a state transition and there is a write command in the queue to be refreshed, determine the target refresh data in the second memory based on the metadata in the write command in the queue to be refreshed, determine the data to be refreshed in the first memory based on the address information in the write command in the queue to be refreshed, and use the target refresh data in the second memory to refresh the data to be refreshed in the first memory to reduce the retention error of the first memory.

[0051] The data storage method provided by the embodiment of the present application obtains the status information of the first memory, determines the storage queue to be stored and the refresh queue to be refreshed according to the status information of the first memory, stores the write command sent by the second controller received in the storage queue to be stored, and based on the write command, obtains the data to be written from the second memory and stores the data to be written in the first memory. The second controller is used to control the data writing and data reading of the second memory; when the first memory undergoes a state transition and there is a write command in the refresh queue to be refreshed, based on the write command in the refresh queue to be refreshed, determine the data to be refreshed in the first memory and the target refresh data in the second memory, and based on the target refresh data, refresh the data to be refreshed. By cyclically switching different states of the first memory, based on the stored data in the second memory, the stored data in the first memory is refreshed. This process does not require reading data from the MRAM memory, performing data verification, and checking whether the data is correct, thereby reducing the retention error in the MRAM memory. It solves the technical problem in the related art that while reducing the retention error, a read error is introduced, increasing the overall data error rate and reducing the data reliability, and achieves the technical effects of reducing the retention error while reducing the overall data error rate, improving the data reliability, and reducing the power consumption.

[0052] The data storage method provided by the embodiment of the present application reduces the disadvantage that the data in the DRAM memory is easily lost when powered off, reduces the retention error of the MRAN, and improves the stability of the storage system.

[0053] An embodiment of the present application provides a data storage method, which is applied to the above-mentioned MRAM controller. The first controller is used to control the data writing and data reading of the first memory. Figure 4 It is a flowchart of the data storage method provided by the embodiment of the present application. As Figure 4 shown, the process includes the following steps:

[0054] Step S401, obtain the status information of the first memory, where the first memory cyclically switches between multiple states. For details, please refer to Figure 3 Step S301 of the embodiment shown, which will not be elaborated here.

[0055] Step S402, based on the status information, determine the storage queue to be stored and the refresh queue to be refreshed in the first memory.

[0056] Specifically, the above step S402 includes:

[0057] Step S4021, when the status information is the first state, determine that the first queue in the first memory is the storage queue to be stored and the second queue is the refresh queue to be refreshed.

[0058] The queue management unit of the MRAM controller divides the queues of the MRAM memory into a first queue and a second queue. Write commands can only enter these two queues, and the data in the MRAM memory is refreshed through the metadata and address of the data to be written. The status management unit divides the status of the first memory into a first status and a second status. That is to say, the status of the first memory includes the first status and the second status, and the queues of the first memory include the first queue and the second queue.

[0059] The truth tables corresponding to the first status and the second status are shown in Table 1.

[0060] Table 1

[0061]

[0062] Among them, during the first status, the write command from the DRAM controller is written into the first queue. That is, the first queue stores the metadata and address of the data to be written, and completes the operation corresponding to the write command, that is, writes the data to be written into the MRAM memory, and then refreshes the second queue.

[0063] It should be noted that the first memory switches cyclically between the first status and the second status. In the case of the first status for the first time, there is no write command in the second queue, that is, there is no write command in the queue to be refreshed, so there is no need to perform a refresh operation.

[0064] After the holding time of the first status reaches the preset holding time, the status management unit switches the first status to the second status. At this time, the write command from the DRAM controller is written into the second queue. That is, the second queue stores the metadata and address of the written data, and completes the operation corresponding to the write command, that is, writes the data to be written into the MRAM memory, and then refreshes the first queue.

[0065] Since the write command is written into the first queue in the first status, there is a write command in the first queue. In the second status, the first queue is the queue to be refreshed. In the case where there is a write command in it, the data to be refreshed in the first memory is refreshed based on the write command in the first queue.

[0066] Step S4022, when the status information is the second status, determine that the first queue in the first memory is the queue to be refreshed, and the second queue is the queue to be stored.

[0067] It can be understood that after the holding time of the second status reaches the preset holding time, the status management unit switches the second status to the first status. At this time, the write command from the DRAM controller is written into the first queue. That is, the first queue stores the metadata and address of the data to be written, and completes the operation corresponding to the write command, that is, writes the data to be written into the MRAM memory, and then refreshes the second queue.

[0068] When there is a write command in the second queue, a refresh operation needs to be performed on it.

[0069] After the holding time of the first state reaches the preset holding time, it switches to the second state again to achieve cyclic switching.

[0070] Step S403: Store the write command sent by the received second controller into the queue to be stored, and based on the write command, obtain the data to be written from the second memory and store the data to be written into the first memory. The second controller is used to control data writing and data reading in the second memory. For details, please refer to Figure 3 Step S303 of the illustrated embodiment, which will not be elaborated here.

[0071] Step S404: When the first memory undergoes a state transition and there is a write command in the queue to be refreshed, based on the write command in the queue to be refreshed, determine the data to be refreshed in the first memory and the target refresh data in the second memory, and refresh the data to be refreshed based on the target refresh data. The first memory is a non-volatile memory.

[0072] Specifically, the above step S404 includes:

[0073] Step S4041: Determine whether there is at least one write command in the queue to be stored that is the same as the write command in the queue to be refreshed.

[0074] Step S4042: If there is at least one write command in the queue to be stored that is the same as the write command in the queue to be refreshed, obtain the target write command in the queue to be refreshed that is the same as the write command in the queue to be stored, and set the stored data corresponding to the target write command in the first memory as invalid stored data.

[0075] Among them, if there is at least one write command in the queue to be stored that is the same as the write command in the queue to be refreshed, it means that the stored data corresponding to the target write command in the queue to be refreshed that is the same as the write command in the queue to be stored is outdated data, so the stored data corresponding to the target write command is set as invalid stored data, and this piece of stored data does not need to be updated.

[0076] Step S4043: Obtain other write commands in the queue to be refreshed except for the target write command.

[0077] Step S4044: Based on the other write commands, determine the data to be refreshed in the first memory and the target refresh data in the second memory.

[0078] That is, based on other write commands, request the second controller to re-fetch data from the second memory and write it to the corresponding position of the data to be refreshed in the first memory.

[0079] Step S4045, refresh the data to be refreshed based on the target refresh data.

[0080] The data storage method provided by the embodiments of the present application distinguishes a storage queue to be stored and a refresh queue to be refreshed in the first memory, and dynamically adjusts these two types of queues according to the status information to refresh the stored data in the first memory, reducing the retention error of the stored data in the first memory.

[0081] By determining whether there is the same target write command in the write commands in the storage queue to be stored and the refresh queue to be refreshed, it is ensured that during the refresh process, the data that really needs to be refreshed is processed, avoiding the refresh operation of invalid data, improving the refresh efficiency, and ensuring the accuracy of the stored data in the first memory.

[0082] In some optional embodiments, the above data storage method further includes:

[0083] Step a1, every first preset time period, write the valid stored data in the first memory to the target memory. After writing the valid stored data to the target memory, set the valid stored data in the first memory to invalid stored data, and set the write command corresponding to the valid stored data to an invalid write command.

[0084] It should be noted that the first preset time period is greater than the sum of the retention times of all states to ensure that all the valid stored data in the MRAM is written to the target memory. The target memory is the above-mentioned NAND Flash memory.

[0085] Furthermore, it should be noted that during the process of writing the valid stored data to the target memory, there is no need to execute the step of determining the data to be refreshed in the first memory and the target refresh data in the second memory based on the write command in the refresh queue to be refreshed when the first memory undergoes a state transition and there is a write command in the refresh queue to be refreshed, and refreshing the data to be refreshed based on the target refresh data.

[0086] That is to say, if a refresh operation occurs during the process of writing the valid stored data to the target memory, set the refresh operation to invalid because there is no data to be refreshed at this time.

[0087] It can be understood that an invalid write command can be regarded as the non-existence of this write command.

[0088] The data storage method provided by the embodiments of the present application ensures that data will not be lost in case of power failure or other abnormalities by regularly writing the valid stored data in the first memory into the target memory, significantly improving the data persistence and reliability of the system.

[0089] In some optional embodiments, before writing the valid stored data in the first memory into the target memory, the above data storage method further includes:

[0090] Step b1, performing error detection on the valid stored data.

[0091] Before writing the valid stored data in the first memory into the target memory, it is first necessary to read out the valid stored data from the first memory.

[0092] After reading out the valid stored data, error detection is first performed on the valid stored data to further reduce retention errors.

[0093] Step b2, if the error detection result of the valid stored data shows that there are uncorrectable errors, determine the error data in the valid stored data, obtain the correct data corresponding to the error data from the second memory, and write the correct data and the other data in the valid stored data except the error data into the target memory.

[0094] Among them, when the error detection result of the valid stored data in the first memory shows that there are uncorrectable errors, obtain the correct data corresponding to the error data from the DRAM, and write the correct data and the other data in the valid stored data except the error data into the target memory. It should be noted that the process of writing the correct data into the target memory does not need to pass through the first memory again.

[0095] The data storage method provided by the embodiments of the present application can timely detect and handle errors in the data by performing error detection on the valid stored data before writing the valid stored data in the first memory into the target memory, ensuring that the data finally written into the target memory is accurate and error-free, and improving the integrity and accuracy of the data. Performing error detection on the valid stored data before writing the valid stored data in the first memory into the target memory reduces the number of reads of the valid stored data in the first memory, reduces the introduction of read errors while reducing retention errors, realizes the reduction of the overall data error rate, and improves data reliability.

[0096] In some optional embodiments, the state of the first memory includes a first state, a second state, a third state, and a fourth state, and the queue of the first memory includes a first queue and a second queue. The above step S402 includes:

[0097] Step c1, when the status information is in the first state, determine that the first queue in the first memory is the queue to be stored, and there is no queue to be refreshed.

[0098] It should be noted that when the status of the first memory includes the first state and the second state, the refresh operation is relatively frequent, resulting in a large system power consumption. Therefore, in this embodiment, the queue management unit still divides the first memory into two queues for management, but the status management unit divides the status of the first memory into four states to reduce the refresh frequency.

[0099] The status truth tables corresponding to the first state, the second state, the third state, and the fourth state are shown in Table 2.

[0100] Table 2

[0101]

[0102] Among them, during the first state, the write command from the DRAM controller is written into the first queue, that is, the first queue stores the metadata and address of the data to be written, and completes the operation corresponding to the write command, that is, writes the data to be written into the MRAM memory, and the second queue does not perform any operation.

[0103] Step c2, when the status information is in the second state, determine that the first queue in the first memory is the queue to be refreshed, and the second queue is the queue to be stored.

[0104] When the holding time of the first state reaches the preset holding time, the status management unit switches the first state to the second state. At this time, the write command from the DRAM controller is written into the second queue, that is, the second queue stores the metadata and address of the written data, and completes the operation corresponding to the write command, that is, writes the data to be written into the MRAM memory, and then refreshes the first queue.

[0105] Since the write command is written into the first queue in the first state, there is a write command in the first queue. In the second state, the first queue is the queue to be refreshed. In the case where there is a write command in it, the data to be refreshed in the first memory is refreshed based on the write command in the first queue. If there is a write command in the first queue in the second queue, it means that the data corresponding to the write command in the first queue is obsolete data, and it is set to invalid. This piece of data does not need to be refreshed, and the data corresponding to other write commands is requested to be rewritten from the DRAM according to the metadata and address in the first queue.

[0106] Step c3, when the status information is in the third state, determine that the first queue in the first memory is the queue to be stored, and there is no queue to be refreshed.

[0107] When the holding time of the second state reaches the preset holding time, the state management unit switches the second state to the third state. At this time, the write command from the DRAM controller is written into the first queue. That is, the first queue stores the metadata and address of the write data, and completes the operation corresponding to the write command, that is, writes the data to be written into the MRAM memory, and the second queue does not perform any operation.

[0108] Step c4, when the state information is the fourth state, determine that the first queue in the first memory is the queue to be stored, and the second queue is the queue to be refreshed.

[0109] When the holding time of the third state reaches the preset holding time, the state management unit switches the third state to the fourth state. At this time, the write command from the DRAM controller is written into the first queue. That is, the first queue stores the metadata and address of the write data, and completes the operation corresponding to the write command, that is, writes the data to be written into the MRAM memory, and then refreshes the second queue.

[0110] Since the write command is written into the second queue in the second state, there is a write command in the second queue. In the fourth state, the second queue is the queue to be refreshed. When there is a write command in it, the data to be refreshed in the first memory is refreshed based on the write command in the second queue. If there is a write command in the second queue in the first queue, it means that the data corresponding to the write command in the second queue is obsolete data, and it is set to invalid. This piece of data does not need to be refreshed, and the data corresponding to other write commands is requested to be rewritten to the DRAM according to the metadata and address in the second queue.

[0111] The data storage method provided by the embodiments of the present application introduces four different states and dynamically adjusts the queue to be stored and the queue to be refreshed according to different states. This data storage method not only improves the flexibility and adaptability of the system, but also does not refresh the data in the first state and the third state, reduces the frequency of refresh operations, reduces system resource consumption, and improves data processing efficiency.

[0112] In some optional embodiments, the states of the first memory include the first state, the second state, and the third state, and the queues of the first memory include the first queue, the second queue, and the third queue. The above step S402 includes:

[0113] Step d1, when the state information is the first state, determine that the first queue in the first memory is the queue to be stored, and the second queue is the queue to be refreshed.

[0114] It should be noted that when the states of the first memory include the first state, the second state, the third state, and the fourth state, the refresh operations are unbalanced, and the refresh operation frequencies of the first queue and the second queue are not equal. Therefore, in this embodiment, the queue management unit divides the first memory into multiple queues for management, such as three queues: the first queue, the second queue, and the third queue. Correspondingly, the state management unit divides the states of the first memory into three states.

[0115] The state truth tables corresponding to the first state, the second state, and the third state are shown in Table 3.

[0116] Table 3

[0117]

[0118] Among them, during the first state, the write command from the DRAM controller is written into the first queue. That is, the first queue stores the metadata and address of the data to be written, and completes the operations corresponding to the write command, that is, writes the data to be written into the MRAM memory, and then refreshes the second queue, and no operation is performed on the third queue.

[0119] Step d2, when the state information is the second state, determine that the second queue in the first memory is the queue to be stored, and the third queue is the queue to be refreshed.

[0120] Among them, during the second state, the write command from the DRAM controller is written into the second queue. That is, the second queue stores the metadata and address of the data to be written, and completes the operations corresponding to the write command, that is, writes the data to be written into the MRAM memory, and then refreshes the third queue, and no operation is performed on the first queue.

[0121] Step d3, when the state information is the third state, determine that the third queue in the first memory is the queue to be stored, and the first queue is the queue to be refreshed.

[0122] Among them, during the third state, the write command from the DRAM controller is written into the third queue. That is, the third queue stores the metadata and address of the data to be written, and completes the operations corresponding to the write command, that is, writes the data to be written into the MRAM memory, and then refreshes the first queue, and no operation is performed on the second queue.

[0123] The data storage method provided by the embodiment of the present application, by introducing multiple different states and multiple queues, dynamically adjusts the queue to be stored and the queue to be refreshed in multiple queues according to different states, so that the refresh operations of different queues are balanced, thereby ensuring the accuracy of the stored data in the first memory.

[0124] In some alternative embodiments, before storing the data to be written into the first memory, the data storage method further includes:

[0125] Performing integrity verification on the data to be written.

[0126] If the integrity verification of the data to be written passes, store the data to be written into the first memory.

[0127] If the integrity verification of the data to be written fails, return to execute the step of obtaining the data to be written from the second memory based on the write command until the integrity verification of the data to be written passes, and then store the data to be written into the first memory.

[0128] If the number of times of returning to execute reaches the preset number threshold and the integrity verification of the data to be written still fails, an alarm is issued. The preset number threshold is set by a technician.

[0129] The number of times of returning to execute is the number of times of returning to execute the step of obtaining the data to be written from the second memory based on the write command.

[0130] In the data storage method provided by the embodiments of the present application, by performing integrity verification before storing the data to be written into the first memory, errors that may occur during data transmission or acquisition can be detected in a timely manner. If the verification fails, immediately return to obtain the data from the second memory again, which can avoid incorrect data from being written into the first memory, reduce the write errors of the first memory, and ensure the accuracy and integrity of the stored data in the first memory.

[0131] From the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0132] The embodiments of the present application further provide a data storage device, as Figure 5 shown, including:

[0133] An acquisition module 501, configured to acquire status information of the first memory, where the first memory switches cyclically among multiple states.

[0134] A determination module 502, configured to determine a storage queue to be stored and a refresh queue to be refreshed of the first memory based on the status information.

[0135] A storage module 503 is configured to store the write commands received from the second controller into a queue to be stored, and based on the write commands, obtain data to be written from the second memory and store the data to be written into the first memory. The second controller is configured to control data writing and data reading of the second memory.

[0136] A refresh module 504 is configured to, when the first memory undergoes a state transition and there are write commands in the queue to be refreshed, based on the write commands in the queue to be refreshed, determine the data to be refreshed in the first memory and the target refresh data in the second memory, and refresh the data to be refreshed based on the target refresh data. The first memory is a non-volatile memory.

[0137] In some alternative embodiments, the determination module 502 includes:

[0138] A first determination unit is configured to, when the status information is in the first state, determine that the first queue in the first memory is the queue to be stored and the second queue is the queue to be refreshed.

[0139] A second determination unit is configured to, when the status information is in the second state, determine that the first queue in the first memory is the queue to be refreshed and the second queue is the queue to be stored.

[0140] In some alternative embodiments, the refresh module 504 includes:

[0141] A first judgment unit is configured to judge whether there is at least one write command in the queue to be stored that is the same as the write commands in the queue to be refreshed.

[0142] A first obtaining unit is configured to, if there is at least one write command in the queue to be stored that is the same as the write commands in the queue to be refreshed, obtain the target write command in the queue to be refreshed that is the same as the write commands in the queue to be stored, and set the stored data corresponding to the target write command in the first memory as invalid stored data.

[0143] A second obtaining unit is configured to obtain the other write commands in the queue to be refreshed except the target write command.

[0144] A third determination unit is configured to, based on the other write commands, determine the data to be refreshed in the first memory and the target refresh data in the second memory.

[0145] A first refresh unit is configured to refresh the data to be refreshed based on the target refresh data.

[0146] In some alternative embodiments, the data storage device further includes:

[0147] A fourth determination unit, configured to write the valid stored data in the first memory into the target memory every first preset time period. After writing the valid stored data into the target memory, set the valid stored data in the first memory as invalid stored data, and set the write command corresponding to the valid stored data as an invalid write command.

[0148] In some alternative embodiments, the data storage device further includes:

[0149] A first detection unit, configured to perform error detection on the valid stored data.

[0150] A fifth determination unit, configured to, if the error detection result of the valid stored data indicates that there are uncorrectable errors, determine the error data in the valid stored data, obtain the correct data corresponding to the error data from the second memory, and write the correct data and the other data in the valid stored data except the error data into the target memory.

[0151] In some alternative embodiments, the determination module 502 includes:

[0152] A sixth determination unit, configured to, when the status information is in the first state, determine that the first queue in the first memory is a queue to be stored and there is no queue to be refreshed.

[0153] A seventh determination unit, configured to, when the status information is in the second state, determine that the first queue in the first memory is a queue to be refreshed and the second queue is a queue to be stored.

[0154] An eighth determination unit, configured to, when the status information is in the third state, determine that the first queue in the first memory is a queue to be stored and there is no queue to be refreshed.

[0155] A ninth determination unit, configured to, when the status information is in the fourth state, determine that the first queue in the first memory is a queue to be stored and the second queue is a queue to be refreshed.

[0156] In some alternative embodiments, the determination module 502 includes:

[0157] A tenth determination unit, configured to, when the status information is in the first state, determine that the first queue in the first memory is a queue to be stored and the second queue is a queue to be refreshed.

[0158] An eleventh determination unit, configured to, when the status information is in the second state, determine that the second queue in the first memory is a queue to be stored and the third queue is a queue to be refreshed.

[0159] A twelfth determination unit, configured to, when the status information is in the third state, determine that the third queue in the first memory is a queue to be stored and the first queue is a queue to be refreshed.

[0160] For the description of the features in the embodiments corresponding to the data storage device, reference can be made to the relevant descriptions in the embodiments corresponding to the data storage method, which will not be elaborated here one by one.

[0161] An embodiment of the present application further provides an electronic device, such as Figure 6 shown, including a processor 601 and a memory 602. A computer program is stored in the memory 602, and the processor 601 is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the data storage method.

[0162] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-mentioned embodiments of the data storage method when running.

[0163] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks or optical discs, etc., various media that can store computer programs.

[0164] An embodiment of the present application further provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned embodiments of the data storage method.

[0165] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned embodiments of the data storage method.

[0166] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0167] The above has introduced in detail a data storage method, apparatus, electronic device, and storage medium provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A data storage method, characterized in that: Applied to a first controller, the first controller is used to control data writing and data reading of a first memory, including: Acquire state information of the first memory, wherein the first memory cyclically switches between multiple states; Based on the state information, determining a queue to be stored and a queue to be refreshed of the first memory; The received write command sent by the second controller is stored in the to-be-stored queue, and based on the write command, the to-be-written data is obtained from the second memory, and the to-be-written data is stored in the first memory, wherein the second controller is used to control the writing and reading of data in the second memory; When the first memory undergoes a state switch and the write command exists in the queue to be refreshed, the data to be refreshed in the first memory and the target refresh data in the second memory are determined based on the write command in the queue to be refreshed, and the data to be refreshed is refreshed based on the target refresh data. The first memory is a non-volatile memory.

2. The data storage method according to claim 1, characterized in that: The state of the first memory includes a first state and a second state, the queue of the first memory includes a first queue and a second queue, and determining the queue to be stored and the queue to be refreshed in the first memory based on the state information includes: When the state information is in the first state, determining that the first queue in the first memory is a queue to be stored, and the second queue is a queue to be refreshed; When the state information is in the second state, it is determined that the first queue in the first memory is a queue to be refreshed, and the second queue is a queue to be stored.

3. The data storage method according to claim 1, characterized in that: The method of determining the data to be refreshed in the first memory and the target refresh data in the second memory based on the write command in the queue to be refreshed, and refreshing the data to be refreshed based on the target refresh data, comprises: Determining whether there is at least one write command in the queue to be stored that is the same as the write command in the queue to be refreshed; If there is at least one write command in the queue to be stored that is identical to the write command in the queue to be refreshed, obtaining a target write command in the queue to be refreshed that is identical to the write command in the queue to be stored, and setting the storage data corresponding to the target write command in the first memory to invalid storage data; Acquire other write commands in the queue to be refreshed except the target write command; Based on the other write commands, determining the to-be-refreshed data in the first memory and the target refreshed data in the second memory; Based on the target refresh data, the data to be refreshed is refreshed.

4. The data storage method according to claim 1, characterized in that: The method further comprises: At intervals of a first preset time period, valid storage data in the first storage is written into a target storage, and after the valid storage data is written into the target storage, the valid storage data in the first storage is set as invalid storage data, and a write command corresponding to the valid storage data is set as an invalid write command.

5. The data storage method according to claim 4, characterized in that: Before writing the valid stored data in the first memory into the target memory, the method further includes: Performing error detection on the valid stored data; If the error detection result of the valid stored data is that there is an uncorrectable error, the erroneous data in the valid stored data is determined, correct data corresponding to the erroneous data is obtained from the second memory, and the correct data and other data in the valid stored data except the erroneous data are written into the target memory.

6. The data storage method according to claim 1, characterized in that: The state of the first memory includes a first state, a second state, a third state, and a fourth state, the queue of the first memory includes a first queue and a second queue, and determining the queue to be stored and the queue to be refreshed in the first memory based on the state information includes: When the state information is in the first state, determining that the first queue in the first memory is a queue to be stored and there is no queue to be refreshed; When the state information is in the second state, determining that the first queue in the first memory is a queue to be refreshed, and the second queue is a queue to be stored; When the state information is in the third state, determining that the first queue in the first memory is a queue to be stored and there is no queue to be refreshed; When the state information is in the fourth state, it is determined that the first queue in the first memory is a queue to be stored, and the second queue is a queue to be refreshed.

7. The data storage method according to claim 1, characterized in that: The state of the first memory includes a first state, a second state, and a third state, the queues of the first memory include a first queue, a second queue, and a third queue, and determining the queue to be stored and the queue to be refreshed in the first memory based on the state information includes: When the state information is in the first state, determining that the first queue in the first memory is a queue to be stored, and the second queue is a queue to be refreshed; When the state information is in the second state, determining that the second queue in the first memory is a queue to be stored, and the third queue is a queue to be refreshed; When the state information is in the third state, it is determined that the third queue in the first memory is a queue to be stored, and the first queue is a queue to be refreshed.

8. A data storage device, characterized in that: Applied to a first controller, the first controller is used to control data writing and data reading of a first memory, including: An acquisition module, used for acquiring state information of the first memory, wherein the first memory is cyclically switched between multiple states; A determination module, configured to determine a queue to be stored and a queue to be refreshed of the first memory based on the state information; a storage module, configured to store the received write command sent by the second controller into the to-be-stored queue, and based on the write command, obtain the to-be-written data from the second memory, and store the to-be-written data into the first memory, wherein the second controller is configured to control the writing and reading of data from the second memory; A refresh module is used to determine the data to be refreshed in the first memory and the target refresh data in the second memory based on the write command in the queue to be refreshed when the first memory undergoes state switching and the write command exists in the queue to be refreshed, and refresh the data to be refreshed based on the target refresh data, wherein the first memory is a non-volatile memory.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data storage method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data storage method according to any one of claims 1 to 7.

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