Batched data format adjustment method, system and dpu device based on heterogeneous architecture

Abstract

The application provides a batch data format adjustment method, system and DPU device based on a heterogeneous architecture, which comprises the following steps: receiving original data and format adjustment parameters through a DDR memory; reading the format adjustment parameters, separating each original sub-data that needs to be adjusted in format from the original data according to the data length contained in the data format before format adjustment; selecting a scheduling strategy according to the data format before and after format adjustment, adjusting the format of each original sub-data according to the selected scheduling strategy to obtain corresponding each output sub-data; merging the output sub-data after format adjustment to obtain format adjustment output data; and writing the format adjustment output data back to the DDR memory through the acceleration core of the DPU device, and transmitting the format adjustment output data to the server side through the DDR memory. The application can greatly improve the data format adjustment capability of the heterogeneous system, including type conversion and precision conversion.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data format adjustment, and particularly relates to a batch data format adjustment method and system based on a heterogeneous architecture and a DPU device. BACKGROUND

[0002] In the current database management process, there are scenarios of large batch type conversion and precision promotion and demotion in the database. In the prior art, the large batch type conversion and precision promotion and demotion are executed on a server CPU.

[0003] However, with the development of technology, the continuous improvement of disk read and write and network bandwidth performance, the performance bottleneck in the database field has shifted to computing power, and the existing CPU scheme cannot provide sufficient computing power to support the type conversion and precision promotion and demotion of the existing large data business scale.

[0004] Prior art A: Type conversion and precision promotion and demotion can be implemented by means of a CPU executing a function provided by a database. For example, a CAST function is used in the database to implement type conversion of INT32, INT64, DECIMAL32, and DECIMAL64, and precision promotion and demotion of DECIMAL32 and DECIMAL64. The CAST function refers to a CAST function included in a SQL database, which can explicitly convert an expression of a certain data type to another data type.

[0005] The disadvantages of prior art A are that: (1) the type conversion and precision promotion and demotion of the current database can only be applied to a CPU scenario, that is, the type conversion of INT32, INT64, DECIMAL32, and DECIMAL64, and the precision promotion and demotion of DECIMAL32 and DECIMAL64 can only be implemented on a CPU. (2) The CPU instruction set architecture cannot efficiently and quickly perform type conversion and precision promotion and demotion operations on a large amount of data. (3) The process will generate a high CPU occupancy rate, so that the server cannot perform other tasks.

[0006] Prior art B: Type conversion and precision promotion and demotion functions can be implemented separately at the hardware layer using a CPU.

[0007] The disadvantage of prior art B is that the type conversion function and the precision promotion and demotion function are placed in two regions of hardware, which will consume additional resources and is not conducive to subsequent timing optimization.

[0008] To this end, how to provide a solution and technical architecture with stronger computing power to meet the type conversion and ascending / descending precision of large data business scale, including but not limited to, INT32, INT64, DECIMAL32, DECIMAL64 type conversion and DECIMAL32, DECIMAL64 ascending / descending precision to improve processing speed, is a problem to be solved. SUMMARY

[0009] In view of this, the embodiment of the present application provides a batch data format adjustment method, system and DPU device based on a heterogeneous architecture to eliminate or improve one or more defects in the prior art.

[0010] One aspect of the present application provides a batch data format adjustment method based on a heterogeneous architecture, which is implemented based on a DPU device connected to a server side through a PCIe mode, and the method comprises the following steps: receiving original data requiring format adjustment and format adjustment parameters for indicating a format adjustment mode from the server side through a DDR memory of the DPU device; wherein the format adjustment parameters contain data formats before and after format adjustment, end processing mode and scheduling strategy, the data formats contain data length and data type, and the scheduling strategy contains type conversion, ascending / descending precision and combination of type conversion and ascending / descending precision; reading the format adjustment parameters through an acceleration core of the DPU device, separating each original sub-data requiring format adjustment from the original data according to the data length contained in the data format before format adjustment; selecting a scheduling strategy according to the data formats before and after format adjustment, and performing format adjustment on each original sub-data according to the selected scheduling strategy to obtain corresponding each output sub-data; wherein in the ascending precision process, a multiplier stored in a preset storage space is used for ascending precision, and in the descending precision process, a preset fixed value is used as a divisor, and the multiplier stored in the storage space is used to implement descending precision after ascending precision; reading the format adjustment parameters through the acceleration core of the DPU device, merging the output sub-data after format adjustment according to the data length contained in the data format after format adjustment to obtain format adjustment output data; and writing the format adjustment output data back to the DDR memory through the acceleration core of the DPU device, and transmitting the format adjustment output data back to the server side through the DDR memory.

[0011] In some embodiments of the present application, the format adjustment parameters further contain the number of input data rows and the number of decimal places before and after format adjustment, the number of input data rows is used to assist in separating each original sub-data requiring format adjustment from the original data, and the number of decimal places before and after format adjustment is used to represent the data precision before and after format adjustment.

[0012] In some embodiments of the present application, the data types include integer types and floating point types, the data lengths include 32 and 64, the method supports type conversion between four types of data, INT32, INT64, DECIMAL32 and DECIMAL64, and supports precision promotion and demotion of two types of data, DECIMAL32 and DECIMAL64.

[0013] In some embodiments of the present application, the step of using the multiplier stored in the preset storage space to promote precision comprises: reading the data formats before and after format adjustment to calculate the precision difference before and after precision promotion; based on the precision difference, the corresponding multiplier is taken out from the storage space; the multiplier and the value before format adjustment are used as the value after format adjustment; the decimal point position before format adjustment is modified to the decimal point position after format adjustment to complete the precision promotion.

[0014] In some embodiments of the present application, the step of using the multiplier stored in the preset storage space to promote precision comprises: reading the data formats before and after format adjustment to calculate the precision difference before and after precision promotion; based on the precision difference, the corresponding multiplier is taken out from the storage space; the multiplier and the value before format adjustment are used as the value after format adjustment; the decimal point position before format adjustment is modified to the decimal point position after format adjustment to complete the precision promotion.

[0015] In some embodiments of the present application, the format adjustment parameter further comprises last digit processing mode information, and the last digit processing mode includes rounding and truncation. In the precision demotion process, the last digit of the data is processed according to the last digit processing mode information.

[0016] In some embodiments of the present application, when the last digit processing mode is truncation, after the dividend after precision promotion is divided by the divisor, the precision demotion result after the last digit is truncated can be obtained.

[0017] In some embodiments of the present application, when the last digit processing mode is rounding, the step of using the multiplier stored in the preset storage space to promote precision and then divide by the fixed value to achieve precision demotion comprises: reading the data formats before and after format adjustment to calculate the precision difference before and after precision promotion; according to the precision difference, the corresponding value is read from the preset second storage space, and the value read from the second storage space is added to the dividend, and the sum is used as the new dividend; wherein the second storage space contains numbers in the form of 5 multiplied by 10 raised to an integer power. Based on the precision difference and the fixed value, the multiplier for promoting the precision of the new dividend is determined, and the new dividend is promoted in precision based on the determined multiplier; the fixed value is used as the divisor, and the dividend after precision promotion is divided by the divisor to obtain the result after precision demotion.

[0018] Corresponding to the above method, the application also provides a DPU device containing a DDR memory and a plurality of acceleration cores, which is used to implement the steps of the method in any one of the above embodiments.

[0019] Corresponding to the above method, the application also provides a batch data format adjustment system based on a heterogeneous architecture, which contains the DPU device in claim 9 and a server, wherein the server is used to unload original data requiring format adjustment to the DPU device and receive format adjustment output data returned by the DPU device.

[0020] The batch data format adjustment method based on a heterogeneous architecture provided by the application can perform precision upgrading based on a pre-set storage space, proposes a mechanism of first performing precision upgrading and then performing precision reduction by dividing by a fixed value to reduce the calculation cost of precision reduction, can unload the format adjustment task on the server side to the DPU device in the heterogeneous architecture, thereby releasing the occupancy rate of the server CPU and saving the computing power of the server CPU, and the method provided by the application can greatly improve the data format adjustment capability of the heterogeneous system, including type conversion and precision upgrading and precision reduction.

[0021] Additional advantages, objects, and features of the application will be set forth in part in the description which follows, and will in part be apparent to those of ordinary skill in the art upon examination of the following or can be learned from practice of the application. The objects and other advantages of the application can be realized and attained by the structure particularly pointed out in the specification and claims hereof as well as the appended drawings.

[0022] Those of skill in the art will appreciate that the objects and advantages of the application can be implemented in a variety of ways, and that the application can be implemented using other structures and systems in addition to those specifically described herein. The present application is neither limited to the applications described herein nor to the constructions and arrangements of parts herein described and shown. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description, serve to explain the principles of the application. In the drawings:

[0024] Figure 1 It is a flow chart of the batch data format adjustment method based on a heterogeneous architecture in an embodiment of the application.

[0025] Figure 2 It is a functional module structure schematic diagram in an embodiment of the application.

[0026] Figure 3 It is a conversion flow chart in an embodiment of the application.

[0027] Figure 4 It is a structure schematic diagram of parallel processing INT32 and DECIMAL32 in an embodiment of the application.

[0028] Figure 5 The structure diagram of splicing INT32 and DECIMAL32 in an embodiment of the present application.

[0029] Figure 6 The structure diagram of splicing INT32 and DECIMAL32 in an embodiment of the present application.

[0030] Figure 7 The structure diagram of splicing INT32 and DECIMAL32 in an embodiment of the present application.

[0031] Figure 8 The structure diagram of splicing INT32 and DECIMAL32 in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the embodiments and drawings. Herein, the illustrative embodiments of the present application and their descriptions are used to explain the present application, but not as a limitation of the present application.

[0033] It should be noted that, in order to avoid the present application being obscured by unnecessary details, only the structures and / or processing steps closely related to the solutions according to the present application are shown in the drawings, and other details not closely related to the present application are omitted.

[0034] It should be emphasized that the term "comprises / comprising" as used herein means the presence of stated features, elements, steps or components, but does not preclude the presence or addition of one or more other features, elements, steps or components.

[0035] It should be noted that, if not specifically stated, the term "connected" as used herein can not only mean direct connection, but also indirect connection with an intermediate.

[0036] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0037] INT32 refers to a 32-bit binary integer, INT64 refers to a 64-bit binary integer, DECIMAL32 refers to a 32-bit binary floating point number, and DECIMAL64 refers to a 64-bit binary floating point number. In the specification of the acceleration core, DECIMAL32 can be understood as an INT32 type data containing a decimal point position, for example, DECIMAL32(205, 2) represents an integer 205 after removing the decimal point and a number of bits after the decimal point 2, that is, 2.05. DECIMAL32 can be understood as an INT64 type data containing a decimal point position, for example, DECIMAL64(407, 3) represents an integer 407 after removing the decimal point and a number of bits after the decimal point 3, that is, 0.407.

[0038] Figure 1 A flowchart of a batch data format adjustment method based on a heterogeneous architecture in an embodiment of the present application. The method proposed in the present application is implemented based on a DPU device connected to the server side through PCIe. The method comprises the following steps:

[0039] Step S110: receiving original data requiring format adjustment and format adjustment parameters for indicating the format adjustment mode from the server side through the DDR memory of the DPU device; wherein the format adjustment parameters include data formats before and after format adjustment, end processing mode and scheduling strategy, the data formats include data length and data type, and the scheduling strategy includes type conversion, precision promotion and precision reduction, and combination of type conversion and precision promotion and precision reduction.

[0040] Step S120: reading the format adjustment parameters through the acceleration core of the DPU device, and separating each original sub-data requiring format adjustment from the original data according to the data length contained in the data format before format adjustment.

[0041] Step S130: selecting a scheduling strategy according to the data format before and after format adjustment, and performing format adjustment on each original sub-data according to the selected scheduling strategy to obtain corresponding each output sub-data; wherein in the process of precision promotion, the multiplier stored in the preset storage space is used for precision promotion, and in the process of precision reduction, the preset fixed value is used as the divisor, and the multiplier stored in the storage space is used to implement precision reduction after precision promotion.

[0042] Step S140: reading the format adjustment parameters through the acceleration core of the DPU device, and merging the output sub-data after format adjustment according to the data length contained in the data format after format adjustment to obtain format adjustment output data.

[0043] Step S150: write back the format adjustment output data to the DDR memory through the acceleration core of the DPU device, and transmit the format adjustment output data to the server side through the DDR memory.

[0044] The batch data format adjustment method and system based on the heterogeneous architecture can perform precision upgrading based on a preset storage space, and a mechanism of first performing precision upgrading and then performing precision reduction by dividing by a fixed value is proposed to reduce the calculation cost of precision reduction, so that the format adjustment task of the server side can be offloaded to the DPU device in the heterogeneous architecture, thereby releasing the occupancy rate of the server CPU and saving the computing power of the server CPU. The method proposed in the application can greatly improve the data format adjustment capability of the heterogeneous system, including type conversion and precision upgrading and precision reduction.

[0045] In some embodiments of the application, the format adjustment parameters further include the number of input data rows and the number of decimal places before and after format adjustment. The number of input data rows is used to assist in separating each original sub-data that needs to be adjusted from the original data, and the number of decimal places before and after format adjustment is used to represent the data precision before and after format adjustment. The above is only an example, and data precision and input data size can also be expressed in other ways.

[0046] By using the embodiment of the application, necessary parameters for indicating the data format adjustment process can be carried in the format adjustment parameters, including but not limited to: the format of the input data through the parameters to facilitate subsequent data splitting and splicing, and the format of the input and output data through the number of decimal places, so as to indicate how to perform data format adjustment.

[0047] In some embodiments of the application, the data type includes integer type and floating point type, and the data length includes 32 and 64. The method proposed in the application supports type conversion between at least four types of data: INT32, INT64, DECIMAL32 and DECIMAL64, and supports precision upgrading and precision reduction of two types of data: DECIMAL32 and DECIMAL64.

[0048] In the specific implementation process, the data type can include integer INT and floating point DECIMAL, and the data length includes 32 and 64. The method proposed in the application is applicable to mutual conversion operations between four types of data: INT32, INT64, DECIMAL32 and DECIMAL64, and precision upgrading and precision reduction operations of two types of data: DECIMAL32 and DECIMAL64.

[0049] By using the embodiment of the application, the scope of use of the method proposed in the application is exemplarily proposed.

[0050] In some embodiments of the present application, the step of increasing the precision in step S130 using the multiplier stored in the preset storage space comprises: (1) reading the data format before and after the format adjustment to calculate the precision difference before and after the precision increase; (2) taking the corresponding multiplier from the storage space based on the precision difference; (3) taking the multiplier and the value before the format adjustment as the value after the format adjustment; and (4) modifying the decimal point position before the format adjustment to the decimal point position after the format adjustment to complete the precision increase.

[0051] In the specific implementation process, the preset storage space can be set in the following form:

[0052]

[0053] The embodiment of the present application can use the multiplier stored in the preset storage space to increase the precision.

[0054] In some embodiments of the present application, the step of decreasing the precision in step S130 using the multiplier stored in the storage space comprises: (1) reading the data format before and after the format adjustment to calculate the precision difference before and after the precision increase; (2) determining the multiplier for increasing the precision of the dividend based on the precision difference and the fixed value, and increasing the precision of the dividend based on the determined multiplier; and (3) dividing the dividend after the precision increase by the fixed value to obtain the result after the precision decrease.

[0055] The embodiment of the present application can use the multiplier stored in the preset storage space to increase the precision, and then use the fixed value as the divisor to decrease the precision, which can greatly reduce the calculation amount in the precision decrease process.

[0056] In some embodiments of the present application, the format adjustment parameter further comprises last digit processing mode information, and the last digit processing mode comprises rounding and truncation. In the precision decrease process, the last digit of the data is processed according to the last digit processing mode information.

[0057] On the one hand, when the last digit processing mode is truncation, the precision decrease result after the last digit is truncated can be obtained after the dividend after the precision increase is divided by the divisor. In a popular way, the above-mentioned precision decrease method can be directly achieved by using the truncation.

[0058] When the last processing mode is rounding, the step of reducing precision by storing the multiplier in the storage space and then dividing the fixed value to realize the step of reducing precision includes: (1) reading the data format before and after format adjustment to calculate the precision difference before and after the precision is increased; (2) reading the corresponding value from the second storage space according to the precision difference, and adding the value read from the second storage space to the dividend, so as to take the sum as the dividend; wherein the second storage space contains an integer power of 5 times 10; (3) determining the multiplier for increasing the precision of the new dividend based on the precision difference and the fixed value, and increasing the precision of the dividend based on the determined multiplier; (4) dividing the dividend after the precision is increased by the fixed value to obtain the result after the precision is reduced. In a popular way, according to the precision difference between the increased and reduced precision, "+5" is selected at the corresponding position of the data, and then the above-mentioned truncation type process is processed, so that the step of reducing precision in the rounding type is simply realized.

[0059] By using the above-mentioned embodiment of the application, the truncation type or rounding type precision reduction processing can be realized based on the newly designed steps, and the calculation amount of the precision reduction step can be greatly reduced based on the prior art.

[0060] In the heterogeneous computing scene to which the application is applied, the type conversion of INT32, INT64, DECIMAL32 and DECIMAL64 and the increasing and reducing precision of DECIMAL32 and DECIMAL64 are aimed at obtaining original data and operation methods according to parameters, calculating results and returning the results to a server. Among them, the type conversion of INT32, INT64, DECIMAL32 and DECIMAL64 and the increasing and reducing precision of DECIMAL32 and DECIMAL64 are executed on an acceleration card, and we call the functional module located on the DPU device as an acceleration core. The acceleration core of the DPU device provides two input interfaces and an output interface to the outside, the two input interfaces are respectively the data A to be type converted / precision increased and reduced and the parameter B, and the output is the calculation result C.

[0061] Figure 2 The functional module structure diagram in an embodiment of the application is shown in FIG. 1. Figure 2 As shown in FIG. 1, the type conversion function and the increasing and reducing precision function both need to use the data separation module and the data merging module, so they can be fused by certain changes to save resources. At the same time, the type conversion / precision increasing and reducing module can be placed in the same position of the hardware, which is beneficial to timing optimization. Figure 2The data type conversion and / or precision raising and lowering are controlled by using the control module 260, and the steps of the data type conversion and / or precision raising and lowering in time sequence are completed by cooperating the data input module 210, the data separation module 220, the data type conversion / precision raising and lowering module 230, the data merging module 240, the data output module 250 and the like. The control module is used to transmit the control instruction from the server CPU, and the control instruction contains the type information of the data format adjustment and the adjustment target information. The type information is used to indicate whether the type conversion or the precision raising and lowering, and the adjustment target information is used to indicate the adjusted data form.

[0062] Figure 3 The data format conversion flowchart in an embodiment of the application contains the following steps:

[0063] Step S310: judging whether the total row number is less than the total row number, if not, directly ending, if yes, entering step S320.

[0064] Step S320: reading data from the DDR, and entering step S330.

[0065] Step S330: judging the operation type, whether the precision raising and lowering only, the type conversion only or the type conversion+precision raising and lowering, if the precision raising and lowering only, entering step S340, otherwise, entering step S350.

[0066] Step S340: performing the precision raising and lowering operation according to the input and the parameter, and then entering step S370.

[0067] Step S350: performing the type conversion according to the input and the parameter, and entering S360.

[0068] Step S360: judging whether the operation type is the type conversion only or the conversion+precision raising and lowering, if containing the precision raising and lowering, returning to step S340, otherwise, entering step S370.

[0069] Step S370: writing back the data to the DDR.

[0070] In a specific embodiment of the application, the main steps of performing the data format conversion in the heterogeneous architecture and the specific explanations thereof are as follows:

[0071] Step 1: data preparation stage, from the server to the DDR of the acceleration card.

[0072] The host sends the data A to be type converted / precision raised and lowered and the parameter B to the DDR of the acceleration card through the PCIe channel and starts the execution of the acceleration core.

[0073] Step 2: data input stage, from the DDR of the acceleration card to the acceleration core of the acceleration card.

[0074] The accelerator reads parameter B data from the DDR for initialization, and the parameter content includes input / output data format, input / output data decimal point position, input data row number, last digit processing mode and scheduling strategy: (1) Input / output data format: the accelerator supports INT32, INT64, DECIMAL32, and DECIMAL64 four data formats. (2) Input / output data decimal point position: when the input / output data format is DECIMAL32 / DECIMAL64, the corresponding input / output decimal point position is required. (3) Input data row number: used to determine the number of type conversion / precision promotion / demotion. (4) Last digit processing mode: used to confirm whether the last digit needs to be rounded when demoting precision. (5) Scheduling strategy, divided into type conversion, precision promotion / demotion, and type conversion+precision promotion / demotion.

[0075] Step 3: Data separation step.

[0076] The bit width of input A is 512 bits, and the length of the data type has only two possible conditions, i.e. 32 bits and 64 bits, so the system needs to judge the input data type to perform parallel processing on the input data.

[0077] Figure 4 The structure diagram for parallel processing of INT32 and DECIMAL32 in an embodiment of the application is shown, which exemplarily shows how to cut 512-bit length data into different sub-data of INT32 and DECIMAL32 (32-bit) length.

[0078] Figure 5 The structure diagram for parallel processing of INT64 and DECIMAL64 in an embodiment of the application is shown, which exemplarily shows how to cut 512-bit length data into different sub-data of INT64 and DECIMAL64 (32-bit) length.

[0079] Step 4 (key step): According to the different input parameters, different scheduling strategies are selected.

[0080] According to the different input parameters, the system will perform different scheduling strategies. This step is divided into three cases according to the scheduling strategy, i.e. type conversion, precision promotion / demotion, and type conversion+precision promotion / demotion.

[0081] Case 1 (type conversion): for the case of converting 32-bit type data into 64-bit type data, zero needs to be added in front of each 32-bit data. For the case of converting INT type data into DECIMAL type data, the default output scale is 0.

[0082] Case two (precision of lifting): the input data of this module can be DECIMAL32 or DECIMAL64 type data directly input by the outside or generated by the type conversion module. If the input data precision is less than the output data precision, it is precision lifting, otherwise, it is precision reduction.

[0083] Hereinafter, two cases of precision lifting and precision reduction are discussed.

[0084] Precision lifting case: possible multipliers are put into a pre-set storage space A, and then the corresponding multipliers are taken out from the storage space A according to the difference between the input / output data precision, which can ensure that the multiplier at one end of the multiplier is fixed, and further optimize the resources and timing of the system. This design is not easy to think of for designers in the field. The pre-set values of the storage space A are as follows:

[0085]

[0086] For example: DECIMAL32 (206, 2) -> DECIMAL32 (206000, 5), the calculation process is: (1) 206*array_mult_div[4] = 206000.

[0087] In addition, if the precision lifting operation causes the output data to overflow, the software side will give an error prompt information.

[0088] The precision reduction case is divided into two cases of rounding and non-rounding end processing.

[0089] When the end processing method is truncation (non-rounding): possible divisors are put into a pre-set storage space A, and then the corresponding divisors are taken out from the storage space A according to the difference between the input / output data precision, which can also optimize the resources and timing of the system. However, in FPGA, the divider often occupies the most resources, and this design cannot meet the needs of system resources and timing, therefore, this hardware design is further optimized.

[0090] Further, the scheme can be optimized as follows: the dividend needs to be expanded to 64 bits, the corresponding value is taken out from the storage space A according to the difference between the calculation input / output data precision, the dividend is multiplied by the corresponding value, and the result is obtained by dividing by a fixed divisor 10 14. Fixing the divisor to 10 14 can maximize the resource consumption of the divider, and this design is not easily thought of by designers in the field, and is the biggest innovation of the patent. For example: DECIMAL32(205700, 5) -> DECIMAL32(205, 2), the calculation process is: (1) 205700*(array_mult_div[15-3]) = 2.057*(10 16); (2) 2.057*(10 16) / (10 14) = 205.

[0091] When the last digit processing method is rounding off: the processing method of rounding off the last digit is only different from the processing method of cutting off the last digit at the beginning, and the processing method of rounding off the last digit needs to take out a corresponding value from the storage space B at the beginning according to the difference between the calculation input / output data precision, first add the dividend and the value, and then perform subsequent operations. The values pre-set in the storage space B are as follows:

[0092]

[0093] For example: DECIMAL32(205700, 5) -> DECIMAL32(206, 2), the calculation process is:

[0094] (1) 205700+array_mod[3] = 206200; (meaning that the rounding off processing is performed from the third digit from the right)

[0095] (2) 206200*(array_mult_div[15-3]) = 2.062*(10 16); (meaning that)

[0096] (3) 2.06*(10 16) / (10 14) = 206

[0097] The effect of rounding off is achieved by adding first and then dividing on the hardware side, which is not easily thought of by designers in the field.

[0098] Step 5: data merging step.

[0099] The bit width of output C is 512 bits, and the length of the data type only has two possible conditions, i.e., 32 bits and 64 bits, so the system needs to splice the output data by judging the output data type. The effect of this step is as shown in Figure 6-7 , wherein, Figure 6A structure diagram for splicing INT32 and DECIMAL32 in an embodiment of the present application, Figure 7 A structure diagram for splicing INT64 and DECIMAL64 in an embodiment of the present application.

[0100] Step 6: data output step, from the acceleration core to the DDR, and then from the DDR to the server.

[0101] This step is to write the output data in a burst mode to the DDR. The burst transmission refers to relatively high-bandwidth data transmission in a short time. The DPU hardware acceleration card includes the DDR and the acceleration core.

[0102] The following table is an example of the function of the acceleration core in an embodiment. For the up and down precision functions of DECIMAL32 and DECIMAL64, the program running results are as follows given different input data and parameters:

[0103]

[0104] Figure 8 A heterogeneous architecture diagram including a DPU device in an embodiment of the present application. The structure relationship of the heterogeneous architecture composed of the (database) server and the DPU device is shown. The number of acceleration cores and operators is only illustrative and is not a specific limitation.

[0105] Corresponding to the above method, the present application also provides a DPU device including a DDR memory and a plurality of acceleration cores, and the DPU device is used to implement the steps of the method according to any one of the above embodiments.

[0106] Corresponding to the above method, the present application also provides a batch data format adjustment system based on a heterogeneous architecture, including a DPU device and a server as proposed in the above embodiments, and the server is used to unload the original data requiring format adjustment to the DPU device and receive the format adjustment output data returned by the DPU device.

[0107] In summary, the batch data format adjustment method and system based on a heterogeneous architecture, and the DPU device proposed in the present application can perform up-precision based on a pre-set storage space, propose a mechanism of up-precision first and then down-precision by division by a fixed value to reduce the calculation cost of down-precision, and can unload the format adjustment task on the server side to the DPU device in the heterogeneous architecture, thereby releasing the occupancy rate of the server CPU and saving the computing power of the server CPU. The method proposed in the present application can greatly improve the data format adjustment capability of the heterogeneous system including type conversion and up and down precision.

[0108] The key points and advantages of the method and system proposed in the present application are that:

[0109] (1) The batch data format adjustment method based on the heterogeneous architecture proposed in the application can be applied to the scene of large batch type conversion and precision conversion in a database. The type conversion of INT32, INT64, DECIMAL32, DECIMAL64 and the precision conversion of DECIMAL32, DECIMAL64 can be executed on the DPU device of the heterogeneous system by scheduling strategy optimization, instead of the CPU, which expands the implementation scheme. The scheme relies on the heterogeneous computing system composed of the DPU hardware acceleration card and the traditional CPU server to replace the corresponding functions of the existing database.

[0110] (2) Based on the type conversion and precision conversion function designed in the heterogeneous system, the type conversion and precision conversion capability of the heterogeneous system can be greatly improved.

[0111] (3) After the task is offloaded to the DPU device in the heterogeneous system, the CPU can avoid executing the heavy batch data format conversion computing task by only sending some control instructions, which releases the CPU occupancy and provides space for the CPU to process other tasks. Based on the unique hardware design, task scheduling and resource optimization are performed, and the scheme can save resources while improving computing efficiency.

[0112] (4) The scheme proposed in the application can realize the type conversion function and the precision conversion function in the same area of the hardware, and fuse some similar modules. In this way, the resources can be optimized, and the scheduling can be faster according to the application scene.

[0113] (5) The scheme proposed in the application puts the realized functions into a module, which is easy for the expansion of functions.

[0114] (6) The scheme proposed in the application has a unique hardware design for the precision conversion function, which can save resources while improving computing efficiency.

[0115] Those of ordinary skill in the art will appreciate that the various illustrative components, systems and methods described in connection with the embodiments disclosed herein can be implemented as hardware, software, or both. The particular implementation is dependent on the specific application and design constraints imposed on the overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application. When implemented in hardware, for example, the hardware can comprise an electronic circuit, an Application Specific Integrated Circuit (ASIC), a suitable firmware, a plug-in, a functional card, etc. When implemented in software, the elements of the application are the program or code segments to perform a specific task. The program or code segments can be stored in a machine-readable medium, or transmitted by a carrier wave as data signals over a transmission medium or communication link.

[0116] It is to be understood that the application is not limited to the particular configurations and processes described herein and shown in the drawings. For simplicity, detailed descriptions of known methods and apparatuses are omitted so as not to obscure the disclosure. In the above-described embodiments, several specific steps are described and illustrated as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and the order of the steps can be changed, or other steps can be added, or replaced, or eliminated, depending on the application.

[0117] In the present application, features described and / or illustrated in relation to one embodiment can be used in the same or a similar way in one or more other embodiments, and / or combined with or instead of features of other embodiments.

[0118] The above description is only preferred embodiments of the present application, and is not intended to limit the present application. The embodiments of the present application can be variously changed and modified by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the present application.

Claims

1. A method for adjusting a batched data format based on a heterogeneous architecture, the method comprising: receiving a batched data format; determining a heterogeneous architecture; and adjusting the batched data format based on the heterogeneous architecture. The method is implemented by a DPU device connected to a server side through a PCIe mode, and comprises the following steps: receiving, by a DDR memory of the DPU device, original data from the server side requiring format adjustment and format adjustment parameters for indicating a format adjustment mode; wherein the format adjustment parameters include data formats before and after format adjustment, end processing mode and scheduling strategy, the data formats include data length and data type, and the scheduling strategy includes type conversion, precision increase and decrease and combination of type conversion and precision increase and decrease; reading, by an acceleration core of the DPU device, the format adjustment parameters, and separating each original sub-data requiring format adjustment from the original data according to the data length included in the data format before format adjustment; selecting a scheduling strategy according to the data formats before and after format adjustment, and performing format adjustment on each original sub-data according to the selected scheduling strategy to obtain corresponding each output sub-data; wherein in the process of precision increase, a multiplier stored in a preset storage space is used for precision increase, and in the process of precision decrease, a preset fixed value is used as a divisor, and the multiplier stored in the storage space is used for precision increase and then divided by the fixed value to realize precision decrease; reading, by the acceleration core of the DPU device, the format adjustment parameters, and merging the output sub-data after format adjustment according to the data length included in the data format after format adjustment to obtain format adjustment output data; writing, by the acceleration core of the DPU device, the format adjustment output data back to the DDR memory, and transmitting the format adjustment output data back to the server side through the DDR memory.

2. The method of claim 1, wherein, The format adjustment parameters further include input data row number and decimal point bit number before and after format adjustment, the input data row number is used for assisting in separating each original sub-data requiring format adjustment from the original data, and the decimal point bit number before and after format adjustment is used for indicating data precision before and after format adjustment.

3. The method of claim 2, wherein, The data type includes integer type and floating point type, the data length includes 32 and 64, the method supports type conversion between four types of data, i.e. INT32, INT64, DECIMAL32 and DECIMAL64, and supports precision increase and decrease of two types of data, i.e. DECIMAL32 and DECIMAL64.

4. The method of claim 2, wherein, The step of using the multiplier stored in the preset storage space for precision increase comprises: reading the data formats before and after format adjustment to calculate precision difference before and after precision increase; based on the precision difference, taking out a corresponding multiplier from the storage space; using the multiplier and the value before format adjustment as the value after format adjustment; modifying the decimal point bit number before format adjustment to the decimal point bit number after format adjustment to complete precision increase.

5. The method of claim 2, wherein, The step of using the multiplier stored in the preset storage space for precision increase and then dividing by the fixed value to realize precision decrease comprises: reading the data formats before and after format adjustment to calculate precision difference before and after precision increase; based on the precision difference and the fixed value, determining a multiplier for precision increase of a dividend, and using the determined multiplier to increase the precision of the dividend first; Divide the dividend after precision promotion by the divisor with the fixed value as the divisor to obtain the result after precision reduction.

6. The method of claim 2, wherein, The format adjustment parameter further comprises last digit processing mode information, and the last digit processing mode comprises rounding and truncation. In the precision reduction process, the last digit of the data is processed according to the last digit processing mode information.

7. The method of claim 6, wherein, When the last digit processing mode is truncation, the result after precision reduction after the last digit is truncated can be obtained after the dividend after precision promotion is divided by the divisor.

8. The method of claim 6, wherein, When the last digit processing mode is rounding, the step of reducing precision by dividing the dividend after precision promotion by the divisor with the fixed value as the divisor comprises: Reading the data format before and after format adjustment to calculate the precision difference before and after precision promotion; According to the precision difference, reading the corresponding value from a second storage space, and adding the value read from the second storage space to the dividend, taking the sum as the new dividend; wherein the second storage space contains numbers in the form of 5 times 10 raised to an integer power; Based on the precision difference and the fixed value, determine the multiplier for promoting the precision of the new dividend, and promote the precision of the dividend based on the determined multiplier; Divide the dividend after precision promotion by the divisor with the fixed value as the divisor to obtain the result after precision reduction.

9. A DPU device, comprising: The DPU device comprises DDR memory and a plurality of acceleration cores, and is used to implement the steps of the method according to any one of claims 1-8.

10. A heterogeneous architecture based batched data format adjustment system, characterized in that, The DPU device comprises the DPU device of claim 9 and a server, and the server is used to unload original data requiring format adjustment to the DPU device and receive format adjustment output data returned by the DPU device.

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