Data type converter and processor

Abstract

The embodiment of the invention discloses a data type converter and a processor, relates to the technical field of integrated circuits, and aims to reduce the production cost of a processor chip. The data type converter comprises a decoding module used for decoding a micro conversion instruction to obtain the type of an operand to be converted, the type of a target operand and the type of a micro instruction; the extraction module is also used for extracting symbols, offset indexes and mantissas of the operands to be converted; the first intermediate operand generation module is used for determining a right shift parameter according to the shift constant and the offset index of the operand to be converted; generating a first intermediate operand according to the right shift parameter, the mantissa of the operand to be converted, the symbol of the operand to be converted and the type of the target operand; and the overflow identifier determination module is used for determining an overflow identifier according to the offset index of the operand to be converted and the type of the target operand. The method and the device are suitable for data type conversion.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a data type converter and processor. Background Technology

[0002] With technological advancements, higher demands are being placed on the data precision conversion capabilities of processors such as Central Processing Units (CPUs). For instance, in the field of Artificial Intelligence (AI), during the AI ​​model training phase, CPUs are required to support data types of different precisions, such as converting from double-precision floating-point (FP64) to single-precision floating-point (FP32) or brain-level floating-point 16 (BF16). This effectively reduces memory usage and computational load, increases training speed, and lowers training costs while ensuring model accuracy. During the AI ​​model inference phase, CPUs are required to support lower-precision data types (such as FP16, FP8, or INT8). This allows for significant improvements in inference speed and data throughput without substantial loss of precision, meeting the real-time requirements of applications. Furthermore, CPUs are needed to better integrate with various AI frameworks and tools, adapting to the computational precision requirements of different models and algorithms, thereby improving overall computational efficiency and performance and contributing to the widespread application and development of AI technology across more fields.

[0003] However, the hardware resource overhead for converting between different data types varies. If a dedicated hardware module is designed for each type of data conversion, it will occupy a large area of ​​the CPU chip, resulting in higher production costs for the CPU chip. Summary of the Invention

[0004] In view of this, embodiments of this application provide a data type converter and processor, which facilitates the reduction of processor chip production costs.

[0005] In a first aspect, embodiments of this application provide a data type converter, comprising: a decoding module, configured to receive a micro-conversion instruction and decode the micro-conversion instruction to obtain the type of the operand to be converted, the type of the target operand, and the micro-instruction type; further configured to receive the operand to be converted and extract the sign, bias exponent, and mantissa of the operand to be converted; the type of the operand to be converted is one of multiple precision floating-point numbers, and the type of the target operand is one of fixed-point and floating-point numbers; when the type of the target operand is a floating-point number, the mantissa bit width of the operand to be converted is greater than the mantissa bit width of the target operand; and a first intermediate operand generation module, connected to the decoding module, configured to generate an intermediate operand based on a shift constant and the type of the operand to be converted. The module generates a first intermediate operand based on the offset exponent of the number, the right shift parameter, the mantissa of the operand to be converted, the sign of the operand to be converted, and the type of the target operand. The shift constant is determined based on the type of the operand to be converted and the type of the target operand. An overflow flag determination module, connected to the decoding module, determines an overflow flag based on the offset exponent of the operand to be converted and the type of the target operand. A target operand determination module, connected to both the first intermediate operand generation module and the overflow flag determination module, determines whether to use the first intermediate operand as the target operand based on the microinstruction type and the overflow flag.

[0006] Secondly, embodiments of this application provide a data type converter, comprising: a decoding module, configured to receive a micro-conversion instruction and decode the micro-conversion instruction to obtain the type of the operand to be converted, the type of the target operand, and the micro-instruction type; further configured to receive the operand to be converted; the type of the operand to be converted is either a fixed-point number or a floating-point number, and the type of the target operand is a floating-point number; when the type of the operand to be converted is a floating-point number, the mantissa bit width of the operand to be converted is smaller than the mantissa bit width of the target operand; a first intermediate operand generation module, connected to the decoding module, configured to extract valid data from the valid data bit field of the operand to be converted; determine a left shift parameter according to the type of the operand to be converted; determine a first mantissa according to the left shift parameter and the valid data; determine a first bias index according to the type of the operand to be converted, the type of the target operand, and the bias index of the operand to be converted, and determine a first bias index according to the type of the operand to be converted. The system defines a subtype of the operand, determines a second bias exponent, and selects a target bias exponent from the first and second bias exponents. When the operand to be converted is a fixed-point number, its bias exponent is 0. Based on the type of the target operand, the sign of the operand to be converted, the target bias exponent, and the first mantissa are concatenated to obtain a concatenated operand. Based on the concatenated operand, a first intermediate operand is determined. An overflow flag determination module, connected to both the decoding module and the first intermediate operand generation module, determines an overflow flag based on the type of the operand to be converted, the type of the target operand, the first mantissa, and the target bias exponent. A target operand determination module, connected to both the first intermediate operand generation module and the overflow flag determination module, determines whether to use the first intermediate operand as the target operand based on the microinstruction type and the overflow flag.

[0007] Thirdly, embodiments of this application provide a data type converter, comprising: a first conversion branch, wherein the first conversion branch is a data type converter according to any embodiment of the first aspect; a second conversion branch, wherein the second conversion branch is a data type converter according to any embodiment of the second aspect; wherein the decoding module in the second conversion branch is the same decoding module as the decoding module in the first conversion branch; and a branch selection module, connected to the decoding module and connected to the first conversion branch through a first switch module and connected to the second conversion branch through a second switch module, for determining branch selection information according to the microinstruction type, so that one of the first switch module and the second switch module is in an on state and the other switch module is in an off state.

[0008] Fourthly, embodiments of this application provide a processor, the processor including a data type converter; wherein the data type converter is a data type converter of any embodiment in the first aspect, or a data type converter of any embodiment in the second aspect, or a data type converter of any embodiment in the third aspect.

[0009] In this embodiment, the data type converter has a decoding module that receives and decodes micro-conversion instructions to obtain the type of the operand to be converted, the type of the target operand, and the micro-instruction type. It also receives the operand to be converted and extracts its sign, bias exponent, and mantissa. A first intermediate operand generation module determines a right shift parameter based on the shift constant and the bias exponent of the operand to be converted. It then generates a first intermediate operand based on the right shift parameter, the mantissa of the operand to be converted, the sign of the operand to be converted, and the type of the target operand. An overflow flag determination module determines an overflow flag based on the bias exponent of the operand to be converted and the type of the target operand. A target operand determination module determines whether to use the first intermediate operand as the target operand based on the micro-instruction type and the overflow flag. This data type converter allows for the conversion of different types of floating-point numbers to either floating-point or fixed-point numbers. Multiple types of floating-point number conversions can share the same data type converter, eliminating the need for dedicated hardware modules for each data type conversion. This reduces the area occupied by the processor chip and lowers the production cost of the processor chip. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of a data type converter provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating the data formats supported by embodiments of this application; Figure 3 This is a schematic diagram illustrating the conversion of a single-precision floating-point number to a half-precision floating-point number or a 32-bit fixed-point number according to a specific embodiment of this application. Figure 4 This is a schematic diagram of the structure of a first intermediate operand generation module provided in an embodiment of this application; Figure 5 for Figure 4 A diagram illustrating the data formats supported in vector mode; Figure 6This is a schematic diagram illustrating the conversion from a 32-bit fixed-point number to a single-precision floating-point number according to a specific embodiment of this application. Figure 7 This is a schematic diagram illustrating the use of a third conversion branch to convert data types in one embodiment of this application. Detailed Implementation

[0012] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0013] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0014] Example 1 Figure 1 This is a schematic diagram of the structure of a data type converter 1 provided in an embodiment of this application, as shown below. Figure 1 As shown, the data type converter 1 of this embodiment may include: a decoding module 10, a first intermediate operand generation module 11, an overflow flag determination module 12, and a target operand determination module 13; wherein, the first intermediate operand generation module 11 is connected to the decoding module 10 and the target operand determination module 13 respectively, and the overflow flag determination module 12 is connected to the decoding module 10 and the target operand determination module 13 respectively; the decoding module 10 is used to receive micro-conversion instructions and decode the micro-conversion instructions to obtain the type of the operand to be converted, the type of the target operand, and the micro-instruction type; it is also used to receive the operand to be converted and extract the sign, bias exponent, and mantissa of the operand to be converted; the type of the operand to be converted is one of multiple precision floating-point numbers, and the type of the target operand is... One of fixed-point and floating-point numbers; when the target operand is of type floating-point, the mantissa width of the operand to be converted is greater than the mantissa width of the target operand; the first intermediate operand generation module 11 is used to determine the right shift parameter based on the shift constant and the bias exponent of the operand to be converted; and to generate the first intermediate operand based on the right shift parameter, the mantissa of the operand to be converted, the sign of the operand to be converted, and the type of the target operand; wherein, the shift constant is determined based on the type of the operand to be converted and the type of the target operand; the overflow flag determination module 12 is used to determine the overflow flag based on the bias exponent of the operand to be converted and the type of the target operand; the target operand determination module 13 is used to determine whether to use the first intermediate operand as the target operand based on the microinstruction type and the overflow flag.

[0015] The data type converter in this embodiment can be integrated into the processor, enabling the conversion between floating-point numbers and fixed-point numbers, as well as the conversion between floating-point numbers with a high mantissa width and those with a low mantissa width (i.e., the mantissa width of the operand to be converted is greater than that of the target operand). The operand to be converted can be a double-precision floating-point number, a single-precision floating-point number, a half-precision floating-point number, an 8-bit mixed-precision floating-point number, or an 8-bit nadir floating-point number, etc. The target operand can be a fixed-point number, a single-precision floating-point number, an 8-bit mixed-precision floating-point number, or an 8-bit nadir floating-point number, etc. For example, a single-precision floating-point number SP can be converted to a fixed-point number INT32 or INT64; a half-precision floating-point number HF16 can be converted to a fixed-point number INT16, INT32, or INT64; a double-precision floating-point number DP can be converted to a single-precision floating-point number SP; a single-precision floating-point number SP can be converted to a nadir floating-point number BF16, etc. Some data formats supported in this embodiment are as follows: Figure 2 As shown.

[0016] The operands to be converted can be scalar operands or vector operands. When the operands to be converted are vector operands, they can specifically include at least two elements, each of which is a floating-point number and all elements are of the same type, such as each element being a half-precision floating-point number.

[0017] Microinstruction types are used to indicate the type of the operand to be converted to the type of the target operand. For example, (1) the PS2PH microinstruction (micro-conversion instruction) indicates that the operand to be converted is a set of FP32 vector operands and the target operand is a set of FP16 vector operands, and converts the FP32 vector operands to FP16 vector operands; (2) the SS2SH microinstruction indicates that the operand to be converted is an FP32 operand and the target operand is an FP16 operand, and converts the FP32 scalar operands to FP16 scalar operands.

[0018] In this embodiment, the operand to be converted is a floating-point operand, consisting of a sign bit S, an offset exponent bit E, and a mantissa bit M, representing a floating-point number according to the IEEE-754 standard. V = (-1) S 2 E-bias (1. M The sign S is either positive (represented by a value of 0) or negative (represented by a value of 1); the bias exponent E is the biased exponent, and bias is the bias threshold. The bias exponent determines the order of magnitude; the mantissa F stores the valid data and determines the precision of the operand to be converted. For example, a 32-bit single-precision floating-point number uses 23 bits to store the mantissa. For example, in the PS2PH microinstruction, the operand to be converted is Src[63:0], which means that the operand to be converted consists of two FP32 floating-point elements, namely Src[63:32] and Src[31:0]. The sign S, bias exponent E, and mantissa M of the two operands can be extracted respectively.

[0019] The shift constant is determined based on the types of the operand to be converted and the target operand. Specifically, the constant can be determined based on the bias exponent range corresponding to the type of the operand to be converted and the bias exponent range corresponding to the type of the target operand.

[0020] The right shift parameter is obtained by adding the shift constant and the bias exponent of the operand to be converted.

[0021] In some examples, the overflow flag determination module 12 may include an overflow parameter determination submodule 12a and an overflow flag determination submodule 12b. The overflow parameter determination submodule 12a is connected to the decoding module 10 and is used to determine the overflow parameter based on the bias exponent and overflow constant of the operand to be converted. The overflow flag determination submodule 12b is connected to the overflow parameter determination submodule 12a and is used to determine the overflow flag based on the overflow parameter and the type of the target operand.

[0022] The overflow constant can be determined by the decoding module 10 based on the type of the operand to be converted and the type of the target operand, and sent to the overflow parameter determination submodule 12a. The overflow parameter determination submodule 12a can perform an addition operation between the overflow constant and the bias exponent (with bias exponent) to calculate the overflow parameter. The overflow flag determination submodule 12b determines the overflow flag based on the overflow parameter and the type of the target operand.

[0023] Overflow parameters can be used to determine whether the conversion result is a denormalized number and whether the result exponent exceeds a fixed value. For example, in a microinstruction for converting a floating-point number to a floating-point number (where the operand to be converted is a floating-point number and the target operand is a floating-point number), if all overflow parameters are 0, it indicates that the result has a bias exponent of 0, meaning the result may be a denormalized number. Overflow flags include overflow flags and underflow flags.

[0024] In specific examples, when both the operand to be converted and the target operand are floating-point numbers, if the unbiased exponent of the operand to be converted is sufficiently small and the result determined by the overflow parameter is a denormalized number, the overflow is identified as underflow. When both the operand to be converted and the target operand are fixed-point numbers, if the unbiased exponent of the operand to be converted is less than -1, the overflow is identified as underflow. When both the operand to be converted and the target operand are floating-point numbers or fixed-point numbers, if the exponent determined by the overflow parameter exceeds the overflow threshold (e.g., the FP16 overflow threshold is set to 5'h1F), the overflow is identified as overflow. When the target operand is a floating-point number, the overflow threshold reflects whether the unbiased exponent of the operand to be converted exceeds the exponent representation range of the target operand; when the target operand is a fixed-point number, the overflow threshold reflects whether the unbiased exponent of the operand to be converted exceeds the effective data bit width of the integer data.

[0025] like Figure 1 In the illustrated embodiment, the overflow parameter is obtained by adding the overflow constant and the bias exponent. Figure 3 The illustrated embodiment is used as an example to assume that data precision conversion from SP to INT32 is implemented: (1) The bias exponent of the operand to be converted is Src.Exp = Src.e + SP.Bias, where Src.e is the unbiased exponent and SP.Bias represents the bias value of SP precision SP.Bias = 127; (2) Based on the SP type of the operand to be converted and the INT32 type of the target operand, the overflow constant const is decoded as: SP.Bias−31+1, where 31 represents the valid bit field of the INT32 type; (3) Overflow parameter = Overflow constant + Bias exponent = (SP.Bias-31 + 1) + (Src.e +SP.Bias) = ​​2 SP.Bias + (Src.e - 30). The overflow threshold is set to 2. SP.Bias + 1 = 8'hFF. When the overflow parameter exceeds this threshold, the overflow is marked as an overflow.

[0026] The target operand determination module 13 determines whether to use the first intermediate operand as the target operand based on the microinstruction type and overflow flag.

[0027] In this embodiment, the decoding module 10 receives a micro-conversion instruction and decodes it to obtain the type of the operand to be converted, the type of the target operand, and the micro-instruction type. It also receives the operand to be converted and extracts its sign, bias exponent, and mantissa. The first intermediate operand generation module 11 determines the right shift parameter based on the shift constant and the bias exponent of the operand to be converted. It then generates the first intermediate operand based on the right shift parameter, the mantissa of the operand to be converted, the sign of the converted operand, and the type of the target operand. The overflow flag determination module 12 determines the overflow flag based on the bias exponent of the operand to be converted and the type of the target operand. The target operand determination module 13 determines whether to use the first intermediate operand as the target operand based on the micro-instruction type and the overflow flag. Through the data type converter 1, different types of floating-point numbers can be converted to floating-point numbers or fixed-point numbers. The conversion of multiple types of floating-point numbers can share the same data type converter 1, eliminating the need to design dedicated hardware modules for each data type conversion. This reduces the area occupied by the processor chip, lowers the production cost of the processor chip, and saves on processor chip area and power consumption.

[0028] In some examples, the first intermediate operand generation module 11 may include a right shift parameter determination submodule 11a, a shift submodule 11b, and a first intermediate operand generation submodule 11c; wherein, the right shift parameter determination submodule 11a is connected to the decoding module 10 and is used to determine the right shift parameter based on the shift constant and the bias exponent of the operand to be converted; the shift submodule 11b is connected to both the right shift parameter determination submodule 11a and the decoding module 10 and is used to right-shift the mantissa of the operand to be converted based on the right shift parameter to generate the shifted operand; the first intermediate operand generation submodule 11c is connected to both the shift submodule 11b and the decoding module 10 and is used to generate the first intermediate operand based on the shifted operand, the sign of the operand to be converted, and the type of the target operand.

[0029] The shift constant can be determined by the decoding module 10 based on the types of the operand to be converted and the target operand. The right shift parameter is calculated by adding the shift constant and the biased exponent of the operand to be converted. When the operand to be converted is a double-precision floating-point number, the right shift parameter ranges from 0 to 64 bits; when the operand to be converted is a single-precision floating-point number, the right shift parameter ranges from 0 to 32 bits. An overflow or underflow may be triggered if the unbiased exponent of the operand to be converted exceeds the range of the right shift parameter. For example, for the PS2PH microinstruction, when the biased exponent of the operand to be converted is 8'h65, its unbiased exponent is -26, resulting in a calculated right shift parameter of 33, which exceeds the range of the right shift parameter. Simultaneously, the calculated overflow parameter is less than 0, meaning the result is a denormalized number, thus triggering an underflow.

[0030] Since right shift does not involve operations on the sign bit, the first intermediate operand, which includes the sign bit information, needs to be obtained based on the microinstruction type, the sign bit, and the integer result after the shift. For example, for the PS2PH microinstruction, when the operand to be converted has an bias exponent of 8'h67 and a sign bit of 1'b1, the integer result after right shifting the mantissa by 31 bits is 16'h0001, and the shift result including the sign bit information is 16'h8001.

[0031] When right-shifting the mantissa of the operand to be converted, a single-level shift or a multi-level shift can be performed. In some examples, the shift submodule 11b may include a first-level shift unit 11b1 and a second-level shift unit 11b2. The first-level shift unit 11b1 is connected to the right shift parameter determination submodule 11a and the decoding module 10, respectively, and is used to generate the first shifted operand based on the first right shift parameter and the mantissa of the operand to be converted. The first right shift parameter is less than the right shift parameter. The second-level shift unit 11b2 is connected to the first-level shift unit 11b1, the right shift parameter determination submodule 11a, and the first intermediate operand generation submodule 11c, respectively, and is used to generate the second shifted operand based on the second right shift parameter and the first shifted operand. The sum of the first right shift parameter and the second right shift parameter is equal to the right shift parameter.

[0032] In this embodiment, a two-stage shift is performed based on the right shift parameter, where the sum of the first and second right shift parameters equals the total right shift parameter. In a specific example, the first-stage shift is a right shift of 0 to 15 bits, and the second-stage shift is a right shift of 0 / 16 / 32 / 48 / 64 bits. If a 31-bit shift is required, the second stage can be a 16-bit shift, and the first stage can be a 15-bit shift.

[0033] Assuming the process of determining the first intermediate operand when implementing SP to INT32 data precision conversion is as follows: (1) Perform a two-stage right shift on the mantissa of the operand to be converted according to the right shift parameter; (2) Modify the output of the second-stage right shifter according to the sign bit and the type of the destination operand. 1) When the target type is INT32, the lower 32 bits of the right shifter output are used as the first intermediate operand; when the target type is INT16, the lower 16 bits of the right shifter output are used as the first intermediate operand.

[0034] 2) If the sign bit is 1, the target operand is negative and needs to be represented in two's complement form. Therefore, the output of the right shifter needs to be inverted as the first intermediate operand. If the sign bit is 0, the target operand is positive and the output of the right shifter is used directly as the first intermediate operand.

[0035] In some examples, the decoding module 10 is also used to decode the micro-conversion instruction to obtain a data processing mode; the data processing mode includes a scalar mode or a vector mode; see also Figure 4The right shift parameter determination submodule 11a includes a first right shift parameter determination unit 11aa and a second right shift parameter determination unit 11ab; the shift submodule 11b includes a first shift unit 11ba and a second shift unit 11bb; the first right shift parameter determination unit 11aa is connected to the first shift unit 11ba; the second right shift parameter determination unit 11ab is connected to the second shift unit 11bb; wherein, the first right shift parameter determination unit 11aa includes a first selector and a first adder connected to the first selector; the first selector is connected to the decoding module 10; the first shift unit 11ba includes... The second selector and the first shifter connected to the second selector; wherein the second selector is connected to the decoding module 10, and the first shifter is connected to the first adder and the first intermediate operand generation submodule 11c respectively; the second right shift parameter determination unit 11ab includes a third selector and a second adder connected to the third selector; the third selector is connected to the decoding module 10; the second shift unit 11bb includes a third selector and a second shifter connected to the third selector; wherein the third selector is connected to the decoding module 10, and the second shifter is connected to the second adder and the first intermediate operand generation submodule 11c respectively.

[0036] When the operand to be converted is a double-precision floating-point number, the data processing mode is scalar mode. Specifically, the decoding module 10 extracts the sign, bias exponent, and mantissa of the operand to be converted based on the data processing mode and the operand's type. A first selector receives a first selection signal from the decoding module 10 based on the operand's type and selects the bias exponent of the operand to be converted as the output. A first adder adds the bias exponent and shift constant of the operand to be converted to obtain a first right shift parameter. A second selector receives the first selection signal and selects the mantissa of the operand to be converted as the output. A first shifter outputs the first operand based on the mantissa of the operand to be converted and the first right shift parameter. The third selector receives the first selection signal and selects the bias exponent of the operand to be converted as the output; the second adder adds the bias exponent and the shift constant of the operand to be converted to obtain the second right shift parameter; the fourth selector receives the first selection signal and selects the mantissa of the operand to be converted as the output; the second shifter outputs the second operand according to the mantissa of the operand to be converted and the second right shift parameter. The first intermediate operand generation submodule 11c generates the first intermediate operand based on the first operand, the second operand, the sign of the operand to be converted, and the type of the target operand.

[0037] The bias exponents of the operands to be transformed are used as inputs to the first and third selectors, respectively, to generate two identical sets of right shift parameters, i.e., the first right shift parameter and the second right shift parameter are equal. like Figure 5In the embodiment shown, the type of the operand to be converted is a double-precision floating-point number, while the input operand (the operand to be converted) is 64-bit, i.e., Src[63:0], which means that the input operand is one FP64 floating-point number.

[0038] like Figure 4 In the embodiment shown, Exp0 and Exp4 are both bias exponents of the operands to be converted, and Mant0 and Mant4 are both mantissas of the operands to be converted. The first right shift parameter determined by the first right shift parameter determination unit 11aa is input to the first right shift unit Right-Shifter0 to shift Mant0, and the second right shift parameter determined by the second right shift parameter determination unit 11ab is input to the second right shift unit Right-Shift4 to shift Mant4.

[0039] Bits 0-31 of the first intermediate operand correspond to the result after shifting the first right shift unit, and bits 32-63 of the first intermediate operand correspond to the result after shifting the first right shift unit.

[0040] When the type of the operand to be converted is a single-precision floating-point number, the data processing mode is vector mode. Specifically, the decoding module 10 decodes the operand to be converted according to the data processing mode and the type of the operand to be converted to obtain a first operand to be converted and a second operand to be converted, and extracts the sign, bias exponent, and mantissa of the first operand to be converted and the second operand to be converted respectively. The first selector receives a second selection signal sent by the decoding module 10 according to the type of the operand to be converted, and selects the bias exponent of the first operand to be converted as the output. The first adder determines a third right shift parameter based on the bias exponent and shift constant of the first operand to be converted. The second selector receives the second selection signal and selects the mantissa of the first operand to be converted as the output. The first shifter right-shifts the mantissa of the first operand to be converted according to the third right shift parameter to obtain the first operand. The third selector receives the second selection signal and selects the bias exponent of the second operand to be converted as the output; the second adder adds the bias exponent of the second operand to be converted and the shift constant to obtain the fourth right shift parameter; the fourth selector receives the second selection signal and selects the mantissa of the second operand to be converted as the output; the second right shifter shifts the mantissa of the second operand to be converted to the right according to the fourth right shift parameter to obtain the second operand; The first intermediate operand generation submodule 11c generates the first intermediate operand based on the first operand, the second operand, the sign of the first operand to be converted, the sign of the second operand to be converted, and the type of the target operand.

[0041] like Figure 5As shown, the type of the operand to be converted is single-precision floating-point number, while the input operand (the operand to be converted) is 64-bit, namely Src[63:0]. This means that the input operand consists of two FP32 floating-point numbers, one of which is Src[63:32] and the other is Src[31:0].

[0042] like Figure 4 In the illustrated embodiment, Exp0 is the bias exponent of the first operand to be converted, and Mant0 is the mantissa of the first operand to be converted. The first right shift parameter determined by the first right shift parameter determination unit 11aa is input to the first right shift unit Right-Shifter0 to shift Mant0. Exp4 is the bias exponent of the second operand to be converted, and Mant4 is the mantissa of the second operand to be converted. The second right shift parameter determined by the second right shift parameter determination unit 11ab is input to the second right shift unit Right-Shifter4 to shift Mant4.

[0043] Bits 0-31 of the first intermediate operand correspond to the result after shifting the first right shift unit, and bits 32-63 of the first intermediate operand correspond to the result after shifting the first right shift unit.

[0044] In some examples, the right shift parameter determination submodule 11a further includes a third right shift parameter determination unit 11ac and a fourth right shift parameter determination unit 11ad; the shift submodule 11b includes a third shift unit 11bc and a fourth shift unit 11bd; The third right shift parameter determination unit 11ac includes a fifth selector and a third adder connected to the fifth selector; the fifth selector is connected to the decoding module 10; the third shift unit 11bc includes a sixth selector and a third shifter connected to the sixth selector; the sixth selector is connected to the decoding module 10, and the third shifter is connected to the third adder and the first intermediate operand generation submodule 11c respectively. The fourth right shift parameter determination unit 11ad includes a seventh selector and a fourth adder connected to the seventh selector; the seventh selector is connected to the decoding module 10; the fourth shift unit 11bd includes an eighth selector and a fourth shifter connected to the eighth selector; wherein, the eighth selector is connected to the decoding module 10, and the fourth shifter is connected to the fourth adder and the first intermediate operand generation submodule 11c respectively. When the type of the operand to be converted is half-precision floating-point number, the data processing mode is vector mode. The decoding module 10 is specifically used to decode the operand to be converted according to the data processing mode and the type of the operand to be converted to obtain the first operand to be converted, the second operand to be converted, the third operand to be converted, and the fourth operand to be converted, and extract the sign, bias exponent, and mantissa of the first operand to be converted, the second operand to be converted, the third operand to be converted, and the fourth operand to be converted one by one. The first selector receives the third selection signal sent by the decoding module 10 according to the type of the operand to be converted, and selects the bias exponent of the first operand to be converted as the output; the first adder determines the fifth right shift parameter according to the bias exponent and shift constant of the first operand to be converted; the second selector receives the third selection signal and selects the mantissa of the first operand to be converted as the output; the first shifter right-shifts the mantissa of the first operand to be converted according to the fifth right shift parameter to obtain the first operand; The third selector receives the third selection signal and selects the bias exponent of the second operand to be converted as the output; the second adder adds the bias exponent of the second operand to be converted and the shift constant to obtain the sixth right shift parameter; the fourth selector receives the third selection signal and selects the mantissa of the second operand to be converted as the output; the second right shifter shifts the mantissa of the second operand to be converted to the right according to the sixth right shift parameter to obtain the second operand; The fifth selector receives the third selection signal and selects the bias exponent of the third operand to be converted as the output; the third adder adds the bias exponent of the third operand to be converted and the shift constant to obtain the seventh right shift parameter; the fourth selector receives the third selection signal and selects the mantissa of the third operand to be converted as the output; the third right shifter right shifts the mantissa of the third operand to be converted according to the seventh right shift parameter to obtain the third operand; The seventh selector receives the third selection signal and selects the bias exponent of the fourth operand to be converted as the output; the fourth adder adds the bias exponent of the fourth operand to be converted and the shift constant to obtain the eighth right shift parameter; the eighth selector receives the third selection signal and selects the mantissa of the fourth operand to be converted as the output; the fourth right shifter right shifts the mantissa of the fourth operand to be converted according to the eighth right shift parameter to obtain the fourth operand; The first intermediate operand generation submodule 11c generates the first intermediate operand based on the first operand, the second operand, the third operand, the fourth operand, the sign of the first operand, the sign of the second operand, the sign of the third operand, the sign of the fourth operand, and the type of the target operand.

[0045] like Figure 5In the illustrated embodiment, the input operands are half-precision floating-point numbers (16-bit wide), and the input operands (operands to be converted) have a bit width of 64 bits, namely Src[63:0]. This means that the input operands consist of four FP16 floating-point numbers, where Src[15:0] is the first operand to be converted, Src[31:16] is the second operand to be converted, Src[47:32] is the third operand to be converted, and Src[63:48] is the fourth operand to be converted.

[0046] like Figure 4 In the illustrated embodiment, Exp0 is the bias exponent of the first operand to be converted, and Mant0 is the mantissa of the first operand to be converted. The first right shift parameter determined by the first right shift parameter determination unit 11aa is input to the first right shift unit Right-Shifter0 to shift Mant0. Exp2 is the bias exponent of the second operand to be converted, and Mant2 is the mantissa of the second operand to be converted. The second right shift parameter determined by the second right shift parameter determination unit 11ab is input to the second right shift unit Right-Shifter2 to shift Mant2. Row shift; Exp4 is the bias exponent of the third operand to be converted, and Mant4 is the mantissa of the third operand to be converted. The third right shift parameter determined by the third right shift parameter determination unit 11ac is input to the third right shift unit Right-Shifter4 to shift Mant4; Exp6 is the bias exponent of the fourth operand to be converted, and Mant6 is the mantissa of the fourth operand to be converted. The fourth right shift parameter determined by the fourth right shift parameter determination unit 11ad is input to the fourth right shift unit Right-Shifter6 to shift Mant6.

[0047] Bits 0-15 of the first intermediate operand correspond to the result after shifting the first right shift unit; bits 16-31 of the first intermediate operand correspond to the result after shifting the second right shift unit; bits 32-47 of the first intermediate operand correspond to the result after shifting the third right shift unit; and bits 48-63 of the first intermediate operand correspond to the result after shifting the fourth right shift unit.

[0048] In some examples, the right shift parameter determination submodule 11a further includes a fifth right shift parameter determination unit 11ae, a sixth right shift parameter determination unit 11af, a seventh right shift parameter determination unit 11ag, and an eighth right shift parameter determination unit 11ah; the shift submodule 11b includes a fifth shift unit 11be, a sixth shift unit 11bf, a seventh shift unit 11bg, and an eighth shift unit 11bh; The fifth right shift parameter determination unit 11ae includes a fifth adder, which is connected to the decoder; the fifth shift unit 11be includes a fifth shifter, which is connected to the fifth adder and the first intermediate operand generation submodule 11c respectively. The sixth right shift parameter determination unit 11af includes a sixth adder, which is connected to the decoder; the sixth shift unit 11bf includes a sixth shifter, which is connected to the sixth adder and the first intermediate operand generation submodule 11c respectively. The seventh right shift parameter determination unit 11ag includes a seventh adder, which is connected to the decoder; the seventh shift unit 11bg includes a seventh shifter, which is connected to the seventh adder and the first intermediate operand generation submodule 11c respectively. The eighth right shift parameter determination unit 11ah includes an eighth adder, which is connected to the decoder; the eighth shift unit 11bh includes an eighth shifter, which is connected to the eighth adder and the first intermediate operand generation submodule 11c respectively. When the type of the operand to be converted is mixed floating-point 8, the data processing mode is vector mode. The decoding module 10 is specifically used to decode the operand to be converted according to the data processing mode and the type of the operand to be converted to obtain the first operand to be converted, the second operand to be converted, the third operand to be converted, the fourth operand to be converted, the fifth operand to be converted, the sixth operand to be converted, the seventh operand to be converted, and the eighth operand to be converted, and extract the sign, bias exponent and mantissa of the first operand to be converted, the second operand to be converted, the third operand to be converted, the fourth operand to be converted, the fifth operand to be converted, the sixth operand to be converted, the seventh operand to be converted, and the eighth operand to be converted, respectively. The first selector receives the fourth selection signal sent by the decoding module 10 according to the type of the operand to be converted, and selects the bias exponent of the first operand to be converted as the output; the first adder determines the ninth right shift parameter according to the bias exponent and shift constant of the first operand to be converted; the second selector receives the fourth selection signal and selects the mantissa of the first operand to be converted as the output; the first shifter right-shifts the mantissa of the first operand to be converted according to the ninth right shift parameter to obtain the first operand; The third selector receives the fourth selection signal and selects the bias exponent of the second operand to be converted as the output; the second adder adds the bias exponent of the second operand to be converted and the shift constant to obtain the tenth right shift parameter; the fourth selector receives the fourth selection signal and selects the mantissa of the second operand to be converted as the output; the second right shifter shifts the mantissa of the second operand to be converted to the right according to the tenth right shift parameter to obtain the second operand; The fifth selector receives the fourth selection signal and selects the bias exponent of the third operand to be converted as the output; the third adder adds the bias exponent of the third operand to be converted and the shift constant to obtain the eleventh right shift parameter; the fourth selector receives the fourth selection signal and selects the mantissa of the third operand to be converted as the output; the third right shifter shifts the mantissa of the third operand to be converted to the right according to the eleventh right shift parameter to obtain the third operand; The seventh selector receives the fourth selection signal and selects the bias exponent of the fourth operand to be converted as the output; the fourth adder adds the bias exponent of the fourth operand to be converted and the shift constant to obtain the twelfth right shift parameter; the eighth selector receives the fourth selection signal and selects the mantissa of the fourth operand to be converted as the output; the fourth right shifter shifts the mantissa of the fourth operand to be converted to the right according to the twelfth right shift parameter to obtain the fourth operand; The fifth adder adds the bias exponent and shift constant of the fifth operand to be converted to obtain the thirteenth right shift parameter; the fifth right shifter shifts the mantissa of the fifth operand to the right according to the thirteenth right shift parameter to obtain the fifth operand. The sixth adder adds the bias exponent and shift constant of the sixth operand to be converted to obtain the fourteenth right shift parameter; the sixth right shifter shifts the mantissa of the sixth operand to be converted to the right according to the fourteenth right shift parameter to obtain the sixth operand. The seventh adder adds the bias exponent and shift constant of the seventh operand to be converted to obtain the fifteenth right shift parameter; the seventh right shifter shifts the mantissa of the seventh operand to the right according to the fifteenth right shift parameter to obtain the seventh operand. The eighth adder adds the bias exponent and shift constant of the eighth operand to be converted to obtain the sixteenth right shift parameter; the eighth right shifter shifts the mantissa of the eighth operand to the right according to the sixteenth right shift parameter to obtain the eighth operand. The first intermediate operand generation submodule 11c generates the first intermediate operand based on the first operand, the second operand, the third operand, the fourth operand, the fifth operand, the sixth operand, the seventh operand, the eighth operand, the sign of the first operand, the sign of the second operand, the sign of the third operand, the sign of the fourth operand, the sign of the fifth operand, the sign of the sixth operand, the sign of the seventh operand, the sign of the eighth operand, and the type of the target operand.

[0049] like Figure 5In the illustrated embodiment, the input operands are mixed 8-bit floating-point numbers (HF8, with a bit width of 8 bits), and the bit width of the input operands (operands to be converted) is 64 bits, i.e., Src[63:0]. This means that the input operands consist of 8 HF8 floating-point numbers, where Src[7:0] is the first operand to be converted, Src[8:15] is the second operand to be converted, Src[16:23] is the third operand to be converted, Src[24:31] is the fourth operand to be converted, Src[32:39] is the fifth operand to be converted, Src[40:47] is the sixth operand to be converted, Src[48:55] is the seventh operand to be converted, and Src[56:63] is the eighth operand to be converted.

[0050] like Figure 4In the illustrated embodiment, Exp0 is the bias exponent of the first operand to be converted, and Mant0 is the mantissa of the first operand to be converted. The first right shift parameter determined by the first right shift parameter determination unit 11aa is input to the first right shift unit Right-Shifter0 to shift Mant0. Exp1 is the bias exponent of the second operand to be converted, and Mant1 is the mantissa of the second operand to be converted. The second right shift parameter determined by the second right shift parameter determination unit 11ab is input to the second right shift unit Right-Shifter1 to shift Mant0. 1. Perform a shift operation; Exp2 is the bias exponent of the third operand to be converted, Mant2 is the mantissa of the third operand to be converted, and the third right shift parameter determined by the third right shift parameter determination unit 11ac is input to the third right shift unit Right-Shifter2 to shift Mant2; Exp3 is the bias exponent of the fourth operand to be converted, Mant3 is the mantissa of the fourth operand to be converted, and the fourth right shift parameter determined by the fourth right shift parameter determination unit 11ad is input to the fourth right shift unit Right-Shifter3 to shift Mant3. Row shift; Exp4 is the bias exponent of the fifth operand to be converted, Mant4 is the mantissa of the fifth operand to be converted, and the fifth right shift parameter determined by the fifth right shift parameter determination unit 11ae is input to the fifth right shift unit Right-Shifter4 to shift Mant4; Exp5 is the bias exponent of the sixth operand to be converted, Mant5 is the mantissa of the sixth operand to be converted, and the sixth right shift parameter determined by the sixth right shift parameter determination unit 11af is input to the sixth right shift unit Right-Shifter5 to shift Mant5. Bit; Exp6 is the bias exponent of the seventh operand to be converted, Mant6 is the mantissa of the seventh operand to be converted, and the seventh right shift parameter determined by the seventh right shift parameter determination unit 11ag is input to the seventh right shift unit Right-Shifter6 to shift Mant6; Exp7 is the bias exponent of the eighth operand to be converted, Mant7 is the mantissa of the eighth operand to be converted, and the eighth right shift parameter determined by the eighth right shift parameter determination unit 11ah is input to the eighth right shift unit Right-Shifter7 to shift Mant7.

[0051] In some examples, the data type converter 1 may further include a second intermediate operand generation module 14, which is connected to the decoding module 10, the overflow parameter determination submodule 12a, and the target operand determination module 13, respectively. The second intermediate operand is generated based on the sign of the operand to be converted, the mantissa of the operand to be converted, and the overflow parameter. Specifically, the target operand determination module 13 is used to select a target intermediate operand from the first intermediate operand and the second intermediate operand based on the microinstruction type and the overflow flag, and to determine the target operand based on the target intermediate operand.

[0052] For microinstructions that convert from a floating-point number (high mantissa width) to a floating-point number (low mantissa width), when the operand to be converted is a normalized number, the exponent range of the target operand is determined based on the overflow parameter. When the target operand is also a normalized number, a right shift is not required; the mantissa of the operand to be converted can be directly truncated, and a fixed shift result containing the sign bit information can be obtained based on the sign bit and the overflow parameter.

[0053] For the conversion between floating-point numbers (high mantissa width) and floating-point numbers (low mantissa width), assuming the conversion from SP to HF16 precision is implemented: (1) The bias exponent of the operand to be transformed, Src.Exp = Src.e + SP.Bias (2) Overflow constant const2 = HF16.Bias - SP.Bias (3) Overflow parameter NormExp = Overflow constant + Bias exponent = Src.e + HF16.Bias 1) If there is no overflow, the overflow parameter is actually the bias exponent of the second intermediate operand: Dest.Exp = Src.e + HF16.Bias 2) If the operand to be converted is represented by SP as Src[31:0], then the second intermediate operand is represented by HF16 as {Src

[31] , Dest.Exp[4:0], Src[22:13]}. That is, the second intermediate operand is generated according to the sign of the operand to be converted, the mantissa of the operand to be converted, and the overflow parameter.

[0054] 3) When the biased exponent Src.Exp of the operand to be converted Src[31:0] is greater than SP.Bias – HF16.Bias, i.e. Src.Exp>8'h71, it can be determined that the result is a normalized number. Therefore, the second intermediate operand is selected as the target operand.

[0055] In some examples, a third intermediate operand generation module 15 may also be included, which is connected to the decoding module 10 and the target operand determination module 13 respectively, and is used to generate a third intermediate operand according to a preset rounding mode, the type of the operand to be converted and the type of the target operand; wherein, the first selection submodule of the target operand determination module 13 is specifically used to select the target intermediate operand from the first intermediate operand, the second intermediate operand and the third intermediate operand according to the microinstruction type and the overflow flag.

[0056] For microinstructions that convert floating-point numbers (high mantissa width) to floating-point numbers (low mantissa width) or floating-point numbers to fixed-point numbers, overflow may occur when the operand to be converted is large enough, exceeding the maximum normalized value that the target operand can represent; conversely, underflow may occur when the input operand is small enough, falling below the minimum normalized value that the target format can represent. In these scenarios, a special result (i.e., a third intermediate operand) needs to be generated, controlled by the rounding mode. The rules for generating the third intermediate operand are as follows: (1) When the target operand is of type INT or UINT, the third intermediate operand is set to a special integer value; (2) When the target operand is of type FP, the rounding mode (RNE = round to nearest, RPI = round to +infinity, RNI = round to -infinity, RTZ = round to zero) and the sign of the operand to be converted need to be considered: 1) RNE: The third intermediate operation value is + / -infinity.

[0057] 2) When RPI is applied and the sign of the operand to be converted is 0: the value of the third intermediate operand is +infinity.

[0058] 3) When RNI is used and the sign of the operand to be converted is 1: the value of the third intermediate operand is -infinity.

[0059] 4) Other modes: The third intermediate operand value is the maximum positive normalized number or the minimum negative normalized number that the target operand type can represent.

[0060] In some examples, the shift submodule 11b is also used to determine a first protection value on the protection bit and a first sticky value on the sticky bit corresponding to the first intermediate operand during the process of shifting the mantissa of the operand to be converted; The second intermediate operand generation module 14 is also used to determine the second protection value on the protection bit and the second stickiness value on the stickiness bit corresponding to the second intermediate operand based on the sign of the operand to be converted, the mantissa of the operand to be converted, and the overflow parameter. The data type converter 1 may further include a carry information determination module 16, which is used to determine carry information based on a preset rounding mode, the sign of the operand to be converted, a first protection value, a first sticky value, a second protection value, and a second sticky value. The target operand determination submodule of the target operand determination module 13 is used to determine the target operand based on the target intermediate operand and carry information.

[0061] During the generation of the first intermediate operand, the guard bit (G) and the sticky bit (S) can be determined. Specifically, during floating-point arithmetic, the mantissa part requires additional bits: the guard bit and the sticky bit. The guard bit is the first additional bit to the right of the least significant bit (LSB). It is the highest bit that is shifted out of the mantissa region but retained during the right shift. The sticky bit is the result of the logical OR operation of all bits to the right of the guard bit. As long as there is a '1' among these bits, the sticky bit is set to '1'. Its function is to record whether there are any non-zero bits on the right, preventing the "half" (0.5) from being mistakenly judged as an "integer" in the "round to even" rounding mode.

[0062] During the generation of the second intermediate operand, corresponding protection bits and sticky bits will also be generated.

[0063] Carry information is determined by carry mode, sign bit, guard bit G, and sticky bit S.

[0064]

[0065] The technical solution of this application will be described below with a specific embodiment. This embodiment can realize the conversion between floating-point numbers and fixed-point numbers (such as SP→INT32 / 64, HF16→INT16 / 32 / 64, etc.) and between high-mantissa-width floating-point numbers and low-mantissa-width floating-point numbers (DP→SP, SP→HF, etc.).

[0066] Figure 3 A schematic diagram of SP→INT / HF conversion is provided. For example, suppose we are performing a data precision conversion from SP to INT32. The input operands are Src[31:0] = 32'h3F800001, with a sign bit Src.Sign = 1'b0, an exponent bias Src.Exp[7:0] = 8'h7F, and a mantissa Src.Mant[22:0] = 23'h000001. The rounding mode is set to RPI.

[0067] 1. Calculate the right shift parameter RShiftNum[6:0] = 7'h1F based on Src.Exp and the shift constant Const; 2. Construct the mantissa to be shifted, Mant0[47:0] = {15'b0, 1'b1, Src.Mant[22:0], 8'b0, 1'b0}, based on Src.Mant; 3. First-level right shift process: The right shift parameter RShiftNum[3:0] = 4'hF, that is, shifting right by 15 bits to obtain the shifted integer, guard bit and sticky bit. The shifted integer RShiftL1[31:0] = {15'b0, 1'b1, Src.Mant[22:7]}, the guard bit g1 = Src.Mant[6], and the sticky bit s1 = |Src.Mant[5:0], the symbol "|" represents the bitwise OR operation; 4. Second-level right shift process: The right shift parameter RShiftNum[6:4] = 3'h1, that is, shifting right by 16-bit to obtain the shifted integer, guard bit and sticky bit. The shifted integer RShiftL2[31:0] = {16'b0, 15'b1, 1'b1} = 32'h1, the guard bit g2 = Src.Mant

[22] , and the sticky bit s2 = |Src.Mant[21:7]; 5. Based on the rounding mode RPI, combined with the guard bits and sticky bits from the two shifts, the final guard bit G = g2 and the sticky bit S = (s2 | g1 | s1) are obtained. Therefore, the carry information round_bit = ~Sign&(G | S) = 1'b1. 6. Based on the overflow / underflow flag and the microinstruction type, select the first intermediate operand as the intermediate value of the target operand.

[0068] In this example, the input operand Src[31:0] = 32'h3F800001 does not exceed the range of INT32 representation, there is no overflow / underflow scenario, and the microinstruction type is SP→INT32, so the first intermediate operand is selected for subsequent carry operations; 7. By carrying over, the final conversion result of F2I Path is obtained: F2IResult = RShiftL2[31:0] + round_bit = 32'h2.

[0069] Continue with Figure 3 For example, suppose we implement data precision conversion from SP to INT32. Given the operand type SP and the target operand type INT32 (corresponding to the microinstruction type SP→INT32), we set the overflow threshold to 2. SP.Bias+1 (8'hFF). As the previous analysis shows, the overflow parameter is 2. SP.Bias + (Src.e - 30) generates an overflow when the overflow parameter is greater than the overflow threshold. The overflow flag Overflow will be set to 1, and the third intermediate operand 15 will be used as the target operand.

[0070] (1) When Src.e = 30, the overflow parameter is 2. SP.Bias did not cause an overflow. Analyzing the right shift parameter, when Src.e = 30, the right shift parameter is 1, indicating that only the mantissa of the operand to be converted needs to be right-shifted by 1 bit. The right shifter output is 32'b01xxxx, which does not exceed the representation range of INT32, so the overflow flag Overflow = 0. At this point, the first intermediate operand is used as the target operand.

[0071] (2) When Src.e = 31, the overflow parameter = 2 Increasing SP.Bias by 1 causes an overflow. Analyzing the right shift parameter, when Src.e = 31, the right shift parameter is 0, indicating that there's no need to right-shift the mantissa of the operand to be converted. At this point, the right shifter output exceeds the INT32 representation range, resulting in an overflow. Therefore, the third intermediate operand needs to be used as the destination operand.

[0072] (3) When Src.e>31, the overflow parameter is always greater than 2. If SP.Bias+1 is used, an overflow will always occur, and the overflow flag Overflow = 1. In this case, the third intermediate operand needs to be used as the target operand.

[0073] Example 2 Figure 1 This is a schematic diagram of the structure of a data type converter 2 provided in an embodiment of this application, as shown below. Figure 1As shown, the data type converter 2 of this embodiment includes: a decoding module 10, a first intermediate operand generation module 21, an overflow flag determination module 22, and a target operand determination module 23; the first intermediate operand generation module 21 is connected to the decoding module 10; the overflow flag determination module 22 is connected to both the decoding module 10 and the first intermediate operand generation module 21; the target operand determination module 23 is connected to both the first intermediate operand generation module 21 and the overflow flag determination module; wherein, the decoding module 10 is used to receive micro-conversion instructions and decode the micro-conversion instructions to obtain the type of the operand to be converted, the type of the target operand, and the micro-instruction type; it is also used to receive the operand to be converted; the type of the operand to be converted is either a fixed-point number or a floating-point number, and the type of the target operand is a floating-point number; when the type of the operand to be converted is a floating-point number, the mantissa bit width of the operand to be converted is smaller than the mantissa bit width of the target operand; the first intermediate operand generation module 21 is used to extract the data type of the operand to be converted. The system selects the following parameters: valid data in the valid data bit field; left shift parameter determined according to the type of operand to be converted; first mantissa determined according to the left shift parameter and valid data; first bias exponent determined according to the type of operand to be converted, type of target operand, and bias exponent of operand to be converted, and second bias exponent determined according to the subtype of operand to be converted, and target bias exponent selected from the first and second bias exponents; wherein, when the operand to be converted is a fixed-point number, the bias exponent of the operand to be converted is 0; concatenating the sign of the operand to be converted, target bias exponent, and first mantissa according to the type of target operand to obtain the concatenated operand, and determining the first intermediate operand according to the concatenated operand; overflow flag determination module 22 is used to determine the overflow flag according to the type of operand to be converted, type of target operand, first mantissa, and target bias exponent; target operand determination module 23 is used to determine whether to use the first intermediate operand as the target operand according to the microinstruction type and overflow flag.

[0074] The data type converter in this embodiment can convert fixed-point numbers to floating-point numbers, and can also convert floating-point numbers with low bit width to floating-point numbers with high mantissa width, that is, the mantissa width of the operand to be converted is smaller than the mantissa width of the target operand.

[0075] The microinstruction in this embodiment can be DQ2PS, indicating that the operand to be converted is of type INT32 and the target operand is of type FP32; it can also be UDQ2PS, indicating that the operand to be converted is of type UINT32 and the target operand is of type FP32; or it can be PH2PS, indicating that the operand to be converted is of type FP16 and the target operand is of type FP32.

[0076] When the operand to be converted is an integer type, the valid data in the valid data bit field is an integer with a full number of digits; when the operand to be converted is a floating-point type, the valid data in the valid data bit field is the mantissa data.

[0077] The rules for determining the left shift parameter are as follows: When the operand to be converted is a fixed-point number, the left shift parameter is determined by performing leading zero detection on the valid data using the leading zero detection technique; when the operand to be converted is a floating-point number and is denormalized, the left shift parameter is determined by performing leading zero detection on the valid data using the leading zero detection technique; when the operand to be converted is a floating-point number and is normalized, a fixed left shift constant (the difference between the target operand bit width and the mantissa bit width of the operand to be converted) is used as the left shift parameter. Taking the PH2PS microinstruction as an example, when the operand to be converted is a normalized number, the mantissa of the operand to be converted is fixedly shifted left by 22 bits (the target operand bit width is 32 bits, the mantissa bit width of the operand to be converted is 10 bits, and the difference is 22 bits) to obtain the target operand mantissa.

[0078] The first mantissa can be obtained by left-shifting the valid data according to the left shift parameter. In one embodiment, the output of the shifter after performing two-stage left shifts on the valid data according to the left shift parameter is the first mantissa.

[0079] When converting data types from fixed-point numbers to floating-point numbers, or from floating-point numbers (low mantissa width) to floating-point numbers (high mantissa width), the type conversion from floating-point numbers to floating-point numbers will only occur in scenarios where normalized numbers are converted to normalized numbers or denormalized numbers are converted to normalized numbers. That is, the result is always a normalized number (not considering special types of operands to be converted).

[0080] In this embodiment, for converting a floating-point number to a floating-point number, the first bias exponent Dest.Exp = Src.Exp – Src.Bias + Dest.Bias + Const5 – LZN; for converting a fixed-point number to a floating-point number, the first bias exponent Dest.Exp = Dest.Bias + INT_WIDTH – LZN, where Src.Exp is the bias exponent of the operand to be converted, Src.Bias is the bias exponent threshold corresponding to the type of the operand to be converted, Dest.Bias is the bias exponent threshold corresponding to the type of the target operand, Const5 is a fixed left shift constant, LZN is the number of leading zeros, and INT_WIDTH is the bit width of the fixed-point number. See also Figure 1For example, in the conversion from floating-point to floating-point, if the operand to be converted is a normalized number, the first bias exponent has a fixed left shift parameter. In this case, the number of leading numbers LZN is equal to the fixed left shift constant Const5. If the operand to be converted is a denormalized number, then LZN is greater than Const5, and the left shift parameter is LZN. The calculation of the bias exponent needs to take into account the difference between LZN and Const5. For the conversion from fixed-point to floating-point, the calculation of the bias exponent needs to take into account the effective bit width of the fixed-point number.

[0081] The subtypes of the operands to be converted can include normal types and special types, where special types include infinity (INF) and NaN (Not a Number, invalid or undefined data). For normal types: the first bias exponent is selected as the target bias exponent; for special types such as NAN or INF: the special type result exponent (NAN or INF, i.e., the second bias exponent) is selected as the target bias exponent.

[0082] When the operand to be converted is a special type such as NAN or INF, the normal left shift operation will also be performed in this embodiment, but the calculation of its exponent will be biased. Since the final result is also NAN or INF, the second bias exponent needs to be selected as the target bias exponent.

[0083] Taking the fixed-point to floating-point data microinstruction as an example, when the target operand is of FP16 / FP8 / BF8 data type, and when the second bias exponent obtained by the conversion of the operand exceeds the maximum range that the target operand exponent can represent, an overflow will be triggered, and the overflow flag Overflow = 1.

[0084] The technical features of the data type converter 2 in the above embodiments can be found in the relevant technical features in the foregoing embodiments, and will not be repeated here.

[0085] In this embodiment, the decoding module 10 receives a micro-conversion instruction and decodes it to obtain the type of the operand to be converted, the type of the target operand, and the micro-instruction type. It also receives the operand to be converted; the operand to be converted is either a fixed-point number or a floating-point number, and the target operand is a floating-point number. When the operand to be converted is a floating-point number, the mantissa bit width of the operand to be converted is smaller than the mantissa bit width of the target operand. The first intermediate operand generation module 21 extracts the valid data from the valid data bit field of the operand to be converted; determines a left shift parameter based on the type of the operand to be converted; determines a first mantissa based on the left shift parameter and the valid data; determines a first bias index based on the type of the operand to be converted, the type of the target operand, and the bias exponent of the operand to be converted; and determines a second bias index based on the subtype of the operand to be converted. Finally, it selects a target bias index from the first bias index and the second bias index. When the operand to be converted is a fixed-point number, the bias exponent of the operand to be converted is 0. Based on the type of the target operand, the sign, target bias exponent, and first mantissa of the operand to be converted are concatenated to obtain the concatenated operand. Based on the concatenated operand, the first intermediate operand is determined. The overflow flag determination module 22 determines the overflow flag based on the type of the operand to be converted, the type of the target operand, the first mantissa, and the target bias exponent. The target operand determination module 23 determines whether to use the first intermediate operand as the target operand based on the microinstruction type and the overflow flag. Through the data type converter 2, either a floating-point number or a fixed-point number can be converted to a floating-point number. The conversion between floating-point and fixed-point numbers can share the same data type converter 2, eliminating the need to design dedicated hardware modules for each data type conversion. This reduces the area occupied by the processor chip, lowers the production cost of the processor chip, and saves on processor chip area and power consumption.

[0086] In some examples, the first intermediate operand generation module 21 includes: a mantissa determination submodule 21a, connected to the decoding module 10, for extracting valid data from the valid data bit field of the operand to be converted; determining a left shift parameter according to the type of the operand to be converted; determining a first mantissa according to the left shift parameter and the valid data; an exponent determination submodule 21b, connected to the decoding module 10, for determining a first bias exponent according to the type of the operand to be converted, the type of the target operand, and the bias exponent of the operand to be converted, and determining a second bias exponent according to the subtype of the operand to be converted, and selecting a target bias exponent from the first bias exponent and the second bias exponent; and a concatenation submodule 21c, connected to the decoding module 10, the mantissa determination submodule 21a, and the exponent determination submodule 21b, for concatenating the sign of the operand to be converted, the target bias exponent, and the first mantissa according to the type of the target operand to obtain the first intermediate operand.

[0087] The overflow flag determination module 22 is connected to the mantissa determination submodule 21a and the exponent determination submodule 21b, respectively. The mantissa determination submodule 21a may include: a valid data extraction unit 21aa, connected to the decoding module 10, used to determine the valid data in the valid data bit field of the operand to be converted based on a masking constant and the operand to be converted; wherein the masking constant is determined according to the microinstruction type and is a set of consecutive binary sequences all 1s, used for AND operation with the operand to be converted; a left shift parameter determination unit 21ab, connected to the decoding module 10 and the valid data extraction unit 21aa, used to determine the left shift parameter based on whether the operand to be converted is a normalized number; and a mantissa determination unit 21ac, connected to the valid data extraction unit 21aa and the left shift parameter determination unit 21ab, used to shift the valid data according to the left shift parameter to obtain the shifted valid data, and determine the first mantissa based on the shifted valid data.

[0088] After performing a bitwise AND operation between the masking constant and the operand to be converted, the valid data in the valid data bit field of the operand to be converted can be extracted. When the operand to be converted is of integer type, the valid data in the valid data bit field is integer data with a full number of bits; when the operand to be converted is of floating-point type, the valid data in the valid data bit field is mantissa data.

[0089] In some examples, the mantissa determination submodule 21a includes a right shift flag determination 21ad, which is connected to the valid data extraction unit 21aa and is used to determine the right shift flag based on the valid data. The right shift flag indicates whether to shift right by 1 bit or not to perform a right shift operation. The mantissa determination unit 21ac includes: a left shift subunit 21ac1, which is connected to the valid data extraction unit 21aa and the left shift parameter determination unit 21ab, respectively, and is used to shift the valid data left according to the left shift parameter to obtain an initial mantissa; and a right shift subunit 21ac2, which is connected to the left shift subunit 21ac1 and the right shift flag determination 21ad, respectively, and is used to shift the initial mantissa right or not according to the right shift flag to obtain a first mantissa.

[0090] In a specific example, based on the left shift parameter, a two-stage shift can be performed to obtain the left shift result. The first-stage shift performs a left shift of 0 / 16 / 32 / 48 / 64 bits, and the second-stage shift performs a left shift of 0~15 bits.

[0091] For microinstructions that convert negative integers to floating-point numbers, the negative integers appear in two's complement form. When performing leading zero detection, there may be a scenario where the number is shifted 1 bit to the left, in which case an additional 1 bit right shift is required.

[0092] The shifted mantissa is obtained by right-shifting the initial mantissa by 1 bit, and then truncating it to get the mantissa without carry.

[0093] In the foregoing embodiments, the first intermediate operand is a result excluding carry information. To make the converted data more accurate, in some examples, the first intermediate operand generation module 21 may further include: a carry information determination submodule 21d, which is connected to the right shift subunit 21ac2 and the decoding module 10 respectively. It is used to obtain the protection value on the protection bit and the sticky value on the sticky bit corresponding to the first mantissa according to the type of the target operand, and generate carry information according to the protection value, the sticky value and the rounding mode. The first intermediate operand generation submodule 21e is connected to the carry information determination submodule 21d and the splicing submodule 21c, respectively, and is used to determine the final first intermediate operand based on the first intermediate operand and the carry information.

[0094] The first intermediate operand generation submodule 21e can be an adder to add the first intermediate operand and the carry information to obtain the final first intermediate operand.

[0095] To make the conversion results more accurate, in one example, the data type converter 2 may also include a second intermediate operand generation module 24, which is connected to the decoding module 10 and the target operand determination module 23 respectively. The second intermediate operand is determined according to the sign and rounding mode of the operand to be converted. The target operand determination module 23 is also used to select a target intermediate operand from the first intermediate operand and the second intermediate operand according to the microinstruction type and overflow flag, and use the target intermediate operand as the target operand.

[0096] In this embodiment, a second intermediate operand containing the sign is generated based on the rounding mode. Since the target operand type is always floating-point, the rounding mode and the sign of the operand to be converted need to be considered. 1) RNE: The second intermediate operation value is + / -infinity 2) When RPI is applied and the sign of the operand to be converted is 0: the value of the second intermediate operand is +infinity. 3) When RNI is called and the sign of the operand to be converted is 1: the value of the second intermediate operand is -infinity. 4) Other modes: The second intermediate operand value is the maximum positive normalization / minimum negative normalization number that the target operand type can represent.

[0097] The technical solution of this application will be described below with reference to a specific embodiment.

[0098] This embodiment can realize the conversion between fixed-point numbers and floating-point numbers (such as INT32 / 64→SP, INT16 / 32 / 64→HF16, etc.) and between low mantissa width floating-point numbers and high mantissa width floating-point numbers (SP→DP, HF→SP, etc.). Figure 6 A schematic diagram of INT32 to SP conversion is provided. For example, assuming an INT32 to SP data precision conversion is performed, the input operands Src[31:0] = 32'hFFFFFFFE = -2, represented in two's complement form, with the sign bit Src.Sign = 1'b1. The result's sign bit Dest.Sign = 1'b1. In FP32 floating-point format, this is represented as 32'hC0000000. The rounding mode is set to RPI.

[0099] 1. Perform an AND operation on the input data and the masking constant to obtain the leading zero detection input Mant0[31:0] and the number of bits to be left-shifted {1'b0, Mant0'[31:0]}, where Mant0'[31:0] = ~Mant0[31:0] + 1'b1 is the two's complement; 2. Perform leading zero detection on Mant0[31:0]. Since the sign bit of the input operand Src.Sign = 1'b1, use the one's complement ~Mant0[31:0] to perform leading zero detection, and get LZN[6:0] = 7'h1F; 3. In this example, if the original code is used for leading zero detection, the actual left shift parameter should be 7'h1E, while the actual left shift parameter is 7'h1F. Therefore, a 1-bit right shift is still required at the end. 4. First-level left shift process: The left shift parameter LShiftNum[6:4] = 3'h1, that is, shifting left by 16-bit to obtain the shifted result LShiftL1[32:0] = {Mant0[16:0], 16'b0}; 5. Second-level left shift process: The left shift parameter LShiftNum[3:0] = 4'hF, that is, shifting left by 15-bit to obtain the shifted result LShiftL2[32:0] = {Mant0[1:0], 16'b0, 15'b0}; 6. Third-level right shift process: Perform a 1-bit right shift to get RShiftL3[31:0] = {Mant0[1:0],16'b0, 14'b0}, extract RShiftL3[30:8] as the mantissa Dest.Mant[22:0], then the Guard bit g1 =RShiftL3[7] = 1'b0, and the Sticky bit s1 = |RShiftL3[6:0] = 1'b0; 7. Calculate the resulting index Dest.Exp[7:0] = 8'h80 according to the formula for calculating the first bias index mentioned above; 8. Based on the rounding mode, and combining the Guard and Sticky bits of the shift, the carry information round_bit = (g1 | s1)&RPI = 1'b0 is obtained; 9. Concatenate the result sign bit Dest.Sign, the result exponent Dest.Exp[7:0], and the result mantissa Dest.Mant[22:0] to obtain the first intermediate operand without carry; 10. Based on the overflow flag and the microinstruction type, select the correct result from the left shift result and the special result. In this example, the input operand Src[31:0] = 32'hFFFFFFFE does not exceed the FP32 representation range, and there is no overflow scenario. Therefore, the first intermediate operand is selected for subsequent carry operations. 11. Through carry operation, the final conversion result of I2F Path is obtained: I2FResult = 32'hC0000000.

[0100] This application also provides a data type converter, including: a first conversion branch and a second conversion branch, wherein the first conversion branch is the data type converter 1 of the aforementioned embodiment 1; the second conversion branch is the data type converter 2 of the aforementioned embodiment 2; wherein the decoding module 1 in the second conversion branch and the decoding module 1 of the first conversion branch are the same decoding module 1; further comprising: a branch selection module, connected to the decoding module 1, and connected to the first conversion branch through a first switch module, and connected to the second conversion branch through a second switch module, for determining branch selection information according to the microinstruction type, so that one of the first switch module and the second switch module is in a conducting state, and the other switch module is in a turning state.

[0101] The data type converter in this embodiment integrates a first conversion branch and a second conversion branch. It can select one of the conversion branches to perform data type conversion according to the actual situation. The first conversion branch and the second conversion branch can respectively realize the conversion of different data types. In this way, the production cost of the chip can be reduced. In addition, the area and power consumption of the processor chip can be saved.

[0102] To enable conversion of more data types, in some examples, the decoding module 1 is also used to decode the operand to be converted as a floating-point number, the target operand as a floating-point number, and the exponent width of the operand to be converted is the same as the exponent width of the target operand, while the mantissa width of the operand to be converted is smaller than the mantissa width of the target operand.

[0103] The data type converter in this embodiment may further include a third conversion branch 3, which is connected to the decoding module 1 and is connected to the branch selection module through a third switch module. It is used to receive the microinstruction type and the operand to be converted sent by the decoding module 1, and according to the microinstruction type, to add a specified number of zeros to the mantissa of the operand to be converted to obtain the target operand; wherein, the specified number of zeros is the difference between the mantissa width of the target operand and the mantissa width of the operand to be converted.

[0104] This embodiment can realize the conversion of BF8 to FP16 and BF16 to FP32 data formats. Among them, BF8 can be called an 8-bit floating-point number with a bit width of 8; BF16 can be called a 16-bit floating-point number with a bit width of 16; FP16 can be called a half-precision floating-point number with a bit width of 16; and FP32 can be called a single-precision floating-point number with a bit width of 32.

[0105] See also Figure 7In the illustrated embodiment, the exponent width of the data formats BF8 and FP16, and BF16 and FP32 is the same. During the data type conversion process, BF8 can be directly converted to FP16 by padding with 0 after the mantissa, and BF16 can be directly converted to FP32 by padding with 0 after the mantissa. At the same time, the conversion result is accurate and does not need to consider the influence of the rounding mode.

[0106] The data type converter in the above embodiments has the ability to convert the data precision of floating-point to floating-point and floating-point to fixed-point vector data with a width of 64, 32, 16 and 8 bits. It can be applied to scenarios involving mixed precision computing such as CPU, high-performance computing (HPC) and artificial intelligence (AI), and can be integrated into scalar computing units, vector computing units, matrix computing units and tensor computing units.

[0107] This application also provides a processor, the processor including a data type converter; wherein the data type converter is the data type converter in Embodiment 1, or the data type converter in Embodiment 1, or the data type converter in Embodiment 1.

[0108] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0109] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0110] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data type converter, characterized in that, include: The decoding module is used to receive micro-conversion instructions and decode the micro-conversion instructions to obtain the type of the operand to be converted, the type of the target operand, and the micro-instruction type; It is also used to receive operands to be converted and extract the sign, bias exponent and mantissa of the operands to be converted; the type of the operands to be converted is one of multiple precision floating-point numbers, and the type of the target operand is one of fixed-point number and floating-point number; when the type of the target operand is floating-point number, the mantissa bit width of the operands to be converted is greater than the mantissa bit width of the target operand. The first intermediate operand generation module, connected to the decoding module, is used to determine the right shift parameter based on the shift constant and the bias exponent of the operand to be converted; and to generate the first intermediate operand based on the right shift parameter, the mantissa of the operand to be converted, the sign of the operand to be converted, and the type of the target operand; wherein the shift constant is determined based on the type of the operand to be converted and the type of the target operand. An overflow flag determination module, connected to the decoding module, is used to determine an overflow flag based on the bias exponent of the operand to be converted and the type of the target operand. The target operand determination module is connected to the first intermediate operand generation module and the overflow flag determination module, respectively, and is used to determine whether to use the first intermediate operand as the target operand based on the microinstruction type and the overflow flag.

2. The data type converter according to claim 1, characterized in that, The first intermediate operand generation module includes a right shift parameter determination submodule, a shift submodule, and a first intermediate operand generation submodule; The right shift parameter determination submodule, connected to the decoding module, is used to determine the right shift parameter based on the shift constant and the bias exponent of the operand to be converted. The shift submodule is connected to the right shift parameter determination submodule and the decoding module respectively, and is used to right shift the mantissa of the operand to be converted according to the right shift parameter to generate the shifted operand; The first intermediate operand generation submodule is connected to the shift submodule and the decoding module, respectively, and is used to generate the first intermediate operand based on the shifted operand, the sign of the operand to be converted, and the type of the target operand.

3. The data type converter according to claim 2, characterized in that, The shift submodule includes a first-level shift unit and a second-level shift unit; The first-stage shift unit is connected to the right shift parameter determination submodule and the decoding module, respectively, and is used to generate the first shifted operand based on the first right shift parameter and the mantissa of the operand to be converted; the first right shift parameter is less than the right shift parameter. The second-level shift unit is connected to the first-level shift unit, the right shift parameter determination submodule, and the first intermediate operand generation submodule, respectively, and is used to generate a second shifted operand based on the second right shift parameter and the first shifted operand; the sum of the first right shift parameter and the second right shift parameter is equal to the right shift parameter.

4. The data type converter according to claim 2, characterized in that, The decoding module is also used to decode the micro-conversion instruction to obtain a data processing mode; the data processing mode includes a scalar mode or a vector mode. The right shift parameter determination submodule includes a first right shift parameter determination unit and a second right shift parameter determination unit; the shift submodule includes a first shift unit and a second shift unit; the first right shift parameter determination unit is connected to the first shift unit; the second right shift parameter determination unit is connected to the second shift unit; The first right shift parameter determination unit includes a first selector and a first adder connected to the first selector; the first selector is connected to the decoding module; the first shift unit includes a second selector and a first shifter connected to the second selector; wherein the second selector is connected to the decoding module, and the first shifter is connected to the first adder and the first intermediate operand generation submodule respectively. The second right shift parameter determination unit includes a third selector and a second adder connected to the third selector; the third selector is connected to the decoding module; the second shift unit includes a third selector and a second shifter connected to the third selector; wherein the third selector is connected to the decoding module, and the second shifter is connected to the second adder and the first intermediate operand generation submodule, respectively.

5. The data type converter according to claim 4, characterized in that, The right shift parameter determination submodule further includes a third right shift parameter determination unit and a fourth right shift parameter determination unit; the shift submodule includes a third shift unit and a fourth shift unit; The third right shift parameter determination unit includes a fifth selector and a third adder connected to the fifth selector; the fifth selector is connected to the decoding module; the third shift unit includes a sixth selector and a third shifter connected to the sixth selector; the sixth selector is connected to the decoding module, and the third shifter is connected to the third adder and the first intermediate operand generation submodule, respectively. The fourth right shift parameter determination unit includes a seventh selector and a fourth adder connected to the seventh selector; the seventh selector is connected to the decoding module; the fourth shift unit includes an eighth selector and a fourth shifter connected to the eighth selector; wherein the eighth selector is connected to the decoding module, and the fourth shifter is connected to the fourth adder and the first intermediate operand generation submodule, respectively.

6. The data type converter according to claim 5, characterized in that, The right shift parameter determination submodule further includes a fifth right shift parameter determination unit, a sixth right shift parameter determination unit, a seventh right shift parameter determination unit, and an eighth right shift parameter determination unit; the shift submodule includes a fifth shift unit, a sixth shift unit, a seventh shift unit, and an eighth shift unit; The fifth right shift parameter determination unit includes a fifth adder, which is connected to the decoder; the fifth shift unit includes a fifth shifter, which is connected to the fifth adder and the first intermediate operand generation submodule respectively. The sixth right shift parameter determination unit includes a sixth adder, which is connected to the decoder; the sixth shift unit includes a sixth shifter, which is connected to the sixth adder and the first intermediate operand generation submodule respectively. The seventh right shift parameter determination unit includes a seventh adder, which is connected to the decoder; the seventh shift unit includes a seventh shifter, which is connected to the seventh adder and the first intermediate operand generation submodule respectively. The eighth right shift parameter determination unit includes an eighth adder, which is connected to the decoder; the eighth shift unit includes an eighth shifter, which is connected to the eighth adder and the first intermediate operand generation submodule.

7. The data type converter according to claim 1, characterized in that, The overflow flag determination module includes an overflow parameter determination submodule and an overflow flag determination submodule. The overflow parameter determination submodule is connected to the decoding module and is used to determine the overflow parameter based on the bias exponent and overflow constant of the operand to be converted. The overflow flag determination submodule is connected to the overflow parameter determination submodule and is used to determine the overflow flag based on the overflow parameter and the type of the target operand.

8. The data type converter according to claim 7, characterized in that, It also includes a second intermediate operand generation module, which is connected to the decoding module, the overflow parameter determination submodule and the target operand determination module, respectively, and is used to generate a second intermediate operand based on the sign of the operand to be converted, the mantissa of the operand to be converted and the overflow parameter; Specifically, the target operand determination module is used to select a target intermediate operand from the first intermediate operand and the second intermediate operand according to the microinstruction type and the overflow flag, and determine the target operand according to the target intermediate operand.

9. The data type converter according to claim 8, characterized in that, It also includes a third intermediate operand generation module, which is connected to the decoding module and the target operand determination module, respectively, and is used to generate a third intermediate operand according to a preset rounding mode, the type of the operand to be converted and the type of the target operand; Specifically, the first selection submodule of the target operand determination module is used to select a target intermediate operand from the first intermediate operand, the second intermediate operand, and the third intermediate operand based on the microinstruction type and the overflow flag.

10. The data type converter according to claim 8, characterized in that, The shift submodule is also used to determine, during the process of shifting the mantissa of the operand to be converted, a first protection value on the protection bit and a first stickiness value on the stickiness bit corresponding to the first intermediate operand. The second intermediate operand generation module is further configured to determine, based on the sign of the operand to be converted, the mantissa of the operand to be converted, and the overflow parameter, a second protection value on the protection bit and a second stickiness value on the stickiness bit corresponding to the second intermediate operand; The data type converter further includes a carry information determination module, which is used to determine carry information based on a preset rounding mode, the sign of the operand to be converted, the first protection value, the first stickiness value, the second protection value, and the second stickiness value. The target operand determination submodule of the target operand determination module is used to determine the target operand based on the target intermediate operand and the carry information.

11. A data type converter, characterized in that, include: The decoding module is used to receive micro-conversion instructions and decode the micro-conversion instructions to obtain the type of the operand to be converted, the type of the target operand, and the micro-instruction type; It is also used to receive operands to be converted; the type of the operands to be converted is either a fixed-point number or a floating-point number, and the type of the target operand is a floating-point number; when the type of the operands to be converted is a floating-point number, the mantissa bit width of the operands to be converted is smaller than the mantissa bit width of the target operand; The first intermediate operand generation module, connected to the decoding module, is used to extract valid data from the valid data bit field of the operand to be converted; determine the left shift parameter according to the type of the operand to be converted; and determine the first mantissa according to the left shift parameter and the valid data. Based on the type of the operand to be converted, the type of the target operand, and the bias exponent of the operand to be converted, a first bias exponent is determined, and based on the subtype of the operand to be converted, a second bias exponent is determined. A target bias exponent is selected from the first bias exponent and the second bias exponent, wherein when the operand to be converted is a fixed-point number, the bias exponent of the operand to be converted is 0. Based on the type of the target operand, the sign of the operand to be converted, the target bias exponent, and the first mantissa are concatenated to obtain a concatenated operand, and based on the concatenated operand, a first intermediate operand is determined. An overflow flag determination module is connected to the decoding module and the first intermediate operand generation module, respectively, and is used to determine an overflow flag based on the type of the operand to be converted, the type of the target operand, the first mantissa, and the target bias exponent. The target operand determination module is connected to the first intermediate operand generation module and the overflow flag determination module, respectively, and is used to determine whether to use the first intermediate operand as the target operand based on the microinstruction type and the overflow flag.

12. The data type converter according to claim 11, characterized in that, The first intermediate operand generation module includes: The mantissa determination submodule, connected to the decoding module, is used to extract valid data from the valid data bit field of the operand to be converted; determine the left shift parameter according to the type of the operand to be converted; and determine the first mantissa according to the left shift parameter and the valid data. An index determination submodule, connected to the decoding module, is used to determine a first bias index based on the type of the operand to be converted, the type of the target operand, and the bias index of the operand to be converted, and to determine a second bias index based on the subtype of the operand to be converted, and to select a target bias index from the first bias index and the second bias index. The splicing submodule, connected to the decoding module, the mantissa determination submodule, and the exponent determination submodule, is used to splice the sign of the operand to be converted, the target bias exponent, and the first mantissa according to the type of the target operand to obtain the first intermediate operand.

13. The data type converter according to claim 12, characterized in that, The tail number determination submodule includes: A valid data extraction unit, connected to the decoding module, is used to determine the valid data in the valid data bit field of the operand to be converted based on a masking constant and the operand to be converted; wherein the masking constant is determined according to the microinstruction type; A left shift parameter determination unit, connected to the decoding module and the valid data extraction unit, is used to determine the left shift parameter according to the type of the operand to be converted; The mantissa determination unit is connected to the effective data extraction unit and the left shift parameter determination unit, respectively, and is used to shift the effective data according to the left shift parameter to obtain the shifted effective data, and determine the first mantissa according to the shifted effective data.

14. The data type converter according to claim 13, characterized in that, The mantissa determination submodule further includes a right shift flag determination unit, which is connected to the valid data extraction unit and is used to determine the right shift flag based on the valid data. The right shift flag is used to indicate a right shift by 1 bit or no right shift operation. The tail number determination unit includes: The left shift subunit is connected to the effective data extraction unit and the left shift parameter determination unit, respectively, and is used to shift the effective data to the left according to the left shift parameter to obtain the initial mantissa; A right shift subunit, which is connected to the left shift subunit and the right shift flag determination unit, is used to right-shift or not shift the initial mantissa according to the right shift flag to obtain the first mantissa.

15. The data type converter according to claim 12, characterized in that, The first intermediate operand generation module further includes: The carry information determination submodule is connected to the right shift subunit and the decoding module respectively. It is used to obtain the protection value on the protection bit and the sticky value on the sticky bit corresponding to the first mantissa of the first intermediate operand according to the type of the target operand, and generate carry information according to the protection value, the sticky value and the rounding mode. The first intermediate operand generation submodule is connected to the carry information determination submodule and the splicing submodule, respectively, and is used to determine the final first intermediate operand based on the first intermediate operand and the carry information.

16. The data type converter according to claim 15, characterized in that, The data type converter further includes a second intermediate operand generation module, which is connected to the decoding module and the target operand determination module, respectively, and is used to determine the second intermediate operand according to the sign and rounding mode of the operand to be converted; The target operand determination module is further configured to select a target intermediate operand from the first intermediate operand and the second intermediate operand based on the microinstruction type and the overflow flag, and use the target intermediate operand as the target operand.

17. A data type converter, characterized in that, include: The first conversion branch is the data type converter as described in any one of claims 1-10; The second conversion branch is the data type converter according to any one of claims 11-16; wherein the decoding module in the second conversion branch is the same decoding module as the decoding module in the first conversion branch. A branch selection module is connected to the decoding module and to the first conversion branch via a first switch module and to the second conversion branch via a second switch module. It is used to determine branch selection information according to the microinstruction type, so that one of the first switch module and the second switch module is in the on state and the other switch module is in the off state.

18. The data type converter according to claim 17, characterized in that, The decoding module is further configured to decode the operand to be converted as a floating-point number, the target operand as a floating-point number, and the exponent width of the operand to be converted is the same as the exponent width of the target operand, and the mantissa width of the operand to be converted is smaller than the mantissa width of the target operand. It also includes a third conversion branch, which is connected to the decoding module and is connected to the branch selection module through a third switch module. The third conversion branch is used to receive the microinstruction type and the operand to be converted sent by the decoding module, and according to the microinstruction type, to add a specified number of zeros to the mantissa of the operand to be converted to obtain the target operand; wherein, the specified number of zeros is the difference between the mantissa width of the target operand and the mantissa width of the operand to be converted.

19. A processor, characterized in that, The processor includes a data type converter; wherein the data type converter is any one of claims 1-10, 11-16, or 17-18.

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