A multi-branch predictor and prediction method based on a RISC-V processor

Abstract

The application belongs to the technical field of processor branch prediction, and specifically discloses a multi-branch predictor and a prediction method based on a RISC-V processor. The multi-branch predictor comprises two-stage branch prediction modules, the first-stage branch prediction module comprises an L0 BTB submodule and an L0 UBTB submodule, and the second-stage branch prediction module comprises an L1 BTB submodule, a COTTAGE submodule and an RAS return address stack submodule. The prediction method is predicted through the pipeline of the first-stage and second-stage branch prediction modules, is fully adapted to RISC-V instructions, the L0 UBTB submodule reduces frequent access to the second-stage module, and also reduces the frequent occurrence of incorrect instructions, the COTTAGE submodule integrates a TAGE predictor and an ITTAGE predictor to adapt to conditional branch jumps, indirect jumps and call / ret instructions, so that the execution efficiency of the processor front end is improved with lower power consumption on the basis of basically adapting to all RISC-V complex instructions.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of processor branch prediction, and particularly relates to a multi-branch predictor and a prediction method based on a RISC-V processor. BACKGROUND

[0002] An instruction set architecture (ISA) is an abstract model of a computer, a collection of instructions (assembly language) that a computer processor can execute, and defines the interface between hardware and software. It can be understood that the ISA is the basis for software developers to write programs, and is also the basis for hardware engineers to design and implement processors. Common ISAs include x86, ARM, and RISC-V.

[0003] In practical applications, compared with the current mature commercial architecture, the RISC-V instruction set architecture has the outstanding advantages of short architecture length, support for modular and configurable instruction subsets, strong expansibility, fewer instructions, simple hardware design and compiler implementation, and is favored by chip design personnel.

[0004] The working pipeline of a processor includes five stages: instruction fetching (for example, fetching a RISC-V instruction set architecture instruction sw), decoding (for example, converting sw into binary machine code), execution, memory access, and write back. Each stage is responsible for different hardware units, which can work in parallel, allowing multiple instructions to be executed in parallel. In theory, in the best case, one instruction can be completed in each clock cycle, greatly improving the throughput. Among them, the branch predictor is a key component of the RISC-V processor front end, directly affecting the instruction supply capability of the instruction fetching stage, and is used to predict the jump direction and target address of a branch instruction (for example: beq, jal, etc. in the RISC-V instruction set) before execution.

[0005] The patent application file with the patent application publication number CN118152012A mentions the following three major problems of the existing branch predictor in the background art:

[0006] 1. Most branch predictors can only predict one branch in one cycle, limiting the throughput of the pipeline.

[0007] 2. Multiple branch prediction requires more hardware resources and more complex control logic, which can lead to increased cost and power consumption.

[0008] 3. Predicting multiple branches in one cycle can reduce the accuracy of prediction, because the existing technology lacks an effective mechanism to handle the correlation and complexity of multiple branches at the same time.

[0009] The solution proposed in the patent application file with the publication number CN118152012A is as shown in Figure 1 As shown in the solution, by using the L0 BTB submodule, the L1 LBTB module and the L1 GBTB module to store different types of branch instructions, different prediction block sizes and branch instruction types can be better adapted. At the same time, the BHT direction prediction module can help to more accurately predict the jump direction of the branch instruction, and the RAS return address stack module can process call and return instructions, realize efficient branch prediction on the RISC-V processor, and improve the execution efficiency of the processor.

[0010] Although this way can improve the execution efficiency of the processor in terms of prediction speed compared with the previous branch processor, the above patent still has the following defects:

[0011] (1) L0 BTB needs to process both conditional and unconditional branches, and the 16 entries of L0 BTB need to store the tags of conditional branches and unconditional branches. The address of the unconditional branch (such as jal direct jump) may conflict with the address of the conditional branch, occupying the entry space, resulting in L0 BTB miss, forced to access the second level module, and further leading to more frequent access to the second level module, which also leads to increased power consumption of the processor;

[0012] (2) L1 GBTB only records the address of the unconditional branch, and does not target indirect jump. For some RISC-V instructions (such as RISC-V, which implements the jalr instruction before loading the high address through the lui / auipc instruction, then combining the offset for indirect jump), the prediction may fail due to complex address calculation, and the above disclosed technology cannot fully adapt to the complex indirect jump instruction combination in RISC-V;

[0013] (3) When the branch predictor makes a mistake in predicting the branch instruction, since the above patent application file does not set a correction module for the wrong instruction, the instructions that have entered the pipeline and are in the wrong prediction path need to be removed from the pipeline, and the instructions need to be taken from the correct address again. The power consumption of the processor is more wasted. The previous processor will lose about 1-2 cycles due to one-time prediction error. However, the current high-performance processor may lose more than ten cycles due to one-time error prediction. Therefore, the above patent technology affects the instruction execution efficiency of the processor in terms of correction of the wrong prediction result. SUMMARY

[0014] The purpose of the present application is to solve the problems in the background art, and to provide a multi-branch predictor and prediction method based on a RISC-V processor, which can improve the execution efficiency of the processor front end with lower power consumption on the basis of adapting to complex instructions such as indirect jump in RISC-V.

[0015] To solve the above technical problems, the technical scheme adopted by the present application is as follows:

[0016] In a first aspect, the present application provides a multi-branch predictor based on a RISC-V processor, configured in the front end of the RISC-V processor, comprising a first-level branch prediction module and a second-level branch prediction module;

[0017] The first-level branch prediction module comprises:

[0018] The L0 BTB submodule is configured with a storage table indexed by the exclusive OR result of the value of the branch history register and the low bits of the current program counter PC value corresponding to the current prediction block, and the matching condition of the branch instruction is determined according to the tag information in the table entry, so as to determine whether to trigger the second-level branch prediction module;

[0019] The L0 UBTB submodule is indexed by the current program counter PC value, and outputs the target address of the hit unconditional jump instruction; if the L0 UBTB submodule does not hit, the second-level branch prediction module is triggered;

[0020] The second-level branch prediction module comprises:

[0021] The L1 BTB submodule is indexed by the current program counter PC value, and outputs the target address of all jump instructions except indirect jump

[0022] The COTTAGE submodule is composed of a TAGE predictor and an ITTAGE predictor, and is indexed by the hash calculation of the current program counter PC value and the global history register value, the TAGE predictor outputs the jump direction of the conditional branch jump instruction, and the ITTAGE predictor outputs the target address of the indirect jump instruction;

[0023] The RAS return address stack submodule outputs the return address of the ret instruction, and the input is the next instruction address of the call instruction output by the L1 BTB submodule;

[0024] The output results of the L0 UBTB submodule, the L1 BTB submodule, the COTTAGE submodule, and the RAS return address stack submodule constitute the prediction result of the target address of the next prediction block corresponding to the current prediction block.

[0025] As a limitation, the TAGE predictor comprises one non-tagged component and n tagged components, the non-tagged component is configured with a basic prediction table, and each table entry contains a 2-bit saturation counter and a valid bit; the tagged component is configured with a standard index table, and each table entry contains a 13-bit branch instruction tag, a 3-bit saturation counter, a valid bit and a useful bit;

[0026] The ITTAGE predictor comprises a non-tagged component, n tagged components and an offset storage unit, the non-tagged component is configured with a base prediction table, each table entry containing a target address; the tagged component is configured with a standard index table, each table entry containing a 20-bit base address, a 13-bit branch instruction tag, a confidence bit and a useful bit; and the offset storage unit contains a 12-bit offset.

[0027] As a further limitation, the effective bit of the TAGE predictor is initially set to 1, and is set to 0 when a tag hit but a prediction error occurs, and is set to 1 when a prediction is correct.

[0028] As a further limitation, the table entry of the index storage table of the L0 BTB submodule comprises: a start address of a next prediction block, a branch jump state of a current prediction block, a conditional branch existence flag and a number of branch instructions.

[0029] As a further limitation, the L0 UBTB submodule comprises 16 table entries, each table entry containing a tag of an unconditional jump instruction and a 20-bit offset address.

[0030] When the L0 UBTB hits and the L0 BTB does not detect a conditional branch jump, the target address of the hit unconditional jump instruction is directly output as a next prediction block address.

[0031] When the L0 UBTB does not hit or the L0 BTB detects a conditional branch jump, a second-level branch prediction module is triggered.

[0032] As a further limitation, the RAS return address stack submodule has a depth of 16 and is a last-in first-out structure; when a call instruction is executed, the next instruction address is pushed into the stack; and when a ret instruction is executed, the top address of the stack is popped out as a return address.

[0033] In a second aspect, the present application provides a prediction method of a multi-branch predictor based on a RISC-V processor, applied to the multi-branch predictor based on a RISC-V processor as described in the first aspect above, the method comprising the following steps performed in sequence:

[0034] Step S1: obtaining a start address of a current prediction block, the prediction block being a plurality of consecutive instructions;

[0035] Step S2: judging the branch type of the prediction block by the first branch prediction module; specifically, the L0 BTB submodule indexes the match result by the index storage table and the XOR result, when the index match result is unconditional jump and hit by the L0 UBTB submodule, the target address of the hit unconditional jump instruction is outputted by the L0 UBTB submodule as the starting address of the next prediction block; when the match result is conditional branch jump, indirect jump, or the L0 UBTB submodule is not hit, step S3 is triggered;

[0036] Step S3: processing the branch instruction by the second branch prediction module; specifically, the L1 BTB submodule classifies the instruction in the current prediction block by the current program counter PC value; if it is an unconditional direct jump instruction, the target address of the unconditional direct jump instruction is outputted by the L1 BTB submodule as the starting address of the next prediction block; if it is a conditional branch jump instruction and an indirect jump instruction, the COTTAGE submodule is entered, which outputs the jump direction of the conditional branch jump instruction and the jump address in the L1 BTB as the starting address of the next prediction block; for the indirect jump instruction, the target address is outputted as the starting address of the next prediction block; if it is a call instruction, the RAS return address stack submodule is entered, which stacks the next instruction address of the call instruction until the ret instruction is received, and then outputs the return address as the starting address of the next prediction block.

[0037] As a limitation, the prediction block satisfies one of the following conditions: when there is no branch instruction, the next prediction block is taken as the prediction block of the current prediction block; when there are n branch instructions, the program counter PC value of the nth branch instruction is taken as the starting address of the next prediction block; when there is an unconditional jump instruction, the program counter PC value of the next branch instruction is taken as the starting address of the next prediction block.

[0038] As a further limitation, the pre-training process of the L0 BTB submodule includes: marking the branch jump state corresponding to the conditional branch of the long-term jump in the table entry as unconditional jump, and restoring the mark to conditional branch jump after the first prediction error.

[0039] The present application has the following technical progress compared with the prior art:

[0040] (1) The application provides a multi-branch predictor based on a RISC-V processor, wherein the L0 BTB submodule is arranged in the first-level branch prediction module, and the L0 UBTB submodule is also arranged, so that unconditional jump instructions and conditional jump instructions can be stored and predicted separately, the target address can be directly output when the unconditional jump instruction hits the L0 UBTB, the access frequency of the second-level branch prediction module is reduced, the power consumption is reduced, the prediction speed is improved, the address conflict caused by the fact that the L0 BTB stores two types of branch instructions simultaneously in the prior art is avoided, and the problem that the table item space is squeezed and the power consumption is increased is solved. The COTTAGE submodule in the second branch module is composed of a TAGE predictor and an ITTAGE predictor, can predict the conditional branch and indirect jump instructions in RISC-V through a global history register and a base address tag mechanism, integrates the two predictors to improve the utilization rate, and adapts to the complex indirect jump mode related to the jalr instruction in RISC-V. The RAS return address stack submodule is further arranged in the application, can specially process the call and ret instructions, guarantees the target address prediction of function calling and returning, can basically adapt to the RISC-V instruction set, and improves the processing efficiency of predicting multiple branch instructions.

[0041] (2) The TAGE predictor of the application adopts a non-tagged component and a plurality of tagged components, wherein the non-tagged component is equivalent to storing basic prediction information, and the tagged component is equivalent to storing standard prediction information, and is mainly used for long-term tracking of the prediction result of the conditional branch, thereby optimizing the table item of the standard prediction information and improving the accuracy of branch prediction. The ITTAGE predictor of the application adopts a non-tagged component, a tagged component and an offset storage unit, optimizes the prediction result of the indirect jump instruction in the standard prediction information, wherein only the high 20 bits of the jump target are saved in all components, the jalr and lui or auipc instructions are used simultaneously in the program for long-distance subroutine calling, and the absolute address of 32 bits is jumped to. The offset of the jalr instruction is fixed, and an additional offset storage unit is used for storage, and the jump target is composed of the predicted base address and the offset, so that the area of the ITTAGE predictor is greatly reduced.

[0042] (3) The application adds a valid bit in the TAGE predictor component table entry, and the initial value of the valid bit of the newly allocated table entry is 1, if the prediction result is not consistent, the valid bit is 0, and the number of valid bits 0 is greater than or equal to 1 / 2, then the prediction result is reversed, which is equivalent to correcting the error prediction result. The application adds a valid bit in the table entry instead of correcting the error prediction result, can dynamically handle branches that have not strong correlation with historical paths, and does not need to be additionally set like the statistical corrector SC in the prior art, the application only adds a valid bit in the table entry, and the occupation of storage resources is lower than that of the SC, and the application is more suitable for low-power and low-area processors.

[0043] (4) The index storage table of the L0 BTB contains current prediction block branch jump state, condition branch flag and other information, compared with the background technology which simply stores target addresses, the application can provide various prediction information and improve the accuracy of prediction.

[0044] (5) The L0 UBTB of the application only stores unconditional jump instructions and is separated from the L0 BTB, avoiding the table entry conflict caused by the L0 BTB needing to simultaneously process conditional and unconditional branches in the background technology, thereby improving the hit rate of the first-level branch prediction module, reducing the number of accessing the second-level branch prediction module, and reducing power consumption.

[0045] (6) The RAS return address stack submodule of the application adopts a last-in first-out (LIFO) structure, ensures that the address of the next instruction before the function call is predicted and executed in order after the order execution of the instructions in the function is completed, and mainly ensures the accuracy of the return address.

[0046] (7) The application provides a prediction method of a multi-branch predictor based on a RISC-V processor, which is applied to the multi-branch predictor based on the RISC-V processor, and the method can predict a plurality of instructions at a time by acquiring a prediction block, thereby improving the processing efficiency of the processor and solving the limitation problem that only one branch can be predicted in one cycle in the background art. The first-level module L0 UBTB submodule independently stores unconditional jump instructions in the hierarchical prediction, reduces the storage conflict of the L0 BTB, improves the hit rate of the L0 BTB, thereby reducing the access to the second-level branch prediction module and reducing the power consumption. The COTTAGE submodule in the second-level branch prediction module adopts the combination of the TAGE and ITTAGE, can not only predict conditional branches but also effectively predict the target addresses of indirect jump instructions, is more suitable for the complex indirect jump instruction combination of the RISC-V compared with the background art which only records the unconditional branch address, can basically adapt to the RISC-V instruction set, and improves the processing efficiency of predicting a plurality of branch instructions.

[0047] (8) When there is no branch instruction, the next prediction block is directly added as the prediction block of the current prediction block, unnecessary prediction calculation is avoided; when there are n branch instructions, the program counter PC value of the nth branch instruction (that is, the last branch instruction) is selected as the starting address of the next prediction block, and when there is an unconditional jump instruction, the program counter PC value of the next branch instruction is selected as the starting address of the next prediction block, and the execution order of the subsequent instructions is ensured to be continuous in the two cases.

[0048] (9) The application sets a pre-training mechanism in the L0 BTB submodule, for a long-term jump conditional branch, the branch jump state is marked as an unconditional jump until the first prediction error is restored to a conditional branch jump. Compared with the background art which processes the conditional branch every time, the application can reduce the branch prediction error of the long-term stable jump and improve the accuracy of the prediction result.

[0049] In summary, the application provides a multi-branch predictor and a prediction method based on a RISC-V processor, the L0 UBTB independently stores unconditional jump instructions, reduces the table conflict and improves the hit rate, thereby reducing the frequency of accessing the second-level branch prediction module and reducing the power consumption, the COTTAGE submodule integrates the TAGE and ITTAGE predictors, combines the global history and base address to effectively process the conditional branch and indirect jump instruction of the RISC-V, the effective bit and pre-training are added to the predictor table to improve the prediction accuracy, and the first-in-first-out structure of the RAS ensures the correct function call return, thereby improving the execution efficiency of the processor front end on the basis of low power consumption.

[0050] The present invention is suitable for instruction branch prediction of a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0052] In the attached figure:

[0053] Figure 1 This is an overall structural diagram of a multi-branch predictor based on a RISC-V processor in the prior art of the present invention;

[0054] Figure 2 This is an overall structural diagram of a multi-branch predictor in Example 1 of the present invention;

[0055] Figure 3 1 is a structural diagram of the TAGE predictor of Example 1 of the present invention;

[0056] Figure 4 1 is a structural diagram of the TAGE predictor of Example 1 of the present invention;

[0057] Figure 5 This is a flow chart of a multi-branch predictor method based on a RISC-V processor in Example 2 of the present invention;

[0058] Figure 6 This is a processing flow chart of the first-level branch prediction module in Example 2 of the present invention;

[0059] Figure 7 FIG. 4 is a processing flow chart of the second-level branch prediction module in Example 2 of the present invention. DETAILED DESCRIPTION

[0060] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0061] It's important to note that in the RISC-V architecture, the way instruction addresses are incremented is directly related to the instruction length. RISC-V uses 32-bit fixed-length instructions (the base instruction set, RV32I), with each instruction occupying 4 bytes (32 bits). The current program counter (PC) value is used to record the address of the current instruction (that is, regardless of the type of instruction, as long as it is the currently executing instruction, the current program counter (PC) value will be updated accordingly). When instructions are executed sequentially, the address of the next instruction is equal to the current instruction address + 4 bytes.

[0062] The classification and examples of RISC-V branch instructions are as follows:

[0063] (1) Unconditional direct jump instruction: jal x1, 0x12345;

[0064] (2) Conditional branch jump instruction: beq x1, x2, 0x12345;

[0065] (3) Indirect jump instruction (two instructions combined): lui x5, 0x12345; jalr x0, x5, 0x678.

[0066] Some descriptions in the following text use the above examples to explain the embodiments.

[0067] Example 1 A multi-branch predictor based on RISC-V processor

[0068] like Figure 2 As shown, this embodiment includes a two-level prediction module, wherein:

[0069] 1. The first-level branch prediction module includes the L0 BTB submodule and the L0 UBTB submodule, specifically:

[0070] The L0 BTB submodule indexes the configured storage table by the value of the branch history register and the low-order XOR result of the current program counter PC value corresponding to the current prediction block. It determines the matching of the branch instruction based on the label information in the table entry to determine whether to trigger the second-level branch prediction module.

[0071] Among them, the table entries of the index storage table of the L0 BTB submodule include: the starting address of the next prediction block, the branch jump status of the current prediction block, the conditional branch existence flag and the number of branch instructions.

[0072] The L0 UBTB submodule is indexed by the current program counter PC value and outputs the target address of the unconditional jump instruction after hitting it; the L0 UBTB submodule includes 16 table entries, each of which contains the label and 20-bit offset address of the unconditional jump instruction.

[0073] This implementation is set to,when the L0 UBTB hits and the L0 BTB does not detect a conditional branch jump,,the target address of the hit unconditional jump instruction is directly output as the,next prediction block address;

[0074] When the L0 UBTB misses or the L0 BTB detects a conditional branch jump, the second-level branch prediction module is triggered.

[0075] The structure and principle of the first-level branch prediction module are explained as follows:

[0076] (1) L0 BTB submodule: the structure includes branch history register, XOR logic unit and index storage table. XOR logic unit XORs the value of branch history register with the low 13 bits of current program counter PC value to generate index address, and each table entry of index storage table stores the following fields: next predicted block start address (e.g. 0x12345 after the jal instruction), 1-bit current predicted block branch jump state (0 / 1), 1-bit conditional branch existence flag (e.g. set to 1 when a beq instruction is detected), and branch instruction number (e.g. can record 7 branch instruction numbers). The principle of its structure is to quickly predict branches by hashing the dynamic history path and the current program counter PC value address, and when a long-jump conditional branch jump instruction is detected, it is treated as an unconditional jump and only the conditional branch attribute is restored when the first prediction error occurs. For example, when executing beq x1, x2, 0x12345, if the history jump rate generated by the branch jump state exceeds a preset threshold (indicating long jump), L0 BTB directly gives the jump address 0x12345.

[0077] (2) L0 UBTB submodule: the structure includes 16 register table entries, each table entry is composed of a tag and an offset address; the principle is that if the high 20 bits of the current program counter PC value match the table entry tag, the offset address is directly output to splice the high 20 bits of the current program counter PC value to form a complete target address. For example, when executing jal x1, 0x12345, the current program counter PC value is 0x10001000, the high 20 bits are 10001, and the tag in the L0 UBTB submodule table entry is 10001 and the offset address is 0x12345, then the target address 0x10013345 composed of the program counter PC value and the offset address is directly output.

[0078] II. Second-level branch prediction module, including L1 BTB submodule, COTTAGE submodule and RAS return address stack submodule.

[0079] L1 BTB submodule is indexed by current program counter PC value, and outputs the target address of all jump instructions except indirect jump. In addition, the L1 BTB submodule transmits conditional branch jump instructions and indirect jump instructions to the COTTAGE submodule; the L1 BTB submodule transmits call instructions to the RAS return address stack submodule.

[0080] The COTTAGE submodule is composed of a TAGE predictor and an ITTAGE predictor, and the whole is indexed by the hash calculation of the current program counter PC value and the global history register value. The TAGE predictor outputs the jump direction of the conditional branch jump instruction, and the ITTAGE predictor outputs the target address of the indirect jump instruction.

[0081] The input of the RAS return address stack submodule is the next instruction address of the call instruction, and the output is the return address of the ret instruction.

[0082] The output result of the L0 UBTB submodule, the output result of the L1 BTB submodule, the output result of the COTTAGE submodule, and the output result of the RAS return address stack submodule constitute the prediction result of the target address of the next prediction block corresponding to the current prediction block.

[0083] To perfect the embodiment, the TAGE predictor includes one non-tagged component and n tagged components. The non-tagged component is configured with a basic prediction table, and each table entry contains a 2-bit saturated counter and a valid bit. The tagged component is configured with a standard index table, and each table entry contains a 13-bit branch instruction tag, a 3-bit saturated counter, a valid bit, and a useful bit. The initial value of the valid bit of the TAGE predictor is 1, which is set to 0 when the tag hits but the prediction is wrong, and is set to 1 when the prediction is correct.

[0084] The ITAGE predictor includes one non-tagged component, n tagged components, and an offset storage unit. The non-tagged component is configured with a basic prediction table, and each table entry contains a target address. The tagged component is configured with a standard index table, and each table entry contains a 20-bit high base address, a 13-bit branch instruction tag, a confidence bit, and a useful bit. The offset storage unit contains a 12-bit offset.

[0085] The structure and principle of the second-level branch prediction module are explained as follows:

[0086] (1) L1 BTB submodule: The structure includes two storage blocks composed of dual-port SRAM, and each storage block table entry contains a jump offset address and a branch type identifier (for example, 00 represents unconditional direct jump, 01 represents conditional branch jump, 10 represents indirect jump, and 11 represents function return instruction ret or call). Since there are two storage blocks, double parallel prediction can be used. For example, when the prediction block contains beq and jal instructions, the L1 BTB outputs the conditional branch direction and the jal target address in parallel. For the combination of lui x5, 0x12345 and jalr x0, x5, 0x678 instructions, the L1 BTB transfers the indirect jump instruction to the COTTAGE module for processing, and the next address of the call instruction is pushed into the RAS stack.

[0087] In addition, it should be noted that in the embodiment, the overall structure of L0 BTB, L0 UBTB, and L1 BTB is similar to that of a general BTB, and the main difference lies in the different storage contents, storage structures, and sizes of the above table entries.

[0088] (2) COTTAGE sub-module: the structure adopts 2024 storage arrays, the overall table item of the COTTAGE sub-module is configured as a signal bit (for example, if the ITTAGE table item is filled, the signal bit is 1, and if the TAGE table item is filled, the signal bit is 0), an existence bit (for example, when it is 1, it indicates that there is a conditional branch at present) and a prediction data bit (predicted by the TAGE predictor and the ITTAGE predictor). Adding the overall table item and the signal bit of one bit can reduce hash collision, and after integrating the two predictors, the utilization rate can be improved.

[0089] (3) TAGE predictor: refer to Figure 3 , which is divided into a non-tagged component (T0) and n tagged components (T1 to Tn). Each tagged component includes a two-bit saturating counter, a valid bit, etc. And the index mode is also different, T0 uses the low 13 bits of the current program counter PC value, and the tagged component uses the hash result of the current program counter PC value and different length history as the index. Figure 3 In the figure, the first structure is T0, the input is the current program counter PC value, the index address is the low 13 bits of the current program counter PC value, and it points to the T0 sub-box, which contains ctr (counter) and v (valid bit). The output prediction result is to the arbitrator MUX and the meta-predictor USE_ALT_ON_NA. The second structure input is the current program counter PC value and H[0:L1], H represents the history length, such as different global history registers. Then the two inputs are calculated by two hash calculations (hash calculation 1 and hash calculation 2). The result of hash calculation 1 is used to index the T1 table, which contains ctr, u, tag, v, and the output prediction result is input to the arbitrator. Hash calculation 2 generates a tag used for matching, which is compared with the tag stored in the table item, and the comparison result is also input to the arbitrator.

[0090] For example, the index address is generated by hash calculation 1 (combination calculation of the current program counter PC value and the history), and the tag is generated by hash calculation 2. The stored tag needs to be compared with the generated tag. If it matches (that is, the output of the "=?" block is true), it means that the table item is hit, and the hash calculation 1 address prediction result of the table item is used; otherwise, it is not hit, and other table items are used for prediction.

[0091] The arbitrator MUX selects the highest priority (that is, the highest confidence) prediction result from all the hit Tagged components (T1-Tn); if no Tagged component hits, the non-Tagged component basic prediction of T0 is used.

[0092] The meta-predictor USE_ALT_ON_NA dynamically adjusts the prediction strategy according to the useful u bits and / or the valid bits v, for example, if the current prediction is wrong and the counter of the valid bits being 0 accounts for more than or equal to 1 / 2, the prediction result is reversed.

[0093] (4) ITTAGE predictor: refer to Figure 4 The whole is divided into one non-tagged component (T0) and n tagged components (T1 to Tn), and an offset storage unit is additionally added. The non-tagged component is a basic prediction table, which uses the low 13 bits of the current program counter PC value for indexing, and stores the most frequently used addresses. The tagged component has n, each of which contains a 20-bit base address, a 13-bit tag, a 2-bit position bit and a 1-bit useful bit. The indexing method is through the hash of the current program counter PC value and the history record. In order to reduce the area, for indirect long-distance jumps, the combination of jalr, lui / auipc instructions is used, and the base address only saves the high 20 bits, and the low 12 bits of the offset of the offset storage unit are added as the jump target. This indirect jump can jump to anywhere in the 32-bit absolute address space through a double instruction sequence. Figure 4 In the above, the first structure input is the current program counter PC value, which is indexed to T0 (target), and the prediction result is output to the arbitrator and the meta-predictor. The second structure starts, the input is the current program counter PC value and H[0:L1], after two hash calculations, it points to T1 (contains target, c, tag, u) and comparison logic respectively, and the comparison result is also input to the arbitrator. Here, it is the same as the TAGE predictor described above, and will not be repeated here.

[0094] (5) RAS return address stack submodule: the principle follows the LIFO rule, when executing the call instruction (such as jal x1, func), the current program counter PC value + 4 (the next instruction address) is pushed to the stack, and when processing the ret instruction, the top address of the stack (i.e. the next instruction address pressed) is popped as the return address.

[0095] It should be noted that the L0 BTB table item in the first level branch prediction module of the embodiment contains the next predicted block start address, branch jump state, conditional branch existence flag and branch instruction number, the index is generated by the exclusive OR operation of the branch history register and the low bits of the current program counter PC value, the L0 UBTB table item only stores the label and offset address of the unconditional jump instruction, simplifies the prediction process of the unconditional jump, does not occupy the table item space, and thus does not cause frequent second level access, thereby reducing power consumption. The second level branch prediction module of the embodiment adopts an L1 BTB submodule, a COTTAGE submodule (integrating TAGE and ITTAGE predictors, the utilization rate of the two predictors can be improved after integration, and the one-bit signal bit can reduce hash collision) and a RAS submodule. In the TAGE of the embodiment, an effective bit table item is added, which is equivalent to omitting the SC statistical counter, so that the occupation of the storage resource of the embodiment is lower than that of the prior art, and the embodiment is more suitable for low-power and low-area processors. Although the SC statistical counter is omitted, the purpose of correcting the misprediction result can still be achieved.

[0096] Embodiment 2: A prediction method of a multi-branch predictor based on a RISC-V processor

[0097] The prediction method provided by the embodiment is applied to the multi-branch predictor based on the RISC-V processor of the above-mentioned embodiment 1, and can refer to Figure 5 , and the method comprises the following steps.

[0098] Step S1: obtaining the start address of a current prediction block, the prediction block being a plurality of consecutive instructions;

[0099] Step S2: determining the branch type of the prediction block by a first level branch prediction module; specifically, the L0 BTB submodule performs index matching on the index storage table and the exclusive OR result, when the index matching result is an unconditional jump and the L0 UBTB submodule is hit, the L0 UBTB submodule outputs the target address of the hit unconditional jump instruction as the start address of the next prediction block; when the matching result is a conditional branch jump, an indirect jump, or the L0 UBTB submodule is not hit, step S3 is triggered;

[0100] The application implementation process of step S2 of the embodiment can refer to Figure 6 , and the following two cases are given as examples.

[0101] Example 1, the instruction pointed by the current program counter PC value is jal x1, 0x12345. The L0 BTB lookup storage table, calculate the index, and match, since the index shows that the jal is an unconditional direct jump instruction, the result is yes, further check whether the L0 UBTB is hit, if the L0 UBTB is hit (i.e. the target address of the jump instruction has been cached into the table item), directly output 0x12345 as the starting address of the next prediction block; if the L0 UBTB is not hit (i.e. the target address of the jump instruction does not appear in the table item), enter step S3 for the prediction of the second level branch prediction module.

[0102] Example 2, the instruction pointed by the current program counter PC value is beq x1, x2, 0x12345. The L0 BTB lookup storage table, calculate the index, and match, since the index shows that the beq is a conditional jump instruction, the result is no, then enter step S3 for the prediction of the second level branch prediction module.

[0103] Step S3: process the branch instruction through the second level branch prediction module; specifically, the L1 BTB submodule classifies the instruction in the current prediction block through the current program counter PC value; if it is an unconditional direct jump instruction, the L1 BTB submodule outputs the target address of the unconditional direct jump instruction as the starting address of the next prediction block; if it is a conditional branch jump instruction and an indirect jump instruction, enter the COTTAGE submodule, which outputs the jump direction combined with the jump address in the L1 BTB as the starting address of the next prediction block for the conditional branch jump instruction; for the indirect jump instruction, output the target address as the starting address of the next prediction block; if it is a call instruction, enter the RAS return address stack submodule, which stacks the next instruction address of the call instruction until the ret instruction is received, then outputs the return address as the starting address of the next prediction block.

[0104] The application implementation flow of step S2 of the embodiment can refer to Figure 7 , and the following four examples of the following four cases are given:

[0105] Example 3, the instruction pointed to by the current program counter PC value is jal x1, 0x12345. The L1 BTB matches through the current program counter PC value, judges the type of the branch instruction, jal is an unconditional direct jump, so the L1 BTB directly outputs 0x12345 as the starting address of the next predicted block. (Here, there may be a case of missing matching when the L0 UBTB caches the table item without the unconditional jump instruction, resulting in a miss, so the unconditional jump branch instruction that does not hit the first level branch prediction module can still be predicted and the target address is output by the second level branch prediction module).

[0106] Example 4, the instruction pointed to by the current program counter PC value is beq x1, x2, 0x12345. The L1 BTB matches through the current program counter PC value, judges the type of the branch instruction, beq is a conditional branch jump instruction, so enter the TAGE predictor for branch prediction, the TAGE predictor predicts the jump direction of the beq instruction in the L1 BTB, and outputs the corresponding next predicted block address.

[0107] Example 5, the instruction pointed to by the current program counter PC value is lui x5, 0x12345; jalr x0, x5, 0x678. The L1 BTB matches through the current program counter PC value, judges the type of the branch instruction, jalr is an indirect jump instruction, so enter the ITTAGE predictor for prediction, the ITTAGE predictor predicts the jump target address of the jalr, and outputs the corresponding next predicted block address.

[0108] Example 6, the instruction pointed to by the current program counter PC value is call XXX. The L1 BTB matches through the current program counter PC value, judges the type of the branch instruction, stacks the next instruction address of the call instruction, and waits for the ret instruction to be used, the instructions are executed in sequence within the function, the instruction pointed to by the current program counter PC value is ret, the L1 BTB matches through the current program counter PC value, judges the type of the branch instruction, and pops the previously stacked return address as the next predicted block address.

[0109] The above two-level branch prediction module is adopted in the embodiment, which can basically effectively adapt to all instructions in the RISC-V instruction set.

Claims

1. A multi-branch predictor based on a RISC-V processor, characterized in that, The first-level branch prediction module comprises: The L0 BTB submodule is configured with a storage table indexed by the exclusive-OR result of the value of the branch history register and the low bits of the current program counter PC value corresponding to the current prediction block, and the matching condition of the branch instruction is determined according to the tag information in the table entry, so as to determine whether the second-level branch prediction module is triggered. The L0 UBTB submodule is indexed by the current program counter PC value, and outputs the target address of the hit unconditional jump instruction; if the L0 UBTB submodule does not hit, the second-level branch prediction module is triggered. The second-level branch prediction module comprises: The L1 BTB submodule is indexed by the current program counter PC value, and outputs the target address of all jump instructions except indirect jump The COTTAGE submodule is composed of a TAGE predictor and an ITTAGE predictor, and is indexed by the hash calculation of the current program counter PC value and the value of the global history register, the TAGE predictor outputs the jump direction of the conditional branch jump instruction, and the ITTAGE predictor outputs the target address of the indirect jump instruction. The RAS return address stack submodule outputs the return address of the ret instruction. The output results of the L0 UBTB submodule, the L1 BTB submodule, the COTTAGE submodule, and the RAS return address stack submodule constitute the prediction result of the target address of the next prediction block corresponding to the current prediction block. The TAGE predictor comprises one non-tagged component and n tagged components, the non-tagged component is configured with a basic prediction table, each table entry contains a 2-bit saturation counter and a valid bit; the tagged component is configured with a standard index table, each table entry contains a 13-bit branch instruction tag, a 3-bit saturation counter, a valid bit and a useful bit; 2. The multi-branch predictor of claim 1, wherein, The ITTAGE predictor comprises one non-tagged component, n tagged components and an offset storage unit, the non-tagged component is configured with a basic prediction table, each table entry contains a target address; the tagged component is configured with a standard index table, each table entry contains a 20-bit high base address, a 13-bit branch instruction tag, a confidence bit and a useful bit; the offset storage unit contains a 12-bit offset. The initial value of the valid bit of the TAGE predictor is 1, which is set to 0 when the tag hits but the prediction is wrong, and is set to 1 when the prediction is correct.

3. The multi-branch predictor of claim 2, wherein, The table entry of the index storage table of the L0 BTB submodule comprises: the start address of the next prediction block, the branch jump state of the current prediction block, the conditional branch existence flag and the number of branch instructions.

4. The multi-way predictor of any of claims 1-3, wherein, The L0 UBTB submodule comprises 16 table entries, each table entry contains the tag of the unconditional jump instruction and a 20-bit offset address; 5. The multi-way predictor of any of claims 1-3, wherein, ​ When the L0 UBTB hits and the L0 BTB does not detect a conditional branch jump, the target address of the hit unconditional jump instruction is directly output as the next predicted block address; When the L0 UBTB misses or the L0 BTB detects a conditional branch jump, the second-level branch prediction module is triggered.

6. The multi-way predictor of any of claims 1-3, wherein, The RAS return address stack submodule has a depth of 16 and is a last-in first-out structure; when a call instruction is executed, the next instruction address is pushed into the stack; when a ret instruction is executed, the top address of the stack is popped out as a return address.

7. A method of prediction based on a RISC-V processor multi-branch predictor, the method comprising: The method is applied to the multi-branch predictor based on the RISC-V processor according to any one of claims 1-6, and the method comprises the following steps performed in sequence: Step S1: obtaining a starting address of a current predicted block, the predicted block being a plurality of consecutive instructions; Step S2: determining the branch type of the predicted block by the first-level branch prediction module; specifically, the L0 BTB submodule performs index matching by the index storage table and the XOR result; when the index matching result is an unconditional jump and is hit by the L0 UBTB submodule, the L0 UBTB submodule outputs the target address of the hit unconditional jump instruction as the starting address of the next predicted block; When the matching result is a conditional branch jump or an indirect jump, or the L0 UBTB submodule misses, step S3 is triggered; Step S3: processing the branch instruction by the second-level branch prediction module; Specifically, the L1 BTB submodule classifies the instructions in the current predicted block by the current program counter PC value; if it is an unconditional direct jump instruction, the L1 BTB submodule outputs the target address of the unconditional direct jump instruction as the starting address of the next predicted block; If it is a conditional branch jump instruction or an indirect jump instruction, it enters the COTTAGE submodule, which outputs the jump direction of the conditional branch jump instruction in combination with the jump address in the L1 BTB as the starting address of the next predicted block; for the indirect jump instruction, the target address is output as the starting address of the next predicted block; if it is a call instruction, the RAS return address stack submodule is entered, which stacks the next instruction address of the call instruction, and outputs the return address as the starting address of the next predicted block when a ret instruction is received.

8. The method of claim 7, wherein, The predicted block satisfies one of the following conditions: when there is no branch instruction, the next predicted block is taken as the predicted block of the current predicted block; when there are n branch instructions, the program counter PC value of the nth branch instruction is taken as the starting address of the next predicted block; when there is an unconditional jump instruction, the program counter PC value of the next branch instruction is taken as the starting address of the next predicted block.

9. The method of claim 8, wherein, The pre-training process of the L0 BTB submodule comprises: marking the branch jump state corresponding to the conditional branch of the long-term jump in the table item as an unconditional jump, and restoring the mark to a conditional branch jump after the first prediction error.

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