Test method for SoC chip and computer readable storage medium
By using the UART module as the main interactive interface in the SoC chip testing method, the problem of low testing efficiency in the existing technology is solved, and efficient test data transmission and rapid testing process are realized.
Patent Information
- Application Number
- CN202510221397.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-06-20
AI Technical Summary
In the existing SoC chip testing methods, the test data transmission process requires processor assistance, resulting in too slow testing efficiency.
The UART module is used as the main interactive interface, and the test data stream is loaded from the outside into the FPGA through the UART module, and the internal module test of the SoC chip is carried out without relying on the CPU.
It improves the efficiency of test data transmission, reduces CPU participation, significantly improves the test speed, and is simple to operate externally and has good compatibility.
Smart Images
Figure CN120179474A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip testing, and particularly relates to a testing method for an SoC chip and a computer-readable storage medium. Background Art
[0002] An SoC (Chinese: System on Chip; English: System On Chip) is a system that integrates multiple functional modules such as a microprocessor, memory, input / output interfaces, etc. on a single chip to achieve specific functions and computing tasks. SoC chips are widely used in many fields such as consumer electronics, communication, Internet of Things, and embedded systems.
[0003] An FPGA is a programmable logic device. Users can configure its internal logic according to their own needs to achieve specific circuit functions. When an FPGA is integrated inside an SoC, it can achieve multiple functions, significantly enhancing the flexibility and adaptability of the SoC. Not only does the SoC have the advantages of traditional processors, but it can also utilize the high parallel processing ability and hardware-level programming performance provided by the FPGA to achieve accelerated computing tasks.
[0004] Each module of the SoC is interconnected through an internal system bus. The functional testing of the SoC includes both single-module test items and multi-module collaborative test items. When the chip is tested after being fabricated, it is necessary to test the internal modules as comprehensively as possible. However, in the existing technology, whether it is the overall chip testing or the internal single-module testing of the SoC chip, there are problems in inconvenient testing. Especially in the process of test data transmission, the assistance of the processor is required, resulting in slow processing efficiency. Summary of the Invention
[0005] The present invention provides a testing method for an SoC chip, which uses a UART module as the main interaction interface, making the test data transfer efficient and having good compatibility.
[0006] The present invention also provides a computer-readable storage medium, which uses the above-mentioned testing method for an SoC chip to implement the testing of the SoC chip, improving the testing efficiency.
[0007] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.
[0008] To achieve one or some or all of the above purposes or other purposes, a test method for an SoC chip provided by a technical solution of the present invention. The SoC chip includes a CPU, an FPGA, and a UART module. The CPU, the FPGA, and the UART module communicate through a bus. The UART module serves as an input port for the SoC chip to receive external data and commands. The test method includes a PL-side test of the chip and a PS-side test of the chip. The UART module inputs the loading conditions of the PL-side test data stream. The CPU parses the loading conditions of the PL-side test data stream. After deciding to load the PL-side test data stream, it determines whether the data stream source is the UART module. When the source of the test data stream is the UART module, the test data stream is loaded from the UART module into the FPGA through the system bus, and the PL-side test is loaded by the FPGA. When the source of the test data stream is not the UART module, the system searches for the test data stream in the storage module of the SoC chip and loads the test data stream from the storage module into the FPGA through the DMA transfer mode to perform the PL-side test. When the PL-side test is completed or the CPU decides not to load the PL-side test data stream, the system performs the PS-side test.
[0009] The loading conditions of the PL-side test data stream input by the UART module include an external identifier. The CPU checks the external identifier and decides whether to load the PL-side test data stream.
[0010] When the PL-side test is completed or the CPU decides not to load the PL-side test data stream, the PS-side test items are judged according to the external input. The UART module inputs a control command and judges whether the PS-side test of the SoC chip depends on the execution of the CPU. When the PS-side test of the SoC chip depends on the execution of the CPU, the DDR SDRAM is initialized, the system enters a waiting state, the UART module sends a test code and a test start command, and the CPU completes the test of the corresponding module. When the PS-side test of the SoC chip does not depend on the execution of the CPU, the UART module inputs a test command and a test data stream to complete the test of the corresponding module in the SoC chip.
[0011] The test code sent by the UART module is placed at a specified position in the DDR SDRAM. The UART module parses the test start command and notifies the CPU to jump to the specified DDR SDRAM area to execute the corresponding module test program.
[0012] When the PS-side test of the SoC chip does not depend on the execution of the CPU, the UART module directly accesses the internal module of the SoC chip and sends the test command and the test data stream to the internal module of the SoC chip to complete the PS-side test.
[0013] When the PS - side test of the SoC chip depends on the execution of the CPU, the CPU parses the test start command sent by the UART module; when it is determined that the test start command is not to execute the test code, the CPU remains in a state of waiting for the UART module to send the PS - side test code.
[0014] If the PS - side test of the SoC chip does not depend on the execution of the CPU, the CPU enters the low - power mode.
[0015] After the CPU jumps to the specified DDR SDRAM area to execute the corresponding module test program and completes the test, the test result is sent to the external module through the UART module.
[0016] After the UART module sends the test result to the external module, the CPU remains in a state of waiting for the UART module to send the next test code.
[0017] A computer - readable storage medium provided by another technical solution of the present invention stores a test program in the computer - readable storage medium, and the program code is called by a processor to execute a test method for an SoC chip as described above.
[0018] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. The present invention uses the UART module as the main data interaction interface, making the external operation simple and having good compatibility;
[0019] 2. It can perform separate command or data operations on the internal modules of the SoC without relying on the CPU, reducing the CPU's participation and significantly improving the test speed;
[0020] 3. The present invention can freely cut and combine test codes to quickly replace the data stream after the test program code is compiled, quickly add new test codes, regenerate the test program through the modified code and quickly import it through the UART module, download the program through the UART module, and can simply and efficiently implement the code download. At this time, only by setting a new CPU jump address can the corresponding test be completed.
[0021] To make the above - mentioned and other purposes, features and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given and described in detail in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0023] Figure 1 It is a system schematic diagram of the SoC chip of the present invention.
[0024] Figure 2 It is a flowchart of the solution of the present invention. Specific embodiments
[0025] Regarding the foregoing and other technical contents, features, and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.
[0026] Embodiment 1
[0027] Embodiment 1 provides a test method for an SoC chip. The SoC chip of the present invention includes a CPU (Central Processing Unit), an FPGA (Field Programmable Gate Array), and a UART module (Universal Asynchronous Receiver / Transmitter module, a hardware circuit or integrated component for realizing serial communication, which receives and transmits data between microcontrollers, computers, or other electronic devices). The CPU, FPGA, and UART module communicate with each other through a bus (such as AXI, AHB, etc.). The UART module serves as the input port for the SoC chip to receive external data and commands.
[0028] The test method includes chip PL side testing (Programmable Logic Side Testing, testing the programmable logic area in the chip. The programmable logic part allows users to design custom logic circuits through a hardware description language and configure them onto the chip. PL side testing mainly focuses on the correctness, performance, and stability of these user-defined logic functions. The PL side testing in this application is to test the FPGA chip in the SoC chip) and chip PS side testing (Processing System Side Testing, testing the embedded processor system in the chip. The processor system usually includes one or more CPU cores, a memory controller, peripheral interfaces, etc. The focus of PS side testing is to verify whether the functions of the processor system and its surrounding components work properly. The PS side testing in this application is to test the entire SoC chip).
[0029] The UART module inputs the test data stream loading conditions on the PL side, and the CPU parses the test data stream loading conditions on the PL side. After deciding to load the test data stream on the PL side, it judges whether the data stream source is the UART module. When the source of the test data stream is the UART module, the test data stream is loaded from the UART module to the FPGA through the system bus for PL side testing.
[0030] When the source of the test data stream is not the UART module, the system searches for the test data stream in the storage module of the SoC chip and loads the test data stream from the storage module to the FPGA through the DMA transfer mode (Direct Memory Access, a data transfer mode that allows peripheral devices or other hardware components to directly exchange data with the system main memory without CPU intervention) for PL side testing; when the PL side testing is completed or the CPU decides not to load the test data stream on the PL side, the system performs PS side testing.
[0031] The solution of this application uses the UART module as the main interaction interface, which is more convenient for external operation and has good compatibility. At the same time, the test data or test instructions of the present invention do not depend on the operation of the CPU, which can further improve the data processing speed.
[0032] Combined with the attached Figure 2 , the technical solution of the present invention will be further explained below. See Figure 2 A test method for an SoC chip of the present invention includes the following main steps:
[0033] Step 1. After the chip is powered on, necessary system initializations are performed, such as CPU initialization, UART baud rate setting, watchdog setting, etc., and then step 2 is executed.
[0034] Step 2. The UART module inputs the PL side data stream loading conditions, including external identifiers. The CPU will check the external identifiers, such as checking GPIO inputs or switch states, etc., to decide whether to load the test data stream on the PL side. If it decides to load, step 3 is executed; otherwise, step 7 is executed.
[0035] Step 3. After the CPU decides to load the test data stream on the PL side, it judges whether the test data stream on the PL side is input by the UART module. The judgment method is to judge the source of the test data stream based on the content of the test data stream input by the UART module. If the test data stream on the PL side is input by the UART module, step 4 is executed; otherwise, step 5 is executed.
[0036] Step 4. When the source of the test data stream is the UART module, the test data stream on the PL side is loaded from the UART module to the FPGA through the system bus, and then step 6 is executed.
[0037] Step 5. When the test data stream on the PL side is not input by the UART module, find the test data stream from the storage module (such as Flash) of the SoC chip and load the test data stream from the storage module to the FPGA through the DMA transfer mode, and then execute Step 6.
[0038] In Step 5, find the data from the storage space and use the DMA module to move the data stream to the FPGA. Specifically, it may include the following steps: Configure the DMA controller, including configuring the source address, target address, transfer length, and other necessary control parameters. After the configuration is completed, the DMA transfer can be triggered by a software command or an external event. At this time, the DMA controller takes over the data transfer process and moves the data from the source address to the target address according to the preset rules. By using the DMA module to move the data stream, it can reduce the assistance of the CPU to the data, reduce the time required for data transfer, and improve the data transfer speed.
[0039] Step 6. After completing the loading of the test data stream on the PL side, the FPGA executes the corresponding test functions. The data test on the PL side is prior art and will not be specifically described in this article. After completing the PL side test, execute Step 7.
[0040] Step 7. After the CPU decides not to load the test data stream on the PL side or after completing the PL side test, judge the PS side test items of the SoC chip according to the external input. At the same time, according to the control command input by the UART module, judge whether the PS side test of the SoC chip needs to rely on the CPU execution. If it relies on the CPU execution, execute Step 8; otherwise, execute Step 13.
[0041] Step 8. If the PS side test of the SoC chip needs to rely on the CPU execution, since the data of the subsequent test code translation needs to be placed in the SDRAM (Synchronous Dynamic Random Access Memory), first execute the DDR SDRAM initialization. The system waits to receive the PS side test code from the UART module, and then execute Step 9.
[0042] Step 9. According to the different module tests of the SoC chip, map the test code data to different execution positions, and place the test code data received from the UART module in the specified area of the SDRAM. For example, place the SPI test code at the starting position (there is no special limit on the specific placement position). After all the codes are downloaded, execute Step 10.
[0043] Step 10. Wait for the UART module to send a test start command. After receiving the command, parse whether to start executing the test code for the corresponding area. If so, execute Step 11; otherwise, continue to execute Step 10, keeping the CPU in a state of waiting for the UART module to send the next test start command.
[0044] Step 11. After the test start command is parsed, the UART module notifies the CPU to jump to the specified SDRAM area to execute the corresponding module test code, and then execute Step 12.
[0045] Step 12. Send the test result through the UART module for external reception. Then execute Step 8, keeping the CPU in a state of waiting to receive the test data stream from the UART module.
[0046] Step 13. When the module test within the SoC chip does not depend on the execution of the CPU, the UART module directly accesses the internal modules of the SoC chip. The UART module inputs commands and test data, where the commands and test data are sent from the UART module according to the custom protocol format and are parsed and processed by the UART module hardware. The modules to be tested within the SoC chip receive the commands and data sent by the UART module for single-step instruction testing and control the CPU to enter the low-power mode, relying only on the commands and data sent by the UART module.
[0047] The above steps are all the steps of the test method for the SoC chip in Embodiment 1. Embodiment 1 uses the UART module as the main data interaction interface, making external operations simple and having good compatibility. At the same time, Embodiment 1 can perform separate command or data operations on the internal modules of the SoC without relying on the CPU, reducing the CPU's participation and significantly improving the test speed. Embodiment 1 can also freely cut and combine the test code to quickly replace the data stream after the test program code is compiled, quickly add new test code, and re-generate the test program through the modified code and quickly import it through the UART module. Downloading the program through the UART module can simply and efficiently implement the code download. At this time, only by setting a new CPU jump address can the corresponding test be completed.
[0048] Embodiment 2
[0049] Embodiment 2 provides a computer-readable storage medium in which relevant test programs are stored. The program code is called by the processor to execute all the steps of the test method for the SoC chip in Embodiment 1. Through the scheduling of the program, the test speed of the SoC chip can be greatly improved.
[0050] The above has introduced in detail a test method and a computer-readable storage medium for an SoC chip provided by the present invention. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A test method for a SoC chip, wherein the SoC chip comprises a CPU, an FPGA and a UART module, wherein the CPU, the FPGA and the UART modules communicate with each other via a system bus, wherein: The UART module serves as an input port for the SoC chip to receive external data and commands; The testing method includes chip PL side testing and chip PS side testing; The UART module inputs the PL side test data stream loading condition, the CPU parses the PL side test data stream loading condition, and after deciding to load the PL side test data stream, determines whether the data stream source is the UART module, and when the test data stream source is the UART module, loads the test data stream from the UART module to the FPGA through the system bus, and the FPGA loads the PL side test; When the source of the test data stream is not the UART module, the system searches for the test data stream from the storage module of the SoC chip and loads the test data stream from the storage module to the FPGA through the DMA transfer mode to perform PL side testing; When the PL side test is completed or the CPU decides not to load the PL side test data stream, the system performs the PS side test.
2. A test method for a SoC chip according to claim 1, characterized in that: The PL side test data stream loading condition input by the UART module includes an external identifier, and the CPU checks the external identifier and determines whether to load the PL side test data stream.
3. A test method for a SoC chip according to claim 1, characterized in that: When the PL side test is completed or the CPU decides not to load the PL side test data stream, the PS side test items are determined according to the external input, and the UART module inputs the control command and determines whether the SoC chip PS side test needs to rely on the execution of the CPU; When the PS side test of the SoC chip depends on the execution of the CPU, the DDR SDRAM is initialized, the system enters a waiting state, the UART module sends a test code and a test start command, and the CPU completes the test of the corresponding module; When the PS side test of the SoC chip does not rely on the execution of the CPU, the UART module inputs the test command and the test data stream to complete the corresponding module test in the SoC chip.
4. A test method for a SoC chip according to claim 3, characterized in that: The test code sent by the UART module is placed in the specified location of the DDR SDRAM; The UART module parses the test start command and notifies the CPU to jump to the specified DDR SDRAM area to execute the corresponding module test program.
5. A test method for a SoC chip according to claim 3, characterized in that: When the PS side test of the SoC chip does not depend on the execution of the CPU, the UART module directly accesses the internal module of the SoC chip, and sends the test command and the test data stream to the internal module of the SoC chip to complete the PS side test.
6. A test method for a SoC chip according to claim 3, characterized in that: When the PS side test of the SoC chip depends on the execution of the CPU, the CPU parses the test start command sent by the UART module; When it is determined that the test start command is not to execute the test code, the CPU keeps waiting for the UART module to send the next test start command.
7. A test method for a SoC chip according to claim 3, characterized in that: If the PS side test of the SoC chip does not depend on the execution of the CPU, the CPU enters a low power consumption mode.
8. A test method for a SoC chip according to claim 4, characterized in that: After the CPU jumps to the designated DDR SDRAM area to execute the corresponding module test program and completes the test, the test result is sent to the external module through the UART module.
9. A test method for a SoC chip according to claim 8, characterized in that: After the UART module sends the test result to the external module, the CPU keeps waiting for the UART module to send the PS side test code.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a test program, and the program code is called by a processor to execute a test method for a SoC chip as described in any one of claims 1-9.