Direct memory access control method, system, electronic device and storage medium

Abstract

The present disclosure provides a direct memory access control method, system, electronic device and storage medium, which relates to the field of computer technology. The method includes: receiving a direct memory access DMA descriptor sent by a driver of an input / output (IO) device; the DMA descriptor includes the starting address, length information and identifier of the virtual address corresponding to the DMA operation in the DMA descriptor; based on the DMA descriptor, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the input / output translation backup buffer (IOTLB); the mapping table is stored in a cache; in response to the absence of the target mapping relationship in the mapping table of the IOTLB, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory based on the DMA descriptor, and updating the target mapping relationship to the mapping table of the IOTLB. The present disclosure can improve the IOVA hit rate of the IOTLB, improve the efficiency of DMA operations, and improve the overall performance of the processor.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a direct memory access control method, system, electronic device, and storage medium. Background Art

[0002] Multi-core Reduced Instruction Set Computing (RISC) server processors have numerous input and output (IO) resources. The most typical IO interface is the Peripheral Component Interconnect Express (PCIe) bus, including PCIe network cards, PCIe graphics cards, PCIe sound cards, PCIe storage, and PCIe to USB bus connections. PCIe peripherals access the memory of multi-core RISC processors (such as RISC-V, the fifth-generation RISC) through the Input and Output Memory Management Unit (IOMMU). The IOMMU is a step in the Direct Memory Access (DMA) process, converting virtual addresses to physical addresses for peripherals such as PCIe during DMA. DMA enables direct communication between devices and memory without going through the Central Processing Unit (CPU).

[0003] However, due to the large number of IO interfaces with integrated DMA functions, multi-core RISC processors may have problems such as low IOMMU function efficiency, high memory overhead and low storage efficiency in applications. They are unable to meet the DMA access requirements of numerous IOs in a timely manner, resulting in low overall performance of the multi-core RISC processor and failure to exert the optimal performance of the multi-core processor. Summary of the Invention

[0004] The present disclosure provides a direct memory access control method, system, electronic device and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a direct memory access control method is provided, comprising: receiving a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device; the DMA descriptor including a starting address and length information of a virtual address corresponding to a DMA operation and an identifier of the IO device; based on the DMA descriptor, querying a mapping table of an input / output translation lookaside buffer (IOTLB) for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation; the mapping table being stored in a cache; and in response to the target mapping relationship not existing in the mapping table of the IOTLB, querying a page table of a memory for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation based on the DMA descriptor, and updating the target mapping relationship in the mapping table of the IOTLB.

[0006] In one possible implementation, querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory based on the DMA descriptor, and updating the target mapping relationship to the mapping table of the IOTLB includes: obtaining the sending order of the DMA descriptors of each of the IO devices; querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory in the sending order based on each of the DMA descriptors, and updating the target mapping relationship to the mapping table of the IOTLB.

[0007] In one embodiment, a direct memory access control method further includes: in response to the existence of the target mapping relationship in the mapping table of the IOTLB, based on the next DMA descriptor received, querying the target mapping relationship between the virtual address and physical address corresponding to the next DMA descriptor in the mapping table of the IOTLB.

[0008] In one possible implementation, before querying the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the input / output translation lookaside buffer (IOTLB) based on the DMA descriptor, the method further includes: obtaining sequential information of all virtual addresses and corresponding physical addresses; the sequential information includes a starting address and length information; generating a sequential mapping table based on the sequential information; and deleting the mapping relationship already existing in the sequential mapping table from the mapping table of the IOTLB.

[0009] In one possible implementation, after receiving the direct memory access (DMA) descriptor sent by the driver of the input / output (IO) device, the method further includes: querying, in the sequential mapping table, based on the DMA descriptor, a target mapping relationship between the virtual address and the physical address corresponding to the DMA operation; and in response to the target mapping relationship not existing in the sequential mapping table, querying, in the mapping table of the IOTLB, a target mapping relationship between the virtual address and the physical address corresponding to the DMA operation.

[0010] In one possible implementation, a direct memory access control method further includes: obtaining the timestamp and the length information of each time the IO device sends the DMA descriptor; determining the unit data transmission time of the statistical period corresponding to the two adjacent DMA descriptors based on the timestamps corresponding to the two adjacent DMA descriptors and the length information of the previous DMA descriptor, and determining the average value of all the unit data transmission times; based on the average value, predicting the target time for the IO device to send the next DMA descriptor; and updating the mapping table of the IOTLB based on the target time.

[0011] In one possible implementation, predicting the target time for the IO device to send the next DMA descriptor based on the average value includes: determining the product of the average value and the length information; and determining the sum of the timestamp of the DMA descriptor last sent by the IO device and the product as the target time.

[0012] In one possible implementation, predicting the target time for the IO device to send the next DMA descriptor based on the average value includes: determining the product of the average value and the length information; determining the difference between the actual timestamp of the DMA descriptor last sent by the IO device and the target time; and determining the sum of the actual timestamp, the product, and the difference as the target time.

[0013] In one embodiment, updating the mapping table of the IOTLB based on the target time includes: in response to the target time being greater than a first threshold, deleting the mapping relationship between the virtual address and the physical address corresponding to the IO device in the mapping table of the IOTLB.

[0014] In one embodiment, a direct memory access control method further includes: in response to the priority of the IO device being greater than a second threshold, retaining a mapping relationship between a virtual address and a physical address corresponding to the IO device in a mapping table of the IOTLB.

[0015] In one possible implementation, a direct memory access control method further includes: determining the IO device that sends the DMA descriptor at a frequency greater than a third threshold as a first target IO device; determining the IO device in which the mapping relationship between the corresponding virtual address and the physical address is only stored in the memory as a second target IO device; and updating the mapping relationship between the virtual address and the physical address corresponding to the first target IO device and / or the second target IO device into the mapping table of the IOTLB.

[0016] According to a second aspect of the present disclosure, a direct memory access control system is provided, comprising: a mapping table update module, the mapping table update module comprising a register configuration submodule, a query submodule and an update submodule; the register configuration submodule is used to receive a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device; the DMA descriptor comprises a starting address, length information and an identifier of a virtual address corresponding to a DMA operation; the query submodule is used to query a mapping table of an input / output translation lookaside buffer (IOTLB) for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation based on the DMA descriptor; the mapping table is stored in a cache; the update submodule is used to query a page table of a memory for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation based on the DMA descriptor, in response to the target mapping relationship not existing in the mapping table of the IOTLB, and update the target mapping relationship to the mapping table of the IOTLB.

[0017] In one embodiment, the mapping table update module also includes a monitoring submodule; the monitoring submodule is used to monitor the sending order of the DMA descriptors of each of the IO devices and send the sending order to the update submodule; the update submodule is also used to query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory in the sending order based on each of the DMA descriptors, and update the target mapping relationship to the mapping table of the IOTLB.

[0018] In one embodiment, the query submodule is further used to: in response to the existence of the target mapping relationship in the mapping table of the IOTLB, based on the received next DMA descriptor, query the target mapping relationship between the virtual address and the physical address corresponding to the next DMA descriptor in the mapping table of the IOTLB.

[0019] In one possible implementation, a direct memory access control also includes: a virtual address processing module; the virtual address processing module includes: a sequence check submodule, a generation submodule, and a deletion submodule; the sequence check submodule is also used to obtain the sequential information of all virtual addresses and corresponding physical addresses; the sequential information includes a starting address and length information; the generation submodule is also used to generate a sequential mapping table based on the sequential information; the deletion submodule is also used to delete the mapping relationship that already exists in the sequential mapping table in the mapping table of the IOTLB.

[0020] In one embodiment, the virtual address processing module also includes: a table lookup enable module, which is used to: based on the DMA descriptor, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the sequential mapping table; in response to the target mapping relationship not existing in the sequential mapping table, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the IOTLB.

[0021] In one possible implementation, a direct memory access control also includes: a resource release module, used to: obtain the timestamp and the length information of each time the IO device sends the DMA descriptor; determine the unit data transmission time of the statistical period corresponding to the two adjacent DMA descriptors based on the timestamps corresponding to the two adjacent DMA descriptors and the length information of the previous DMA descriptor, and determine the average value of all the unit data transmission times; based on the average value, predict the target time for the IO device to send the next DMA descriptor; based on the target time, update the mapping table of the IOTLB.

[0022] In one possible implementation, the resource release module is further configured to: determine a product of the average value and the length information; and determine a sum of a timestamp of a DMA descriptor last sent by the IO device and the product as the target time.

[0023] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a direct memory access control system according to the present disclosure, wherein the direct memory access control system can execute a direct memory access control method according to the present disclosure.

[0024] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0025] The present disclosure discloses a direct memory access control method, system, electronic device, and storage medium. The method receives a DMA descriptor, which includes the starting address and length information of the virtual address corresponding to the DMA operation, and an identifier of the IO device. When the physical address corresponding to the virtual address is not found in the IOTLB mapping table, the method queries the memory page table for the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation, and updates the target mapping relationship to the IOTLB mapping table. Thus, the present disclosure updates the mapping relationship between the virtual address and the physical address required for the corresponding DMA operation to the IOTLB mapping table before the DMA operation instruction reaches the IOMMU, significantly improving the IOTLB's input / output virtual address (IOVA) hit rate, enhancing the efficiency of DMA operations, and improving the overall performance of the processor.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0028] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0029] Figure 1 A schematic diagram of a direct memory access control method according to an embodiment of the present disclosure is shown. Figure 1 ;

[0030] Figure 2 A schematic diagram of a direct memory access control method according to an embodiment of the present disclosure is shown. Figure 2 ;

[0031] Figure 3 A schematic diagram of the structure of a direct memory access control system in the prior art is shown;

[0032] Figure 4 A schematic diagram of a page table query in the prior art is shown;

[0033] Figure 5 A schematic structural diagram of a direct memory access control system according to an embodiment of the present disclosure is shown;

[0034] Figure 6 A schematic structural diagram of a mapping table update module according to an embodiment of the present disclosure is shown;

[0035] Figure 7 A schematic diagram of the structure of a virtual address processing module according to an embodiment of the present disclosure is shown;

[0036] Figure 8 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0038] Figure 3 The structure diagram of the direct memory access control system of the prior art is shown as follows: Figure 3 As shown, the N+1 core RISC-V server CPU integrates M+1 IO devices with DMA function, where N+1 can be 64, 96, 128, etc., and M+1 can be 96, 128, etc. The N+1 core is as follows Figure 3 Core0~CoreN in the M+1 IO devices with DMA function such as Figure 3 IO device 0 to IO device M in the IO device. When accessing the server CPU memory, many IO devices need to be processed by the IOMMU module to complete the conversion from virtual address to physical address, and then write data into the double data rate (DDR) memory or read it from the DDR memory through the network on a chip (NoC) interconnect bus. To access the IOMMU, the IO device needs to provide IOVA and also provide information for querying the device table, such as the device identifier (Device ID) and process identifier (Process ID). These device table information needs to be entered into Figure 3 In the Context Device Walker (CDW) hardware unit module, query the device table in the physical memory.

[0039] To achieve fast translation from IOVA to physical addresses (PA), traditional solutions employ an I / O Translation Lookaside Buffer (IOTLB), a cache for I / O page tables that internally caches the IOVA-to-PA mapping. If the PA corresponding to the IOVA is found in the IOTLB, there's no need to query the page table in memory. Since the IOMMU's page table is stored in memory, querying the page table in memory is inefficient. Therefore, traditional IOMMUs configure an IOTLB to accelerate the IOVA-to-PA lookup process. However, the IOTLB cache space is typically small, and the cache cost is high. Increasing the IOTLB cache space by adding more cache is also costly. Therefore, the present disclosure addresses the question of how to improve IOMMU efficiency and accelerate the rate at which numerous IO devices access DDR memory via DMA without increasing the IOMMU's internal cache.

[0040] Figure 4 A schematic diagram of a page table query in the prior art is shown. Figure 4 As shown, the global page directory (PGD, PageGlobal Directory) stores the base address of the next level page table, and the page table entry (PTE, Page Table Entrys) stores the page table of the physical address. Both PGD and PTE are stored in memory. IOMMU obtains the base address of the first-level page table PGD by accessing the page table base register, and then finds the base address of the next-level page table PTE by combining the PGD index (index) in the virtual address, and then finds the page frame number (PFN, Page Frame Number) by combining the PTE index in the virtual address, and then adds it to the VA to get the physical address. Whether it is a second-level page table, a third-level page table or a fourth-level page table, the second-level page table is found through the first-level page table, the third-level page table is found through the second-level page table, and finally the physical address is found. The page table query process is in Figure 3 It is implemented in the Page Table Walker (PTW) in .

[0041] Traditional multi-core RISC-V server processor IOMMUs have the following drawbacks:

[0042] 1. The cache capacity of the IOMMU's internal IOTLB module is limited. In server processor applications (such as server CPUs), there are numerous peripheral I / O devices with integrated DMA functionality. Multiple processes often access the IOMMU simultaneously, but a hit fails in the IOTLB (that is, the IOTLB does not cache the mapping between the corresponding process's IOVA and PA). In this case, the IOVA (IO virtual address) of the process that fails to hit the IOTLB must be repeatedly queried in the PTW module's physical memory to obtain the PA, and then perform DMA operations. Multiple memory table lookups not only inefficiently perform IO DMA operations and slow the execution of the corresponding processes, but also incur additional memory overhead, further exacerbating the overall performance degradation of multi-core RISC-V server CPUs.

[0043] 2. In the traditional solution, the IOTLB mapping update strategy within the IOMMU is "update on demand." That is, address translation and IOTLB updates are performed only when IO DMA accesses an uncached IO address. While this design introduces unnecessary operations, it also delays certain accesses, requiring them to wait until address translation is complete. For example, if IO device 0 accesses the IOVA 0x1000_0000-0x1000_2000, the PA corresponding to the IOVA is not cached in the IOTLB. In this case, the traditional solution first performs a page table lookup to obtain the PA corresponding to the IOVA, then updates the IOTLB and waits for the next DMA access. However, the next DMA access address for this IO may not necessarily match the previous IOVA, so another page table lookup and IOTLB update are required. This traditional solution results in a large number of invalid IOTLB updates and page table accesses. The root cause is that the IOMMU cannot determine the address to be accessed by the IO DMA operation, resulting in a decrease in the overall performance of the multi-core RISC-V server CPU.

[0044] 3. In traditional solutions, the storage efficiency of the IOVA and PA mapping relationship (mapping table) cached in the IOMMU cache is low. That is, the cache caches the mapping relationship between IOVA and PA, that is, 1000 IOVAs correspond to 1000 PAs. This mapping relationship leads to low storage efficiency and cannot cache more IOVA and PA address mappings.

[0045] 4. In the traditional solution, the update and exit mechanism of the IOVA and PA mapping tables cached in the IOMMU's IOTLB is not sensitive. It is unable to promptly update and replace the mapping tables corresponding to IO devices that no longer need to be cached for a long time, and thus cannot leave cache space for IO devices that need it more. As a result, the IOTLB cache hit rate is not high, which in turn leads to a decline in the overall performance of the multi-core RISC-V server CPU.

[0046] Figure 1 A schematic diagram of a direct memory access control method according to an embodiment of the present disclosure is shown. Figure 1 ,like Figure 1 As shown, a direct memory access control method includes:

[0047] Step S101: receiving a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device.

[0048] In this embodiment, the DMA descriptor includes the starting address of the virtual address corresponding to the DMA operation, length information, and the identifier of the IO device. The IOMMU unit of the multi-core RISC-V server processor receives DMA descriptors sent by the drivers of various input and output IO devices. These DMA descriptors contain detailed information about the starting address of the virtual address for the upcoming DMA operation, which can clearly indicate the starting position of the DMA operation in the virtual address space. They also include length information, which is used to indicate the amount of data involved in the DMA operation to determine the scope of the operation, and the identifier of the IO device, which is used to accurately distinguish which specific IO device initiated the DMA operation.

[0049] Figure 5 A schematic diagram of the structure of a direct memory access control system according to an embodiment of the present disclosure is shown. Figure 5 As shown, a direct memory access control system includes a mapping table update module for updating a virtual address physical address mapping table. In the present disclosure, the mapping table update module receives the starting address information, length information and the ID of the corresponding IO device in the descriptor sent by each IO device driver, and also involves software driver modification, that is, when the software driver of the IO device sends the DMA descriptor, it not only sends the descriptor to the DDR, but also sends the DMA descriptor to the DDR. Figure 5 The mapping table update module in .

[0050] Step S102 : Based on the DMA descriptor, query the mapping table of the input / output translation lookaside buffer (IOTLB) for a target mapping relationship between the virtual address and the physical address corresponding to the DMA operation.

[0051] In this embodiment, when the mapping table update module receives a DMA descriptor, the IOMMU unit queries the IOTLB mapping table based on the starting address and other information in the descriptor. The IOTLB mapping table is stored in the cache and is used to quickly find the correspondence between virtual addresses and physical addresses. By searching the IOTLB mapping table, the physical address to which the virtual address corresponding to the DMA operation is mapped can be quickly determined, thereby providing accurate physical address information for the DMA operation so that subsequent data transfers can be performed at the correct physical memory location.

[0052] Step S103, in response to the target mapping relationship not existing in the mapping table of the IOTLB, based on the DMA descriptor, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation is searched in the page table of the memory, and the target mapping relationship is updated in the mapping table of the IOTLB.

[0053] In this embodiment, if the mapping table update module does not find the corresponding target mapping relationship between the virtual address and the physical address in the mapping table of the IOTLB, the IOMMU unit will further query in the page table of the memory. The page table of the memory is a data structure that stores the mapping relationship between the virtual address and the physical address in a more comprehensive and detailed manner. Although the query speed is relatively slow, it can find all possible mapping relationships. After the target mapping relationship is queried in the memory page table, in order to improve the efficiency of subsequent queries for the same virtual address, the mapping table update module will update the newly queried target mapping relationship to the mapping table of the IOTLB, so that the next time the same virtual address query is encountered, it can be directly hit quickly in the IOTLB, thereby improving the overall address conversion efficiency and the efficiency of DMA operations.

[0054] In the present disclosure, the mapping table update module can update the mapping table in the IOTLB required for the corresponding DMA operation before the IOMMU executes the DMA operation instruction, greatly improving the IOVA hit rate of the IOTLB, improving the efficiency of IO DMA operations, and improving the overall performance of the processor.

[0055] In another embodiment, a direct memory access control method further includes:

[0056] In response to the existence of a target mapping relationship in the mapping table of the IOTLB, based on the received next DMA descriptor, the target mapping relationship between the virtual address and the physical address corresponding to the next DMA descriptor is queried in the mapping table of the IOTLB.

[0057] In this embodiment, once the target mapping relationship corresponding to the current DMA descriptor is found in the IOTLB mapping table, it indicates that the address mapping information required for this DMA operation is available and the DMA operation can be successfully executed. At this point, the system will continue to receive the next DMA descriptor sent by the IO device and, based on this new DMA descriptor, query the IOTLB mapping table for the target mapping relationship between the virtual address and the physical address corresponding to the next DMA operation, thereby achieving continuous and efficient processing of multiple DMA operations and improving the data transmission efficiency and performance of the entire system.

[0058] In another embodiment, the step S103 of “searching the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory based on the DMA descriptor, and updating the target mapping relationship into the mapping table of the IOTLB” includes:

[0059] Obtain the sending order of the DMA descriptors of each IO device; based on each DMA descriptor, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory in the sending order, and update the target mapping relationship to the mapping table of the IOTLB.

[0060] In this embodiment, the mapping table update module records and obtains the order in which each IO device sends DMA descriptors, and searches the page table of the memory for the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in this order.

[0061] In one example, if there are 6 IO devices with IDs 0-5, the order in which the IO device DMA controller initiates DMA descriptors is: 0-3-2-4-1-6-5, then the mapping table update module will perform page table queries and update the IOTLB mapping table in the order of IO device 0, IO device 3, IO device 2, IO device 4, IO device 1, IO device 6, and IO device 5.

[0062] In another embodiment, before step S102 of “searching a mapping table of an input-output translation lookaside buffer (IOTLB) based on the DMA descriptor for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation”, the method further includes:

[0063] Get the sequential information of all virtual addresses and corresponding physical addresses; the sequential information includes the starting address and length information.

[0064] In this embodiment, if Figure 5The virtual address processing module shown in the will collect and organize the sequential information of all virtual addresses and the corresponding physical addresses. This sequential information mainly includes the starting address of each continuous segment and the length information of the continuous segment. By obtaining this sequential information, the continuity relationship between virtual addresses and physical addresses can be understood, which is used to subsequently optimize the mapping table storage structure and query efficiency in the IOTLB. For example, by analyzing this sequential information, it can be found that some virtual address segments and physical address segments are continuous. In this way, a more efficient storage and query method can be used in the IOTLB to process these continuous address mapping relationships, thereby improving the address conversion efficiency of the entire system.

[0065] In one example, in a traditional solution, the IOTLB caches all the correspondences between IOVA and PA. For example, if IOVA = 0x1000_0000-0x1000_0FFC (a total of 0x1000 addresses), the corresponding PAs are 0x1F00_2000-0x1F00_3FFC, 0x3E00_7000-0x3E00_74FC, and 0x68A0_5000-0x68A0_52FC. The traditional IOTLB cache needs to cache 0x2000 addresses, but the cache efficiency is very low and the cache usage is too large. In this embodiment, the order of IOVA and PA is checked, that is, the continuous length of IOVA and PA and their corresponding starting addresses are checked and counted. For example, IOVA=0x1000_0000-IOVA=0x1000_01FC maps PA0=0x1F00_2000-0x1F00_3FFC, then IOVA=0x1000_0000, PA=0x1F00_2000, LENGTH=0x200 are extracted; IOVA=0x1000_0200-IOVA=0x1000_01FC maps PA0=0x1F00_2000-0x1F00_3FFC. 00_06FC, mapping PA=0x3E00_7000-0x3E00_74FC, then extract IOVA=0x1000_0200, PA=0x3E00_7000, LENGTH=0x500; IOVA=0x1000_0700-IOVA=0x1000_0FFC, mapping PA=0x68A0_5000-0x68A0_58FC, then extract IOVA=0x1000_0700, PA=0x68A0_5000, LENGTH=0x900.

[0066] A sequence mapping table is generated based on the sequential information.

[0067] In this embodiment, after obtaining the sequential information of the virtual address and the physical address, the virtual address processing module generates a sequential mapping table based on the information. The sequential mapping table can be stored in a file such as Figure 5In the virtual address processing module shown. This sequential mapping table is specifically used to store continuous segment information of virtual addresses and physical addresses, including key information such as the starting address and length of each continuous segment. Through this sequential mapping table, continuous address mapping relationships can be managed and queried more efficiently. For example, when it is necessary to query the physical address corresponding to a certain virtual address, you can first quickly find the continuous segment where the virtual address is located in the sequential mapping table, and then quickly determine the specific physical address based on the starting address and length information of the continuous segment, thereby greatly improving the efficiency of address query. Especially when processing a large number of continuous address mapping relationships, the advantages of this sequential mapping table are more obvious, which can significantly improve the performance of the system.

[0068] In one example, a sequential mapping table created based on the start address and length LENGTH of the IOVA and PA continuous segments is shown in Table 1 below:

[0069] Table 1 Sequential mapping table

[0070]

[0071] Delete the mapping relationship that already exists in the sequential mapping table in the IOTLB mapping table.

[0072] In this embodiment, after the sequential mapping table is generated, the virtual address processing module optimizes the IOTLB mapping table. Specifically, the mapping relationships that already exist in the sequential mapping table are deleted from the IOTLB mapping table. That is, the IOTLB mapping table only caches the mapping relationships that are not in the sequential mapping table. Because the sequential mapping table is already able to efficiently manage and query these continuous address mapping relationships, the IOTLB mapping table can focus on storing those discontinuous, more complex address mapping relationships. In this way, the storage burden of the IOTLB mapping table and cache can be reduced, and its storage efficiency and query efficiency can be improved.

[0073] In another embodiment, after step S101 of "receiving a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device", the method further includes:

[0074] Based on the DMA descriptor, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the sequential mapping table;

[0075] In response to the target mapping relationship not existing in the sequential mapping table, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation is searched in the mapping table of the IOTLB.

[0076] In this embodiment, after receiving a DMA descriptor from an I / O device, the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation is first queried in a sequential mapping table. Because the sequential mapping table stores information about consecutive segments of virtual and physical addresses, this query method can quickly determine whether the virtual address belongs to a specific consecutive segment and quickly determine the corresponding physical address. This method greatly improves query efficiency, especially when processing a large number of consecutive address mapping relationships. It can significantly reduce query time, speed up DMA operations, and thus improve overall system performance.

[0077] In this embodiment, if the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation is not found in the sequential mapping table, the target mapping relationship will be further queried in the mapping table of the IOTLB. The mapping table of the IOTLB stores those discontinuous and more complex address mapping relationships. By querying in the IOTLB mapping table, those address mapping relationships that do not belong to continuous segments can be found. In this way, both the efficient management of continuous address mapping relationships by the sequential mapping table and the storage and query capabilities of the IOTLB mapping table for complex address mapping relationships are utilized, thereby achieving efficient query and management of all address mapping relationships, ensuring that DMA operations can quickly obtain the required address mapping information, and improving the overall performance of the system.

[0078] Figure 2 A schematic diagram of a direct memory access control method according to an embodiment of the present disclosure is shown. Figure 2 ,like Figure 2 As shown, a direct memory access control method further includes:

[0079] Step S201: obtaining the timestamp and length information of each DMA descriptor sent by the IO device.

[0080] In this embodiment, the system records the timestamp and corresponding length information of each DMA descriptor sent by each IO device. The timestamp is used to accurately record the specific moment when the DMA descriptor is sent, while the length information indicates the amount of data involved in this DMA operation. By obtaining this information, basic data can be provided for subsequent prediction and analysis of the DMA behavior of the IO device. For example, by analyzing the timestamp and length information of two adjacent DMA descriptors, the frequency and pattern of the DMA operations sent by the IO device can be understood, thereby providing a basis for predicting its subsequent DMA behavior, and then optimizing and updating the IOTLB mapping table to improve the performance and efficiency of the system.

[0081] Step S202 : determining the unit data transmission time of the statistical period corresponding to the two adjacent DMA descriptors based on the timestamps corresponding to the two adjacent DMA descriptors and the length information of the previous DMA descriptor, and determining the average value of all the unit data transmission times.

[0082] In this embodiment, after obtaining the timestamp and length information of each DMA descriptor sent by the IO device, the unit data transmission time of the statistical period corresponding to the two adjacent DMA descriptors is calculated. The specific method is to use the timestamp difference between the two adjacent DMA descriptors, combined with the length information of the previous DMA descriptor, to calculate the time required to transmit unit data within the statistical period. Then, the average value of the unit data transmission time of all statistical periods is calculated. This average value can reflect the average rate and regularity of the DMA operation sent by the IO device within a certain time range. Through this average value, the time interval and data volume of the subsequent DMA descriptor sent by the IO device can be more accurately predicted, providing a more reliable basis for the optimization and update of the IOTLB mapping table, thereby improving the prediction accuracy and performance optimization effect of the system.

[0083] In one example, assume that the timestamp of the IO device initiating the first DMA descriptor is T0, the length of the DMA descriptor is DMA_LENGTH, and the timestamp of initiating the second DMA descriptor is T1. According to the formula T0 + DMA_LENGTH × PRED_PARAM_1 = T1, PRED_PARAM_1, that is, the unit data transmission time, is obtained. Repeat the above steps to obtain PRED_PARAM_1 ... PRED_PARAM_N in all statistical periods, and calculate the average value PRED_PARAM_AVERAGE of PRED_PARAM_1 ... PRED_PARAM_N.

[0084] Step S203: predicting the target time for the IO device to send the next DMA descriptor based on the average value.

[0085] Step S204: updating the IOTLB mapping table based on the target time.

[0086] In this embodiment, after determining the average unit data transfer time across all statistical cycles, the target time for the IO device to send the next DMA descriptor is predicted based on this average. Specifically, the prediction method utilizes the known average unit data transfer time, combined with currently available information, such as the timestamp of the last DMA descriptor transmission, to infer the likely time point for the next DMA descriptor transmission. This prediction process is based on the IO device's past behavior patterns. This approach allows for preemptive updates and adjustments to the IOTLB mapping table, enabling the system to better prepare for upcoming DMA operations, thereby improving DMA operation efficiency and overall system performance. In one example, the formula T_PRED = T_N+1 + PRED_PARAM_AVERAGE × (DMA_LENGTH_N) can be used as the predicted initiation time for T_N+2 DMA descriptors. If this initiation time is greater than a certain time threshold, it is determined that the IO device will not initiate a DMA operation within a certain period of time. At this time, the address mapping relationship corresponding to the IO device in the cache is cleared, and the saved cache is replaced with the IOVA and PA mapping relationships corresponding to other IO devices, thereby achieving timely replacement and updating of the IOMMU's internal cache. If the formula T_PRED = T_N+1 + PRED_PARAM_AVERAGE × (DMA_LENGTH_N) is used as the predicted time for T_N+2 DMA initiations, and if this time is within a certain time threshold, the IO device is predicted to initiate another DMA operation within the time threshold. Therefore, the corresponding IOVA and PA mapping in the IO device's cache is not processed and the next prediction is performed. It is important to note that PRED_PARAM_AVERAGE must also be continuously updated to further improve prediction accuracy.

[0087] In another embodiment, step S203 of “predicting a target time for the IO device to send the next DMA descriptor based on the average value” includes:

[0088] Determine the product of the average value and the length information;

[0089] The sum of the timestamp and product of the DMA descriptor last sent by the IO device is determined as the target time.

[0090] In this embodiment, to predict the target time for the IO device to send the next DMA descriptor, the average value is first multiplied by the current DMA descriptor length information. The timestamp of the DMA descriptor last sent by the IO device is then added to this product. The result is the predicted target time for the IO device to send the next DMA descriptor. In one example, the target time for the IO device to send the next DMA descriptor can be calculated based on the following formula: T_PRED = T_N+1 + PRED_PARAM_AVERAGE × (DMA_LENGTH_N), where T_N+1 is the timestamp of the last DMA descriptor sent by the IO device, PRED_PARAM_AVERAGE is the average value, and DMA_LENGTH_N is the current DMA descriptor length information. T_PRED is actually the possible send time of N+2 DMA descriptors.

[0091] In another embodiment, step S203 of “predicting a target time for the IO device to send the next DMA descriptor based on the average value” includes:

[0092] Determine the product of the average value and the length information;

[0093] Determine the difference between the actual timestamp of the DMA descriptor last sent by the IO device and the target time;

[0094] The actual timestamp, the product, and the sum of the differences are determined as the target time.

[0095] To further improve prediction accuracy, in this embodiment, in addition to calculating the product of the average value and the current DMA descriptor length, the difference between the actual timestamp of the last DMA descriptor sent by the IO device and the previously predicted target time is also calculated. This difference reflects the degree of deviation between the actual occurrence time of the last DMA descriptor sent by the IO device and the predicted time. The actual timestamp, the product of the previously calculated average value and the length information, and the difference are then added together to obtain the new target time. In one example, the target time T_PRED_OPT for the IO device to send the next DMA descriptor can be calculated using the following formula: T_PRED_OPT = T_N+1 + PRED_PARAM_AVERAGE × (DMA_LENGTH_N) + (T_REAL - T_PRED). T_N+1 is the timestamp of the DMA descriptor sent by the IO device for the last time (i.e., N+1 times), PRED_PARAM_AVERAGE is the average, DMA_LENGTH_N is the length of the current DMA descriptor, T_REAL is the real timestamp of the DMA descriptor sent N+1 times, and T_PRED is the target time of the DMA descriptor sent N+1 times. T_PRED is actually the possible send time of N+2 DMA descriptors. This allows for a more accurate target time.

[0096] In another embodiment, step S204 “updating the IOTLB mapping table based on the target time” includes:

[0097] In response to the target time being greater than the first threshold, a mapping relationship between the virtual address and the physical address corresponding to the IO device is deleted from the mapping table of the IOTLB.

[0098] In this embodiment, when the predicted target time for the IO device to send the next DMA descriptor is greater than the set first threshold, corresponding measures will be taken. The first threshold is a time threshold pre-set according to the system's performance requirements and actual operating conditions, and is used to determine whether the IO device will initiate a DMA operation again within a certain period of time. If the target time is greater than the first threshold, it means that the IO device may not initiate a DMA operation again within a relatively long period of time. At this time, in order to improve the storage efficiency and utilization of the IOTLB mapping table, the mapping relationship between the virtual address and the physical address corresponding to the IO device will be deleted in the IOTLB mapping table, thereby freeing up the storage space occupied in the IOTLB mapping table so that these spaces can be used by other IO devices that need them more, thereby improving the resource utilization efficiency and performance of the entire system.

[0099] In another embodiment, a direct memory access control method further includes:

[0100] In response to the priority of the IO device being greater than the second threshold, a mapping relationship between the virtual address and the physical address corresponding to the IO device is retained in a mapping table of the IOTLB.

[0101] In this embodiment, in addition to considering the target time for the IO device to send the next DMA descriptor, the priority of the IO device is also comprehensively considered. If the priority of the IO device is greater than the set second threshold, even if the target time predicted by the IO device is greater than the first threshold, the mapping relationship between the virtual address and the physical address corresponding to the IO device will be retained in the mapping table of the IOTLB, thereby ensuring the priority processing of important processes and the reliability of the system.

[0102] In another embodiment, a direct memory access control method further includes:

[0103] Determine an IO device whose frequency of sending DMA descriptors is greater than a third threshold as a first target IO device;

[0104] Determine the IO device whose mapping relationship between the corresponding virtual address and the physical address is only stored in the memory as the second target IO device;

[0105] The mapping relationship between the virtual address and the physical address corresponding to the first target IO device and / or the second target IO device is updated into the mapping table of the IOTLB.

[0106] In this embodiment, the first target IO device is determined based on the frequency at which the IO device sends DMA descriptors. If the frequency at which an IO device sends DMA descriptors is greater than a set third threshold, then this IO device is determined to be the first target IO device. At the same time, the IO devices whose corresponding mapping relationships between virtual addresses and physical addresses are only stored in the memory are determined to be the second target IO devices, that is, low-hit devices. For these two target IO devices, the mapping relationships between their corresponding virtual addresses and physical addresses are updated to the mapping table of the IOTLB, thereby improving the DMA operation efficiency of these IO devices that frequently send DMA descriptors or need to look up the corresponding mapping relationships between virtual addresses and physical addresses in the memory. In one example, if the mapping relationships between the virtual addresses and physical addresses corresponding to IO device 0 and IO device 5 are deleted in the mapping table of the IOTLB, the mapping relationships between IOVA and PA corresponding to the frequently accessed IO device 2 and the low-hit IO device 7 can be updated to the cache space corresponding to the original IO device 0 and IO device 5.

[0107] Figure 5 A schematic structural diagram of a direct memory access control system according to an embodiment of the present disclosure is shown; Figure 6 The structural diagram of the mapping table update module according to the embodiment of the present disclosure is shown as follows: Figure 5 and Figure 6 As shown, a direct memory access control system includes:

[0108] A mapping table update module, which includes a register configuration submodule, a query submodule, and an update submodule;

[0109] The register configuration submodule is used to receive the direct memory access (DMA) descriptor sent by the driver of the input and output (IO) device; the DMA descriptor includes the starting address, length information and identifier of the virtual address corresponding to the DMA operation;

[0110] A query submodule is used to query a target mapping relationship between a virtual address and a physical address corresponding to a DMA operation in a mapping table of an input / output translation lookaside buffer (IOTLB) based on a DMA descriptor; the mapping table is stored in a cache;

[0111] The update submodule is used to query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory based on the DMA descriptor in response to the absence of the target mapping relationship in the mapping table of the IOTLB, and update the target mapping relationship to the mapping table of the IOTLB.

[0112] In one embodiment, the mapping table update module also includes a monitoring submodule; the monitoring submodule is used to monitor the sending order of the DMA descriptors of each IO device and send the sending order to the update submodule; the update submodule is also used to query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory in the sending order based on each DMA descriptor, and update the target mapping relationship to the mapping table of the IOTLB.

[0113] In one embodiment, the query submodule is further used to: in response to the existence of a target mapping relationship in the mapping table of the IOTLB, based on the received next DMA descriptor, query the mapping table of the IOTLB for a target mapping relationship between the virtual address and the physical address corresponding to the next DMA descriptor.

[0114] Figure 7 FIG. 1 shows a schematic diagram of the structure of the virtual address processing module according to an embodiment of the present disclosure. Figure 5 He Ru Figure 7As shown, a direct memory access control system also includes a virtual address processing module, which includes: a sequence checking submodule, a generation submodule, and a deletion submodule; the sequence checking submodule is also used to obtain the sequence information of all virtual addresses and corresponding physical addresses; the sequence information includes the starting address and length information; the generation submodule is also used to generate a sequence mapping table based on the sequence information; the deletion submodule is also used to delete the mapping relationship that already exists in the sequence mapping table in the IOTLB mapping table.

[0115] In one embodiment, the virtual address processing module also includes: a table lookup enable module, which is used to: based on the DMA descriptor, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the sequential mapping table; in response to the absence of the target mapping relationship in the sequential mapping table, query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the mapping table of the IOTLB.

[0116] In one possible implementation, a direct memory access control system further includes: a resource release module, configured to: obtain the timestamp and length information of each DMA descriptor sent by the IO device; determine the unit data transmission time of the statistical period corresponding to the two adjacent DMA descriptors based on the timestamps corresponding to the two adjacent DMA descriptors and the length information of the previous DMA descriptor, and determine the average value of all unit data transmission times; predict the target time for the IO device to send the next DMA descriptor based on the average value; and update the mapping table of the IOTLB based on the target time.

[0117] In one possible implementation, the resource release module is further configured to: determine the product of the average value and the length information; and determine the sum of the timestamp of the DMA descriptor last sent by the IO device and the product as the target time.

[0118] In one embodiment, the resource release module is further used to: determine the product of the average value and the length information; determine the difference between the actual timestamp of the DMA descriptor last sent by the IO device and the target time; and determine the sum of the actual timestamp, the product and the difference as the target time.

[0119] In one embodiment, the resource releasing module is further configured to: in response to the target time being greater than the first threshold, delete the mapping relationship between the virtual address and the physical address corresponding to the IO device in the mapping table of the IOTLB.

[0120] In one embodiment, a direct memory access control system further includes: an important IO processing module, configured to: in response to the priority of the IO device being greater than a second threshold, retain a mapping relationship between a virtual address and a physical address corresponding to the IO device in a mapping table of the IOTLB.

[0121] In one possible implementation, a direct memory access control system further includes: a DMA status detection module, configured to: determine an IO device whose frequency of sending DMA descriptors is greater than a third threshold as a first target IO device; determine an IO device whose corresponding mapping relationship between virtual addresses and physical addresses is only stored in memory as a second target IO device; and update the mapping relationship between the virtual addresses and physical addresses corresponding to the first target IO device and / or the second target IO device into a mapping table of the IOTLB.

[0122] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0123] Figure 8 A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0124] like Figure 8 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. Computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to bus 804.

[0125] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0126] The computing unit 801 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as a direct memory access control method. For example, in some embodiments, a direct memory access control method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the direct memory access control method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform a direct memory access control method by any other suitable means (e.g., via firmware).

[0127] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0128] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0129] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0130] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0131] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0132] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0133] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0134] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0135] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A direct memory access control method, characterized in that: The method comprises: Receive a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device; the DMA descriptor includes a starting address and length information of a virtual address corresponding to a DMA operation and an identifier of the IO device; Based on the DMA descriptor, querying a mapping table of an input / output translation lookaside buffer (IOTLB) for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation; the mapping table is stored in a cache; In response to the target mapping relationship not existing in the mapping table of the IOTLB, querying the page table of the memory for a target mapping relationship between the virtual address and the physical address corresponding to the DMA operation based on the DMA descriptor, and updating the target mapping relationship into the mapping table of the IOTLB; The method further comprises: Obtain the timestamp and length information of each time the IO device sends the DMA descriptor; Determine, based on the timestamps corresponding to the two adjacent DMA descriptors and the length information of the previous DMA descriptor, the unit data transmission time of the statistical period corresponding to the two adjacent DMA descriptors, and determine the average value of all the unit data transmission times; Based on the average value, predicting a target time for the IO device to send a next DMA descriptor; Based on the target time, the mapping table of the IOTLB is updated.

2. The method according to claim 1, characterized in that The querying, based on the DMA descriptor, a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation in a page table of a memory, and updating the target mapping relationship into a mapping table of the IOTLB includes: Obtaining the sending order of the DMA descriptors of each of the IO devices; Based on each of the DMA descriptors, a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation is searched in a page table of a memory in the sending order, and the target mapping relationship is updated into a mapping table of the IOTLB.

3. The method according to claim 1, characterized in that The method further comprises: In response to the target mapping relationship existing in the mapping table of the IOTLB, based on the received next DMA descriptor, the target mapping relationship between the virtual address and the physical address corresponding to the next DMA descriptor is queried in the mapping table of the IOTLB.

4. The method according to claim 1, wherein Before querying a mapping table of an input / output translation lookaside buffer (IOTLB) based on the DMA descriptor for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation, the method further includes: Obtaining sequential information of all virtual addresses and corresponding physical addresses; the sequential information includes starting address and length information; generating a sequence mapping table based on the sequential information; The mapping relationship already existing in the sequential mapping table is deleted from the mapping table of the IOTLB.

5. The method according to claim 4, characterized in that After receiving the direct memory access (DMA) descriptor sent by the driver of the input / output (IO) device, the method further includes: Based on the DMA descriptor, querying the sequential mapping table for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation; In response to the target mapping relationship not existing in the sequential mapping table, a target mapping relationship between the virtual address and the physical address corresponding to the DMA operation is queried in the mapping table of the IOTLB.

6. The method according to claim 1, characterized in that The predicting, based on the average value, a target time for the IO device to send a next DMA descriptor includes: determining a product of the average value and the length information; The sum of the timestamp of the DMA descriptor last sent by the IO device and the product is determined as the target time.

7. The method according to claim 1, characterized in that The predicting, based on the average value, a target time for the IO device to send a next DMA descriptor includes: determining a product of the average value and the length information; Determine the difference between the actual timestamp of the DMA descriptor last sent by the IO device and the target time; The target time is determined as a sum of the actual timestamp, the product, and the difference.

8. The method according to claim 1, characterized in that The updating of the IOTLB mapping table based on the target time includes: In response to the target time being greater than a first threshold, a mapping relationship between the virtual address and the physical address corresponding to the IO device is deleted from the mapping table of the IOTLB.

9. The method according to claim 8, characterized in that The method further comprises: In response to the priority of the IO device being greater than a second threshold, a mapping relationship between a virtual address and a physical address corresponding to the IO device is retained in a mapping table of the IOTLB.

10. The method according to claim 8, characterized in that The method further comprises: Determine the IO device whose frequency of sending the DMA descriptor is greater than a third threshold as a first target IO device; Determine the IO device whose corresponding mapping relationship between the virtual address and the physical address is stored only in the memory as the second target IO device; The mapping relationship between the virtual address and the physical address corresponding to the first target IO device and / or the second target IO device is updated into the mapping table of the IOTLB.

11. A direct memory access control system, characterized in that: The system comprises: A mapping table update module, comprising a register configuration submodule, a query submodule, and an update submodule; The register configuration submodule is used to receive a direct memory access (DMA) descriptor sent by a driver of an input / output (IO) device; the DMA descriptor includes a starting address and length information of a virtual address corresponding to a DMA operation and an identifier of the IO device; The query submodule is configured to query a mapping table of an input / output translation lookaside buffer (IOTLB) based on the DMA descriptor for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation; the mapping table is stored in a cache; The updating submodule is configured to query a page table of a memory for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation based on the DMA descriptor in response to the target mapping relationship not existing in the mapping table of the IOTLB, and update the target mapping relationship into the mapping table of the IOTLB; The resource release module is configured to obtain the timestamp and length information of each DMA descriptor sent by the IO device; determine the unit data transmission time of the statistical period corresponding to the two adjacent DMA descriptors based on the timestamps corresponding to the two adjacent DMA descriptors and the length information of the previous DMA descriptor, and determine the average value of all the unit data transmission times; predict the target time for the IO device to send the next DMA descriptor based on the average value; and update the mapping table of the IOTLB based on the target time.

12. The system according to claim 11, wherein: The mapping table updating module also includes a monitoring submodule; The monitoring submodule is configured to monitor the sending order of the DMA descriptors of each of the IO devices and send the sending order to the updating submodule; The update submodule is further used to query the target mapping relationship between the virtual address and the physical address corresponding to the DMA operation in the page table of the memory in the sending order based on each of the DMA descriptors, and update the target mapping relationship into the mapping table of the IOTLB.

13. The system according to claim 11, wherein: The query submodule is further used to: In response to the target mapping relationship existing in the mapping table of the IOTLB, based on the received next DMA descriptor, the target mapping relationship between the virtual address and the physical address corresponding to the next DMA descriptor is queried in the mapping table of the IOTLB.

14. The system according to claim 11, wherein: The system further comprises: a virtual address processing module; the virtual address processing module comprises: a sequence checking submodule, a generating submodule, and a deleting submodule; The sequence checking submodule is further used to obtain sequence information of all virtual addresses and corresponding physical addresses; the sequence information includes starting address and length information; The generating submodule is further configured to generate a sequence mapping table based on the sequential information; The deleting submodule is further configured to delete, from the mapping table of the IOTLB, the mapping relationship that already exists in the sequential mapping table.

15. The system according to claim 14, wherein: The virtual address processing module further includes a table lookup enabling module, which is configured to: Based on the DMA descriptor, querying the sequential mapping table for a target mapping relationship between a virtual address and a physical address corresponding to the DMA operation; In response to the target mapping relationship not existing in the sequential mapping table, a target mapping relationship between the virtual address and the physical address corresponding to the DMA operation is queried in the mapping table of the IOTLB.

16. The system according to claim 11, wherein: The resource release module is further configured to: determining a product of the average value and the length information; The sum of the timestamp of the DMA descriptor last sent by the IO device and the product is determined as the target time.

17. An electronic device, characterized in that: include: A direct memory access control system as claimed in any one of claims 11 to 16.

18. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 1-10.

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