Embedded Program Integrity Multi-Granularity Verification System and Method Based on On-Chip Hardware

Abstract

The present invention belongs to the technical field of information security of embedded systems, and discloses an embedded program integrity multi-granularity verification system and method based on on-chip hardware. The present invention supports setting the program integrity verification granularity to instruction level, basic block level, function level, and hybrid level through hardware and software methods, which is convenient for users to operate and enriches user choices; at the same time, the present invention relies on the hash table algorithm and stack structure to improve the efficiency of reference label storage and retrieval; in addition, based on the characteristics of the sponge structure hash function, the present invention adopts multi-channel calculation of hash values, which not only increases the difficulty of external attacks to damage the code, but also effectively reduces the time delay of hash calculation; furthermore, the dual verification mechanism based on sampled values and random numbers adopted by the present invention can not only reduce the space occupied by reference label storage, but also detect errors as early as possible, alleviating the inherent lag of program integrity verification, and is applicable to the security protection and program integrity verification of embedded systems.

Description

Technical Field

[0001] The present invention belongs to the technical field of information security of embedded systems, and particularly relates to an embedded program integrity multi-granularity verification system and method based on on-chip hardware, which is particularly suitable for the security protection and program integrity verification of embedded systems. Background Art

[0002] As an important protected object of the security mechanism of embedded systems, program integrity is such that any tampering or destruction of program code may lead to abnormal execution of system functions, data leakage, or even serious security accidents. The program integrity verification mechanism aims to ensure that the embedded program code always remains in a state where it has not been illegally tampered with or destroyed during compilation, deployment, and operation.

[0003] The current program integrity verification methods for program execution mainly adopt the method of comparing reference tags and actual tags (such as digital signatures, hash values) to verify the integrity of the code. First, in the pre-analysis stage, a customized analysis tool is used to calculate the reference tags of each granularity in the program, and these tags are embedded into the binary code or stored separately in a fixed area. In the execution stage of the user program, the program integrity verification mechanism, based on the key information in the pipeline, sequentially executes steps such as granularity boundary recognition, reference tag extraction, and actual tag calculation. Finally, by comparing the reference tag and the actual tag, it is determined whether the program integrity within the current granularity of the user program has been damaged.

[0004] When the reference tags are stored in a specific area, the program integrity verification mechanism can only use discontinuous granularity boundary addresses as indexes for retrieval. This approach not only results in inefficient use of storage space but also slows down the retrieval speed of the reference tags. Although embedding the reference tags into the executable binary code of the user program can simplify the retrieval process to a certain extent, it usually involves complex modifications to the compilation tool chain and the processor pipeline, and has problems such as poor portability and high implementation difficulty. In addition, the calculation of the actual tags usually consumes a large number of clock cycles and hardware resources, which not only increases the overhead of the program integrity verification mechanism but also drags down the efficiency of the processor pipeline in executing the user program and the program integrity verification mechanism in verifying program integrity.

[0005] The program integrity verification mechanism has an inherent "lag" in verifying program integrity, that is, only after all instructions of a granularity enter the pipeline can the verification result of the program integrity of that granularity be output. This means that if a tampered instruction has been executed before the program integrity verification mechanism triggers an exception alarm, especially when the instruction involves sensitive operations such as writing to external memory, it may cause serious and irreversible consequences. This shows that simply taking multiple instructions as an integrity verification granularity may not provide sufficient security in some cases. Summary of the Invention

[0006] The object of the present invention is to propose an embedded program integrity multi-granularity verification system based on on-chip hardware, which supports setting the program integrity verification granularity to instruction level, basic block level, function level and mixed level through hardware or software; with the support of the program integrity multi-granularity verification module, the overhead of retrieving reference tags and calculating actual tags during the program integrity verification process can be reduced, and the inherent lag of the program integrity verification can be effectively alleviated.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] An embedded program integrity multi-granularity verification system based on on-chip hardware includes a program integrity multi-granularity verification module, a processor pipeline, an on-chip memory, and a flash memory controller;

[0009] Among them, the program integrity verification granularity is set to instruction level, basic block level, function level and mixed level;

[0010] The program integrity multi-granularity verification module includes:

[0011] An instruction analyzer, which is responsible for the interaction between the program integrity multi-granularity verification module and the processor pipeline, and is built-in with a synchronous decoder, a granularity register and its setting circuit, and a sensitive instruction type register group;

[0012] A lightweight hash calculator, which uses a hash function with a sponge structure to calculate the actual hash values of each granularity;

[0013] A hash table memory, which takes functions as basic units and is used to store storage information about each reference tag, and assists in locating the position of the reference tag of the granularity belonging to the current function in the flash memory at one time;

[0014] Among them, the reference tag consists of a reference sampling value, a reference random value and an offset value;

[0015] A hash table mapper, which is used to map the sensitive instruction address or the entry address of the function to the corresponding address in the hash table memory;

[0016] A metadata cache, which is used to store the reference tags of the current granularity and manages the reference tags using a stack structure;

[0017] And a checker, which is used to compare the reference tag and the actual tag, detect the granularity where the program integrity is damaged, and the checker is built-in with a random number generator, a sampling bitmap, a sampling value register and an exception code address register.

[0018] In addition, the present invention also provides a method for multi-granularity verification of the integrity of an embedded program based on on-chip hardware corresponding to the above multi-granularity verification system for the integrity of an embedded program based on on-chip hardware, which adopts the following technical solutions:

[0019] The method for multi-granularity verification of the integrity of an embedded program based on on-chip hardware includes the following steps:

[0020] Step 1. Select the granularity of program integrity verification and simulate the execution process of the user program;

[0021] Obtain the path information of the user program, and construct a call relationship tree diagram and the metadata required for program integrity verification; among them, the metadata includes the reference tags of each granularity and their storage information;

[0022] Step 2. Power on and initialize;

[0023] Step 3. The pipeline continues to run, and the lightweight hash calculator absorbs the instructions entering the decoding stage;

[0024] Step 4. The instruction analyzer analyzes the nature of the instructions in the decoding stage according to the set granularity of program integrity verification;

[0025] When a sensitive instruction is detected, the pipeline is paused and Step 5 is executed; when a function call instruction is detected, Step 5 is directly executed; when a function return instruction or a jump instruction is detected, Step 6 is executed; in other cases, Step 3 is executed;

[0026] Step 5. The hash table mapper maps the address of the sensitive instruction or the entry address of the called function to the address in the hash table memory of the storage information of its reference tag, and extracts the reference tag to the metadata cache; at the same time, the random number generator uses the address of the sensitive instruction or the entry address of the called function as the random number seed to generate a random number sequence; each random number is not greater than the sum of the lengths of the partial hash values squeezed out for the first time by all channels of the lightweight hash calculator, and then go to Step 6;

[0027] Step 6. The lightweight hash calculator enters the squeezing stage, and the verifier samples the first partial hash value output by each channel of the lightweight hash calculator using the random number sequence generated by the random number generator; every time a sampling is completed, the bit position of the used random number in the sampling bitmap is set to 1, and the actual sampling value and the reference sampling value are compared during the sampling process;

[0028] If they are consistent, the random number generator generates a random number with the sum of the mean of the partial hash values squeezed out in two adjacent times and the first partial hash value squeezed out earlier as the random number seed, otherwise execute Step 9;

[0029] Step 7. The random number generator uses the sum of the mean of two consecutive random numbers in the generation order and the first random number generated earlier as the random number seed, and continues to generate random numbers in this iterative process until the last random number is generated;

[0030] Step 8. The verifier clears the sampling bitmap and determines whether the generated actual random number is consistent with the reference random value; if they are consistent, it executes step 3; otherwise, it executes step 9;

[0031] Step 9. The checker issues an alarm signal and writes the entry address of the function / basic block where the program integrity is destroyed or the address of the sensitive instruction into the exception code address register.

[0032] The present invention has the following advantages:

[0033] As described above, the present invention describes a multi-granularity verification system and method for embedded program integrity based on on-chip hardware. The present invention supports setting the program integrity verification granularity to instruction level, basic block level, function level, and mixed level through hardware and software, facilitating user operation and enriching user choices. At the same time, the present invention relies on hash table algorithms and stack structures to improve the efficiency of reference tag storage and retrieval. Furthermore, based on the characteristics of sponge-structured hash functions, the present invention uses multi-channel hash value calculations, which increases the difficulty of external attacks destroying the code and effectively reduces the time delay of hash calculations. Furthermore, the dual verification mechanism based on sampling values and random numbers adopted by the present invention can reduce the space occupied by reference tag storage and detect errors as early as possible, thereby effectively alleviating the inherent lag in program integrity verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 1 is a structural block diagram of a multi-granularity verification system for embedded program integrity based on on-chip hardware in an embodiment of the present invention;

[0035] Figure 2 Flowchart of a multi-granularity verification method for embedded program integrity based on on-chip hardware in an embodiment of the present invention;

[0036] Figure 3 It is a call relationship tree diagram of the pseudo code in the specific example of the present invention;

[0037] Figure 4 Schematic diagram of the process of retrieving reference tags in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0038] This embodiment describes an embedded program integrity multi-granularity verification system and method based on on-chip hardware. The invention supports the verification of program integrity at four granularities: instruction level, basic block level, function level, and hybrid level. It realizes the efficient extraction, storage, and retrieval of reference tags, the fast operation of actual tags, the fast comparison of reference tags and actual tags, and the interaction between the on-chip program integrity verification module and the pipeline during the process of verifying program integrity through the cooperation of software and hardware. It effectively alleviates the inherent lag of program integrity verification, reduces the loss of the security defense mechanism to program execution efficiency and system performance while enhancing the security of the embedded system, and achieves the balance of security, performance, and overhead.

[0039] The following further elaborates on the present invention in conjunction with the accompanying drawings and specific embodiments:

[0040] Embodiment 1

[0041] As Figure 1 shown, the embedded program integrity multi-granularity verification system based on on-chip hardware in this Embodiment 1 includes a program integrity multi-granularity module, a processor pipeline, an on-chip memory, and a flash memory controller.

[0042] The program integrity multi-granularity verification module includes: an instruction analyzer, a lightweight hash calculator, a hash table mapper, a hash table memory, a metadata cache, and a checker. The functions of each part of the program integrity multi-granularity verification module are as follows:

[0043] The instruction analyzer is responsible for the interaction between the program integrity multi-granularity verification module and the processor pipeline, and includes a synchronous decoder, a granularity register and its setting circuit, and a sensitive instruction type register group.

[0044] The instruction analyzer sets the granularity register to a value indicating the four levels of program integrity verification granularity: instruction level, basic block level, function level, and hybrid level by identifying write instructions that write to specific addresses or detecting signals from an external dedicated key circuit; the characteristics that can characterize sensitive instructions can be written into one register in the sensitive instruction type register group through write instructions or an external dedicated key circuit. Among them, the characteristics that can characterize sensitive instructions are machine code fields selected according to the instruction set, including but not limited to the opcode and function bits (func3, func7) fields of the RISC-V instruction set.

[0045] The synchronous decoder executes an analysis strategy that matches the set granularity according to the value of the granularity register, and synchronously analyzes the instructions entering the pipeline decoding stage. When the synchronous decoder identifies an instruction that matches one of the instruction types recorded in the sensitive instruction type register group, it immediately issues a pipeline pause signal until the integrity verification of the instruction is completed.

[0046] The granularity register consists of 3 bits, corresponding to instruction-level, basic block-level, and function-level granularities respectively. When the synchronous decoder recognizes a specific write instruction or receives a signal from the external dedicated key circuit, the corresponding bit in the granularity register is set to 1. When only one bit is set to 1, it means only the program integrity at the granularity corresponding to this bit is verified. When two or three bits are set to 1, it means it is set to the mixed-level granularity, supporting the verification of the program integrity at multiple granularities.

[0047] Specifically, when the bit corresponding to the instruction-level granularity in the granularity register is set to 1, the opcode of the sensitive instruction and the func3 and func7 fields can be written into one of the registers in the sensitive instruction type register group through a write instruction or the external dedicated key circuit. When the synchronous decoder recognizes an instruction that matches one of the instruction types recorded in the sensitive instruction type register group, it immediately issues a pipeline pause signal until the integrity verification of this instruction is completed.

[0048] The lightweight hash calculator uses a hash function with a sponge structure to calculate the actual hash values at each granularity. It has T + 1 built-in channels, where T is the number of clock cycles required to complete one absorption or squeezing. Each channel is a pipeline that can independently absorb instructions and squeeze hash values. Every time the lightweight hash calculator absorbs a branch instruction, it backs up the states of all channels. When the instruction analyzer detects a branch prediction failure, all channels restore to the backed-up states and continue to absorb subsequent instructions.

[0049] The hash table mapper is used to map the address of the sensitive instruction or the entry address of the function (collectively referred to as the addresses at each granularity) to an address in the hash table memory.

[0050] The hash table memory stores the storage information about each reference label in units of functions, and is used to assist in locating the position of the reference label belonging to the current function granularity in the flash memory at one time.

[0051] Among them, the storage information of each reference label refers to the storage address and length of the reference label in the flash memory.

[0052] The metadata cache is used to store the reference labels at the current granularity. The metadata cache adopts a stack structure and organizes each reference label in the order of execution in units of functions internally. The reference label of the newly executed function is always at the top of the stack. When the function execution is completed, a pop operation is performed to make the reference label of the previous called function return to the top of the stack.

[0053] The checker is used to compare the reference label and the actual label to quickly detect the granularity whose program integrity is damaged. It has a built-in random number generator, sampling bitmap, sampling value register, and exception code address register.

[0054] On the one hand, a random number sequence is generated using the addresses of each granularity as random number seeds. On the other hand, the mean value of the adjacent output hash values of each channel or the mean value of the already generated random numbers is used as a random number seed to generate the actual random numbers corresponding to each granularity.

[0055] The verifier samples the first partial hash values extruded by each channel of the lightweight hash calculator according to the random number sequence generated by the random number generator, uses a sampling bitmap to record the sampling process. For each sampling, the actual sampling value is compared with the reference sampling value during the sampling process, and at the same time, the bit positions of the random numbers in the sampling bitmap are set to 1; when the actual sampling value and the reference sampling value are exactly the same, the verifier needs to further compare the finally generated actual random numbers and the reference random values.

[0056] The exception code address register built into the verifier consists of two parts: the address of the granularity where the program integrity is damaged and the status exception flag bit. The status exception flag bit is set to 1 when it is detected that the program integrity is damaged.

[0057] In this embodiment, the processor pipeline, for example, adopts a five-stage pipeline, which includes five stages: fetching, decoding, executing, memory access, and write-back. The on-chip memory includes flash memory, instruction memory, and data memory.

[0058] Among them, the flash memory is divided into four regions: a bootloader area, a user program area, a reference tag area, and other data areas. During the system startup process, the user program and its data are copied to the instruction memory and the data memory respectively through the system bus, and the reference tags of each granularity are written into the metadata buffer through the flash memory controller.

[0059] Custom Processor is a processor after customized modification, which integrates a multi-granularity verification module for program integrity internally, supports setting the granularity of verifying program integrity through software and hardware methods, and efficiently verifies the program integrity of the set granularity.

[0060] SoC, that is, System on Chip, is composed of Custom Processor, on-chip memory, flash memory controller, and system bus. The multi-granularity verification system for program integrity runs on this SoC.

[0061] Embodiment 2

[0062] This Embodiment 2 describes a multi-granularity verification method for embedded program integrity based on on-chip hardware, which is implemented based on the multi-granularity verification system for embedded program integrity based on on-chip hardware in the above Embodiment 1.

[0063] As Figure 2 shown, the multi-granularity verification method for embedded program integrity based on on-chip hardware includes the following steps:

[0064] Step 1. Select the program integrity verification granularity, simulate the execution process of the user program, obtain the path information of the user program, and construct a call relationship tree diagram and the metadata required for program integrity verification.

[0065] Among them, the metadata includes the reference tags of each granularity and their storage information. The reference tag consists of a reference sampling value, a reference random value, and an offset value. The metadata is constructed by a custom script through analyzing the path information of the user program in accordance with the method of hardware verifying program integrity.

[0066] The program integrity verification granularities available for the user to select are divided into four types: instruction level, basic block level, function level, and hybrid level. Among them, the instruction level, basic block level, and function level respectively represent verifying program integrity when the processor pipeline finishes decoding a sensitive instruction, a basic block, and a function. The hybrid level is obtained by combining three or two of the instruction level granularity, basic block level granularity, and function level granularity: The hybrid level granularity composed of the instruction level granularity means that during the process of decoding a basic block or function, if a preset sensitive instruction is found, it is necessary to give priority to verifying the program integrity of the sensitive instruction. At the same time, the hybrid level granularity composed of the basic block level and function level granularities means that not only the program integrity needs to be verified when the pipeline finishes decoding a basic block or function each time, but also the previously verified basic block is required to be used as a parameter for verifying the program integrity of the subsequent basic blocks, so as to verify the control flow integrity while verifying the program integrity.

[0067] Among them, the sensitive instruction refers to a specific instruction type involving a certain operation or operation, which is specified by the user through software and hardware according to security needs.

[0068] Since a function usually contains multiple basic blocks, the metadata required for verifying the program integrity at the function level granularity is less than that at the basic block level. While verifying the program integrity, it can also verify the execution order of each basic block, but the latency of error discovery is greater than that at the basic block level. The hybrid level that combines the basic block level granularity and the function level granularity can take into account both the control flow integrity and the program integrity. When calculating the actual tag of the next basic block, it is necessary to inherit the state calculated last time. Each time a basic block or function is executed, it is compared with the reference tag once, so as to alleviate the latency of verifying the control flow integrity and program integrity at the function level granularity. Correspondingly, the hybrid level granularity requires the most metadata and consumes the largest storage space, and takes into account both the program integrity and the control flow integrity in security protection.

[0069] The process of simulating the execution of a user program refers to using software to create a simulation environment that matches the embedded processor architecture on which the user program runs, and running the compiled user program in this simulation environment. The software used to simulate the execution of the user program includes but is not necessarily limited to the hardware virtualization software QEMU (Quick Emulator).

[0070] The path information obtained from the user program simulation refers to the execution order of basic blocks and functions in the user program, the entry address of each basic block and the number of instructions and loop times it contains, the entry address of each function and the number of basic blocks and loop times it contains, and the call relationships between functions and between functions and basic blocks.

[0071] The nodes of the call relationship tree diagram correspond one by one to each basic block, function, and instruction on the execution path of the user program. The function is the parent node of the basic blocks and calling functions it contains, and all executed instructions are leaf nodes.

[0072] The metadata required for program integrity verification is constructed based on the obtained path information and call relationship tree diagram, and consists of an index, a collision flag bit, a reference tag, and its storage information.

[0073] Among them, the reference tag consists of a reference sampling value, a reference random value, and an offset value. The reference tags of basic blocks within the same function are continuously stored in the flash memory in the order of basic block execution, and the actual storage address of the reference tag in the flash memory under each function is calculated based on this storage method.

[0074] One index in the metadata corresponds to one entry in the hash table memory. The index of the metadata required to verify the program integrity at the instruction level granularity is obtained by performing a hash table mapping on the addresses of each sensitive operation instruction, and the index of the metadata required to verify the program integrity at the basic block level, function level, and mixed level granularity is obtained by performing a hash table mapping on the entry addresses of each function.

[0075] When there is no collision where multiple addresses are mapped to the same index, the collision flag bit is set to 0, and the storage information of the reference tag consists of the actual address of the reference tag in the flash memory and the number of basic blocks contained in the function to which it belongs. The collision flag bit and the storage information form the hash table entry pointed to by the index.

[0076] When addresses of multiple granularities are mapped to the same index by the hash table, the collision flag is set to 1. The lower x bits of these granularity addresses are intercepted (the selection of x needs to ensure that the lower x bits of each granularity address are different). Together with the actual address of the reference tag in the flash memory and the number of basic blocks included in the function to which it belongs, they form the storage information of the reference tags of these granularities and are continuously stored in a specific area of the hash table memory. The hash table entry pointed to by this index is composed of the number of collisions and the storage information of the reference tags. When reading the hash table entry pointed to by the collided index, first, it is determined that the index of this entry has a collision through the collision flag bit being 1. Then, the address of the storage information of the reference tag with index collision in the hash table is obtained, and it is determined whether this storage information is the storage information of the reference tag to be retrieved by comparing the lower x bits of each granularity address in the storage information.

[0077] The offset value refers to the difference between the storage address of the jump target reference tag and the storage address of the current reference tag. Whenever a granularity is executed, the metadata cache stack pointer quickly locks the reference tag of the next granularity to be executed by adding the offset value.

[0078] The reference tag of the granularity ending with a branch instruction contains two offset values, corresponding to the two cases of jumping and not jumping respectively; the reference tag of the granularity ending with a non - branch instruction only needs to contain one offset value.

[0079] The reference hash value of the instruction - level granularity metadata is obtained by performing a hash operation on sensitive instructions. The reference hash value of the basic - block - level granularity metadata is obtained by performing a hash operation on the instructions included in each basic block. The reference hash value of the function - level granularity metadata is obtained by performing a hash operation on the reference hash values of its internal basic blocks. The mixed - level granularity metadata simultaneously has the reference hash values of the granularity metadata it contains.

[0080] The hash operation uses a lightweight hash function with a sponge structure. Based on the characteristics that the sponge - structure hash function sequentially absorbs data blocks and sequentially squeezes out partial hash values, and each absorption or squeezing consumes several clock cycles, the hardware - implemented lightweight hash calculator uses multiple channels to calculate the reference hash value, and the process of software calculating the hash value is consistent with the process of hardware calculating the hash value. In the absorption stage of using software to calculate the hash value, except that the hash value of the instruction - level granularity can be directly calculated, the instructions within each basic block or function need to be grouped for absorption, and the number of groups N c is equal to the number of clock cycles consumed by the hardware to complete one absorption plus 1.

[0081] The reference sample value and the reference random value are generated based on the partial hash values output successively in the squeezing stage. The sample value is used to detect as early as possible the granularity whose program integrity is damaged before all partial hash values are output. The wider the width of the sample value, the better the effect.

[0082] The reference sample values are generated by sampling the reference hash values of this granularity with random numbers generated with the granularity address as the random number seed in the range [0: -1]. The random numbers are used to sample the reference hash values of this granularity to generate bit data. Among them, represents the number of bits of the hash value generated by the first extrusion, which represents both the length of the random number sequence generated with the granularity address as the random number seed and the bit width of the reference hash value.

[0083] The specific sampling process for generating the sample values is as follows:

[0084] The first partial hash values extruded from each channel are combined to form P1; with the current granularity address as the random number seed, w random numbers r i are generated to form a random number sequence, where i = 1, 2, 3... w, and each random number is not greater than the length of P1; according to the order of the random numbers in the random number sequence, the r i -th bit of P1 is selected, and finally a w-bit sample value is spliced.

[0085] In order to reduce the probability of misjudgment caused by the contingency that the reference sample values of two different hash values may be the same, reference random values are further generated according to the content of all partial hash values of each channel. The specific process is as follows: First, use the sum of the mean of the adjacent two output partial hash values (round down when the mean is not an integer) and the first partial hash value as the random number seed to generate a 33-bit random number; then continue to use the sum of the mean of the adjacent two generated random numbers and the first random number as the random number seed to continue generating random numbers, and so on by iteration. The finally generated random number is used as the reference random value.

[0086] With the assistance of the dual detection mechanism of sample values and random numbers, the relatively large reference hash values are no longer directly stored, the storage space occupied by the reference tags is effectively reduced, and the efficiency of program integrity verification is also improved.

[0087] Step 2. Power-on initialization.

[0088] The initialization process includes loading the reference tags regarding the first function or basic block into the metadata cache, downloading the remaining reference tags to the flash memory, loading the storage information into the hash table memory, and writing binary values representing the program integrity verification granularity at the instruction level, basic block level, function level, and mixed level into the granularity register in a software or hardware manner.

[0089] Set the granularity register in a software or hardware manner.

[0090] Among them, the granularity register consists of 3 bits, corresponding to the instruction-level, basic block-level, and function-level granularities respectively. It supports setting each bit in the granularity register to 1 through a write instruction or a dedicated key circuit. When only one bit is set to 1, it means only verifying the program integrity at a single level of granularity. When two or three bits are set to 1, it means setting to a mixed-level granularity and initiating verification of the program integrity at multiple granularities. In addition, if the set program integrity verification granularity is the instruction-level granularity or a mixed-level granularity that includes the instruction-level granularity, that is, when the bit corresponding to the instruction-level granularity is set to 1, it is also necessary to write the machine code field that can characterize the sensitive instruction type into the instruction type register group of the instruction analyzer.

[0091] Step 3. The pipeline continues to run, and the lightweight hash calculator absorbs the instructions entering the decoding stage.

[0092] The hardware-implemented lightweight hash calculator is consistent with the method of calculating the hash value in Step 1, ensuring that when operating normally and not damaged by external attacks, for the same input code, it can output a hash value that is exactly the same as the reference hash value.

[0093] The lightweight hash calculator uses multiple channels to calculate the actual hash values at each granularity. Each channel can independently absorb instructions and output hash values. The number of channels c is equal to the number of clock cycles T + 1 required for a channel to complete one absorption or extrusion. This makes it such that in the next cycle after the (T + 1)-th channel starts absorbing instructions, the 1st channel just finishes absorbing the old instructions. Therefore, the 1st channel is selected to continue absorbing the next instruction. Similarly, the 2nd, 3rd, and (T + 1)-th channels also sequentially complete the absorption of the old instructions and continue to absorb new instructions, realizing the continuous absorption of instructions by the lightweight hash calculator. Except when calculating the hash value at the function-level granularity or a mixed granularity composed of the function-level granularity where the absorption result of the previous round needs to be used as the initial state for the next round of absorption, each new round of absorption restores to the initial state.

[0094] In addition, to avoid having some instructions wrongly enter the decoding stage in a short period due to branch prediction failure, every time a branch instruction is absorbed, the lightweight hash calculator needs to back up the absorption state at this time. When detecting the branch prediction failure signal, the lightweight hash calculator restores to the backed-up absorption state and re-absorbs the subsequent instructions entering the decoding stage.

[0095] Step 4. The instruction analyzer analyzes the nature of the instructions in the decoding stage according to the set program integrity verification granularity. When detecting a sensitive instruction, it pauses the pipeline and executes Step 5. When detecting a function call instruction, it directly executes Step 5. When detecting a function return instruction or a jump instruction, it executes Step 6. In other cases, it executes Step 3.

[0096] The value of the granularity register determines the strategy for analyzing the nature of instructions in the decoding stage of the program integrity verification mechanism. The synchronous decoder inside the instruction analyzer first determines the set program integrity verification granularity according to the value of the granularity register, and then selects the corresponding code analysis strategy:

[0097] For instruction-level granularity, the synchronous decoder determines whether the instruction is a sensitive instruction by comparing the characteristics of the instruction with those recorded in the instruction type register group, and issues a pipeline control signal when a sensitive instruction is detected, pausing the pipeline and executing step 5, otherwise executing step 3;

[0098] For basic block-level granularity, it is necessary to determine whether the instruction in the decoding stage is a jump instruction. The synchronous decoder determines whether the instruction is a jump instruction through the machine code field that can reflect the instruction type, such as the opcode, func3, and func7 fields of RISC-V instructions; if it is not a jump instruction, execute step 3, otherwise it is necessary to further determine whether the jump instruction is a function call instruction. If it is a function call instruction, execute step 5, otherwise execute step 6;

[0099] For function-level granularity, the synchronous decoder needs to determine whether the instruction is a function call or return instruction, including but not limited to call, ret, and other link jump instructions in the RISC-V instruction set; for function-level granularity, when it is determined that the instruction in the decoding stage is a function call instruction, execute step 5, and when it is determined that the instruction in the decoding stage is a function return instruction, execute step 6;

[0100] For mixed-level granularity, which includes the instruction analysis strategies of granularity, the synchronous decoder needs to execute all of them.

[0101] Of course, in this embodiment, the characteristics that can characterize sensitive instructions are the machine code fields selected according to the instruction set, including but not limited to the opcode and function bits (func3, func7) fields of the RISC-V instruction set.

[0102] Step 5. The hash table mapper maps the address of the sensitive instruction or the entry address of the called function to the address in the hash table memory where the storage information of its reference label is located, extracts the reference label to the metadata cache, and at the same time, the random number generator uses the address of the sensitive instruction or the entry address of the called function as the random number seed to generate a random number sequence, and each random number is not greater than the sum of the lengths of the partial hash values squeezed out by all channels of the lightweight hash calculator for the first time.

[0103] The hash table algorithm adopted in Step 5 is consistent with the hash table algorithm used in Step 2 for extracting metadata. The hash table memory takes functions as the basic unit and records the storage information of reference tags. Based on the storage address and the number of basic blocks recorded in the storage information, the reference tags belonging to the basic blocks within the same function can be extracted into the metadata cache at one time.

[0104] The metadata cache manages reference tags using a stack structure. The reference tags at the granularity within the newly called function are stored at the top of the stack. When the function execution is completed, a pop operation is performed, and the reference tags of the basic blocks within the previously called function are at the top of the stack.

[0105] The specific process of extracting reference tags into the metadata cache is as follows:

[0106] By performing a hash table mapping on the address of the sensitive instruction or the entry address of the function to obtain the index of the reference tag, determining the address of the storage information of the reference tag in the hash table memory, reading the storage information of the reference tag, and finally, according to the storage address of the reference tag recorded in the storage information in the flash memory, reading the reference tag stored in the flash memory through the flash memory controller; pushing the newly read reference tag onto the top of the stack of the metadata cache.

[0107] Step 6. The lightweight hash calculator enters the squeezing stage. The verifier samples the first partial hash values output by each channel of the lightweight hash calculator using the random number sequence generated by the random number generator. Each time a sampling is completed, the used random number sets the bit at the corresponding position in the sampling bitmap to 1. During the sampling process, the actual sampling value is compared with the reference sampling value.

[0108] If they are consistent, the random number generator generates a random number with the sum of the average of the partial hash values squeezed out in two adjacent squeezes and the earlier squeezed first partial hash value as the random number seed, otherwise, directly execute Step 9.

[0109] Obtaining the reference tag: If it is the first time to obtain the reference tag after the system starts, directly extract the first reference tag starting from the top of the metadata cache stack. Otherwise, if the previous executed granularity ends with a branch instruction, select the offset value in the reference tag of this granularity according to whether there is a jump and add it to the metadata cache stack pointer; if the previous executed granularity ends with a non-branch instruction, directly add the offset value in the reference tag of this granularity to the metadata cache stack pointer.

[0110] Obtaining the actual sampling value: Use … to represent the first partial hash values squeezed out by each channel of the lightweight hash calculator. Starting from the right and moving left, starting from 0, concatenate the first partial hash values squeezed out by each channel of the bit labels, and use to represent the generated random number sequence. Then, sequentially The value of the th bit is written into the sampling value register of the checker, and 0 , and the i-th bit of the sampling bitmap is set to 1. Random numbers outside the label range are skipped;

[0111] After each sampling of a partial hash value is completed, the sampling bitmap is bitwise ANDed with the reference sampling value and then bitwise XORed with the sampling value register. If some bits in the result are 1, it is determined that the program integrity is damaged.

[0112] Step 7. The random number generator uses the sum of the mean of two sequentially adjacent random numbers generated and the first random number generated earlier as the random number seed to continue generating random numbers, and so on until the last random number is generated.

[0113] Step 8. The checker clears the sampling bitmap and determines whether the actually generated random number is consistent with the reference random value. If they are consistent, go to Step 3; otherwise, go to Step 9.

[0114] Step 9. The checker issues an alarm signal and writes the entry address of the function / basic block where the program integrity is damaged or the address of the sensitive instruction into the exception code address register.

[0115] Taking the E906 processor as an example below, in combination with the attached Figure 1 , and the attached Figure 3 to the attached Figure 4 a specific application example of the on-chip hardware-based embedded program integrity multi-granularity verification method provided by the present invention is enumerated.

[0116] In this specific example, the on-chip hardware-based embedded program integrity multi-granularity verification method includes the following steps:

[0117] Step 1. Select the program integrity verification granularity, simulate the execution process of the user program, obtain the path information of the user program, and construct a call relationship tree diagram and the metadata required for program integrity verification.

[0118] In this example, the program integrity verification granularity is set to a mixed-level granularity composed of basic block level and instruction level, and the sensitive instruction is set to a write storage operation. The pseudocode of the running user program is as follows:

[0119] void Func(void)

[0120] {

[0121] BB_0; / / Basic block 0

[0122] SubFunc_1(); / / Sub-function 1

[0123] SubFunc_2(); / / Subfunction 2

[0124] BB_8; / / Basic Block 8

[0125] }

[0126] void SubFunc_1(void)

[0127] {

[0128] BB_1;

[0129] BB_2;

[0130] BB_3;

[0131] BB_4;

[0132] }

[0133] void SubFunc_2(void)

[0134] {

[0135] BB_5;

[0136] BB_6;

[0137] BB_7;

[0138] }

[0139] After the user program is successfully compiled, the execution process of the user program is simulated using the XuanTie QEMU that matches the E906 processor architecture: First, enter the instruction in the QEMU terminal: qemu-system-riscv32 -nographic -machine smartl -cpu e906fdp -kernel {qemu_elf_file} -d nochain,exec,in_asm -D{output_file} to obtain the log file reflecting the user program path; then use the script written in the Python language to analyze the log file to obtain the execution order of basic blocks and functions in the user program, the entry address of each basic block and the instructions it contains, the entry address of each function and the basic blocks it contains, as well as the call relationship between functions, and mark the instructions of the write and store type. Based on these path information, construct the call relationship tree diagram of the user program. The nodes in the call relationship tree diagram correspond one by one to each basic block or function on the user program execution path, and the function is the parent node of the basic blocks and called functions it contains.

[0140] Taking the above pseudocode snippet as an example, the constructed call relationship tree diagram is as shown in Figure 3 shown.

[0141] Based on this call relationship tree diagram, construct the metadata required for program integrity verification. The metadata required for program integrity verification consists of an index, a reference tag, and its storage information.

[0142] Among them, the reference tag is composed of a reference sampling value, a reference random value, and an offset value. The reference tags of basic blocks within the same function are stored in the flash memory in the execution order. Based on this storage method, calculate the actual storage address of the reference tag in the flash memory under each function. The index is the address of the storage information of the reference tag in the hash table memory.

[0143] Among them: The index of the metadata required for verifying the program integrity of the write instruction is obtained by performing a hash table mapping on the address of the write instruction. The index of the metadata required for verifying the program integrity of each basic block is obtained by performing a hash table mapping on the address of the jump instruction; in the case where there is no index collision, the storage information of the reference tag consists of its actual storage address in the flash memory and the number of basic blocks included in the function to which it belongs; in the case of an index collision, the storage information of each reference tag is continuously stored in the hash table memory, called a sub-entry. The hash table entry pointed to by this index consists of a collision flag bit, the number of collisions, and the storage address of its sub-entries in the hash table.

[0144] For the convenience of description, the modulo operation is used as the hash table mapping in this example. Still taking the above pseudocode as an example: The user program contains three functions, Func, SubFunc_1, and SubFunc_2. Assume the entry addresses are 0x0000_0000, 0x0000_0010, and 0x0000_0020 respectively. If the hash table can accommodate at most 256 entries, after taking the modulo 256 of the three entry addresses, the indexes of the three functions obtained are 0x00, 0x10, and 0x20 respectively.

[0145] If the number of functions in a user program exceeds the maximum number of entries that the hash table can accommodate, it means that the entry addresses of multiple functions are assigned to the same entry. Then the collision flag bit in the storage information of this entry is set to 1, and multiple sub-entries are divided under this entry. Each sub-entry consists of the high 24 bits of the entry address and the actual storage address of the reference tag in the flash memory.

[0146] Assuming that the number of hash table entries is 256, and the entry addresses of functions a, b, and c are all mapped to the same entry in the hash table, then the storage information of functions a, b, and c will be the three sub-entries under the entry. The collision flag in the entry is 1, the number of collisions is 3, and the address of the sub-entry in the hash table memory is recorded. When a hash table mapping is performed on any entry address of a, b, and c, and the storage information in the entry is obtained, the storage information in each sub-entry can be obtained in turn according to the collision flag being 1, the number of collisions being 3, and the storage address of its sub-entry. By comparing the entry addresses recorded therein, the corresponding storage information is selected.

[0147] Since this example uses a hybrid instruction-level and basic block-level granularity, the metadata only needs to calculate reference hash values for each basic block and write-store type instruction. The reference hash value for each basic block is obtained by hashing the instructions it contains, while the reference hash value for each function is obtained by hashing the reference hash value of the basic block it calls. Since the lightweight hash calculator in this example uses a lightweight hash function with a sponge structure, at an operating frequency of 125MHz, each absorption or squeeze requires T=4 clock cycles. Therefore, the lightweight hash calculator uses five channels to calculate the reference hash value. When the fifth channel begins absorbing instructions in the next cycle, the first channel has just completed absorbing the old instruction and can be selected to continue absorbing the next instruction. Similarly, the second, third, and fourth channels complete absorbing the old instruction and continue absorbing the new instruction. Therefore, in order to match the output results of the lightweight hash calculator implemented in hardware, during the absorption phase where software is used to calculate hash values, except for the hash values of write-store type instructions which can be calculated directly, the instructions in each basic block need to be divided into 5 groups for calculation, and each group is equivalent to a channel of the lightweight hash calculator implemented in hardware.

[0148] In this example, each channel squeezes out three 32-bit partial hash values in succession, and finally outputs 15 partial hash values. The total hash value length is 480-bit. Therefore, in order to avoid the reference hash value taking up a large amount of storage space and to detect errors as early as possible, only 15-bit sampling values and 33-bit random numbers generated based on the hash values output by each channel are stored and verified. Among them, the sampling value is used to detect the granularity of program integrity damage as early as possible before all partial hash values are output. The larger the width of the sampling value, the better the effect. The specific sampling process for generating the reference sampling value is: first, the five partial hash values generated by the first squeeze are spliced into a hash value P1 with a length of 160-bit; then, the entry address of each function is used as the random number seed, and 15 random numbers r are generated in the range of 0~159. i The random number sequence composed of i=1,2,3…15, the rth iUse one bit as the i-th bit of the reference sampling value, and finally splice them into a 15-bit reference sampling value.

[0149] To avoid misjudgment caused by the contingency that the sampling values of two different hash values may be the same, it is necessary to further generate a 33-bit random number according to the content of all partial hash values of each channel. The specific process is as follows: First, use the sum of the mean value of two adjacent partial hash values in the generation order (round down when the mean value is not an integer) and the first partial hash value as the random number seed to generate ( 33-bit random numbers; then continue to use the sum of the mean value of two adjacent random numbers in the generation order and the first random number as the random number seed to generate (15 - 2) random numbers, and so on, until only one random number is generated, and use this random number as the reference random value in the metadata.

[0150] Step 2. Power on and initialize the embedded system integrated with the program integrity multi-granularity verification module.

[0151] Since the first instruction of the user program is usually not a jump instruction, the on-chip security mechanism cannot be triggered to retrieve the reference tag. Therefore, it is necessary to load the reference tags of the basic blocks in the first function into the metadata cache during power-on initialization.

[0152] Load the remaining reference tags and their storage information into the reference tag area of the flash memory and the hash table memory respectively, and set the granularity register through the external key circuit. It is pre-specified that the granularity register values 001, 010, and 100 correspond to the instruction level, basic block level, and function level granularity respectively. Therefore, in this example, it is necessary to set the granularity register to 011 through the external key circuit, and input the operation code 010001 of the write instruction in the RISC-V instruction set into the sensitive instruction type register group.

[0153] Step 3. The pipeline continues to run, and the lightweight hash calculator absorbs the instructions entering the decoding stage.

[0154] To avoid some instructions entering the decoding stage incorrectly in a short time due to branch prediction failure, every time a branch instruction is absorbed, the lightweight hash calculator needs to back up the absorption state at this time. When the branch prediction failure signal is detected, the lightweight hash calculator restores to the backup state and re-absorbs the subsequent instructions entering the decoding stage.

[0155] Step 4. The instruction analyzer analyzes the nature of the instructions in the decoding stage according to the set program integrity verification granularity. When a sensitive instruction is detected, pause the pipeline and execute Step 5. When a function call instruction is detected, directly execute Step 5. When a function return instruction or jump instruction is detected, execute Step 6. In other cases, execute Step 3.

[0156] In this example, the granularity register is set to 011. Therefore, on the one hand, the synchronous decoder needs to determine whether the operation code and function bits of the instruction entering the decoding stage are the same as 010001 recorded in the sensitive instruction type register group. If they are the same, the instruction analyzer issues a pipeline control signal to pause the pipeline and execute step 5; otherwise, execute step 3. On the other hand, it needs to determine whether the instruction entering the decoding stage is a jump instruction. If it is not a jump instruction, execute step 3; otherwise, it needs to further determine whether the jump instruction is a function call instruction. If it is a function call instruction, execute step 5; otherwise, execute step 6.

[0157] Step 5. The hash table mapper maps the address of the sensitive instruction or the entry address of the called function to the address in the hash table memory where the storage information of its reference label is located through the hash table algorithm, extracts the reference label to the metadata cache. At the same time, the random number generator uses the address of the sensitive instruction or the entry address of the called function as the random number seed to generate a random number sequence composed of random numbers, and each random number is not greater than the sum of the lengths of the partial hash values squeezed out by all channels of the lightweight hash calculator for the first time.

[0158] The hash table algorithm used in step 5 is consistent with the hash table algorithm used in step 1. The metadata cache manages the reference labels using a stack structure. The reference label under the newly called function is always stored at the top of the stack. When the function finishes execution, a pop operation is performed so that the reference label of the previous called function is at the top of the stack. During the execution of the pseudo-code fragment shown above, when an instruction to call a function is detected, after the address of the instruction is mapped through the hash table, the address in the hash table memory where the storage information of the reference label under function Func is located is obtained, and according to this storage information, the address of the reference label under function Func in the flash memory is obtained, and then it is read into the metadata cache; when a jump instruction is detected, it indicates that the decoding of basic block BB_0 is completed, and the first reference label at the top of the metadata cache stack is the reference label of basic block BB_0; then function SubFunc_1 is called, and the reference label of SubFunc_1 is read into the metadata cache in the same way. At this time, the reference label of SubFunc_1 is at the top of the metadata cache stack. When the decoding of basic block BB_1 is completed, the first reference label at the top of the metadata cache stack is the reference label of BB_1; when the decoding of function SubFunc_1 is completed and the decoding of function SubFunc_2 starts, the metadata cache performs a pop operation, pops the reference label of SubFunc_1, and pushes the reference label of SubFunc_2, and continues to perform similar operations. The whole process is as shown in the appendix Figure 4 as follows.

[0159] In this example, the random number sequence generated by the random number generator with the entry address of basic block BB_0 as the random number seed is [144, 147, 153, 11, 135, 68, 77, 122, 19, 122, 97, 66, 130, 98, 131].

[0160] Step 6. The lightweight hash calculator enters the squeezing stage, and the verifier samples the first partial hash values output by each channel of the lightweight hash calculator using the random number sequence generated by the random number generator. During the sampling process, the actual sampling value is compared with the reference sampling value.

[0161] If they are consistent, the random number generator uses the sum of the mean of the two adjacent partial hash values squeezed out and the first partial hash value squeezed out earlier as the random number seed to generate a 33-bit random number, otherwise directly execute Step 9.

[0162] In this example, during the process of calculating the hash value of basic block BB_0 by the lightweight hash calculator, channels 1, 2, 3, 4, and 5 successively output partial hash values h1 = 0x4dd38906, h2 = 0x17d7f2c2, h3 = 0xd03bcb08, h4 = 0x925d8b7d, h5 = 0x8b44fb2b, totaling 160 bits. From right to left, the bit positions are labeled with 0 - 159. Since only the 7th and 12th random numbers 19 and 11 in the random number sequence generated in Step 5 fall within the label range of h1, the final sampling of h1 is 1, 1, the sampling bitmap is updated to 0b000_1000_1000_0000, and the sampling value register is updated to 0b000_1000_1000_0000. The result of bitwise AND of the sampling bitmap and the reference sampling value is XORed with the sampling value register to obtain: 0b000_0000_0000_0000, indicating that the first sampling and comparison pass; since no random number falls within the bit positions of h2, there is no need to sample h2; during the sampling of h3, the 3rd random number 66, the 8th random number 77, and the 9th random number 68 fall within the bit positions of h2, and the sampling result of h2 is: 0, 1, 1, the sampling bitmap is updated to 0b000_1011_1000_1000, and the sampling value register is updated to 0b000_1011_1000_0000. The result of bitwise AND of the sampling bitmap and the reference sampling value is XORed with the sampling value register. If a "1" appears in the result, it indicates that the program integrity is damaged, and directly execute Step 9.

[0163] Step 7. The random number generator uses the sum of the mean of two adjacent random numbers generated in sequence and the first random number generated earlier as the random number seed to continue generating random numbers, and so on iteratively until the last random number is generated.

[0164] Step 8. The verifier clears the sampling bitmap and determines whether the generated actual random number is the same as the reference random number. If they are the same, go to Step 3; otherwise, go to Step 9.

[0165] Step 9. The verifier issues an alarm signal and writes the entry address of the basic block where the program integrity is damaged or the address of the sensitive instruction into the exception code address register.

[0166] Compared with the traditional method, the method of the present invention has the following advantages:

[0167] (1) It supports setting different levels of program integrity verification granularity, regulating the frequency of program integrity verification, meeting different security requirements of users, and effectively balancing the security, performance, and overhead of the system.

[0168] The instruction analyzer identifies the write instruction for writing to a specific address or detects the signal from the external dedicated key circuit through the internal synchronous decoder, sets the granularity register to the values corresponding to the four granularity levels of instruction level, basic block level, function level, and mixed level in software or hardware, and writes the sensitive instruction features that need special attention into the sensitive instruction type register group. During the program integrity verification process, the instruction analyzer executes different analysis strategies according to the value of the granularity register. The synchronous decoder synchronously analyzes the instructions entering the pipeline decoding unit, identifies the granularity boundary according to the instruction jump type, and sends a control signal to other circuits of the program integrity multi-granularity verification module based on the analysis result: when the instruction analyzer detects that the currently decoded instruction matches one of the items in the sensitive instruction type register group, the pipeline is immediately paused, and the pipeline can continue to run only after the integrity verification of this instruction passes, effectively avoiding the situation where the sensitive instruction is executed before the program integrity verification is completed, resulting in irreparable consequences.

[0169] (2) It effectively shortens the delay of program integrity.

[0170] It usually takes dozens or even hundreds of clock cycles for a sponge-structured hash function to complete one absorption or squeezing operation, resulting in subsequent instructions not being absorbed in a timely manner and causing an unacceptable delay in program integrity verification. In the hash calculator, on the one hand, the iteration of the sponge-structured hash function is moderately unfolded into a cascade of combinational logic circuits, reducing the number of clock cycles required for one absorption or squeezing operation while ensuring that the operating frequency of the lightweight hash calculator meets the system requirements. On the other hand, T+1 channels are used to sequentially absorb instructions from the instruction analyzer, so that there is always an idle channel whenever a new instruction arrives, thus enabling continuous absorption of instructions. This way of calculating hash values by distributing the originally sequentially executed instructions to different channels also increases the difficulty for attackers to undermine program integrity to a certain extent. In addition, to output the verification result of the current-granularity program integrity as early as possible, a dual verification mechanism of sampled values and random numbers is adopted. First, the checker randomly samples the first part of the hash values output by each channel. When the actual sampled value is inconsistent with the reference sampled value, it can be determined that the program integrity of the current granularity has been damaged before all hash values are calculated. Even if the attacker breaks through the sampled value verification mechanism by chance, the checker still needs to generate a random number based on all partial hash values output by each channel. Only when the finally generated random number is exactly the same as the reference random value can it be determined that the code integrity of the current granularity has not been damaged.

[0171] (3) Overcomes the interference of branch prediction failure to program integrity verification.

[0172] When the instruction analyzer detects a pipeline branch prediction failure, a small number of instructions not on the program execution path will enter the pipeline decoding unit in a short period of time and be wrongly absorbed by the lightweight hash calculator, thus interfering with the verification of program integrity. For this reason, every time the lightweight hash calculator in the present invention absorbs a branch instruction, it will back up the states of each channel to the channel state backup register group. When a branch prediction failure is detected, each channel of the lightweight hash calculator will restore to the backup state and continue to absorb subsequent instructions, thus avoiding misjudgment caused by branch prediction interference.

[0173] (4) Effectively improves the efficiency of retrieving reference tags.

[0174] The granularity address range is large and discontinuous. Directly using the granularity address as the address of its reference label in the flash memory not only requires a large amount of storage space but also has low utilization efficiency of the storage space. Therefore, the reference labels of each granularity under each sensitive instruction or each function are continuously stored in the flash memory in the execution order to obtain the storage information (storage address and length) of each reference label. Then, taking the entry address of the sensitive instruction or each function as the input, the storage information of each reference label is mapped through a hash table to obtain the address of the storage information of each reference label in the hash table memory. Every time the instruction analyzer detects a function call instruction or a sensitive instruction, the hash table mapper takes the function entry address or the sensitive instruction address as the input, calculates the address of the storage information of the reference label in the hash table memory, obtains the actual storage address and length of the reference label in the flash memory from the hash table memory, and writes the reference labels of the granularity under the called function into the metadata cache of the stack structure at one time, thereby effectively reducing the frequency of the program integrity accessing the external memory. Every time the instruction analyzer detects a function return instruction or when the sensitive instruction verification passes, the metadata cache performs a stack pop operation to clear the reference labels of the verified granularity or sensitive instruction. Since the reference labels are continuously stored in the execution order, during the process of verifying the program integrity, the stack pointer of the metadata cache can point to the reference label of the next possibly executed granularity by moving down or adding an offset value, thereby quickly locking the reference label of the current granularity, reducing the overhead of frequently accessing the memory, and effectively improving the retrieval efficiency of the reference label.

[0175] Certainly, the above description is only a preferred embodiment of the present invention. The present invention is not limited to listing the above embodiments. It should be noted that all equivalent substitutions and obvious deformation forms made by any person skilled in the art under the teaching of this specification fall within the substantial scope of this specification and should be protected by the present invention.

Claims

1. An embedded program integrity multi-granularity verification system based on on-chip hardware, characterized in that It includes a program integrity multi-granularity verification module, a processor pipeline, on-chip memory, and a flash memory controller; Among them, the program integrity verification granularity is set to instruction level, basic block level, function level, and mixed level; The program integrity multi-granularity verification module includes: An instruction analyzer, which is responsible for the interaction between the program integrity multi-granularity verification module and the processor pipeline, and is built-in with a synchronous decoder, a granularity register and its setting circuit, and a sensitive instruction type register group; A lightweight hash calculator, which uses a hash function with a sponge structure to calculate the actual hash value of each granularity; A hash table memory, with functions as the basic unit, which is used to store the storage information about each reference tag, and assists in positioning the reference tag of the granularity belonging to the current function in the flash memory at one time; Among them, the reference tag consists of a reference sampling value, a reference random value, and an offset value; A hash table mapper, which is used to map the sensitive instruction address or the entry address of a function to the corresponding address in the hash table memory; A metadata cache, which is used to store the reference tag of the current granularity, and manages the reference tag using a stack structure; And a checker, which is used to compare the reference tag and the actual tag, detect the granularity where the program integrity is damaged, and the checker is built-in with a random number generator, a sampling bitmap, a sampling value register, and an exception code address register; The random number generator generates a random number sequence with the address of each granularity as the random number seed, and generates the actual random number corresponding to each granularity with the mean value of the hash values output by adjacent two channels or the mean value of the generated random numbers as the random number seed; The checker samples the first partial hash value extruded by each channel of the lightweight hash calculator according to the random number sequence generated by the random number generator, uses the sampling bitmap to record the sampling process, uses the sampling value register to record the actual sampling value obtained during the sampling process, and at the same time compares the corresponding bit positions of the obtained actual sampling value and the reference sampling value, and sets the bit position of each random number in the sampling bitmap to 1; When the actual sampling value and the reference sampling value are exactly the same, the checker further compares the finally generated actual random number and the reference random value; the exception code address register built in the checker consists of the address of the granularity where the program integrity is damaged and a status exception flag bit, and the status exception flag bit is set to 1 when it is detected that the program integrity is damaged.

2. The embedded program integrity multi-granularity verification system based on on-chip hardware according to claim 1, characterized in that The instruction analyzer sets the granularity register to a value indicating the program integrity verification granularity of the four levels of instruction level, basic block level, function level, and mixed level by identifying write instructions or detecting the signals of an external dedicated key circuit; The instruction analyzer writes the characteristics that can characterize sensitive instructions into a register in the sensitive instruction type register group according to the write instruction or the signal of the external dedicated key circuit; Among them, the characteristics that can characterize sensitive instructions are machine code fields selected according to the instruction set; The synchronous decoder executes and sets the analysis strategy matching the granularity according to the value of the granularity register, and synchronously analyzes the instructions entering the pipeline decoding stage; When the synchronous decoder identifies an instruction that matches one of the instruction types recorded in the sensitive instruction type register group, it immediately issues a pipeline pause signal until the integrity verification of the instruction is completed.

3. The embedded program integrity multi-granularity verification system based on on-chip hardware according to claim 1, wherein The lightweight hash calculator has T + 1 built-in channels, and each channel is a pipeline that independently absorbs instructions and squeezes hash values; every time the lightweight hash calculator absorbs a branch instruction, it backs up the states of each channel; When the instruction analyzer detects a branch prediction failure signal, each channel resumes to the backed-up state and continues to absorb subsequent instructions; where T is the number of clock cycles required for the lightweight hash calculator to complete one absorption or squeeze.

4. An embedded program integrity multi-granularity verification method based on on-chip hardware, implemented based on the on-chip hardware-based embedded program integrity multi-granularity verification system according to any one of claims 1 to 3, characterized in that It includes the following steps: Step 1. Select the program integrity verification granularity and simulate the execution process of the user program; Obtain the path information of the user program and construct a call relationship tree diagram and the metadata required for program integrity verification; among them, the metadata includes the reference tags of each granularity and their storage information; Step 2. Power-on initialization; Step 3. The pipeline continues to run, and the lightweight hash calculator absorbs the instructions entering the decoding stage; Step 4. The instruction analyzer analyzes the nature of the instructions in the decoding stage according to the set program integrity verification granularity; When a sensitive instruction is detected, pause the pipeline and execute Step 5; when a function call instruction is detected, directly execute Step 5; when a function return instruction or jump instruction is detected, execute Step 6; in other cases, execute Step 3; Step 5. The hash table mapper maps the address of the sensitive instruction or the entry address of the called function to the address in the hash table memory where the storage information of its reference tag is located, and extracts the reference tag to the metadata cache; at the same time, the random number generator uses the address of the sensitive instruction or the entry address of the called function as the random number seed to generate a random number sequence; Step 6. The lightweight hash calculator enters the squeeze stage, and the checker samples the first partial hash value output by each channel of the lightweight hash calculator using the random number sequence generated by the random number generator, and compares the actual sampled value with the reference sampled value; If they are consistent, the random number generator generates a random number with the sum of the mean of the two adjacent partial hash values squeezed out and the earlier squeezed-out first partial hash value as the random number seed, otherwise execute Step 9; Step 7. The random number generator uses the sum of the mean of two adjacent generated random numbers and the earlier generated first random number as the random number seed to continue generating random numbers, and so on iteratively until the last random number is generated; Step 8. The checker clears the sampling bitmap and judges whether the generated actual random number is consistent with the reference random value; If they are consistent, execute Step 3, otherwise execute Step 9; Step 9. The checker writes the entry address of the function / basic block whose program integrity is damaged or the address of the sensitive instruction into the exception code address register.

5. The multi-granularity verification method for the integrity of an embedded program based on on-chip hardware according to claim 4, wherein In the said Step 1, the program integrity verification granularity is divided into 4 types: instruction level, basic block level, function level, and mixed level; Among them, the instruction level, basic block level, and function level respectively represent verifying the program integrity when the processor pipeline completes the decoding of a sensitive instruction, a basic block, and a function; The instruction-level granularity, basic block-level granularity, and function-level granularity are combined in threes or in combinations of two of them to obtain a hybrid-level granularity: The hybrid-level granularity formed by the participation of the instruction-level granularity means that during the decoding of a basic block or function, if a preset sensitive instruction is found, it is necessary to first complete the verification of the program integrity of the sensitive instruction; At the same time, the hybrid-level granularity formed by the participation of the basic block-level and function-level granularities means that not only the program integrity needs to be verified every time a basic block or function is decoded in the pipeline, but also the previously verified basic block is used as a parameter for verifying the program integrity of the subsequent basic blocks, so as to verify the program control flow integrity while verifying the program integrity.

6. The multi-granularity verification method for the integrity of an embedded program based on on-chip hardware according to claim 4, characterized in that, In step 3, when the lightweight hash calculator calculates the hash value of the hybrid-level granularity formed by the participation of the function-level granularity, it needs to use the absorption result of the previous round as the initial state of the next round of absorption, and restore the initial state every time a new round of absorption starts; The lightweight hash calculator needs to back up the absorption state every time it absorbs a branch instruction; when a branch prediction failure signal is detected subsequently, the lightweight hash calculator restores to the backed-up absorption state and re-absorbs the instructions that subsequently enter the decoding stage.

7. The method for multi-granularity verification of the integrity of an embedded program based on on-chip hardware according to claim 4, wherein In step 4, the synchronous decoder inside the instruction analyzer first determines the preset program integrity verification granularity according to the value of the granularity register and selects the corresponding code analysis strategy: For the instruction-level granularity, the synchronous decoder determines whether the instruction is a sensitive instruction by comparing the characteristics of the instruction and the characteristics recorded in the instruction type register group, and issues a pipeline control signal to pause the pipeline when a sensitive instruction is detected; for the basic block-level granularity, the synchronous decoder only needs to determine whether the instruction is a jump instruction through the machine code field that can characterize the instruction characteristics; for the function-level granularity, the synchronous decoder needs to determine whether the instruction is a function call or return instruction; for the hybrid-level granularity, including the instruction analysis strategies of the granularity, the synchronous decoder needs to execute all of them.

8. The multi-granularity verification method for the integrity of an embedded program based on on-chip hardware according to claim 4, wherein In step 5, the latest read reference tag is always at the top of the stack in the metadata cache, and the reference tag that has completed the granularity execution is popped out through the stack pop operation; The specific process of extracting the reference tag to the metadata cache is: The index of the reference tag is obtained by making a hash table mapping of the address of the sensitive instruction or the entry address of the function, the address of the storage information of the reference tag in the hash table memory is determined, the storage information of the reference tag is read, and finally, according to the storage address of the reference tag recorded in the storage information, the reference tag stored in the flash memory is read through the flash memory controller; The latest read reference tag is pushed onto the top of the stack in the metadata cache.

9. The multi-granularity verification method for the integrity of an embedded program based on on-chip hardware according to claim 4, wherein In step 6, the checker uses the random number sequence generated by the random number generator to sample the first partial hash value output by each channel of the lightweight hash calculator. The specific process of comparing the actual sampled value and the reference sampled value is: Obtain reference tag: If it is the first time to obtain the reference tag after the system starts, directly extract the first reference tag starting from the top of the metadata cache stack; otherwise, if the previous executed granularity ends with a branch instruction, select the offset value in the reference tag of this granularity according to whether there is a jump and add it to the metadata cache stack pointer; If the previous executed granularity ends with a non-branch instruction, directly add the offset value in the reference tag of this granularity to the metadata cache stack pointer; Obtain the actual sampling value: Use to represent the first partial hash value squeezed out by each channel of the lightweight hash calculator. From right to left, starting from 0, splice the first partial hash values squeezed out by each channel of each bit label. Use to represent the generated random number sequence. Then, in sequence, write the value of the r i -th bit into the sampling value register of the checker, where 0 ≤ i ≤ N r - 1, and set the i-th bit of the sampling bitmap to 1. Skip the random numbers outside the label range; After each partial hash value is sampled, the sampling bitmap is bitwise ANDed with the reference sampling value and then bitwise XORed with the sampling value register. If some bits in the result are 1, it is determined that the program integrity is damaged and the sampling is ended in advance.

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