PCB press-fit forming simulation system and method

Abstract

The invention relates to the technical field of circuit board press-fit simulation, in particular to a PCB press-fit forming simulation system and method, and the system comprises a simulation design module, a member simulation module, a simulation maintenance module, a state monitoring module and a simulation diagnosis module. In response to the circuit board lamination simulation request, obtaining each position parameter during each lamination, and forming a morphological network of each layer; receiving the position size of each layer in the layer form network, and controlling the form change modulus and the warping height of each layer on a single operation step length when the circuit board is pressed; determining a preset change direction and a displacement difference of each morphological change modulus on the basis of the morphological change modulus and the warping height of each layer; performing simulation check on the displacement difference in the preset change direction to generate the displacement difference and a finite element simulation model of each cavity; comparing the displacement difference with the finite element simulation model of each cavity, and determining the difference angle and type of each model during difference; and the precision and the efficiency of circuit board production are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB lamination simulation, and specifically to a simulation system and method for the forming of a PCB circuit board by lamination. Background Art

[0002] With the iterative upgrade of electronic products, consumers' demands for devices are evolving towards being lighter, thinner, shorter, smaller, and more powerful. The Cavity is a customized groove formed on the PCB board through laser etching or chemical processing, and its depth can be precisely controlled without penetrating all the board layers; it can significantly reduce the physical space limitation of traditional surface mounting and improve the utilization efficiency of electronic products. When producing the corresponding PCB circuit board, the multi-layer board lamination method is generally adopted, and the following problems are likely to occur when a corresponding cavity needs to be reserved: during the lamination of multi-layer boards, due to the difference in the thermal expansion coefficients of the resin material and the copper foil, and the uneven distribution of the interlayer materials, the board surface warps and deforms after lamination. At the same time, the insufficient mechanical strength or the decline in signal transmission performance will be caused by the loose interlayer bonding. Due to the uneven distribution of local materials in the cavity on the circuit board, stress concentration or displacement offset is likely to occur during lamination, resulting in cracking or delamination around the cavity.

[0003] For example, Chinese Patent Publication No. CN117787208A discloses a printed circuit board deformation simulation method, device, electronic device, and storage medium. The method includes obtaining the first property parameters of the woven composite material; correspondingly assigning the first property parameters of the woven composite material and the second property parameters of the conductive material to the first representative volume unit model of the laminated structure for the woven composite material and the conductive material; obtaining the first finite element model of the laminated structure through the first representative volume unit model; obtaining the third property parameters of the laminated structure through the first representative volume unit model and the first finite element model; assigning the third property parameters to the second finite element model of the printed circuit board; and performing simulation through the second finite element model under the preset temperature field and preset boundary constraint conditions to obtain the deformation information of the printed circuit board.

[0004] For example, Chinese Patent Publication No. CN117391036A discloses a printed circuit board simulation method, device, equipment, and storage medium, which relates to the technical field of printed circuit board simulation. The method includes: in response to receiving a printed circuit board simulation request from a user, obtaining the input parameters of the current user and the copper foil network to be inspected selected by the current user; drawing a plurality of virtual cutting lines according to the input parameters to cut each layer of the copper foil network to be inspected, and calculating the copper foil current-carrying length of each virtual cutting line corresponding to each layer of the copper foil network to be inspected; calculating the total current-carrying area of each virtual cutting line corresponding to each layer according to the copper foil network to be inspected and the copper foil current-carrying length of each virtual cutting line corresponding to each layer, and outputting the total current-carrying area.

[0005] The prior art separately describes simulating the production process of the current circuit board from the intersection points of the displacement field and cutting lines laminated from the circuit board layers. It mainly shows that when the circuit board warps, the relative displacement of its displacement field can be used to describe the situation of the whole board. However, it ignores the relative displacement difference between individual circuit board layers, easily neglects the alignment deviation caused by the displacement amount difference between the circuit board layers, and results in the problem of layer offset of the circuit board. At the same time, when identifying the copper foil trend of the cutting line, it only shows the current trend corresponding to the circuit board. These processing methods all ignore the relative alignment of multiple circuit board layers and whether the offset of the dimensions of each layer will affect the formed cavity, thus affecting the embedded installation of electronic components. Summary of the Invention

[0006] To solve the above technical problems, the technical solution adopted by the present invention is: A PCB circuit board pressing and forming simulation system, including: A simulation design module, used to respond to the circuit board pressing simulation request, obtain the position parameters at each pressing, and form a morphological network of each layer.

[0007] A member simulation module, used to receive the position dimensions of each layer in the layer morphological network, and control the morphological change modulus and warping height of each layer at a single running step during circuit board pressing.

[0008] A simulation maintenance module, used to verify the displacement trend of the circuit board at the boundary position based on the morphological change modulus and warping height of each layer, and determine the preset change direction and displacement amount difference of each morphological change modulus.

[0009] A status monitoring module, used to perform a simulation check on the displacement amount difference in the preset change direction, record the simulation transfer data of the circuit board displacement, and based on the simulation transfer data, perform a displacement amount excitation calculation to generate a finite element simulation model of the displacement amount difference; and extract the morphological change modulus of each cavity on the circuit board to generate a finite element simulation model of each cavity.

[0010] A simulation diagnosis module, used to compare the displacement amount difference with the finite element simulation models of each cavity, determine the difference angle and type when there are differences in each model, and obtain the pressing diagnosis result of the circuit board.

[0011] A PCB circuit board pressing and forming simulation method, including: S1, in response to the circuit board pressing simulation request, obtain the position parameters at each pressing, and form a morphological network of each layer.

[0012] S2, receive the position dimensions of each layer in the layer morphological network, and control the morphological change modulus and warping height of each layer at a single running step during circuit board pressing.

[0013] S3. Based on the morphological change modulus and warpage height of each layer, verify the displacement trend of the circuit board at the boundary position, and determine the preset change direction and displacement difference of each morphological change modulus.

[0014] S4. Conduct a simulation check on the displacement difference in the preset change direction. Based on the simulated transmission data, generate the displacement difference and the finite element simulation models of each cavity.

[0015] S5. Use the displacement difference and the finite element simulation models of each cavity for comparison, determine the difference angles and types when there are differences in each model, and obtain the lamination diagnosis result of the circuit board.

[0016] The beneficial effects of the present invention are as follows: First, by obtaining the position parameters during the lamination of the circuit board, combining with the current shape of the circuit board, dynamically obtaining multiple sets of spatially related position parameters, and iteratively updating the obtained parameters with the first design space and the second design space, the obtained position parameters are closer to the displacements and relative deformations generated during multiple laminations of the current circuit board, facilitating the quantification of the displacement differences between more layers during the lamination of the circuit board, so as to improve the accuracy of circuit board design and production.

[0017] Second, at intervals of the running step length, associate the position dimensions and morphological relationships in the layer morphological network, quantify the morphological changes between each layer of the circuit board, capture the scale with relatively small relative changes in the gradients of each layer when the circuit board is obtained, and identify this part of the content with the morphological change modulus and warpage height; then identify the boundary position, fit the information such as the copper bars and copper foils etched on the circuit board to verify the displacement trend generated by each layer of the circuit board, and identify the main displacement changes of the circuit board to achieve the prediction and processing of the displacement amounts at multiple layers and multiple boundaries.

[0018] Third, form a mapping relationship between the positions of each point on the circuit board and the layer morphological network with the displacement difference and the finite element simulation models of each cavity; then judge and combine the situations of these nodes, and it is possible to identify the dimensions near the cavity when generating the corresponding cavity of the circuit board, prevent the problem that the cavity size error occurs due to the displacement of each layer, resulting in the inability to install electronic components, so as to improve the accuracy during the production of the circuit board and reduce the production defects of the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below with reference to the drawings and embodiments.

[0020] Figure 1 It is a schematic framework diagram of a PCB circuit board lamination and forming simulation system.

[0021] Figure 2 It is a schematic diagram of the circuit board lamination of a PCB circuit board lamination and forming simulation system.

[0022] Figure 3 It is a schematic flow chart of the status monitoring module of a PCB board pressing and forming simulation system.

[0023] Figure 4 It is a schematic flow chart of the simulation diagnosis module of a PCB board pressing and forming simulation system.

[0024] Figure 5 It is a schematic flow chart of a PCB board pressing and forming simulation method. Specific Embodiments

[0025] The embodiments of the present invention will be described in detail below. The embodiments described below are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention. For those not specified in the embodiments in terms of specific technologies or conditions, they shall be carried out according to the technologies or conditions described in the literature in this field or according to the product specifications.

[0026] Refer to Figure 1 , a PCB board pressing and forming simulation system, including: a simulation design module, a member simulation module, a simulation maintenance module, a status monitoring module, and a simulation diagnosis module; wherein, the output end of the simulation design module is connected to the member simulation module, the output end of the member simulation module is connected to the simulation maintenance module, the output end of the simulation maintenance module is connected to the status monitoring module, and the output end of the status monitoring module is connected to the simulation diagnosis module.

[0027] The simulation design module is used to respond to the PCB board pressing simulation request, obtain the position parameters at each pressing, and form the morphological network of each layer.

[0028] The member simulation module is used to receive the position dimensions of each layer in the morphological network of the layer, and control the morphological change modulus and warping height of each layer at a single running step during the PCB board pressing.

[0029] The simulation maintenance module is used to verify the displacement trend of the PCB board at the boundary position based on the morphological change modulus and warping height of each layer, and determine the preset change direction and displacement difference of each morphological change modulus.

[0030] The status monitoring module is used to perform a simulation check on the displacement difference in the preset change direction, record the simulation transfer data of the PCB board displacement, perform a displacement excitation calculation based on the simulation transfer data, and generate a finite element simulation model of the displacement difference; and extract the morphological change modulus of each cavity on the PCB board to generate a finite element simulation model of each cavity.

[0031] The simulation diagnosis module is used to compare the displacement difference with the finite element simulation models of each cavity to determine the difference angle and type when there are differences in each model, and obtain the pressing diagnosis result of the PCB board.

[0032] In the circuit board lamination simulation request, the shape that the current circuit board needs to be laminated, the corresponding dimensions of each shape, and the required dimensions and shapes at positions such as cavities will be described. Then, these dimensions and shapes will be converted into position parameters for each position to illustrate the processing methods required for each position during circuit board lamination. When obtaining the position parameters for each position, mainly compare the dimensions on the circuit board after each lamination and perform inspections during the final completion to determine whether there are problems in some positions. These data can be obtained by using a camera to capture images of the circuit board after lamination and performing three-dimensional mapping on the images to form a layer morphology network.

[0033] In order to adapt to the shapes of different chips, when performing circuit board lamination, it is necessary to determine the scales of expansion and relative orientations of each layer for the curved surface or irregular shape of its outer shape to prevent the thermal expansion modulus and warping parts generated by lamination in individual layers from affecting the subsequent embedded installation of electronic components during the installation of electronic components.

[0034] Preferably, as Figure 2 shown, when laminating a PCB circuit board, the first lamination uses the lamination of layers L2 to L5, and then L1 is added for secondary lamination. UV laser forming is used for the laminated part to generate a cavity. Finally, layer L6 is laminated for the third lamination to form a Cavity cavity that can be used for the embedded installation of electronic components.

[0035] Preferably, it is required that the R corner of the circuit board after lamination is 0.2 mm and the residual thickness < 0.1 mm, so as to facilitate the installation and combination of embedded electronic components. At the same time, the subsequent Cavity cavities are all described using cavities.

[0036] That is, the implementation method of the simulation design module includes: initializing the position parameter list for each position, based on the shape of the current circuit board, and obtaining at least one set of position parameters. Each set of position parameters contains multiple design spaces. A design space refers to a set used to describe lamination process parameters.

[0037] Whenever the position parameters of the first design space are obtained; the first design space contains the dimensions of each layer after alignment for lamination to determine whether the position of the circuit board after lamination is accurate; determine the preset shape modulus of the circuit board at each corner based on the position parameters of the first design space; set the layer morphology network of the current layer according to the distribution of the preset morphology modulus on each layer.

[0038] Whenever the position parameters of the second design space are obtained, compare the current lamination process with the position parameters of the previous lamination, and add the position parameters of the second design space to the end of the position parameters of the previous lamination.

[0039] When the position parameters corresponding to the morphological network at the current level do not exist in the design space, the position parameters will be re-acquired and the corresponding position parameters will be adjusted to the available design space.

[0040] The first design space represents the initial design space, which is a set of benchmark parameters for the first lamination or new layer lamination, and is used to establish the initial hierarchical morphological network and verify the position accuracy after lamination. It mainly covers its layer alignment parameters, post-lamination dimensions, corner preset shape modulus, and layer morphological network.

[0041] The layer alignment parameters mainly indicate the coordinates of the positioning holes of each layer and the deviation of the target position in the X and Y directions, indicating whether the layers can form an aligned relationship during lamination.

[0042] The dimensions after pressing describe the mapping relationship between the theoretical dimensions after pressing, length, width, thickness, etc. and the actual measured values.

[0043] The preset shape modulus of the corners defines the displacement direction limit of the board edge during the lamination process, such as the maximum warpage height on the Z axis, which represents the maximum shape condition. At this time, a sampling inspection will be used to scan the laminated circuit board by laser ranging to see if there is warping or other shape changes.

[0044] The layer morphology network combines the coordinates of the nodes in each layer to obtain a network about the position, such as the cavity area, and other position coordinates containing the alignment of each layer. During the lamination process, the circuit board is composed of multiple layers of materials, such as copper skin layer, substrate layer, prepreg layer, etc. The morphology and position relationship of each layer forms a network structure, namely the layer morphology network.

[0045] The second design space is a set of parameters that are dynamically updated in multiple lamination iterations, which is used to record historical lamination data and optimize subsequent processes. It mainly records real-time process data such as temperature, pressure curve, lamination time, etc. during the current lamination, and checks whether these parameters change in size and shape at each position after production.

[0046] When comparing parameters in the second design space, the displacement difference and rotation angle deviation between the current layer and the previous pressing layer are mainly compared. If the rotation angle deviation is greater than 0.5 degrees or the displacement difference is greater than 0.5 mm, recalibration is performed. Otherwise, the valid second design space parameters are added to the end of the previous data to form a rolling updated database to update the parameters at all levels of the pressing situation.

[0047] In one embodiment of the present invention, the member simulation module mainly receives the running step in the pressing simulation request to determine the morphological changes of each layer, and distinguishes the morphological change modulus generated by each layer according to the process of each pressing to determine whether the circuit board will produce excessive deformation and warping after multiple pressings.

[0048] That is, the implementation method of the member simulation module includes: at intervals of the running step length, correlating the position dimensions and morphological relationships included in the layer morphology network to determine the displacement of each layer during the lamination process.

[0049] Compare the displacements of each layer at multiple running step lengths each time, and set the displacement change rate of each layer as the morphological change modulus of each layer.

[0050] Extract the warpage height corresponding to the morphological change modulus, and perform height mapping to determine the morphological change modulus at the corresponding positions under the distribution of the warp height at each point.

[0051] When performing member simulation, if the circuit board being laminated or the laminated circuit board is identified, a fixed time interval is used as the running step length. For example, time intervals such as 1 minute or 30 seconds are adopted. Then, the part being laminated or being cooled is collected through a laser or other image recognition device, and it is identified whether there are multiple warped parts and displaced parts on each laminated layer to prevent problems with alignment caused by the use of resin during lamination or the expansion of other materials. Identify the edges corresponding to each layer to determine the displacement of each layer. Then, mark the change rate of the displacement as the morphological change modulus after lamination of the circuit board. At the same time, identify the warped parts on the circuit board based on the average height of the circuit board, and combine the height values of this part with the generated displacement to obtain the output morphological change modulus.

[0052] In an embodiment of the present invention, during simulation maintenance, the main displacement is in the preset change direction. The occurrence direction and relative angle of the displacement generated in this direction are used to judge the layer offset in the alignment of each layer and the different situations in the extending directions of each layer, which is convenient for subsequent displacement of the corresponding material at the corresponding position after the cavity is dug out, resulting in the cavity not being able to embed the corresponding electronic components.

[0053] That is, the implementation method of the preset change direction in the simulation maintenance module includes: at least obtaining a layer of the circuit board subjected to lamination processing, scanning the lamination positions of each layer during lamination processing, determining the lamination boundary of each layer, and setting the displacement difference of each lamination boundary based on the relative distance of each layer at the lamination boundary.

[0054] Taking each lamination boundary as the starting point, setting the copper foil direction existing on the circuit board on each layer as the initial direction, and comparing the distribution order of the morphological change modulus and the corresponding position of the warpage height on each layer in the initial direction.

[0055] Take the direction with the largest distribution order as the displacement trend on the corresponding layer. After fitting the displacement trends of each layer according to their angles, a preset change direction is obtained. Project the displacement difference of each lamination boundary onto the preset change direction as the displacement difference of each morphological change modulus.

[0056] When setting the initial direction, set up a three-dimensional coordinate system for the plane where the circuit board is located. Set the XY axes corresponding to the length and width of the circuit board on the horizontal plane, and the Z axis corresponding to the height of the circuit board. Select the initial recognized direction of each layer on the circuit board starting from the X axis. Then compare the morphological change moduli that appear at this time. At this time, focus on comparing the part that can be directly observed after the circuit board is laminated. This part will be considered the lamination boundary. Then calculate the relative distance of each layer to identify whether the height of each layer is normal. After that, obtain its morphological change module according to the corresponding coordinates, and identify its warpage height. Use the morphological change modulus and warpage height to sort from large to small to illustrate the order of the recognized morphological changes and warpage positions. Then select the angle and direction where the part with the largest value is located to combine the possible expansion change directions on each layer. The calculation method of vector or angle fitting can be used. After combining multiple angles, a preset change direction is obtained. This direction will present the main trend of warpage or morphological changes that mainly occur during the production of the current circuit board, to identify whether the current circuit board meets the expected settings during the lamination process and prevent the problem that some production defective products are not recognized. The preset change direction represents the main trend of the overall morphological changes of the circuit board during the lamination process. It can be used to guide subsequent process optimization, such as adjusting lamination parameters, such as pressure, temperature, etc. to reduce warpage or deformation; this direction can also help engineers design a more reasonable copper foil wiring scheme to avoid signal integrity problems caused by deformation.

[0057] When fitting to obtain the preset change direction of each layer, the overall displacement trend that occurs during the lamination of the circuit board in the production process can also be described and sorted out by fitting the recognized directions after each lamination process.

[0058] For each output preset change direction, it can represent that when performing the initial direction fitting, the circuit board is divided into multiple regions according to the position of the lamination boundary. After fitting the initial directions of these multiple regions, multiple preset change directions are output. Or based on the inspection data of multiple groups of circuit boards, illustrate the displacement differences existing at the angles of multiple preset change directions.

[0059] In an embodiment of the present invention, when the status monitoring module performs simulation inspection, it determines that the simulation transfer data mainly identifies the transfer change of the displacement amount, determines whether the displacement generated by the previous lamination will affect the subsequent generated displacement, and after projecting and accumulating the total displacement generated onto all existing nodes on the layer morphology network, it can represent the comprehensive change of the displacement amount in several directions.

[0060] like Figure 3 As shown, the implementation method of displacement excitation calculation includes: extracting the displacement difference generated in the preset change direction during each pressing to form a displacement difference matrix, and setting it as the displacement state during simulation inspection, and establishing a mapping relationship between the displacement state and the layer morphology network.

[0061] The mapping relationship between the displacement state and the layer morphology network is used to verify the corresponding position of the displacement state in the layer morphology network, and the displacement transfer coefficient between each displacement state under clock offset and position offset is determined.

[0062] The validity of each displacement transfer coefficient is verified recursively. If the displacement transfer coefficient is valid, the credibility of the displacement transfer coefficient is used as the result of the displacement excitation calculation.

[0063] At this time, it is explained that the simulation transfer data is to calculate the displacement transfer coefficient according to the corresponding position of the layer morphology network according to the displacement difference. The corresponding process is the content of the simulation transfer data. Whether the displacement transfer coefficient is valid is determined by calculating the displacement between each layer through the displacement transfer coefficient. When the accuracy of the error between the calculated value and the actual value is greater than 0.95, the data corresponding to the displacement transfer coefficient identification is output as the result of the displacement excitation calculation at this time, and this part of the data is combined into a finite element simulation model of the displacement difference.

[0064] The corresponding position of the displacement state in the layer morphological network is verified by compensating the error between the displacement states when the time step and the spatial coordinates are inconsistent, and then using the displacement transfer coefficient to compensate for this part.

[0065] For example, after each pressing, the displacement difference projected to the preset direction along the XYZ axis is extracted. , forming the displacement difference matrix , ; There are n elements in the displacement difference matrix.

[0066] Assuming that the displacement is transferred linearly between layers, a transfer matrix is ​​established at the corresponding level in the layer morphological network according to the corresponding displacement difference, and the corresponding position of the displacement state in the layer morphological network is verified.

[0067] The displacement difference matrix is ​​mapped to the layer morphology network to generate the displacement vectors of all nodes in each layer after compression. , k represents the number of layers currently identified, and can also represent the number of displacement vectors, and its value range is 1 to K.

[0068] ;in, represents the displacement vector of the (k + 1)-th layer, represents the displacement transfer coefficient from the k-th layer to the (k + 1)-th layer, represents the displacement vector of the k-th layer, represents the error term of the k-th layer.

[0069] ; where, , , respectively represent the relationship coefficients of the current layer and the next layer affected by thermal expansion in the X, Y, and Z directions, , , respectively represent the relationship coefficients of the current layer and the next layer in terms of shear deformation in the X, Y, and Z directions, , , respectively represent the relationship coefficients of the current layer and the next layer in terms of layer position in the X, Y, and Z directions. The relationship coefficients set at this time are set according to the displacement amounts that appeared at the corresponding positions during historical data analysis.

[0070] For example, independent solutions are carried out for each direction ; where, N represents the number of nodes included in each layer, and the value range of i is from 1 to N, represents the displacement vector of the i-th node in the X direction of the (k + 1)-th layer, represents the displacement vector of the i-th node in the X direction of the k-th layer, represents the displacement vector of the i-th node in the Y direction of the k-th layer, represents the displacement vector of the i-th node in the Z direction of the k-th layer; after comprehensively calculating these contents, the corresponding ones with the minimum error are required , , After output, the remaining several unit parameters are calculated in the same way. The least squares method is used to calculate the displacement vector of each layer to obtain the matrix value represented by the displacement transfer coefficient at this time.

[0071] Or the displacement transfer coefficient set at present can be obtained by means of matrix element settlement, such as ; where, represents the operation of vector transposition of the displacement vector of the k-th layer to solve the corresponding displacement transfer coefficient.

[0072] Finally, the displacement transfer coefficient is used to predict the value of the displacement vector, and the average value of the difference between the predicted value and the actual displacement vector value is set as the confidence score; for example, taking the reciprocal of 1 plus the average value of the difference, that is the confidence score used here, to represent the result of the displacement amount excitation calculation.

[0073] The calculated credibility scores are applied to the layer morphology network to describe the boundary conditions and displacement distribution in the finite element simulation model of the displacement difference combination to obtain the finite element simulation model of the displacement difference.

[0074] That is, the implementation method of generating a finite element simulation model of displacement difference also includes: using the displacement transfer coefficient and credibility score obtained at each level as boundary conditions, interpolating each node in the level morphology network, and combining the distribution of the displacement transfer coefficient and credibility score after interpolation with the value of the displacement difference as the output finite element simulation model; this simulation model is mainly used to describe the distribution of the calculated displacement difference and the relationship between the displacement transfer coefficient representing the displacement transmission, so as to express the relative effects of the current circuit board after the compression treatment of its various boundaries during production.

[0075] In the finite element simulation model of displacement difference, the main output is the overall displacement distribution diagram of the circuit board, which shows the displacement of each node. The distribution of these displacement conditions is used to represent the relative problems existing in the current circuit board production.

[0076] The finite element simulation model of each cavity tends to illustrate that when the required cavity holes are generated, the hole boundaries and sizes can meet the installation size of the electronic components. When setting up the finite element model, the cavity edge constraints, material response and concentrated displacement around the cavity are used as its boundary conditions, and the three-dimensional geometric shape and pressing time are used as its simulation conditions to describe the realization process of the finite element model in the composition of each boundary position. At the same time, it explains the realization content of the final influencing factors and troubleshooting results when its three-dimensional geometric shape changes.

[0077] The finite element simulation model of each cavity is generated by using the cavity edge constraint, material response and concentrated displacement around the cavity as boundary conditions, and the three-dimensional geometry and pressing time as simulation conditions. Cavity edge constraint refers to the fixed or moving restrictions imposed on the area around the cavity in finite element analysis; material response includes material properties such as elastic modulus and Poisson's ratio, which determine the behavior of the material under stress. The concentrated displacement around the cavity represents the average displacement around the cavity, which indicates whether pressing during processing will cause dimensional deviation in the production of the cavity.

[0078] Based on the state transition probability of each boundary condition and simulation condition in the layer morphology network, the distribution of each cavity is described, and the maximum value of the state transition probability is used as the output of the finite element simulation model of each cavity. At this time, the state transition probability represents the conditional probability of at least one set of related data that satisfies the boundary conditions and simulation conditions, to represent the probability of the corresponding data changing, so as to predict the displacement and morphological changes that occur during the production of circuit boards under different conditions, and prevent displacement deviations at the cavity, which may lead to problems in the subsequent installation of electronic components.

[0079] The selected state transition probability is based on the probability value of the selected boundary conditions and simulation conditions in the layer morphological network within a specific time period, that is, the currently sampled data is used as the standard to determine the selected boundary conditions and simulation conditions that appear in the current sampled data, and the values ​​of these conditions are combined with historical data to statistically calculate the state transition probability of the corresponding conditions.

[0080] The cavity edge constraint is expressed as the condition of whether the coordinate point at the cavity edge is allowed to displace. In general, in order to prevent the stress concentration effect, the cavity edge of the circuit board needs to verify the displacement of the points at the cavity edge to prevent excessive displacement from causing deformation of the cavity edge. That is, the cavity edge constraint will be expressed as the displacement value allowed for multiple nodes at the cavity edge, which can be zero or allow very small displacement. To verify this condition, laser scanning is used to determine the displacement, and the displacement at the cavity edge is regarded as its cavity edge constraint.

[0081] The material response is manifested as Young's modulus, Poisson's ratio, yield strength, thermal expansion coefficient and nonlinear characteristics. These contents will mark the material properties of each layer superimposed by the circuit boards around the cavity. These parameters can be obtained according to the materials used to prevent the corresponding material from being unable to be queried when the cavity is generated abnormally.

[0082] Young's modulus measures the material's ability to resist stretching or compression and determines the material's stiffness; Poisson's ratio represents the ratio of the material's lateral strain to its longitudinal strain, reflecting the material's degree of lateral contraction or expansion when subjected to stress; yield strength represents the stress level at which the material begins to permanently deform; the coefficient of thermal expansion describes the dimensional change of the material with temperature, which is particularly important for applications involving temperature changes; nonlinear characteristics indicate that some materials exhibit nonlinear behavior under high stress, such as hardening or softening effects; these reactions will indicate the material properties of each layer of the circuit board when it is pressed together, to reflect whether there are corresponding problems in the pressing of the circuit board, that is, the standard property values ​​of the corresponding materials are used as the boundary conditions of the material response at this time.

[0083] The concentrated displacement around the cavity is manifested as the significant displacement generated around the cavity, that is, part of the data screened by the magnitude of the displacement generated by the surrounding nodes, and this part will significantly exceed the average value of the displacement around the cavity. These points are used as the boundary conditions corresponding to the concentrated displacement around the cavity.

[0084] For the simulation conditions of the three-dimensional geometry and the pressing time, it means that under the dimensional requirements corresponding to the three-dimensional geometry of the circuit board, how long the pressing time is used, and then the simulation conditions appear. The values taken by the simulation conditions and the form of the co-occurrence conditional probability of the current simulation conditions are used to quantify the situations corresponding to different circuit boards under various productions.

[0085] In an embodiment of the present invention, as Figure 4 shown, the implementation method of the simulation diagnosis module includes: using the displacement difference and the finite element simulation models of each cavity for feature characterization, and randomly extracting multiple data as the characterization features.

[0086] Processing the characterization features with the finite element simulation model of the displacement difference, querying at least one difference node, and determining the effectiveness of the characterization features according to the physical position of the difference node; wherein, the difference node is used to represent the mapping relationship between the characterization features; the statement that the difference node represents the mapping relationship between the characterization features indicates that the positions of the first characterization feature and the second characterization feature used subsequently are mutually mapped.

[0087] Retrieving the difference angle with the effectiveness of the characterization features, determining the difference angle corresponding to the characterization features, and marking the type corresponding to each difference angle; outputting the data corresponding to the difference angle and the type as the pressing diagnosis result.

[0088] Determining the effectiveness of the characterization features includes: if the current characterization feature is abnormally distributed in the finite element simulation model of the displacement difference, taking the characterization feature of the corresponding difference node as the first characterization feature, and obtaining the characterization features of the finite element simulation models of each cavity as the second characterization feature, and comparing the priorities of the first characterization feature and the second characterization feature; if the priority of the first characterization feature is greater than the priority of the second characterization feature, then it is determined that the first characterization feature is effective, otherwise the second characterization feature is regarded as effective.

[0089] The implementation method of retrieving the difference angle with the effectiveness of the characterization features includes: extracting the effective duration and the update interval of the characterization features, and using the update interval as an index to retrieve the difference angle with differences, associating the difference angle with the effective duration, and then marking the type corresponding to each difference angle.

[0090] Preferably, the data extracted by the characterization features can be expressed as the following content as shown in Table 1.

[0091] Table 1. Example data of characterization features

[0092]

[0093] Among them, the nodes represent the data randomly obtained from the relevant finite element models of the displacement difference and the cavity. These data are used as node identifiers. Then, the values of the displacement difference in the X, Y, and Z directions, namely ΔX, ΔY, and ΔZ, are obtained. At the same time, the maximum stress value σ_max existing at the corresponding acquisition position is recorded. This stress value can be calculated from the stress generated by the thermal expansion of the material. For the parameters such as the R angle and the remaining thickness near the cavity, they represent the parameter sizes measured at this cavity after multiple pressings. These contents represent whether the production of the current cavity meets the final standard.

[0094] The data extracted from the finite element simulation model of the displacement difference in the first characterization feature will include the displacements in its X, Y, and Z directions, and then the maximum stress value and the distance from the cavity edge are added to represent the position of the corresponding node. The second characterization feature is to obtain the maximum stress value of the corresponding node, the distance from the cavity edge, as well as the R angle and the remaining thickness.

[0095] When extracting the differential nodes from the first characterization feature, they are selected according to the displacement differences in its three directions and the maximum stress value. For example, based on the displacement difference in the X direction and the maximum stress value of the node, when either ΔX > 0.1 mm or σ_max > 40 MPa is satisfied, the node corresponding to the first characterization feature is regarded as a differential node. Or, the average value of the historical data of the displacement differences in the X, Y, and Z directions, as well as the average value of the maximum stress value in the historical data, are extracted. When there is data corresponding to the first characterization feature greater than this average value, the corresponding node is marked as a differential node. At this time, the selected nodes are the nodes where there are obvious changes in the corresponding layer of the circuit board after pressing. These nodes will reflect the overall deformation of the circuit board or the relevant data of the relative layers after pressing, preventing problems such as layer offset and other issues that cause deviations in the production size of the circuit board.

[0096] After comparing the priorities of the first characterization feature and the second characterization feature, when judging their priorities, it is necessary to compare the conditions of the remaining thickness and the distance from the cavity edge. The purpose of judging this priority is mainly to identify the points located at the cavity edge, preventing problems with the corresponding dimensions of the cavity formed after multiple pressings, resulting in the inability to directly fit the corresponding electronic components to this position during installation.

[0097] That is, when comparing the priorities of the first characterization feature and the second characterization feature, the distance value from the cavity edge corresponding to the first characterization feature and the remaining thickness value in the second characterization feature are extracted. If neither the distance value from the cavity edge nor the remaining thickness value satisfies any of the conditions in the preset rules, the first characterization feature is regarded as valid. When any of the conditions in the preset rules is satisfied, the second characterization feature is regarded as valid.

[0098] Its preset rules are represented by two conditions: the residual thickness is less than 0.1 mm and the distance from the cavity edge is less than 1.0 mm. When the condition corresponding to the residual thickness is not met, it indicates that the problems existing in the current circuit board may not be limited to the points at the cavity edge. It is necessary to mainly verify other positions to determine why its residual thickness does not conform to the preset rules and identify the displacement difference generated during its production, etc. That is, mainly process the data covered by the first characterization feature. When the condition of the distance from the cavity edge is not met, it indicates that its position is far from the cavity and there is no need to additionally judge the cavity-related data. Just judge according to the content shown by the first characterization feature. When both conditions are met, it indicates that after the production of its residual thickness meets the standard, it is necessary to judge other parameters around the cavity, mainly based on the second characterization feature. After identifying whether its R angle is 0.2 mm, identify the parameters around the cavity and sequentially complete the identification and processing of the main problems of the current circuit board.

[0099] Assume that the nodes described in Table 1 are all regarded as differential nodes, and the validity of this characterization feature is illustrated by the data corresponding to these three nodes. Among them, for node 1001, the residual thickness is 0.119 mm, which is greater than 0.1 mm, and the distance value from the cavity edge is 2.0 mm, which is greater than 1 mm. Neither of the two rules for priority comparison is satisfied. It indicates that at this time, it is necessary to mainly use the data in the first characterization feature to identify the data difference generated at the current position.

[0100] For node 1002, the residual thickness is 0.095 mm, which is less than 0.1 mm, and the distance value from the cavity edge is 1.2 mm, which is greater than 1 mm. It indicates that at this time, when the residual thickness of the cavity meets the condition, since this node is far from the cavity edge, it is necessary to identify the displacement difference and the maximum stress value in the corresponding direction to prevent the values at this position from being too large and affecting the cavity size. That is, mainly use the data of the first characterization feature to identify the relevant positions.

[0101] For node 1003, the residual thickness is 0.091 mm, which is less than 0.1 mm, and the distance value from the cavity edge is 0.5 mm, which is less than 1 mm. It indicates that at this time, both priority comparison rules are satisfied, and mainly identify the data covered in the second characterization feature to identify whether the corresponding R angle is normal, so as to judge the production situation of the current circuit board.

[0102] Preferably, when identifying the size of its R angle, it is required that the R angle is 0.2 mm and does not exceed three times the standard deviation value calculated during its production, that is, within the range of 0.2 mm plus three times the standard deviation, it is regarded that the R angle corresponding to the cavity of this circuit board is compliant content.

[0103] For the subsequent differential angles used, the angle values are mainly based on the angle between the three-dimensional vector represented by the displacement difference generated at this node and the three-dimensional vector represented by the maximum allowable displacement difference at the corresponding position. This angle is used as the differential angle, and this differential angle is used to retrieve data in the database to identify the reasons represented by this differential angle. As shown in Table 2, corresponding possible reasons can be retrieved according to the range where the differential angle is located, as well as the type corresponding to this differential angle.

[0104] Table 2. Angle Classification Rules

[0105]

[0106] At this time, multiple data samplings will be performed according to the number of pressings and the cooling time of the circuit board after pressing, and after retrieving the differential angle with the number of pressings as an additional index, the existing type will be identified to determine whether there are corresponding problems during the production of the current circuit board.

[0107] After that, according to the judgment of the effective durations corresponding to the first characterization feature and the second characterization feature, the effective duration represents the time period length when the differential angle is retrieved using the first characterization feature and the second characterization feature respectively, and according to the differences between these two characterization features and the time interval between the retrieval time periods, the types of the retrieved differential angles are sorted to output the pressing diagnosis result of the circuit board; the pressing diagnosis result of the circuit board will include the time period when the output differential angle is retrieved, the retrieved type, and other retrieved data, and also include the extracted first characterization feature and the second characterization feature, and finally describe the relevant problems during the production of the circuit board in the corresponding time period to reduce the error of the corresponding dimensions during the production of the circuit board.

[0108] Finally, the staff will adjust the production method of the circuit board according to the pressing diagnosis result. For example, if interlayer misalignment is detected, it is recommended to check the pressure distribution of the press; if structural mismatch is detected, it is recommended to recalibrate the mold or adjust the material matching.

[0109] As Figure 5 shown, the present invention also provides a method for simulating the pressing and forming of a PCB circuit board, including: S1, in response to a circuit board pressing simulation request, obtaining the position parameters at each pressing to form a morphological network for each layer.

[0110] S2, receiving the position dimensions of each layer in the morphological network of the layers, and controlling the morphological change modulus and warping height of each layer at a single running step during the pressing of the circuit board.

[0111] S3, based on the morphological change modulus and warping height of each layer, verifying the displacement trend of the circuit board at the boundary position, and determining the preset change direction and displacement difference of each morphological change modulus.

[0112] S4. Perform a simulation check on the displacement difference in the preset change direction, and based on the simulated transmission data, generate a finite element simulation model of the displacement difference and each cavity.

[0113] S5. Compare using the displacement difference and the finite element simulation models of each cavity to determine the difference angle and type of each model at the time of the difference, and obtain the lamination diagnosis result of the circuit board.

[0114] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention, and still be covered by the protection scope of the present invention.

Claims

1. A PCB circuit board pressing and forming simulation system, characterized in that: include: The simulation design module is used to respond to the circuit board pressing simulation request, obtain the position parameters of each pressing, and form the morphological network of each layer; A member simulation module is used to receive the position size of each layer in the layer morphology network, and control the morphology change modulus and warpage height of each layer on a single running step when the circuit board is pressed; A simulation maintenance module is used to verify the displacement direction of the circuit board at the boundary position based on the morphological change modulus and warpage height of each layer, and determine the preset change direction and displacement difference of each morphological change modulus; The state monitoring module is used to simulate and check the displacement difference in the preset change direction, record the simulation transfer data of the circuit board displacement, perform displacement excitation calculation based on the simulation transfer data, and generate a finite element simulation model of the displacement difference; and extract the morphological change modulus of each cavity on the circuit board to generate a finite element simulation model of each cavity; The simulation diagnosis module is used to compare the displacement difference with the finite element simulation model of each cavity, determine the difference angle and type of each model when it is different, and obtain the pressing diagnosis result of the circuit board.

2. A PCB circuit board pressing and forming simulation system according to claim 1, characterized in that: The implementation methods of the simulation design module include: Initialize each position parameter list, based on the shape of the current circuit board, obtain at least one set of position parameters, each set of position parameters contains multiple design spaces; Whenever the position parameters of the first design space are obtained, the preset shape modulus of the circuit board at each corner is determined according to the position parameters of the first design space; and the layer morphology network of the current layer is set according to the distribution of the preset shape modulus at each layer; Whenever the position parameters of the second design space are obtained, the position parameters of the current pressing process are compared with the position parameters of the last pressing process, and the position parameters of the second design space are added to the end of the position parameters of the last pressing process; When the position parameters corresponding to the morphological network at the current level do not exist in the design space, the position parameters will be re-acquired and the corresponding position parameters will be adjusted to the available design space.

3. A PCB circuit board pressing and forming simulation system according to claim 1, characterized in that: The member simulation module is implemented by associating the position size and morphological relationship contained in the layer morphological network with the operation step length as the interval to determine the displacement of each layer during the pressing process; Compare the displacement of each layer at each multiple running step, and set the displacement change rate of each layer as the morphological change modulus of each layer; The warping height corresponding to the morphological change modulus is extracted, and height mapping is performed to determine the morphological change modulus at the corresponding position under the distribution of the warping height at each point.

4. A PCB circuit board pressing and forming simulation system according to claim 1, characterized in that: The implementation methods of preset change direction in the simulation maintenance module include: At least one layer of the circuit board is obtained for lamination, and the positions of the layers during lamination are scanned to determine the lamination boundaries of the layers, and the displacement difference of the lamination boundaries is set according to the relative distances of the layers on the lamination boundaries; Taking each lamination boundary as the starting point, the direction of the copper foil on each layer of the circuit board is set as the initial direction, and the distribution order of the corresponding positions of the morphological change modulus and the warpage height on each layer in the initial direction is compared; The direction with the largest distribution order is taken as the displacement direction on the corresponding level. After fitting the displacement directions of each level according to its angle, the preset change direction is obtained. The displacement difference of each pressed boundary is projected onto the preset change direction as the displacement difference of each morphological change modulus.

5. A PCB circuit board pressing and forming simulation system according to claim 1, characterized in that: The implementation methods of displacement excitation calculation include: The displacement difference generated in the preset change direction during each pressing is extracted to form a displacement difference matrix, and is set as the displacement state during the simulation inspection, and a mapping relationship is established between the displacement state and the layer morphology network; By using the mapping relationship between the displacement state and the layer morphology network, the corresponding position of the displacement state in the layer morphology network is verified, and the displacement transfer coefficient between each displacement state under the clock offset and position offset is determined; The validity of each displacement transfer coefficient is verified recursively. If the displacement transfer coefficient is valid, the credibility of the displacement transfer coefficient is used as the result of the displacement excitation calculation.

6. A PCB circuit board pressing and forming simulation system according to claim 5, characterized in that: The implementation method of generating a finite element simulation model of displacement difference also includes: The displacement transfer coefficient and credibility score obtained at each level are used as boundary conditions, and each node in the level morphology network is interpolated. The distribution of the displacement transfer coefficient and credibility score after interpolation is combined with the value of the displacement difference as the output finite element simulation model.

7. A PCB circuit board pressing and forming simulation system according to claim 5, characterized in that: The implementation methods of generating the finite element simulation model of each cavity include: The cavity edge constraint, material response and concentrated displacement around the cavity are used as boundary conditions, and the three-dimensional geometry and pressing time are used as simulation conditions; Based on the state transition probabilities of each boundary condition and simulation condition in the layer morphology network, the distribution of each cavity is described, and the maximum value of the state transition probability is used as the output of the finite element simulation model of each cavity.

8. A PCB circuit board pressing and forming simulation system according to claim 1, characterized in that: The implementation methods of the simulation diagnosis module include: The displacement difference and the finite element simulation model of each cavity are used for feature characterization, and multiple data are randomly extracted as the characterization features; Processing the characterization feature with a finite element simulation model of the displacement difference, querying at least one difference node, and determining the validity of the characterization feature based on the physical position of the difference node; The difference angles are searched based on the validity of the characterization features, the difference angles corresponding to the characterization features are determined, and the types corresponding to the difference angles are marked; the data corresponding to the difference angles and types are output as the pressing diagnosis results.

9. A PCB circuit board pressing and forming simulation system according to claim 8, characterized in that: Determining the validity of a characterization feature includes: If the current characterization feature is abnormally distributed in the finite element simulation model of the displacement difference, the characterization feature of the corresponding difference node is used as the first characterization feature, and the characterization feature of the finite element simulation model of each cavity is obtained as the second characterization feature, and the priority of the first characterization feature and the second characterization feature is compared; if the priority of the first characterization feature is greater than the priority of the second characterization feature, the first characterization feature is judged to be valid, otherwise the second characterization is deemed to be valid; The implementation methods of retrieving the difference angle based on the effectiveness of the characterization features include: The effective duration and update interval of the characterization feature are extracted, and the difference angle where the difference occurs is retrieved with the update interval as the index. After associating the difference angle with the effective duration, the type corresponding to each difference angle is marked.

10. A PCB circuit board pressing and forming simulation method, characterized in that: include: S1, in response to the circuit board pressing simulation request, obtains the position parameters of each pressing, and forms the morphological network of each layer; S2, receiving the position size of each layer in the layer morphology network, controls the morphology change modulus and warpage height of each layer on a single running step when the circuit board is pressed; S3, based on the morphological change modulus and warpage height of each layer, verify the displacement direction of the circuit board at the boundary position, and determine the preset change direction and displacement difference of each morphological change modulus; S4, performing simulation inspection on the displacement difference in the preset change direction, and generating a finite element simulation model of the displacement difference and each cavity based on the simulation transfer data; S5, using the displacement difference and the finite element simulation model of each cavity to compare, determine the difference angle and type of each model when different, and obtain the press-fit diagnosis result of the circuit board.

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