Gate driving circuit and display device including the same

Abstract

The invention discloses a gate drive circuit and a display device. The gate driving circuit may include: a gate signal generation circuit configured to sequentially output at least one gate signal having a square wave pulse; and a ramp voltage generation circuit configured to receive the at least one gate signal and a slope data voltage to output a ramp voltage signal including a ramp waveform based on a square wave pulse of the at least one gate signal and the slope data voltage.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0185938, filed on December 19, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a gate driving circuit and a display device including the gate driving circuit. Background art

[0004] A variety of flat panel displays are known, including electroluminescent displays (ELDs) such as liquid crystal displays (LCDs) and organic light - emitting diode (OLED) displays, field emission displays (FEDs), plasma display panels (PDPs), and electrophoretic displays (EPDs).

[0005] A display device includes: a display panel having pixels arranged to display an input image; and a display panel driving circuit that writes data into the pixels of the display panel. The display panel driving circuit includes: a data driving circuit that supplies a data voltage to data lines of the display panel; and a gate driving circuit that supplies a gate signal to gate lines of the display panel.

[0006] The gate driving circuit outputs a gate signal having a pulse shape. The gate signal may include a scan signal, an emission signal, etc. When the gate signal is applied as a ramp waveform, it provides many design advantages in improving the driving characteristics and image quality of pixels. However, a conventional gate driving circuit cannot output a gate signal having a ramp waveform. Summary of the invention

[0007] Accordingly, the present disclosure aims to provide a gate driving circuit and a display device including the gate driving circuit that substantially eliminate one or more problems caused by limitations and disadvantages of the prior art.

[0008] The present disclosure aims to provide a gate driving circuit capable of outputting a ramp voltage signal and a display device including the gate driving circuit.

[0009] The object of the present disclosure is not limited to the above - mentioned object, and those skilled in the art can clearly understand other objects not mentioned from the following description.

[0010] To achieve these objects and other advantages of the present disclosure, as embodied and broadly described herein, a gate driving circuit may include: a gate signal generating circuit configured to sequentially output at least one gate signal having a square wave pulse; and a ramp voltage generating circuit configured to receive the at least one gate signal and a slope data voltage and output a ramp voltage signal including a square wave pulse based on the at least one gate signal and a ramp waveform based on the slope data voltage.

[0011] In some example embodiments, the at least one gate signal includes: an (n - 1)th scan signal, and an nth scan signal after the (n - 1)th scan signal, where n is a natural number. The ramp voltage generating circuit includes: a driving transistor including a first electrode configured to receive a driving voltage, a gate electrode connected to a first node, and a second electrode connected to a second node; a first capacitor connected between a VDD node configured to receive the driving voltage and the first node; a first switching transistor connected between a data line configured to receive the slope data voltage and the first node, the first switching transistor being configured to conduct in response to a gate turn-on voltage of the nth scan signal; a second switching transistor connected between the second node and a reference voltage node configured to receive a reference voltage lower than the driving voltage, or connected between the second node and a ground node, the second switching transistor being configured to conduct in response to a gate turn-on voltage of the (n - 1)th scan signal; and a second capacitor connected between the second node and the ground node, or connected between the second node and the reference voltage node. The square wave pulse of the (n - 1)th scan signal may have the gate turn-on voltage of the (n - 1)th scan signal, and the square wave pulse of the nth scan signal may have the gate turn-on voltage of the nth scan signal.

[0012] In some example embodiments, the at least one gate signal may include a scan signal. The ramp voltage generation circuit may include: a driving transistor including a first electrode configured to receive a driving voltage, a gate electrode connected to a first node, and a second electrode connected to a second node; a first capacitor connected between a VDD node configured to receive the driving voltage and the first node; a first switching transistor connected between a data line configured to receive the slope data voltage and the first node, the first switching transistor being configured to conduct in response to a gate conduction voltage of the scan signal; a second switching transistor connected between the second node and a reference voltage node configured to receive a reference voltage lower than the driving voltage, or connected between the second node and a ground node, the second switching transistor being configured to conduct in response to the gate conduction voltage of the scan signal; and a second capacitor connected between the second node and the ground node, or connected between the second node and the reference voltage node. A square wave pulse of the scan signal may have the gate conduction voltage.

[0013] In some example embodiments, the at least one gate signal may include: an (n - 1)-th scan signal; an n-th scan signal after the (n - 1)-th scan signal, and a ramp switch signal, where n is a natural number. A square wave pulse of the ramp switch signal may overlap with a square wave pulse of the (n - 1)-th scan signal and a square wave pulse of the n-th scan signal. The ramp voltage generation circuit may include: a driving transistor including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node; a first capacitor connected between a VDD node configured to receive a driving voltage and the second node; a first switching transistor connected between the VDD node and the first node and configured to conduct in response to a gate conduction voltage of the ramp switch signal; a second switching transistor connected between a data line configured to receive the slope data voltage and the first node and configured to conduct in response to a gate conduction voltage of the n-th scan signal; a third switching transistor connected between the second node and the third node and configured to conduct in response to the gate conduction voltage of the n-th scan signal; a fourth switching transistor connected between the second node and an initialization voltage node configured to receive an initialization voltage and configured to conduct in response to a gate conduction voltage of the (n - 1)-th scan signal; a fifth switching transistor connected between the third node and a fourth node and configured to conduct in response to the gate conduction voltage of the ramp switch signal; a sixth switching transistor connected between the fourth node and a reference voltage node configured to receive a reference voltage or between the fourth node and a ground node, the sixth switching transistor being configured to conduct in response to the gate conduction voltage of the (n - 1)-th scan signal; and a second capacitor connected between the fourth node and the reference voltage node or between the fourth node and the ground node. The square wave pulse of the (n - 1)-th scan signal may have a gate conduction voltage of the (n - 1)-th scan signal, and the square wave pulse of the n-th scan signal may have a gate conduction voltage of the n-th scan signal. The square wave pulse of the ramp switch signal may have a gate off voltage, and the ramp switch signal may be at the gate conduction voltage after the square wave pulse of the ramp switch signal.

[0014] In some example embodiments, the first switching transistor includes a first electrode connected to the VDD node, a gate electrode configured to receive the ramp switching signal, and a second electrode connected to the first node. The second switching transistor may include a first electrode connected to the data line, a gate electrode configured to receive the n-th scan signal, and a second electrode connected to the first node. The third switching transistor may include a first electrode connected to the second node, a gate electrode configured to receive the n-th scan signal, and a second electrode connected to the third node. The fourth switching transistor may include a first electrode connected to the second node, a gate electrode configured to receive the (n-1)-th scan signal, and a second electrode connected to the initialization voltage node; the fifth switching transistor may include a first electrode connected to the third node, a gate electrode configured to receive the ramp switching signal, and a second electrode connected to the fourth node. The sixth switching transistor may include a first electrode connected to the fourth node, a gate electrode configured to receive the (n-1)-th scan signal, and a second electrode connected to the reference voltage node or the ground node.

[0015] In some example embodiments, the ramp waveform of the ramp voltage signal may have a slope; and the degree of the slope varies based on the slope data voltage.

[0016] In some example embodiments, the ramp voltage generating circuit may have a driving period, the driving period including an initialization period and a ramp period after the initialization period; during the initialization period, the voltage of the ramp voltage signal may be configured to decrease to a reference voltage. During the ramp period, the voltage of the ramp voltage signal is configured to gradually increase to be higher than the reference voltage to have the ramp waveform.

[0017] In some example embodiments, during the ramp period, the voltage of the ramp voltage signal may be configured to gradually increase from the reference voltage.

[0018] In some example embodiments, the driving period may further include a holding period between the initialization period and the ramp period. During the holding period, the ramp voltage signal may be configured to be held at the reference voltage.

[0019] In some example embodiments, the driving period may further include a programming period between the initialization period and the ramp period. During the programming period, the voltage of the ramp voltage signal may be configured to gradually increase from the reference voltage. During the ramp period, the voltage of the ramp voltage signal may be configured to continue to gradually increase after the gradual increase in the programming period.

[0020] According to another aspect of the present disclosure, a display device may include: a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits; a data driver configured to output data voltages of pixel data to the pixel circuits through the data lines respectively; and a gate driver configured to output at least one gate signal including a square wave pulse and a ramp voltage signal including a ramp waveform to the pixel circuits through the gate lines respectively.

[0021] In some example embodiments, the at least one gate signal may include a scan signal and an emission signal. Each of the plurality of pixel circuits may include: a pixel driving transistor, a pixel switching transistor, and a light emitting element connected in series between a pixel driving voltage and a cathode voltage; and a gate electrode of the pixel switching transistor is configured to receive the emission signal or the ramp voltage signal.

[0022] In some example embodiments, each of the plurality of pixel circuits may further include a compensation circuit configured to receive at least one of the scan signal, the emission signal, the ramp voltage signal, and the data voltage of the pixel data, and connected to the pixel driving transistor and the pixel switching transistor.

[0023] In some example embodiments, each of the plurality of pixel circuits may include: a current generation circuit configured to receive a pixel driving voltage and output a constant current; a pulse width control circuit configured to receive the data voltage of the pixel data and the ramp voltage signal and output a pulse width modulation (PWM) signal; and a switching transistor configured to switch a current flowing through the light emitting element in response to the PWM signal.

[0024] In some example embodiments, the gate driver may include: a gate signal generation circuit configured to sequentially output the at least one gate signal including the square wave pulse; and a ramp voltage generation circuit configured to receive the at least one gate signal and a slope data voltage, and output the ramp voltage signal based on the square wave pulse of the at least one gate signal and the slope data voltage.

[0025] According to an embodiment of the present disclosure, a display panel advantageous in terms of high efficiency, high brightness, and long service life can be realized.

[0026] According to an embodiment of the present disclosure, a gate signal having a ramp waveform can be output from a gate driving circuit that supplies a gate signal to a pixel.

[0027] According to an embodiment of the present disclosure, a gate signal having a ramp waveform can be stabilized by compensating for the threshold voltage of a transistor that generates a current, so as to generate a stable constant current in a gate driver.

[0028] According to an embodiment of the present disclosure, the brightness of a pixel can be adjusted by applying a gate signal having a ramp waveform to a pixel circuit.

[0029] According to an embodiment of the present disclosure, the image quality can be improved by improving the gray-scale representation of each gray level and by improving the brightness and color perception of the pixels.

[0030] The advantages and effects according to the present disclosure are not limited to the above-mentioned advantages and effects. Other advantages and effects are included in the present disclosure, or other advantages and effects can be obtained from the present disclosure.

[0031] Other features and aspects of the present disclosure will be set forth in the following description, and some features and aspects will become apparent from the description, or can be learned by practicing the inventive concept provided herein. Other features and aspects of the inventive concept can be achieved and obtained by structures specifically pointed out or derivable from the description, claims, and drawings.

[0032] It should be understood that the above general description and the following detailed description of the present disclosure are both provided by way of example, and are intended to provide further explanation of the claimed disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by referring to the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0034] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0035] Figure 2A and Figure 2B are diagrams showing other examples of the display device;

[0036] Figure 3 is a block diagram showing a gate signal generation circuit and a ramp voltage generation circuit;

[0037] Figure 4 and Figure 5 are diagrams showing examples of pixel circuits applicable to the present disclosure;

[0038] Figures 6A to 6B is showing Figure 5 the waveforms of the operations of the pixel circuit shown;

[0039] Figure 7 is a circuit diagram showing a ramp voltage generation circuit according to an embodiment of the present disclosure;

[0040] Figure 8 is a diagram showing Figure 7 an example of a waveform of a ramp voltage signal sequentially output from the ramp voltage generation circuit shown;

[0041] Figure 9 is a circuit diagram showing a ramp voltage generation circuit according to a first embodiment of the disclosure;

[0042] Figures 10A to 12B is a diagram showing Figure 9 the operation of the ramp voltage generation circuit shown;

[0043] Figure 13 is a circuit diagram showing a ramp voltage generation circuit according to a second embodiment of the present disclosure;

[0044] Figures 14A to 15B is a diagram showing Figure 13 the operation of the ramp voltage generation circuit shown;

[0045] Figure 16A and Figure 16B is a circuit diagram showing a ramp voltage generation circuit according to a third embodiment of the present disclosure;

[0046] Figure 17 is a diagram showing a gate signal applied to Figure 16A and Figure 16B and an example of a waveform of a ramp voltage signal output from the ramp voltage generation circuit shown;

[0047] Figures 18A to 20B is a diagram showing Figure 16A and Figure 16B the operation of the ramp voltage generation circuit shown;

[0048] Figure 21 is a waveform diagram showing the slope of a ramp voltage signal varying with a slope data voltage; and

[0049] Figure 22 is a waveform diagram showing an example of the illumination time of a light-emitting element varying with the slope of a ramp voltage signal. Detailed Description

[0050] The advantages and features of the present disclosure, and the methods for achieving these advantages and features, will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, these embodiments will make the disclosure of the present disclosure complete and enable those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only limited by the scope of the appended claims.

[0051] The shapes, sizes, ratios, angles, numbers, etc. shown in the accompanying drawings for describing the embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0052] Terms such as "comprising", "including", "having", and "comprising" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise expressly stated.

[0053] Even if not expressly stated, components are construed to include an ordinary error range.

[0054] When describing the positional or interconnecting relationship between two components, such as "on top of", "above", "below", "next to", "connected or coupled to", "crossing", "intersecting", etc., one or more other components may be interposed between them unless the terms "immediately" or "directly" are used.

[0055] When describing a temporal precedence relationship, such as "after", "behind", "next", "before", etc., it may not be continuous on a time basis unless the terms "immediately" or "directly" are used.

[0056] Terms such as "first", "second", etc. may be used to distinguish elements from each other, but the functions or structures of the components are not limited by the serial numbers or component names in front of the components.

[0057] The following embodiments may be partially or wholly joined or combined with each other, and may be linked and operated in various ways technically. The embodiments may be executed independently or in association with each other.

[0058] The pixel circuit and the gate driving circuit of the display device may include a plurality of transistors. The transistors may be implemented as thin film transistors (TFTs). The transistors may be implemented as oxide thin film transistors (TFTs) including an oxide semiconductor, low temperature polycrystalline silicon TFTs (LTPS TFTs) including low temperature polycrystalline silicon, and the like.

[0059] A transistor is a three - electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is an electrode through which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. The n - channel transistor has a current direction from the drain to the source. In the case of a p - channel transistor (p - channel metal - oxide - semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0060] The gate signal swings between a gate - on voltage and a gate - off voltage. The transistor turns on in response to the gate - on voltage and turns off in response to the gate - off voltage. In the case of an n - channel transistor, the gate - on voltage may be a gate high voltage VGH, and the gate - off voltage may be a gate low voltage VGL. In the case of a p - channel transistor, the gate - on voltage may be a gate low voltage VGL, and the gate - off voltage may be a gate high voltage VGH.

[0061] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0062] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure. Figure 2A and Figure 2B are diagrams showing other examples of the display device.

[0063] Referring to Figures 1 to 2B , a display device according to an embodiment of the present disclosure includes: a display panel 100; a display panel driving circuit for writing pixel data to the pixels 101 of the display panel 100; and a power supply device 140 for generating the power required to drive the pixels 101 and the display panel driving circuit.

[0064] The substrate of the display panel 100 can be, but is not limited to, a plastic substrate, a thin glass substrate, or a metal substrate. The display panel 100 can be, but is not limited to, a rectangular panel having a length in the X-axis direction (or the first direction), a width in the Y-axis direction (or the second direction), and a thickness in the Z-axis direction (or the third direction). For example, at least a part of the display panel 100 can have a curved perimeter.

[0065] The display panel 100 can be implemented with a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device in which an image is displayed on the screen and the actual object in the background is visible. The display panel 100 can be made into a flexible display panel. Additionally, the display panel 100 can be made of a stretchable panel that can be stretched.

[0066] The display area AA of the display panel 100 includes a pixel array for displaying an input image thereon. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix form. The display panel 100 can also include power lines commonly connected to the pixels 101. The power lines are generally connected to pixel circuits and supply a constant voltage required to drive the pixels 101 to the pixels. The power lines can be implemented as strip-shaped wirings along the first direction or the second direction, or as a mesh wiring in which the wirings in the first direction and the second direction are electrically connected. The power lines can also include a VGL line and a VGH line connected to the gate driver 120. A gate low voltage can be applied to the VGL line, and a gate high voltage can be applied to the VGH line.

[0067] Each of the pixels 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each of the pixels can also include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light-emitting element. Each of the pixel circuits is connected to a data line, a gate line, and a power line. Hereinafter, "pixel" can be understood to have the same meaning as "sub-pixel".

[0068] The pixels can be arranged in the form of true color pixels and pentile pixels. By driving two sub-pixels having different colors as one pixel 101 using a preset pixel rendering algorithm, the pentile pixels can achieve a higher resolution than the true color pixels. The pixel rendering algorithm can utilize the color of the light emitted from its adjacent pixels to compensate for the insufficient color representation in each pixel.

[0069] The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes a row of pixels arranged in the line direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel line share the gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of the pixel lines L1 to Ln.

[0070] The power supply device 140 generates a constant voltage (or direct current (DC) voltage) required to drive the pixel array of the display panel 100 and the display panel driving circuit by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply device 140 can adjust the level of the DC input voltage applied from the host system 200 to output a gamma reference voltage, a gate low voltage, a gate high voltage, a pixel driving voltage, a cathode voltage, etc. The gamma reference voltage is supplied to the data driver 110. The dynamic range of the data voltage output from the data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the range of the voltage between the highest gray scale voltage and the lowest gray scale voltage.

[0071] The gate high voltage and the gate low voltage are supplied to the level shifter 150 and the gate driver 120. Constant voltages such as the pixel driving voltage and the cathode voltage are supplied to the pixel 101 through a power line commonly connected to the pixel 101. The pixel driving voltage can be supplied from the main power supply of the host system 200 to the display panel 100. In this case, the power supply device 140 does not need to output the pixel driving voltage.

[0072] The display panel driving circuit writes the pixel data of the input image into the pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0073] The display panel driving circuit may further include a touch sensor driver for driving a touch sensor. From Figures 1 to 2B the touch sensor driver is omitted. The data driver 110 and the touch sensor driver may be integrated into a single driving integrated circuit (IC). In a mobile terminal or a wearable terminal, the timing controller 130, the power supply device 140, the level shifter 150, the data driver 110, the touch sensor driver, etc. may be integrated into one driving IC (DIC), as Figure 2A and Figure 2B shown.

[0074] The data driver 110 receives pixel data of an input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 outputs the data voltage by converting the pixel data of the input image into a gamma-compensated voltage using a digital-to-analog converter (DAC). A voltage divider circuit in the data driver 110 divides a gamma reference voltage into gamma-compensated voltages for each gray level, and the gamma-compensated voltages are supplied to the DAC. The DAC generates a data voltage as the gamma-compensated voltage corresponding to the gray level value of the pixel data. The data voltage output from the DAC is output to the data line 102 through the corresponding data output channel of the data driver 110 via an output buffer.

[0075] The gate driver 120 may be formed on the display panel 100 together with the TFT array and wirings of the pixel array. The gate driver 120 may be disposed in a non-display area NA outside the display area AA of the display panel 100, or at least a part thereof may be disposed in the display area AA.

[0076] The gate driver 120 may be disposed on either the left non-display area NA or the right non-display area NA outside the display area AA in the display panel 100, and supplies a gate signal to the gate line 103 in a single-feed method. In the single-feed method, the gate signal is applied to one end of the gate line. The gate driver 120 may be disposed in both the left non-display area NA and the right non-display area NA of the display panel 100, and applies the gate signal to the gate line 103 in a double-feed method. In the double-feed method, the gate signal is simultaneously applied to both ends of the gate line 103. At least some circuits of the gate driver 120 may be disposed within the display area AA.

[0077] The gate driver 120 includes: a gate signal generation circuit that generates pulses of a gate signal; and a ramp voltage generation circuit connected to an output terminal of the gate signal generation circuit. The gate signal may include one or more of a scan signal, an emission signal, and a ramp switch signal.

[0078] The gate signal generation circuit may include a plurality of shift registers for sequentially shifting the pulses of the gate signal. The ramp voltage generation circuit receives at least one gate signal and slope control data. The slope control data may be generated from the timing controller 130 and input to the ramp voltage generation circuit through a level shifter 150. The ramp voltage generation circuit outputs a ramp voltage signal having a ramp waveform, and the voltage of the ramp waveform changes with a slope determined by the voltage level of the slope data voltage. The gate signal output from the gate signal generation circuit and the ramp voltage signal output from the ramp voltage generation circuit may be supplied to the pixel. The ramp voltage signal may be interpreted as a gate signal having a ramp waveform.

[0079] The gate signal and the ramp voltage signal from the gate driver 120 are supplied to the pixel circuit of the pixel 101 through the gate line. For example, the scan signal and the ramp voltage signal may be applied to the pixel circuit, or the scan signal, the emission signal, and the ramp voltage signal may be applied to the pixel circuit.

[0080] The timing controller 130 receives the pixel data of the input image and the timing signal synchronized with the pixel data from the host system 200. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0081] The timing controller 130 controls the data driver 110 and the gate driver 120 of the display panel driving circuit by generating signals or timing information for controlling the operation timing of the data driver 110 and the gate driver 120 based on the timing signals (e.g., Vsync, Hsync, and DE) received from the host system 200.

[0082] The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driver 120 through the level shifter 150. The level shifter 150 may receive the gate timing control signal and generate a clock to supply it to the shift register of the gate driver 120. The input signal to the level shifter 150 is a signal having a digital signal voltage level. The output signal of the level shifter 150 includes a clock of an analog voltage that swings between a gate high voltage and a gate low voltage. The data timing control signal generated from the timing controller 130 is transmitted to the data driver 110.

[0083] The host system may scale the image signal from the video source to match the resolution of the display panel 100 and may transmit it to the timing controller 130 together with the timing signal. In a mobile system, the host system 200 may be implemented with an application processor (AP). The host system 200 may transmit the pixel data of the input image to the Figure 2A and Figure 2B shown driver IC (DIC). The host system 200 may be electrically connected to the driver IC (DIC) through a flexible printed circuit such as a flexible printed circuit (FPC), as Figure 2AAs shown. The driving IC (DIC) can be attached to the display panel 100 during chip-on-glass (COG) processing. The driving IC (DIC) can be electrically connected to the wiring on the display panel 100 as a chip-on-film (COF) structure mounted on a flexible circuit film, as Figure 2B shown.

[0084] When a still image or an always-on display (AOD) data is input, the timing controller 130 or the host system 200 can enter a low-power mode to reduce the power consumption of the display device. In the normal mode, the pixels 101 can have a refresh rate of 60 Hz, 144 Hz, 240 Hz, etc. The refresh rate is the frequency at which pixel data is written to the pixels 101. In the low-power mode, the refresh rate of the pixels 101 is reduced to a frequency lower than 60 [Hz], for example, 1 [Hz] to 30 [Hz]. When the refresh rate is 1 [Hz], the first frame out of 60 frames per second can be a refresh frame, and the next 59 frames can be hold frames. After the data voltage Vdata of the pixel data is charged in the pixels 101 during the refresh frame period, the pixels 101 can hold the data voltage charged during the previous refresh frame period without recharging the data voltage Vdata during the subsequent hold frame period to maintain the light-emitting state.

[0085] Figure 3 is a block diagram showing a gate signal generation circuit and a ramp voltage generation circuit.

[0086] Referring to Figure 3 , the gate driver 120 includes a gate signal generation circuit 121 and a ramp voltage generation circuit 122.

[0087] The gate signal generation circuit 121 and the ramp voltage generation circuit 122 can be provided on the display panel 100.

[0088] The shift register of the gate signal generation circuit 121 receives clock signals GCLK1 to GCLKN and ECLK1 to ECLKN from a level shifter and outputs pulses of the gate signals in a clock timing sequence. The gate signals can include scan signals, emission signals, or ramp switch signals. Each of the gate signals output from the gate signal generation circuit 121 can include a square-wave pulse, which can be applied to the pixel circuits through the gate lines, and at least some of these gate signals can be applied to the ramp voltage generation circuit 122.

[0089] The pulses of the gate signal output from the gate signal generation circuit 121 can be output in synchronization with the clocks GCLK1 to GCLKN and ECLK1 to ECLKN. The clocks GCLK1 to GCLKN and ECLK1 to ECLKN can control the rising time, pulse width duration, and falling time of the gate signal pulses. The first clocks GCLK1 to GCLKN can be the clocks of the first shift register that inputs the pulses of the output scan signal. The second clocks ECLK1 to ECLKN can be the clocks of the second shift register that inputs the pulses of the output emission signal or the ramp switch signal. The clocks GCLK1 to GCLKN and ECLK1 to ECLKN can be N-phase clocks (where N is a natural number greater than or equal to 2). The emission signal and the ramp switch signal can be output from separate shift registers.

[0090] The ramp voltage generation circuit 122 is provided between the gate signal generation circuit 121 and the pixel lines L1 to Ln. A plurality of ramp voltage generation circuits 122 each connected to a pixel line can be provided on the display panel 100. One ramp voltage generation circuit 122 can be connected to each of the pixel lines L1 to Ln, but is not limited thereto.

[0091] The ramp voltage generation circuit 122 receives the pulses of the gate signal input from the gate signal generation circuit 121. In addition, the ramp voltage generation circuit 122 receives the slope data voltage SCD. The slope data voltage SCD can be output from the data driver 110 or can be output from the power supply device 140. The slope data voltage SCD can be generated as the same data value during one frame period. Therefore, the slope data voltage SCD can be commonly input to all the ramp voltage generation circuits 122 formed on the display panel 100 through a single wiring formed on the display panel 100.

[0092] The digital data corresponding to the slope data voltage SCD can be adjusted by the timing controller 130 or the host system 200. The data driver 110 or the power supply device 140 can convert the digital data corresponding to the slope data voltage SCD into a voltage and output the converted slope data voltage SCD. Therefore, the timing controller 130 or the host system 200 can change the slope of the ramp voltage signal Vramp by changing the voltage level of the slope data voltage SCD.

[0093] The ramp voltage generation circuit 122 outputs a ramp voltage signal Vramp whose voltage gradually changes on the time axis. As Figure 4 and Figure 5 shown, the ramp voltage signal Vramp can be applied to the pixel circuit together with the pulses of the gate signal.

[0094] Figure 4 and Figure 5is an example of a pixel circuit applicable to the present disclosure. In Figure 4 and Figure 5 an example is shown in which the driving device DT and the switching devices M1 and M2 are implemented as p-channel transistors, but it is not limited thereto.

[0095] Referring to Figure 4 , the pixel circuit includes a light-emitting element LD, a driving element DT, a switching element M1, and a compensation circuit 10.

[0096] The light-emitting device LD can be implemented as an organic light-emitting diode (hereinafter referred to as "OLED") including an anode electrode and a cathode electrode, or can be implemented as an inorganic light-emitting element (e.g., a micro LED). The light-emitting element LD can be driven by a current from the driving element DT to emit light.

[0097] The OLED includes an anode electrode, a cathode electrode, and an organic compound layer interposed therebetween. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode electrode and the cathode electrode of the light-emitting element LD, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the light-emitting layer (EML) to form excitons. In this case, visible light is emitted from the light-emitting layer EML. The OLED can be implemented as an OLED having a tandem structure in which a plurality of light-emitting layers are stacked therein. The OLED having a tandem structure can improve the brightness and lifetime of the pixel.

[0098] The inorganic light-emitting element can be implemented as a micro LED chip having a vertical structure (where electrodes are provided above and below the chip and the light-emitting element is integrated in the chip), or a lateral structure or a flip-chip structure.

[0099] The driving element DT, the light-emitting element LD, and the switching element M1 can be connected in series between the pixel driving voltage EVDD and the cathode voltage EVSS. In Figure 4 the light-emitting device LD is connected between the switching device M1 and the cathode voltage EVSS, but it is not limited thereto. The light-emitting element LD can be connected between the pixel driving voltage EVDD and the driving element DT.

[0100] The driving element DT adjusts the current flowing through the drain-source channel based on the gate-source voltage. The gate-source voltage of the driving element DT varies with the data voltage Vdata of the pixel data applied to the gate electrode of the driving element DT. A storage capacitor (not shown in the figure) is connected between the gate electrode and the source electrode of the driving element DT.

[0101] The switching element M1 switches the current path between the pixel driving voltage EVDD and the cathode voltage EVSS. The switching element M1 can be turned on in response to an emission signal EM or a ramp voltage signal Vramp applied to its gate electrode. When the switching element M1 is turned on, the driving element DT and the light-emitting element LD can be electrically connected so that current can be supplied to the light-emitting element LD. When the first switching element M1 is turned off, the current path between the pixel driving voltage EVDD and the cathode voltage EVSS is blocked so that no current is supplied to the light-emitting element LD.

[0102] The compensation circuit 10 receives one or more scan signals SCAN, an emission signal EM, a ramp voltage signal Vramp, and a data voltage Vdata of pixel data, and the compensation circuit 10 is connected to the driving element DT and the switching element M1. The compensation circuit 10 can initialize the main node and the storage capacitor of the pixel circuit in response to a pulse of the scan signal SCAN. The compensation circuit 10 can apply the data voltage Vdata to the storage capacitor and the gate electrode of the driving element DT, sample the threshold voltage of the driving element DT, and compensate the gate-source voltage of the driving element DT through the threshold voltage. The compensation circuit 10 can use a source follower or a diode-connected circuit to compensate for the threshold voltage deviation of the driving element DT.

[0103] Referring to Figure 5 , the pixel circuit includes a light-emitting element LD, a switching element M2, a current generation circuit 20, and a pulse width control circuit (hereinafter referred to as "PWM control circuit") 30. Figure 5 An example in which the switching element M2 is implemented as an n-channel transistor is shown, but it is not limited thereto.

[0104] The current generation circuit 20, the switching element M2, and the light-emitting element LD can be connected in series between the pixel driving voltage EVDD and the cathode voltage EVSS. In Figure 5 , the light-emitting device LD is connected between the switching device M2 and the cathode voltage EVSS, but it is not limited thereto. The light-emitting element LD can be connected between the pixel driving voltage EVDD and the driving element DT.

[0105] The switching element M2 switches the current path between the pixel driving voltage EVDD and the cathode voltage EVSS. The switching element M2 is turned on in response to a PWM signal from the PWM control circuit 30 to adjust the emission time of the light-emitting element LD.

[0106] In the case of an inorganic LED, color shift may occur at low currents, resulting in color distortion. To prevent this color shift, the current generation circuit 20 supplies a constant current with high luminous efficiency to the light-emitting element LD. The PWM control circuit 30 can switch the constant current supplied to the light-emitting element LD under pulse-width modulation (PWM) control so that the light-emitting element LD emits light at a target brightness corresponding to the gray level of the pixel data.

[0107] The current generation circuit 20 generates a constant current with high luminous efficiency of the light-emitting element LD. The current generation circuit 20 may include a driving element, that is, a transistor that generates a current according to the gate-source voltage. In this case, the current generation circuit 20 may include a compensation circuit that samples and compensates the threshold voltage of the transistor.

[0108] The PWM control circuit 30 receives the data voltage Vdata of the pixel data and the ramp voltage signal Vramp, and generates a PWM signal based on the result of comparing the data voltage Vdata and the ramp voltage signal Vramp.

[0109] Refer to Figure 6A and Figure 6B , during the period when the data voltage Vdata is greater than the ramp voltage signal Vramp, the PWM signal can be generated using a high voltage, but it is not limited thereto. When the data voltage Vdata decreases, the pulse width of the PWM signal becomes smaller, which shortens the light emission time of the light-emitting element LD, resulting in a decrease in the brightness of the corresponding sub-pixel. On the other hand, when the data voltage Vdata increases, the pulse width of the PWM signal becomes larger, which increases the emission time of the light-emitting element LD and increases the brightness of the corresponding sub-pixel. When the pixel data is data with a low gray level value, the pulse width of the PWM signal is small, and as the gray level value increases to the middle gray level and the high gray level, the pulse width of the PWM signal becomes larger. Therefore, as Figure 6B shown, the light-emitting device LD has a longer illumination time (on) proportional to the gray level value.

[0110] In Figure 6A and Figure 6B , "Vsync" is a vertical synchronization signal that appears every 1 frame period. "VB" is a vertical blanking period during which no pixel data is written to the pixel. In FIG. 6, the shaded portion indicates the interval during which the data voltage Vdata is greater than the ramp voltage signal Vramp. The on-period during which the light-emitting element LD emits light is substantially the same as the pulse period of the PWM signal. The off-period during which the light-emitting device LD is off is equal to the interval during which the data voltage Vdata is lower than the ramp voltage signal Vramp.

[0111] Figure 7is a circuit diagram showing a ramp voltage generation circuit according to an embodiment of the present disclosure. Figure 8 is a diagram showing Figure 7 an example of a ramp voltage waveform sequentially output from the ramp voltage generation circuit shown.

[0112] Referring to Figure 7 and Figure 8 , the gate driver 120 may include a plurality of ramp voltage generation circuits 701 to 703. The ramp voltage generation circuits 701 to 703 may be provided on the display panel 100.

[0113] The ramp voltage generation circuits 701 to 703 may receive gate signals shifted in sequence, such as scan signals SCAN(n - 1) to SCAN(n + 2) and a ramp switch signal RP(n). The ramp voltage generation circuits 701 to 703 are commonly connected to a slope data line SL to receive a slope data voltage SCD.

[0114] In Figure 7 , it is shown that two scan signals and one ramp switch signal are input to the ramp voltage generation circuits 701 to 703, but it is not limited thereto. For example, one scan signal among the gate signals may be input to the ramp voltage generation circuits 701 to 703. The ramp switch signal RP(n) may be commonly input to two or more of the ramp voltage generation circuits 701 to 703, but it is not limited thereto. The ramp switch signal RP(n) may be independently input to each of the ramp voltage generation circuits 701 to 703.

[0115] Each of the ramp voltage generation circuits 701 to 703 includes a current generation part 72, a ramp waveform control part 74, and a charging part 76. The current generation part 72 receives one or more of the gate signals SCAN(n - 1) to SCAN(n + 2) and RP(n) to generate a current. The ramp waveform control part 74 controls the waveform of the ramp voltage signal by initializing the charging part 76 and adjusting the amount of charge charged into the charging part 76. The charging part 76 charges the charge from the current generation part 72.

[0116] The n-th ramp voltage generation circuit 701 (where n is a natural number) receives the (n - 1)-th scan signal SCAN(n - 1), the n-th scan signal SCAN(n), and the ramp switch signal RP(n), and outputs the n-th ramp voltage signal Vramp(n). The (n + 1)-th ramp voltage generation circuit 702 receives the n-th scan signal SCAN(n), the (n + 1)-th scan signal SCAN(n + 1), and the ramp switch signal RP(n), and outputs the (n + 1)-th ramp voltage signal Vramp(n + 1). The (n + 2)-th ramp voltage generation circuit 703 receives the (n + 1)-th scan signal SCAN(n + 1), the (n + 2)-th scan signal SCAN(n + 2), and the ramp switch signal RP(n), and outputs the (n + 2)-th ramp voltage signal Vramp(n + 2). When the pulses of the scan signals SCAN(n - 1) to SCAN(n + 2) are sequentially input to the ramp voltage generation circuits 701 to 703 in units of one horizontal period (1H), the n-th ramp voltage signal Vramp(n) to the (n + 2)-th ramp voltage signal Vramp(n + 2) can be sequentially delayed by one horizontal period, as Figure 8 shown.

[0117] Figure 9 is a circuit diagram showing a ramp voltage generation circuit according to a first embodiment of the present disclosure. Figure 9 The ramp voltage generation circuit shown is an example of the n-th ramp voltage generation circuit 701. Figures 10A to 12B is a diagram showing Figure 9 the operation of the ramp voltage generation circuit shown.

[0118] Referring to Figure 9 , the ramp voltage generation circuit receives a driving voltage VDD, a low-potential reference voltage (hereinafter referred to as "reference voltage") Vlow, the (n - 1)-th scan signal SCAN(n - 1), the n-th scan signal SCAN(n), the ramp switch signal RP(n), and a slope data voltage SCD, and outputs a ramp voltage signal Vramp(n).

[0119] The driving voltage VDD is a constant voltage higher than the reference voltage. The slope data voltage SCD has a voltage corresponding to the slope of the ramp voltage signal Vramp. The slope data voltage SCD can be selected from the voltage range between the maximum voltage and the minimum voltage. The maximum voltage of the slope data voltage SCD is lower than the driving voltage VDD. The driving voltage VDD can be a constant voltage selected from 5V to 15V, and the reference voltage Vlow can be a constant voltage selected from -5V to 5V, but is not limited thereto. The slope data voltage SCD can be selected from, but is not limited to, the voltage between 0V and 10V.

[0120] As can be seen from Q = CV = it, the ramp voltage signal Vramp increases linearly with current (i) and time (t). In Q = CV, Q represents the charge stored in the capacitor, C represents the capacitance of the capacitor, and V represents the voltage. The minimum voltage of the ramp voltage signal Vramp(n) can be a voltage between -5V and 5V, and the maximum voltage can be controlled by a voltage between 5V and 10V, but is not limited thereto.

[0121] constitute Figure 9 The transistors constituting the ramp voltage generation circuit shown below are p-channel transistors. Hereinafter, the gate low voltage VGL and the gate high voltage VGH will be referred to as the gate turn-on voltage and the gate turn-off voltage, respectively. The gate signals SCAN(n - 1), SCAN(n), and RP(n) swing between the gate turn-off voltage VGH and the gate turn-on voltage VGL. The gate turn-off voltage VGH is a voltage selected from 5V to 15V, and the gate turn-on voltage VGL can be a voltage selected between -10V and 5V, but is not limited thereto.

[0122] The current generation section 72 includes a first switching element M01, a first capacitor C1, and a driving element DT. The ramp waveform control section 74 includes a second switching element M02. The charging section 76 includes a second capacitor C2. The switching elements M01, M02, and the driving element DT can be implemented as p-channel transistors, but are not limited thereto. Each of the switching elements M01 and M02 conducts in response to the gate turn-on voltage VGL and turns off in response to the gate turn-off voltage VGH.

[0123] A current is generated from the current generation section 72 to charge the second capacitor C2. According to V = it / C, the ramp voltage signal Vramp increases slowly as the value of C, i.e., the capacitance of the second capacitor C2, increases. The smaller the capacitance of the second capacitor C2, the greater the slope of the ramp voltage signal Vramp, and the larger the capacitance of the second capacitor C2, the smaller the slope of the ramp voltage signal Vramp.

[0124] The first switching element M01 is connected between the slope data line SL to which the slope data voltage SCD is applied and the first node 81, and conducts in response to the gate turn-on voltage VGL of the n-th scan signal SCAN(n). When the first switching element M01 conducts, the slope data line SL is electrically connected to the first node 81. The first switching element M01 includes a first electrode connected to the slope data line SL to which the slope data voltage SCD is applied, a gate electrode to which the n-th scan signal SCAN(N) is applied, and a second electrode connected to the first node 81.

[0125] The driving element DT is connected between the VDD node to which the driving voltage VDD is applied and the second node 82 to generate a current according to the gate-source voltage. The first capacitor C1 charges the gate-source voltage Vgs of the driving element DT. The driving element DT includes a first electrode connected to the VDD node to which the driving voltage VDD is applied, a gate electrode connected to the first node 81, and a second electrode connected to the second node 82. The first capacitor C1 is connected between the VDD node and the first node 81.

[0126] The second switching element M02 is connected between the second node 82 and the reference voltage node to which the reference voltage Vlow is applied, and is turned on in response to the gate conduction voltage VGL of the (n - 1)th scan signal SCAN(n - 1). The voltage at the second node 82 is equal to the ramp voltage signal Vramp(n). The second node 82 is connected to the pixel circuit of the pixel 101 through a gate line. When the second switching element M02 is turned on, the reference voltage node is electrically connected to the second node 82, so that the reference voltage Vlow is applied to the second node 82. The second switching element M02 includes a first electrode connected to the second node 82, a gate electrode to which the (n - 1)th scan signal SCAN(n - 1) is applied, and a second electrode connected to the reference voltage node to which the reference voltage Vlow is applied or the ground node GND. Although Figure 9 an example in which the second electrode of the second switching element M02 is connected to the reference voltage node is shown, the second capacitor C2 and the second electrode of the second switching element M02 can be commonly connected to the ground node GND.

[0127] The second capacitor C2 can be connected between the second node 82 and the ground node GND, or between the second node 82 and the reference voltage node. Although Figure 9 an example in which the second capacitor C2 is connected to the ground node GND is shown, the second capacitor C2 can be commonly connected to the reference voltage node and the second switching element M02.

[0128] The driving period of the ramp voltage generation circuit can be divided into an initialization period Ti, a programming period Tp, and a ramp period Tramp, as Figures 10A to 12B shown.

[0129] Referring to Figure 10A and Figure 10B , during the initialization period Ti, the voltage of the (n - 1)th scan signal SCAN(n - 1) is the gate conduction voltage VGL, and the voltage of the nth scan signal SCAN(n) is the gate off voltage VGH. Therefore, during the initialization period Ti, the second switching element M02 is turned on, while the first switching element M01 is turned off.

[0130] During the initialization period Ti, the first node 81 is floating and at the previously charged slope data voltage SCD. Since the reference voltage Vlow is applied to the second node 82 during the initialization period Ti, the second capacitor C2 is initialized to the reference voltage Vlow. During the initialization period Ti, a current can be generated from the driving element DT, but this current is discharged to the reference voltage node through the second switching element M02 in the conducting state and does not charge the second capacitor C2.

[0131] Referring to Figure 11A and Figure 11B , during the programming period Tp, the voltage of the (n - 1)th scan signal SCAN(n - 1) is the gate-off voltage VGH, and the voltage of the nth scan signal SCAN(n) is the gate-on voltage VGL. Therefore, during the programming period Tp, the first switching element M01 is conducting, while the second switching element M02 is off.

[0132] During the programming period Tp, the slope data voltage SCD is applied to the first node 81. During the programming period Tp, the driving element DT generates a constant current according to the gate-source voltage charged in the first capacitor C1. During the programming period Tp, the second capacitor C2 starts to be charged by the constant current from the driving element DT, so that the voltage of the second node 82, i.e., the voltage of the ramp voltage signal Vramp(n), increases.

[0133] Referring to Figure 12A and Figure 12B , during the ramp period Tramp, the voltages of the (n - 1)th scan signal SCAN(n - 1) and the nth scan signal SCAN(n) are the gate-off voltage VGH. Therefore, during the ramp period Tramp, the first switching element M01 and the second switching element M02 are in the off state.

[0134] During the ramp period Tramp, the second capacitor C2 is charged by the constant current from the driving element DT, and thus the voltage of the second node 82 increases. Therefore, during the ramp period Tramp, the voltage of the ramp voltage signal Vramp(n) applied to the pixel circuit increases linearly with time.

[0135] Figure 13 is a circuit diagram showing a ramp voltage generation circuit according to a second embodiment of the present disclosure. Figure 13 The shown ramp voltage generation circuit is an example of the nth ramp voltage generation circuit 701. Figures 14A to 15B is a diagram showing Figure 13 the operation of the shown ramp voltage generation circuit. In the embodiment, detailed descriptions of components that are substantially the same as those of the above first embodiment will be omitted.

[0136] Reference Figure 13 As shown in Figure 13 , the current generation section 72 includes a first switching element M11, a first capacitor C1, and a driving element DT. The ramp waveform control section 74 includes a second switching element M12. The charging section 76 includes a second capacitor C2. The switching elements M11, M02, and the driving element DT may be implemented as p-channel transistors, but are not limited thereto.

[0137] The first switching element M11 and the second switching element M12 may be turned on / off simultaneously in response to a scan signal SCAN(n).

[0138] The first switching element M11 is connected between the ramp data line SL to which the slope data voltage SCD is applied and the first node 91, and is turned on in response to the gate conduction voltage VGL of the n-th scan signal SCAN(n). When the first switching element M11 is turned on, the ramp data line SL is electrically connected to the first node 91. The first switching element M11 includes a first electrode connected to the ramp data line SL to which the slope data voltage SCD is applied, a gate electrode to which the n-th scan signal SCAN(N) is applied, and a second electrode connected to the first node 91.

[0139] The driving element DT is connected between the VDD node to which the driving voltage VDD is applied and the second node 92 to generate a current according to the gate-source voltage. The driving element DT includes a first electrode connected to the VDD node to which the driving voltage VDD is applied, a gate electrode connected to the first node 91, and a second electrode connected to the second node 92. The first capacitor C1 is connected between the VDD node and the first node 91.

[0140] The second switching element M12 is connected between the second node 92 that outputs the ramp voltage signal Vramp(n) and the reference voltage node to which the reference voltage Vlow is applied, and is turned on in response to the gate conduction voltage VGL of the n-th scan signal SCAN(n). When the second switching element M12 is turned on, the reference voltage node is electrically connected to the second node 92, so that the reference voltage Vlow is applied to the second node 92. The second switching element M12 includes a first electrode connected to the second node 92, a gate electrode to which the n-th scan signal SCAN(n) is applied, and a second electrode connected to the reference voltage node to which the reference voltage Vlow is applied or the ground node GND. Although Figure 13 an example in which the second electrode of the second switching element M12 is connected to the reference voltage node is shown, the second capacitor C2 and the second electrode of the second switching element M12 may be commonly connected to the ground node GND.

[0141] The second capacitor C2 may be connected between the second node 92 and the ground node GND, or between the second node 92 and the reference voltage node. Although Figure 13An example in which the second capacitor C2 is connected to the ground node GND is shown, but the second capacitor C2 may be commonly connected to the reference voltage node and the second switching element M12.

[0142] The driving period of the ramp voltage generation circuit may be divided into an initialization period Ti and a ramp period Tramp, as Figures 14A to 15B shown.

[0143] Referring to Figure 14A and Figure 14B , the voltage of the n-th scan signal SCAN(n) during the ramp period Ti is the gate-on voltage VGL. Therefore, during the initialization period Ti, the first switching element M11 and the second switching element M12 are turned on simultaneously.

[0144] During the initialization period Ti, the slope data voltage SCD is applied to the first node 91, and the reference voltage Vlow is applied to the second node 91. At the end of the initialization period Ti, the voltage of the ramp voltage signal Vramp(n) is the reference voltage Vlow.

[0145] Referring to Figure 15A and Figure 15B , the voltage of the n-th scan signal SCAN(n) during the ramp period Tramp is the gate-off voltage VGH. Therefore, during the ramp period Tramp, the first switching element M11 and the second switching element M12 are in the off state.

[0146] During the ramp period Tramp, the second capacitor C2 is charged by a constant current from the driving element DT, and thus the voltage of the second node 92 increases. Therefore, during the ramp period Tramp, the voltage of the ramp voltage signal Vramp(n) applied to the pixel circuit increases linearly with time.

[0147] Figure 16A and Figure 16B are circuit diagrams showing a ramp voltage generation circuit according to a third embodiment of the present disclosure. Figure 16A and Figure 16B The ramp voltage generation circuit shown is an example of the n-th ramp voltage generation circuit 701. Figure 17 is a diagram showing Figure 16A and Figure 16B an example of a gate signal applied to the ramp voltage generation circuit shown and a ramp voltage signal output from the ramp voltage generation circuit; Figures 18A to 20B is a diagram showing Figure 16A and Figure 16B the operation of the ramp voltage generation circuit shown. The components of this embodiment are substantially the same as those of the foregoing embodiment, and will not be described in detail.

[0148] Reference Figures 16A to 17 As shown in Figures 16A to 17 , the ramp voltage generation circuit includes a current generation section 72, a ramp waveform control section 74, and a charging section 76. The current generation section 72 receives gate signals SCAN(n - 1) to SCAN(n + 2) and RP(n) to generate a current. The gate signals SCAN(n - 1) to SCAN(n + 2) and RP(n) include the (n - 1)-th scan signal SCAN(n - 1), the n-th scan signal SCAN(n), and the ramp switch signal RP(n). Instead of the ramp switch signal RP(n), the emission signal EM may be input to the current generation section 72. The current generation section 72 includes a compensation circuit that samples the threshold voltage of the drive element DT and compensates the gate-source voltage of the drive element DT by the threshold voltage.

[0149] The ramp waveform control section 74 controls the waveform of the ramp voltage signal by initializing the charging section 76 and adjusting the amount of charge charged into the charging section 76. The charging section 76 charges the charge from the current generation section 72.

[0150] Figure 16A and Figure 16B The ramp voltage generation circuit shown in Figure 16B receives a drive voltage VDD, an initialization voltage Vini, a reference voltage Vlow, the (n - 1)-th scan signal SCAN(n - 1), the n-th scan signal SCAN(n), the ramp switch signal RP(n), and a slope data voltage SCD, and outputs a ramp voltage signal Vramp(n). The drive voltage VDD may be a constant voltage selected from 5V to 15V, and the initialization voltage Vini and the reference voltage Vlow may be constant voltages selected from -5V to 5V, but are not limited thereto. The initialization voltage Vini and the reference voltage Vlow may be set to a single constant voltage having the same voltage level, or they may be set to different constant voltages having different voltage levels. The slope data voltage SCD may be selected from, but is not limited to, voltages between 0V and 10V. The gate-off voltage VGH of the gate signals SCAN(n - 1), SCAN(n), and RP(n) may be a voltage selected from 5V to 15V, and its gate-on voltage VGL may be a voltage selected from -10V to 5V, but is not limited thereto.

[0151] The current generation section 72 includes a first switch element M31 to a fifth switch element M35, a first capacitor C1, and a drive element DT. The ramp waveform control section 74 includes a sixth switch element M36. The charging section 76 includes a second capacitor C2. The switch elements M31 to M36 and the drive element DT may be implemented as p-channel transistors, but are not limited thereto. Each of the switch elements M31 to M36 conducts in response to the gate-on voltage VGL and turns off in response to the gate-off voltage VGH.

[0152] The driving device DT is connected between a first node n1 to which a driving voltage VDD is applied and a third node n3 to generate a current according to the gate-source voltage. A first capacitor C1 charges the gate-source voltage Vgs of the driving element DT. The driving element DT includes a first electrode connected to the first node n1, a gate electrode connected to a second node n2, and a second electrode connected to the third node n3. The first capacitor C1 is connected between a VDD node to which a pixel driving voltage VDD is applied and the second node n2.

[0153] A first switching element M31 is connected between the VDD node and the first node n1 and conducts in response to the gate conduction voltage VGL of a ramp switching signal RP(n). When the first switching element M31 conducts, the VDD node is electrically connected to the first node n1. The first switching element M31 includes a first electrode connected to the VDD node, a gate electrode to which the ramp switching signal RP(n) is applied, and a second electrode connected to the first node n1.

[0154] A second switching element M32 is connected between a ramp data line SL to which a slope data voltage SCD is applied and the first node n1 and conducts in response to the gate conduction voltage VGL of the n-th scan signal SCAN(n). When the second switching element M32 conducts, the ramp data line SL is electrically connected to the first node n1. The second switching element M32 includes a first electrode connected to the ramp data line SL to which the slope data voltage SCD is applied, a gate electrode to which the n-th scan signal SCAN(N) is applied, and a second electrode connected to the first node n1.

[0155] A third switching element M33 is connected between the second node n2 and the third node n3 and conducts in response to the gate conduction voltage VGL of the n-th scan signal SCAN(n). When the third switching element M33 conducts, the second node n2 is electrically connected to the third node n3. The third switching element M33 includes a first electrode connected to the second node n2, a gate electrode to which the n-th scan signal SCAN(n) is applied, and a second electrode connected to the third node n3.

[0156] A fourth switching element M34 is connected between the second node n2 and an initialization voltage node to which an initialization voltage Vini is applied and conducts in response to the gate conduction voltage VGL of the (n - 1)-th scan signal SCAN(n - 1). When the fourth switching element M34 conducts, the second node n2 is electrically connected to the initialization voltage node. The fourth switching element M34 includes a first electrode connected to the second node n2, a gate electrode to which the (n - 1)-th scan signal SCAN(n - 1) is applied, and a second electrode connected to the initialization voltage node.

[0157] The fifth switching element M35 is connected between the third node n3 and the fourth node n4, and conducts in response to the gate conduction voltage VGL of the ramp switching signal RP(n). When the fifth switching element M35 conducts, the third node n3 is electrically connected to the fourth node n4. The fifth switching element M35 includes a first electrode connected to the third node n3, a gate electrode to which the ramp switching signal RP(n) is applied, and a second electrode connected to the fourth node n4.

[0158] The sixth switching element M36 is connected between the fourth node n4 and a reference voltage node to which a reference voltage Vlow is applied, and conducts in response to the gate conduction voltage VGL of the (n - 1)-th scan signal SCAN(n - 1). The voltage at the fourth node n4 is equal to the ramp voltage signal Vramp(n). The fourth node n4 is connected to the pixel circuit of the pixel 101 through a gate line. When the sixth switching element M36 conducts, the reference voltage node is electrically connected to the fourth node n4, such that the reference voltage Vlow is applied to the fourth node n4. The sixth switching element M36 includes a first electrode connected to the fourth node n4, a gate electrode to which the (n - 1)-th scan signal SCAN(n - 1) is applied, and a second electrode connected to the reference voltage node or the ground node GND. As Figure 16A shown, the second electrode of the sixth switching element M36 may be connected to the reference voltage node. As Figure 16B shown, the second capacitor C2 and the second electrode of the sixth switching element M36 may be commonly connected to the ground node GND.

[0159] The second capacitor C2 may be connected between the fourth node n4 and the ground node GND, or between the fourth node n4 and the reference voltage node. Although Figure 16A and Figure 16B show an example in which the second capacitor C2 is connected to the ground node GND, the second capacitor C2 may be commonly connected to the reference voltage node together with the sixth switching element M36.

[0160] Referring to Figure 17 , Figure 16A and Figure 16BThe driving period of the ramp voltage generating circuit shown can be divided into an initialization period Ti1, a programming period Ti2, and a ramp period Tramp. A holding period Th during which the first switching element M31 to the sixth switching element M36 are in an off state can be set between the programming period Ti2 and the ramp period Tramp. Pulses of the (n - 1)-th scan signal SCAN(n - 1) and the n-th scan signal SCAN(n) can be generated with a pulse width of one horizontal period (1H). Pulses of the (n - 1)-th scan signal SCAN(n - 1) and the n-th scan signal SCAN(n) can be generated as a gate-on voltage VGL during one horizontal period (1H). After generating a pulse of the (n - 1)-th scan signal SCAN(n - 1) in the initialization period Ti1, a pulse of the n-th scan signal SCAN(n) is generated in the programming period Ti2. Pulses of the ramp switch signal RP(n) are generated as a gate-off voltage VGH during two horizontal periods or three horizontal periods including the initialization period Ti1 and the programming period Ti2. Pulses of the ramp switch signal RP(n) overlap with pulses of the (n - 1)-th scan signal SCAN(n - 1) and the n-th scan signal SCAN(n).

[0161] Referring to Figure 18A and Figure 18B , during the initialization period Ti1, the voltage of the (n - 1)-th scan signal SCAN(n - 1) is the gate-on voltage VGL, and the voltages of the n-th scan signal SCAN(n) and the ramp switch signal RP(n) are the gate-off voltage VGH. Therefore, during the initialization period Ti1, the fourth switching element M34 and the sixth switching element M36 are turned on, while the first switching element M31, the second switching element M32, the third switching element M33, and the fifth switching element M35 are turned off.

[0162] During the initialization period Ti1, the second node n2 is initialized to the initialization voltage Vini, and the fourth node n4 is initialized to the reference voltage Vlow. Therefore, during the initialization period, the voltage Vg of the second node n2 is reduced to the initialization voltage Vini, and the voltage of the ramp voltage signal Vramp(n) is reduced to the reference voltage Vlow. During the initialization period Ti, current can be generated from the driving element DT, but this current is discharged to the reference voltage node through the turned-on sixth switching element M36 and does not charge the second capacitor C2.

[0163] Referring to Figure 19A and Figure 19B, during the programming period Ti2, the voltages of the (n - 1)-th scan signal SCAN(n - 1) and the ramp switch signal RP(n) are the gate-off voltage VGH, and the voltage of the n-th scan signal SCAN(n) is the gate-on voltage VGL. Therefore, during the programming period Ti2, the second switching element M32 and the third switching element M33 are turned on, while the first switching element M31, the fourth switching element M34, the fifth switching element M35, and the sixth switching element M36 are turned off.

[0164] During the programming period Ti2, the slope data voltage SCD is applied to the second node n2 through the first node n1, the channel of the driving element DT, the third node n3, and the channel of the third switching element M33. During the programming period Ti2, the voltage at the second node n2 becomes the slope data voltage SCD - Vth compensated by the threshold voltage Vth of the driving element DT. Therefore, at the end of the programming period Ti2, the voltage of the first capacitor C1 becomes VDD - (SCD - Vth).

[0165] During the programming period Ti2, since the fifth switching element M35 is in the off state, the fourth node n4 floats, causing the voltage of the ramp voltage signal Vramp(n) to remain at the reference voltage Vlow.

[0166] During the holding period Th after the programming period Ti2, the voltages of the (n - 1)-th scan signal SCAN(n - 1), the n-th scan signal SCAN(n), and the ramp switch signal RP(n) are the gate-off voltage VGH. Therefore, during the holding period Th, the first switching element M31 to the sixth switching element M36 are turned off, causing the voltages at the first node n1 to the fourth node n4 to remain at the voltages at the end of the programming period Ti2.

[0167] Referring to Figure 20A and Figure 20B , during the ramp period Tramp, the voltages of the (n - 1)-th scan signal SCAN(n - 1) and the n-th scan signal SCAN(n) are the gate-off voltage VGH, and the voltage of the ramp switch signal RP(n) is the gate-on voltage VGL. Therefore, during the ramp period Tramp, the first switching element M31 and the fifth switching element M35 are turned on, while the second switching element M32, the third switching element M33, the fourth switching element M34, and the sixth switching element M36 are turned off.

[0168] During the ramp period Tramp, the second capacitor C2 is charged by a constant current from the driving element DT, causing the voltage at the fourth node n4 to increase. Therefore, during the ramp period Tramp, the voltage of the ramp voltage signal Vramp(n) applied to the pixel circuit increases linearly with time.

[0169] Figure 21 is a waveform showing the slope of the ramp voltage signal Vramp that changes with the slope data voltage SCD.

[0170] Referring to Figure 21 , the minimum voltage and the maximum voltage of the ramp voltage signal Vramp required to obtain the target brightness of the pixel can be determined according to the characteristics of the display panel 100. The amount of current flowing through the light-emitting element LD via the driving element DT can be changed by the slope data voltage SCD. For example, in Figures 16A to 20B the ramp voltage generation circuit shown, the higher the slope data voltage SCD, the lower the gate-source voltage of the driving element DT, thereby reducing the amount of current, and the lower the slope data voltage SCD, the higher the gate-source voltage of the driving element DT, thereby increasing the amount of current. Therefore, the slope of the ramp voltage signal Vramp(n) can change with the slope data voltage SCD such that the maximum voltage of the ramp voltage signal Vramp(n) is adjusted within a defined period (e.g., one frame period).

[0171] The ramp voltage signal Vramp(n) can control Figure 4 the switching element M1 of the pixel circuit shown. In this case, the lighting-on time of the light-emitting element LD can change with the slope of the ramp voltage signal Vramp(n) to adjust the brightness of the pixel.

[0172] As Figure 22 shown, the on-periods ton1, ton2, and ton3 during which the switching element M1 is on can change with the slope of the ramp voltage signal Vramp(n). In Figure 22 , “Von” represents the on-voltage of the switching element M1. In Figure 22 , the horizontal axis represents time (T), and the vertical axis represents voltage (V). As the on-periods ton1, ton2, and ton3 of the switching element M1 increase, the lighting-on time of the light-emitting element LD increases, which increases the brightness of the pixel. For the first ramp voltage signal Vramp1 with a large slope, the on-period ton1 of the switching element M1 is short, while for the third ramp voltage signal Vramp3 with a small slope, the on-period ton3 of the switching element M1 is long. For the second ramp voltage signal Vramp2 with an intermediate slope, the on-period ton2 of the switching element M1 is approximately moderate. Therefore, by applying the ramp voltage signal Vramp to the pixel circuit and appropriately selecting its slope, the brightness of the pixel can be finely adjusted to improve the gray-scale representation of each gray level. Additionally, the color of the pixel can be appropriately adjusted by differentially applying the slope and the maximum voltage of the ramp voltage signal Vramp for each color of the sub-pixel.

[0173] According to one or more embodiments of the present disclosure, the display device may be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, a sliding device, a variable device, an electronic organizer, an e-book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation, a vehicle navigation, a vehicle display device, a vehicle device, a theater device, a theater display device, a television, a wallpaper device, a signage device, a gaming device, a notebook computer, a monitor, a camera, a video camera, and household appliances, etc. Additionally, the display device according to one or more embodiments of the present disclosure may be applied to an organic light-emitting lighting device or an inorganic light-emitting lighting device.

[0174] The object to be achieved by the present disclosure, the means for achieving the object, and the effects of the present disclosure described above do not specify the essential features of the claims, and thus, the scope of the claims is not limited to the disclosure of the present disclosure.

[0175] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A gate drive circuit, comprising: a gate signal generating circuit configured to sequentially output at least one gate signal having square wave pulses; as well as A ramp voltage generating circuit is configured to receive the at least one gate signal and the slope data voltage and output a ramp voltage signal including a square wave pulse based on the at least one gate signal and a ramp waveform based on the slope data voltage.

2. The gate drive circuit according to claim 1, wherein: The at least one gate signal includes: an n-1th scanning signal, and an nth scanning signal after the n-1th scanning signal, where n is a natural number; The ramp voltage generating circuit comprises: a driving transistor including a first electrode configured to receive a driving voltage, a gate electrode connected to a first node, and a second electrode connected to a second node; a first capacitor connected between a VDD node configured to receive a driving voltage and the first node; a first switch transistor connected between a data line configured to receive the slope data voltage and the first node, the first switch transistor being configured to be turned on in response to a gate-on voltage of the nth scan signal; a second switching transistor connected between the second node and a reference voltage node configured to receive a reference voltage lower than the driving voltage, or connected between the second node and a ground node, the second switching transistor being configured to be turned on in response to a gate-on voltage of the (n-1)th scan signal; and a second capacitor connected between the second node and the ground node, or connected between the second node and the reference voltage node; and The square wave pulse of the (n-1)th scan signal has the gate-on voltage of the (n-1)th scan signal, and the square wave pulse of the (n)th scan signal has the gate-on voltage of the (n)th scan signal.

3. The gate drive circuit according to claim 1, wherein: The at least one gate signal comprises a scan signal; The ramp voltage generating circuit comprises: a driving transistor including a first electrode configured to receive a driving voltage, a gate electrode connected to a first node, and a second electrode connected to a second node; a first capacitor connected between a VDD node configured to receive the driving voltage and the first node; a first switch transistor connected between a data line configured to receive the slope data voltage and the first node, the first switch transistor being configured to be turned on in response to a gate-on voltage of the scan signal; a second switching transistor connected between the second node and a reference voltage node configured to receive a reference voltage lower than the driving voltage, or connected between the second node and a ground node, the second switching transistor being configured to be turned on in response to a gate-on voltage of the scanning signal; and a second capacitor connected between the second node and the ground node, or connected between the second node and the reference voltage node; and The square wave pulse of the scanning signal has the gate-on voltage.

4. The gate drive circuit according to claim 1, wherein: The at least one gate signal includes: an n-1th scanning signal; an n-th scanning signal after the n-1th scanning signal and a ramp switch signal, where n is a natural number; The square wave pulse of the ramp switch signal overlaps with the square wave pulse of the (n-1)th scanning signal and the square wave pulse of the (n)th scanning signal; The ramp voltage generating circuit comprises: a driving transistor including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to a third node; a first capacitor connected between a VDD node configured to receive a driving voltage and the second node; a first switch transistor connected between the VDD node and the first node and configured to be turned on in response to a gate-on voltage of the ramp switch signal; a second switch transistor connected between a data line configured to receive the slope data voltage and the first node and configured to be turned on in response to a gate-on voltage of the nth scan signal; a third switching transistor connected between the second node and the third node and configured to be turned on in response to the gate-on voltage of the nth scan signal; a fourth switching transistor connected between the second node and an initialization voltage node configured to receive an initialization voltage and configured to be turned on in response to a gate-on voltage of the (n-1)th scan signal; a fifth switch transistor connected between the third node and a fourth node and configured to be turned on in response to the gate-on voltage of the ramp switch signal; a sixth switching transistor connected between the fourth node and a reference voltage node configured to receive a reference voltage, or connected between the fourth node and a ground node, the sixth switching transistor being configured to be turned on in response to the gate-on voltage of the (n-1)th scan signal; and a second capacitor connected between the fourth node and the reference voltage node, or connected between the fourth node and the ground node; The square wave pulse of the n-1th scanning signal has the gate-on voltage of the n-1th scanning signal, and the square wave pulse of the nth scanning signal has the gate-on voltage of the nth scanning signal; and The square wave pulse of the ramp switch signal has a gate-off voltage, and the ramp switch signal is at the gate-on voltage after the square wave pulse of the ramp switch signal.

5. The gate driving circuit according to claim 4, wherein: The first switch transistor includes a first electrode connected to the VDD node, a gate electrode configured to receive the ramp switch signal, and a second electrode connected to the first node; The second switch transistor includes a first electrode connected to the data line, a gate electrode configured to receive the nth scan signal, and a second electrode connected to the first node; The third switch transistor includes a first electrode connected to the second node, a gate electrode configured to receive the nth scan signal, and a second electrode connected to the third node; The fourth switch transistor includes a first electrode connected to the second node, a gate electrode configured to receive the (n-1)th scan signal, and a second electrode connected to the initialization voltage node; the fifth switch transistor comprising a first electrode connected to the third node, a gate electrode configured to receive the ramp switch signal, and a second electrode connected to the fourth node; as well as The sixth switching transistor includes a first electrode connected to the fourth node, a gate electrode configured to receive the (n-1)th scan signal, and a second electrode connected to the reference voltage node or the ground node.

6. The gate driving circuit according to claim 1, wherein: The ramp waveform of the ramp voltage signal has a slope; and The degree of the slope varies based on the slope data voltage.

7. The gate driving circuit according to claim 1, wherein: The slope voltage generating circuit has a driving period, the driving period including an initialization period and a slope period after the initialization period; During the initialization period, the voltage of the ramp voltage signal is configured to decrease to a reference voltage; as well as During the ramp period, the voltage of the ramp voltage signal is configured to gradually increase to be higher than the reference voltage to have the ramp waveform.

8. The gate driving circuit according to claim 7, wherein: During the ramp period, the voltage of the ramp voltage signal is configured to gradually increase from the reference voltage.

9. The gate driving circuit according to claim 8, wherein: The driving period also includes a holding period between the initialization period and the ramp period; and During the holding period, the ramp voltage signal is configured to be held at the reference voltage.

10. The gate driving circuit according to claim 7, wherein: The driving period also includes a programming period between the initialization period and the ramp period; During the programming period, the voltage of the ramp voltage signal is configured to gradually increase from the reference voltage; as well as In the ramp period, the voltage of the ramp voltage signal is configured to continue to gradually increase after gradually increasing in the programming period.

11. A display device, comprising: A display panel, the display panel comprising a plurality of data lines, a plurality of gate lines and a plurality of pixel circuits; a data driver configured to output data voltages of pixel data to the pixel circuits through the data lines; as well as A gate driver is configured to output at least one gate signal including a square wave pulse and a ramp voltage signal including a ramp waveform to the pixel circuit through the gate line.

12. The display device according to claim 11, wherein: The at least one gate signal includes a scan signal and an emission signal; Each of the plurality of pixel circuits comprises: A pixel driving transistor, a pixel switching transistor and a light emitting element connected in series between a pixel driving voltage and a cathode voltage; as well as The gate electrode of the pixel switch transistor is configured to receive the emission signal or the ramp voltage signal.

13. The display device according to claim 12, wherein: Each of the plurality of pixel circuits further comprises: A compensation circuit is configured to receive at least one of the scan signal, the emission signal, the ramp voltage signal, and the data voltage of the pixel data, and is connected to the pixel driving transistor and the pixel switching transistor.

14. The display device according to claim 11, wherein: Each of the plurality of pixel circuits comprises: a current generating circuit configured to receive a pixel driving voltage and output a constant current; a pulse width control circuit configured to receive a data voltage of the pixel data and the ramp voltage signal and output a pulse width modulation (PWM) signal; and A switching transistor is configured to switch a current flowing through a light emitting element in response to the PWM signal.

15. The display device according to claim 11, wherein: The gate driver comprises: a gate signal generating circuit configured to sequentially output the at least one gate signal including the square wave pulse; and A ramp voltage generating circuit is configured to receive the at least one gate signal and a slope data voltage, and output the ramp voltage signal based on a square wave pulse of the at least one gate signal and the slope data voltage.

16. The display device according to claim 15, wherein: The at least one gate signal includes: an n-1th scanning signal and an n-th scanning signal after the n-1th scanning signal, where n is a natural number; The ramp voltage generating circuit comprises: a driving transistor including a first electrode configured to receive a driving voltage, a gate electrode connected to a first node, and a second electrode connected to a second node; a first capacitor connected between a VDD node configured to receive the driving voltage and the first node; a first switch transistor connected between a data line configured to receive the slope data voltage among the data lines and the first node, the first switch transistor being configured to be turned on in response to a gate-on voltage of the nth scan signal; a second switching transistor connected between the second node and a reference voltage node configured to receive a reference voltage lower than the driving voltage, or connected between the second node and a ground node, the second switching transistor being configured to be turned on in response to a gate-on voltage of the (n-1)th scan signal; and a second capacitor connected between the second node and the ground node, or connected between the second node and the reference voltage node; and The square wave pulse of the (n-1)th scanning signal has the gate-on voltage of the (n-1)th scanning signal, and the square wave pulse of the (n)th scanning signal has the gate-on voltage of the (n)th scanning signal.

17. The display device according to claim 15, wherein: The at least one gate signal comprises a scan signal; The ramp voltage generating circuit comprises: a driving transistor including a first electrode configured to receive a driving voltage, a gate electrode connected to a first node, and a second electrode connected to a second node; a first capacitor connected between a VDD node configured to receive the driving voltage and the first node; a first switch transistor connected between a data line configured to receive the slope data voltage among the data lines and the first node, the first switch transistor being configured to be turned on in response to a gate-on voltage of the scan signal; a second switching transistor connected between the second node and a reference voltage node configured to receive a reference voltage lower than the driving voltage, or connected between the second node and a ground node, the second switching transistor being configured to be turned on in response to a gate-on voltage of the scanning signal; and a second capacitor connected between the second node and the ground node, or connected between the second node and the reference voltage node; and Wherein, the square wave pulse of the scanning signal has the gate-on voltage.

18. The display device according to claim 15, wherein: The at least one gate signal includes: an n-1th scanning signal, an n-th scanning signal after the n-1th scanning signal, and a ramp switch signal, where n is a natural number; The square wave pulse of the ramp switch signal overlaps with the square wave pulse of the (n-1)th scanning signal and the square wave pulse of the (n)th scanning signal; The ramp voltage generating circuit comprises: a driving transistor including a first electrode connected to the first node, a gate electrode connected to the second node, and a second electrode connected to a third node; a first capacitor connected between a VDD node configured to receive a driving voltage and the second node; a first switch transistor connected between the VDD node and the first node and configured to be turned on in response to a gate-on voltage of the ramp switch signal; a second switch transistor, the second switch transistor being connected between a data line configured to receive the slope data voltage among the data lines and the first node, the second switch transistor being configured to be turned on in response to a gate-on voltage of the nth scan signal; a third switching transistor connected between the second node and the third node and configured to be turned on in response to the gate-on voltage of the nth scan signal; a fourth switch transistor connected between the second node and an initialization voltage node configured to receive an initialization voltage, the fourth switch transistor being configured to be turned on in response to a gate-on voltage of the (n-1)th scan signal; a fifth switch transistor connected between the third node and a fourth node and configured to be turned on in response to the gate-on voltage of the ramp switch signal; a sixth switching transistor connected between the fourth node and a reference voltage node configured to receive a reference voltage, or connected between the fourth node and a ground node, the sixth switching transistor being configured to be turned on in response to the gate-on voltage of the (n-1)th scan signal; and a second capacitor connected between the fourth node and the reference voltage node, or connected between the fourth node and the ground node; and The square wave pulse of the n-1th scanning signal has the gate-on voltage of the n-1th scanning signal, and the square wave pulse of the nth scanning signal has the gate-on voltage of the nth scanning signal; and The square wave pulse of the ramp switch signal has a gate-off voltage, and the ramp switch signal is at the gate-on voltage after the square wave pulse of the ramp switch signal.

19. The gate driving circuit according to claim 15, wherein: The ramp waveform of the ramp voltage signal has a slope; and The degree of the slope varies based on the slope data voltage.

20. The gate driving circuit according to claim 15, wherein: The slope voltage generating circuit has a driving period, the driving period including an initialization period and a slope period after the initialization period; During the initialization period, the voltage of the ramp voltage signal is configured to decrease to a reference voltage; as well as During the ramp period, the voltage of the ramp voltage signal is configured to gradually increase to be higher than the reference voltage to have the ramp waveform.

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