Accelerator based on parallel ferroelectric capacitance storage calculation framework and retention loss error correction method

Abstract

The invention relates to the technical field of storage and calculation integration, and discloses an accelerator based on a parallel ferroelectric capacitor storage and calculation architecture and a retention loss error correction method. The accelerator comprises an offset charge offset circuit, a charge offset reference column, an error correction reference column and a weight column; the method comprises the following steps: controlling an offset charge offset circuit to read charges of a charge offset reference column and generate positive charges to offset negative charges generated by a plate line in a weight column; counting the number of 1 input every time in the error correction reference column to obtain a theoretical value of the error correction reference column; carrying out in-memory calculation to obtain a calculation value of the error correction reference column and a calculation value of the weight column; and obtaining the theoretical value of the weight column according to the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column. According to the method, the interference of the LCS unit in the weight column on the calculation result is eliminated, and then the error correction reference column is introduced to carry out error correction on the weight column, so that the calculation deviation caused by ferroelectric capacitance retention loss is reduced, and the stability and the reliability of the accelerator are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of in-memory computing, and particularly to an accelerator based on a parallel ferroelectric capacitor in-memory computing architecture and a retention loss correction method. Background Art

[0002] Currently, the parallel in-memory computing accelerator scheme based on ferroelectric capacitors generally adopts a switched-capacitor integration circuit scheme. The computing mechanism of this scheme mainly relies on the characteristic that the ferroelectric capacitor stores different amounts of charge at the same voltage when storing 0 and storing 1. Specifically, when mapping the weights of a neural network in a ferroelectric array, the cells representing logic 1 are programmed to a high capacitance state (HCS), while the cells representing logic 0 are programmed to a low capacitance state (LCS). Before computing, the ferroelectric capacitors are charged according to the input; during computing, the ferroelectric capacitors are discharged, and the computing result is closely related to the total charge released by each column of capacitors.

[0003] However, as the data retention time increases, the ferroelectric capacitors will experience retention loss. This loss will cause the capacitance value of the HCS cells to decrease, while the capacitance value of the LCS cells to increase. Due to the change in the capacitance value of the ferroelectric capacitors, the computing result will deviate, resulting in a decrease in the stability and reliability of the in-memory computing accelerator.

[0004] Therefore, the prior art still needs to be improved and developed. Summary of the Invention

[0005] In view of the above deficiencies of the prior art, the purpose of the present invention is to provide an accelerator based on a parallel ferroelectric capacitor in-memory computing architecture and a retention loss correction method to solve the problem of the decrease in the stability and reliability of the in-memory computing accelerator caused by retention loss in the existing parallel in-memory computing accelerator scheme based on ferroelectric capacitors.

[0006] The technical solution of the present invention is as follows: In a first aspect, the present invention provides a retention loss correction method based on a parallel ferroelectric capacitor in-memory computing architecture, which is applied to an accelerator. The accelerator includes an in-memory computing array and an offset charge cancellation circuit. The in-memory computing array includes a charge cancellation reference column, an error correction reference column, and a weight column. The retention loss correction method includes: Controlling the offset charge cancellation circuit to read the charge of the charge cancellation reference column and generate a positive charge to cancel the offset charge generated by the plate line in the weight column; Counting the number of 1s input each time in the error correction reference column to obtain the theoretical value of the error correction reference column; Performing in-memory computing to obtain the computed value of the error correction reference column and the computed value of the weight column; The theoretical value of the weight column is obtained based on the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column.

[0007] A further setting of the present invention includes, before the step of the control offset charge cancellation circuit reading the charge of the charge cancellation reference column and generating a positive charge to cancel the offset charge generated by the plate line in the weight column, the steps of: Charging the ferroelectric capacitors in the memory and computing array using binary voltages according to the input data.

[0008] A further setting of the present invention is that, in the step of charging the ferroelectric capacitors in the memory and computing array using binary voltages according to the input data, when the input data is 1, the MOS transistors in the corresponding row are turned on, and the supply voltage connected to the bit line charges the turned-on ferroelectric capacitors.

[0009] A further setting of the present invention is that, in the step of the control offset charge cancellation circuit reading the charge of the charge cancellation reference column and generating a positive charge to cancel the offset charge generated by the plate line in the weight column, the charge generated by the charge cancellation reference column is a negative charge, and the number of negative charges is equal to the number of offset charges generated by the plate line in the weight column.

[0010] A further setting of the present invention, the step of obtaining the theoretical value of the weight column according to the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column includes: Judging whether hold loss error correction is required; When hold loss error correction is required, the theoretical value of the weight column is obtained according to the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column; When hold loss error correction is not required, controlling each weight column to perform a shift and accumulation operation.

[0011] A further setting of the present invention, the step of judging whether hold loss error correction is required includes: Representing the change degree of hold loss by the ratio of the calculated value to the theoretical value of the error correction reference column, and determining whether hold loss error correction is required according to the change degree of hold loss and the loss coefficient.

[0012] A further setting of the present invention is that the data stored in the error correction reference column are all 1.

[0013] In a second aspect, the present invention further provides an accelerator applied to the hold loss error correction method based on the parallel ferroelectric capacitor memory and computing architecture described above, which includes a memory and computing array, an input counter, a decoder and its driving circuit, a bit line and a plate line driving circuit, an integration circuit, an offset charge cancellation circuit, an analog-to-digital converter and an error correction circuit; The decoder and its driving circuit are connected to the word lines of the memory and computing array, and are used to control the conduction and disconnection of the MOS transistors in each row of the memory and computing array according to the input data; The input counter is connected to the word lines of the memory and computing array, and is used to sum the input data, output and store the theoretical value of the error correction reference column; The bit line and board line driving circuit are connected to the bit lines and board lines of the memory and computing array; The integrating circuit is connected to the board lines of each weight column in the memory and computing array, and is used to transfer the charge generated on the board line to the output end and output it in the form of voltage during the operation process; The offset charge cancellation circuit is respectively connected to the board line of the charge cancellation reference column and the board line of the weight column, and is used to read the negative charge of the charge cancellation reference column and generate a positive charge to cancel the offset charge generated on the board line in the weight column; The analog-to-digital converter is connected to the integrating circuit, and is used to convert the output voltage of the integrating circuit into a digital signal; the digital signal includes the calculated value and theoretical value of the error correction reference column and the calculated value of the weight column; The error correction circuit is connected to the analog-to-digital converter, and is used to obtain the theoretical value of the weight column according to the theoretical value and calculated value of the error correction reference column and the calculated value of the weight column.

[0014] In a further setting of the present invention, the offset charge cancellation circuit includes: a charge cancellation integration unit and a plurality of charge cancellation feedback capacitors; The input end of the offset charge cancellation integration unit is connected to the board line of the charge cancellation reference column; One end of the charge cancellation feedback capacitor is connected to the output end of the charge cancellation integration unit, and the other end of the charge cancellation feedback capacitor is connected to the board line of the weight column.

[0015] In a further setting of the present invention, the integrating circuit includes a first operational amplifier and a first feedback capacitor; the integrating circuit further includes a first switch, and the first switch is connected between the output end of the first operational amplifier and the ground; the offset charge cancellation unit includes a second operational amplifier and a second feedback capacitor, and the offset charge cancellation circuit further includes a second switch, and the second switch is connected between the second operational amplifier and the ground.

[0016] An accelerator and a retention loss error correction method based on a parallel ferroelectric capacitor computing-in-memory architecture provided by the present invention. The retention loss error correction method is applied to the accelerator. The accelerator includes a computing-in-memory array and an offset charge cancellation circuit. The computing-in-memory array includes a charge cancellation reference column, an error correction reference column, and a weight column. The retention loss error correction method includes: controlling the offset charge cancellation circuit to read the negative charges of the charge cancellation reference column and generate positive charges to cancel the offset charges generated by the plate lines in the weight column; counting the number of 1s input each time in the error correction reference column to obtain the theoretical value of the error correction reference column; performing in-memory computing to obtain the calculated value of the error correction reference column and the calculated value of the weight column; and obtaining the theoretical value of the weight column according to the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column. The present invention first eliminates the interference of the LCS unit in the weight column on the calculation result through the offset charge cancellation circuit, and then introduces the error correction reference column to correct the weight column, reducing the calculation deviation caused by the retention loss of the ferroelectric capacitor, thereby improving the stability and reliability of the in-memory computing accelerator. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without creative efforts.

[0018] Figure 1 is a schematic flowchart of the retention loss error correction method based on the parallel ferroelectric capacitor computing-in-memory architecture in the present invention.

[0019] Figure 2 is a schematic working principle diagram of a FeRAM computing-in-memory system based on a switched-capacitor integration circuit in an embodiment of the present invention.

[0020] Figure 3 is a schematic diagram of the influence principle of retention loss on ferroelectric capacitors.

[0021] Figure 4 is a schematic architecture diagram of the accelerator in an embodiment of the present invention.

[0022] Figure 5 is a schematic diagram of the first stage of in-memory computing of the accelerator in an embodiment of the present invention.

[0023] Figure 6 is a schematic diagram of the second stage of in-memory computing of the accelerator in an embodiment of the present invention.

[0024] Figure 7 is a schematic flowchart of the retention loss error correction principle in an embodiment of the present invention.

[0025] Figure 8 are the differential linearity and integral linearity of the output voltage before error correction in an embodiment of the present invention.

[0026] Figure 9 are the differential linearity and integral linearity of the output voltage after error correction in an embodiment of the present invention.

[0027] Figure 10 is a comparison chart of the accuracy of the inference system with and without an error correction scheme in an embodiment of the present invention. Detailed implementation manners

[0028] The present invention provides an accelerator based on a parallel ferroelectric capacitor memory and computing architecture and an error correction method for holding losses. To make the objectives, technical solutions, and effects of the present invention clearer and more definite, the following further describes the present invention in detail with reference to the accompanying drawings and by way of examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0029] In the embodiments and the scope of the patent application, unless otherwise specifically defined in the text for articles, the articles "a", "an", "the", and "said" may also include the plural form. If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, such descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features.

[0030] It should be further understood that the term "comprising" used in the description of the present invention means that there are the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups. It should be understood that when an element is "connected" or "coupled" to another element, it can be directly connected or coupled to other elements, or there may also be intermediate elements. In addition, the "connection" or "coupling" used here may include wireless connection or wireless coupling. The term "and / or" used here includes all or any unit and all combinations of one or more of the associated listed items.

[0031] Those skilled in the art can understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as the general understanding of those of ordinary skill in the art to which the present invention pertains. It should also be understood that terms such as those defined in a general dictionary should be understood to have a meaning consistent with the meaning in the context of the prior art, and will not be interpreted with an idealized or overly formal meaning unless specifically defined as herein.

[0032] In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0033] Through the research of the inventors, it is found that with the increasing enhancement of the functions of artificial intelligence models, the demand for hardware systems that can support large-scale, high-performance, and high-efficiency computing is also increasing. Due to the separation of storage and computing in the traditional von Neumann architecture, serious "memory wall" and "power wall" problems have occurred, severely restricting the development of artificial intelligence. While the Computing-in-Memory (CIM) technology, by integrating the storage and computing functions, enables specific computing tasks to be completed inside the memory, significantly reducing the frequent data exchanges between the processor and the memory, and thus significantly improving the computing energy efficiency.

[0034] As a new type of non-volatile memory, Ferroelectric Random Access Memory (FeRAM) stands out with its many advantages such as fast access speed, low read / write energy consumption, good durability, high integration density, and easy backend integration, becoming an optimal solution for constructing high-performance in-memory computing systems. In addition, the natural low static power consumption and no leakage current and other characteristics of FeRAM make it have more unique advantages and broad development space in the application prospect of large-scale and high-performance memory computing systems compared with Resistive Random Access Memory (RRAM). Currently, the parallel memory computing accelerator scheme based on ferroelectric capacitors generally adopts the switched-capacitor integration circuit scheme. The computing mechanism of this scheme mainly relies on the characteristic that the ferroelectric capacitor stores different amounts of charge at the same voltage when storing 0 and storing 1. Specifically, when mapping the weights of the neural network in the ferroelectric array, the unit representing logic 1 is programmed to the high-capacitance state, while the unit representing logic 0 is programmed to the low-capacitance state. Before the calculation, the ferroelectric capacitor is charged according to the input; during the calculation, the ferroelectric capacitor is discharged, and the calculation result is closely related to the total charge released by each column of capacitors.

[0035] At present, there is still a large gap between the FeRAM in-memory computing technology and its actual application. The non-ideal characteristics of ferroelectric capacitors, such as low switching ratio (the ratio of the capacitance values between the high-capacitance state and the low-capacitance state of the ferroelectric capacitor), retention loss, and D2D variation (the characteristic difference between ferroelectric capacitor devices), pose severe challenges to system performance. In addition, the retention loss characteristic of ferroelectric capacitors will also lead to a decrease in the accuracy and stability of the inference system based on ferroelectric memory and computing, affecting its overall performance. The low switching ratio of ferroelectric capacitors will greatly limit the parallel processing ability of ferroelectric memory and computing, thereby significantly reducing the operation efficiency. As the data retention time increases, the retention loss of ferroelectric capacitors will cause the capacitance value of the HCS unit to decrease, while the capacitance value of the LCS unit to increase. Due to the change in the capacitance value of ferroelectric capacitors, the calculation results will deviate, making the FeRAM memory and computing system face severe challenges in terms of robustness, resulting in a decrease in the stability and reliability of the accelerator, and further leading to a decrease in the accuracy and stability of the inference system based on ferroelectric memory and computing, affecting the overall performance of the inference system based on ferroelectric memory and computing.

[0036] To address the above technical problems, the present invention provides an accelerator and a retention loss error correction method based on a parallel ferroelectric capacitor memory and computing architecture. The accelerator includes a memory and computing array and an offset charge cancellation circuit. The memory and computing array includes a charge cancellation reference column, an error correction reference column, and a weight column. The retention loss error correction method includes: controlling the offset charge cancellation circuit to read the negative charge of the charge cancellation reference column and generate a positive charge to cancel the offset charge generated by the plate line in the weight column; counting the number of 1s input each time in the error correction reference column to obtain the theoretical value of the error correction reference column; performing in-memory computing to obtain the calculated value of the error correction reference column and the calculated value of the weight column; and obtaining the theoretical value of the weight column according to the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column. The present invention first uses the offset charge cancellation circuit to interfere with the calculation results of the LCS units in the weight column, and then introduces the error correction reference column to correct the weight column, reducing the calculation deviation caused by the retention loss of ferroelectric capacitors and improving the robustness of the in-memory computing accelerator. Even when facing non-ideal states of ferroelectric capacitors, the stability and reliability of the in-memory computing accelerator can still be maintained.

[0037] Please also refer to Figures 1 to 10 , the present invention provides a preferred embodiment of a retention loss error correction method based on a parallel ferroelectric capacitor memory and computing architecture.

[0038] In some embodiments, as Figure 1 and Figure 4 shown, the present invention provides a retention loss error correction method applied to an accelerator. The accelerator includes a memory and computing array and an offset charge cancellation circuit. The memory and computing array includes a charge cancellation reference column, an error correction reference column, and a weight column. The retention loss error correction method includes the steps: S100. The control offset charge cancellation circuit reads the negative charge of the charge cancellation reference column and generates a positive charge to cancel the offset charge generated by the plate line in the weight column; Specifically, as Figure 2 shown, the working principle of the FeRAM memory and computing system based on the switched-capacitor integration circuit is as follows: The in-memory computing process is divided into two stages. The first stage is the capacitor charging stage, as shown in Figure 2 a of , where represents the binary voltage. For example, the binary voltage , the binary voltage . BL (Bit Line) represents the bit line, WL (Word Line) represents the word line, represents the ferroelectric capacitor. First, the input terminal and the output terminal of the operational amplifier are connected to the common-mode voltage Vcm. Then, according to the input data, the ferroelectric capacitor is charged using the binary voltage . In this way, the calculation result of each unit is stored in the ferroelectric capacitor in the form of charge. In the second stage, as shown in Figure 2 b of , the connection between the common-mode voltage Vcm and the negative input terminal and the output terminal of the operational amplifier is disconnected, and the operational amplifier starts to work as an integrator. The word line voltage changes from to the common-mode voltage Vcm. The charge generated on the bit line BL will be transferred to the output terminal due to the action of the integrator and output in the form of voltage at the output terminal. The output voltage expression is as follows: ; where represents the binary voltage, which is used to represent the input binary data; represents the stored binary weight value, which has two states: HCS and LCS; represents the capacitance value of the capacitor between the output terminal and the negative input terminal of the operational amplifier in the integration circuit.

[0039] Please refer to Figure 3 . Figure 3 shows the influence of the ferroelectric capacitor retention loss on the ferroelectric memory and computing system. The reason why the ferroelectric capacitor can store binary data even after power-off is the remanent polarization intensity inside the ferroelectric capacitor. However, as the retention time increases, due to the redistribution of charges by the built-in electric field at the electrode interface, the remanent polarization charge will continuously decrease, thereby causing a change in the remanent polarization intensity. Since the capacitance value of the ferroelectric capacitor is related to the remanent polarization intensity, that is, as the retention time increases, the capacitance value of the ferroelectric capacitor will also change to a certain extent, and the change trend is related to the state of the ferroelectric capacitor. The remanent polarization voltage of the HCS capacitor is +Pr, +Pr， Indicates the change in the polarization value caused by retention loss. As time increases, the remaining polarization voltage tends to 0, and the capacitance value of the ferroelectric capacitor decreases; the remaining polarization voltage of the LCS capacitor is -Pr, -Pr ， Indicates the change in the polarization value caused by retention loss. As time increases, the remaining polarization voltage tends to 0, and the capacitance value of the ferroelectric capacitor increases. The difference in capacitance values between the HCS capacitor and the LCS capacitor decreases, further limiting the parallelism of the memory and computing array. Additionally, from the output expression of the integrator, it can be seen that the output voltage is related to the capacitance values of the HCS capacitor and the LCS capacitor. The change in the capacitance value of the ferroelectric capacitor makes the calculation result inaccurate and reduces the stability of system inference.

[0040] Please refer to Figures 4 to 6 , in the memory and computing array, a charge cancellation reference column and an offset charge cancellation circuit are set. As Figure 5 shown, in the first stage, i.e., the capacitor charging stage, in the memory and computing array, the MOS transistors in the rows where the input data is 1 are turned on, and the supply voltage Vc input by the bit line charges the ferroelectric capacitors turned on by the MOS transistors. The direction of current flow is shown by the arrows in Figure 5 . As Figure 6 shown, in the second stage, the supply voltage Vc of all the bit lines in the memory and computing array is pulled down to a low level.

[0041] Due to capacitive coupling, a large amount of negative charges will be generated on each plate line in the memory and computing array. For the charge cancellation reference column, the amount of charge to be cancelled is generated on the plate line . Then these charges are read out by the offset charge cancellation circuit and output as a positive voltage and copied to the weight column to become positive charges. Since the offset charge cancellation circuit is connected to the plate line of the weight column, at this time, an equal amount of charge will also be generated on the plate line in each weight column , that is to say, the charge generated by the charge cancellation reference column is negative charge, and the number of negative charges is equal to the number of negative charges generated on the plate line in the weight column. The direction of current flow in this process is indicated by arrows. Subsequently, the original negative charges on the plate line of the weight column will be partially cancelled by the positive charges copied by the offset charge cancellation circuit, thereby reducing the influence of the charges generated by the LCS unit.

[0042] S200. Count the number of 1s input each time in the error correction reference column to obtain the theoretical value of the error correction reference column; Specifically, error correction is performed using the error correction reference column in the memory and computing array. The input counter counts the number of 1s in the input data to obtain the theoretical value of the error correction reference column. It should be understood that if the stored value of the ferroelectric capacitor is 0, regardless of the input value, the contribution of the memory and computing unit to the output voltage during in-memory operation is 0. Therefore, in this embodiment, the data stored in the error correction reference column are all 1s, so that the output voltage of the error correction reference column is equal to the theoretical value.

[0043] S300. Perform in-memory calculation to obtain the calculated value of the error correction reference column and the calculated value of the weight column; Specifically, after obtaining the theoretical value of the error correction reference column, in-memory operation is started to obtain the calculated value of the error correction reference column and the calculated value of the weight column.

[0044] S400. Obtain the theoretical value of the weight column according to the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column.

[0045] Specifically, please combine Figure 7 , assume that there are 1s input in a certain operation, and the input counter will sum and output the input data and store it. The input counter is a digital module, and its output is used for subsequent error correction processes. After obtaining the theoretical value of the error correction reference column , perform in-memory operation. For the error correction reference column, since the stored data are all 1s, the quantization result is also , however, due to the existence of retention loss, the quantization result is , that is, the calculated value. Then, can be used to describe the change caused by retention loss. Similarly, for any column, there is a quantization result and the theoretical value , essentially also describes the change caused by retention loss. Ignoring the influence of D2D variation, can be obtained, , since , and are all known, the theoretical value of each column can be obtained through this formula, thus completing the error correction process.

[0046] The working principle of the present invention is: since the switching ratio of the ferroelectric capacitor cannot tend to infinity, when the input is 1, due to , the LCS cell will contribute to the output voltage to a certain extent. Since the weight column does not fully store 1, the output voltage of the weight column will be relatively large. Due to the fact that the error correction reference column stores all 1s, the output voltage of the error correction reference column is equal to the theoretical value. Since the error correction process multiplies the output result of the weight column by a number greater than 1, the deviation brought by the LCS cell will be further amplified. Therefore, the present invention introduces a charge cancellation technique during the error correction process to eliminate the interference of the LCS cell in the weight column on the calculation result. In the present invention, while performing charge transfer, a contribution generated by one LCS cell is subtracted from each calculation unit with an input data of 1. In the weight column, for the LCS cell, its contribution to the generated contribution is from becomes 0; for the HCS cell, its contribution to the generated contribution is from becomes , since the error correction reference column and the weight column undergo the same process during operation, the output voltages of both the error correction reference column and the weight column are the contributions of the HCS cell to , and the calculation deviation is eliminated. The expression of the output voltage at this time is as follows: .

[0047] After eliminating the calculation deviation, the theoretical value of the weight column can be obtained based on the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column, thereby realizing accurate error correction for other columns and improving the robustness of the in-memory computing accelerator. Even when the ferroelectric capacitor is in a non-ideal state, the stability and reliability of the in-memory computing accelerator can still be maintained.

[0048] In some embodiments, the steps of obtaining the theoretical value of the weight column based on the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column include: S410. Determine whether it is necessary to perform hold loss error correction; S420. When it is necessary to perform hold loss error correction, obtain the theoretical value of the weight column based on the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column; S430. When it is not necessary to perform hold loss error correction, control each weight column to perform a shift and accumulation operation.

[0049] Specifically, please combine Figure 7 , in this embodiment, the ratio of the calculated value to the theoretical value of the error correction reference column represents the change degree of the hold loss. Whether it is necessary to perform hold loss error correction is determined based on the change degree of the hold loss and the loss coefficient. During specific implementation, the change of D2D is ignored, , where is the loss coefficient, so To some extent, it describes the degree of device loss. Before error correction, according to the value to determine whether the system needs error correction. As Figure 8 shown, assuming Figure 8 the intersection of the red and blue lines in is equal to , represents the retention loss error correction threshold. When , it can be considered that the accuracy of not adopting the error correction scheme is higher than that of adopting the error correction scheme, so error correction is not required. On the contrary, when , it can be considered that the accuracy of not adopting the error correction scheme is smaller than that of adopting the error correction scheme, so error correction is required.

[0050] To verify that the present invention can improve the performance of the memory-computation system, in this embodiment, (where ) is used to represent the capacitance difference between the HCL unit and the LCS unit after the remaining polarization decay. Under the conditions that the switching ratio is 10, the D2D change amount is 1%, is 0.1, the differential linearity (DNL) and integral linearity (INL) of the output voltage are simulated, and the simulation results are as Figure 9 shown. Due to the existence of ferroelectric capacitor retention loss, the absolute value of DNL is less than 1 least significant bit (LSB), but the INL increases continuously, indicating that the integral linearity of the output voltage is poor and the performance of the array is low. On this basis, this embodiment uses the retention loss error correction scheme to correct the output result, and the DNL and INL of the output voltage after error correction are as Figure 10 shown. The results show that the absolute values of INL and DNL are both less than 1 LSB, indicating that the present invention effectively improves the linearity of the output voltage and improves the performance of the system.

[0051] To evaluate the effectiveness of the retention loss error correction scheme, in this embodiment, the present invention is deployed in the VGG16 model and experimentally verified on the CIFAR-10 dataset using the Neurosim emulator. This embodiment conducts experiments on the inference system without adopting the error correction scheme and the inference system adopting the error correction scheme, and the results are as Figure 8 shown. As can be seen from Figure 8 , in the case where the switching ratio is 30 and the D2D change amount is 1%, when When changing from 0 to 0.1, the accuracy of the system without the error correction scheme will continuously drop to 10%. In contrast, the accuracy of the system with the error correction scheme will be maintained at a relatively high level. When the switching ratio is 10 and the D2D change amount is 10%, the increase in the D2D change rate will lead to an increase in the difference between the reference column and other weight columns. In Introducing the error correction scheme into the system with

[0052] In some embodiments, the present invention also provides an accelerator applied to the retention loss error correction method based on the above-mentioned parallel ferroelectric capacitor computing-in-memory architecture, which includes a computing-in-memory array, an input counter, a decoder and its driving circuit, a bit line and a plate line driving circuit, an integrating circuit, an offset charge cancellation circuit, an analog-to-digital converter and an error correction circuit; the decoder and its driving circuit are connected to the word lines of the computing-in-memory array for controlling the on and off of the MOS transistors in each row of the computing-in-memory array according to the input data; the input counter is connected to the word lines of the computing-in-memory array for summing the input data and outputting and storing the theoretical value of the error correction reference column; the bit line and the plate line driving circuit are connected to the bit lines and the plate lines of the computing-in-memory array; the integrating circuit is connected to the plate lines of each weight column in the computing-in-memory array for transferring the charge generated on the plate line to the output end and outputting it in the form of a voltage during the operation process; the offset charge cancellation circuit is respectively connected to the plate line of the charge cancellation reference column and the plate line of the weight column for reading the negative charge of the charge cancellation reference column and generating a positive charge to cancel the negative charge generated on the plate line in the weight column; the analog-to-digital converter is connected to the integrating circuit for converting the output voltage of the integrating circuit into a digital signal; the digital signal includes the calculated value and the theoretical value of the error correction reference column and the calculated value of the weight column; the error correction circuit is connected to the analog-to-digital converter for obtaining the theoretical value of the weight column according to the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column.

[0053] Specifically, the memory - in - computing array is provided with a charge cancellation reference column and an error - correction reference column. The charge cancellation reference column is used to reduce the influence of the charge generated by the LCS cells, and the error - correction reference column is used to accurately correct the calculation results of the weight columns. The decoder and its driving circuit control the conduction and disconnection of the MOS transistors in each row of the memory - in - computing array according to the input data and can also provide the ability to drive the load. During the hold loss error - correction process, first, the offset charge cancellation circuit cancels the negative charge on the plate line in the weight column to eliminate the influence of the charge generated by the LCS cells. Then, the input data counter counts the number of 1s in the input data to obtain the theoretical value of the error - correction reference column. During in - memory computing, the integration circuit can output the charges on the plate lines of the weight column and the error - correction reference column in the form of voltage, and further obtain the calculated values of the weight column and the error - correction reference column and the theoretical value of the error - correction reference column through the analog - to - digital converter. Then, the error - correction circuit can obtain the theoretical value of the weight column according to the theoretical value and the calculated value of the error - correction reference column and the calculated value of the weight column, completing the correction of the hold loss.

[0054] In some embodiments, the offset charge cancellation circuit includes: a charge cancellation integration unit and a plurality of charge cancellation feedback capacitors Cr2; the input end of the charge cancellation integration unit is connected to the plate line of the charge cancellation reference column; one end of the charge cancellation feedback capacitor Cr2 is connected to the output end of the charge cancellation integration unit, and the other end of the charge cancellation feedback capacitor is connected to the plate line of the weight column.

[0055] Specifically, the charge cancellation integration unit has the same structure as the integration circuit, both of which are composed of an operational amplifier and a feedback capacitor. As Figure 5 shown, in the integration circuit, it is composed of a first operational amplifier OP and a first feedback capacitor Cref, and the offset charge cancellation unit is composed of a second operational amplifier OP1 and a second feedback capacitor Cr1. In the second stage, the negative charge generated by the charge cancellation reference column is read out by the charge cancellation integration unit and copied into each of the charge cancellation feedback capacitors. In this way, an equal amount of positive charge will also be generated on the plate line in each weight column to cancel the original negative charge in the weight column, eliminating the influence of the charge generated by the LCS cells.

[0056] In some embodiments, the integration circuit includes a first operational amplifier OP and a first feedback capacitor Cref; the integration circuit further includes a first switch S1, and the first switch S1 is connected between the output end of the first operational amplifier OP and the ground; the offset charge cancellation unit includes a second operational amplifier OP1 and a second feedback capacitor Cr1, and the offset charge cancellation circuit further includes a second switch S2, and the second switch S2 is connected between the second operational amplifier OP1 and the ground. Both the first switch S1 and the second switch S2 play the role of resetting the node voltage.

[0057] In some embodiments, the present invention further provides a computer device, which includes the above-mentioned accelerator. Specifically, as described in the embodiment of an in-memory accelerator, it will not be elaborated here.

[0058] In summary, the accelerator and the retention loss error correction method based on the parallel ferroelectric capacitor computing-in-memory architecture provided by the present invention have the following beneficial effects: First, the charge cancellation technique is used to eliminate the interference of LCS cells in the weight array on the calculation results. Subsequently, an error correction reference column is introduced to accurately correct the calculation results of other columns. The present invention significantly reduces the calculation errors caused by the retention loss of ferroelectric capacitors, so that the FeRAM computing-in-memory system can still exhibit excellent robustness when facing the non-ideal characteristics of ferroelectric capacitors, ensuring the stability and reliability of system operations.

[0059] It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A method for correcting retention loss based on a parallel ferroelectric capacitor computing-in-memory architecture, which is applied to an accelerator. The accelerator includes a computing-in-memory array and an offset charge cancellation circuit. The computing-in-memory array includes a charge cancellation reference column, an error correction reference column, and a weight column. It is characterized in that, The hold loss error correction method includes: Controlling the offset charge cancellation circuit to read the charge of the charge cancellation reference column and generate a positive charge to cancel the offset charge generated by the plate line in the weight column; Counting the number of 1s input each time in the error correction reference column to obtain the theoretical value of the error correction reference column; Performing in-memory calculation to obtain the calculated value of the error correction reference column and the calculated value of the weight column; Obtaining the theoretical value of the weight column based on the theoretical value and calculated value of the error correction reference column and the calculated value of the weight column.

2. The method for correcting retention loss based on the parallel ferroelectric capacitor computing-in-memory architecture according to claim 1, characterized in that, Before the step of controlling the offset charge cancellation circuit to read the charge of the charge cancellation reference column and generate a positive charge to cancel the offset charge generated by the plate line in the weight column, there is also a step: Charging the ferroelectric capacitors in the memory and computing array using binary voltages according to the input data.

3. The method for correcting retention loss based on the parallel ferroelectric capacitor computing-in-memory architecture according to claim 2, characterized in that, In the step of charging the ferroelectric capacitors in the memory and computing array using binary voltages according to the input data, for the rows corresponding to the input data being 1, the MOS transistors are turned on, and the supply voltage accessed by the bit line voltage charges the turned-on ferroelectric capacitors.

4. The method for correcting retention loss based on the parallel ferroelectric capacitor computing-in-memory architecture according to claim 1, characterized in that, In the step of controlling the offset charge cancellation circuit to read the charge of the charge cancellation reference column and generate a positive charge to cancel the offset charge generated by the plate line in the weight column, the charge generated by the charge cancellation reference column is a negative charge, and the quantity of the negative charge is equal to the quantity of the offset charge generated by the plate line in the weight column.

5. The method for correcting retention loss based on the parallel ferroelectric capacitor computing-in-memory architecture according to claim 1, characterized in that, The step of obtaining the theoretical value of the weight column based on the theoretical value and calculated value of the error correction reference column and the calculated value of the weight column includes: Judging whether hold loss error correction is required; When hold loss error correction is required, obtaining the theoretical value of the weight column based on the theoretical value and calculated value of the error correction reference column and the calculated value of the weight column; When hold loss error correction is not required, controlling each weight column to perform a shift and accumulation operation.

6. The method for correcting retention loss based on the parallel ferroelectric capacitor computing-in-memory architecture according to claim 5, characterized in that, The step of judging whether hold loss error correction is required includes: Representing the change degree of hold loss by the ratio of the calculated value to the theoretical value of the error correction reference column, and determining whether hold loss error correction is required according to the change degree of hold loss and the loss coefficient.

7. The method for correcting retention loss based on the parallel ferroelectric capacitor computing-in-memory architecture according to claim 1, characterized in that, The data stored in the error correction reference column are all 1s.

8. An accelerator applied to the method for correcting retention loss based on the parallel ferroelectric capacitor computing-in-memory architecture according to any one of claims 1-7, characterized in that, It includes a memory and computing array, an input counter, a decoder and its driving circuit, a bit line and plate line driving circuit, an integrating circuit, an offset charge cancellation circuit, an analog-to-digital converter, and an error correction circuit; The decoder and its driving circuit are connected to the word lines of the memory and computing array, and are used to control the conduction and disconnection of the MOS transistors in each row of the memory and computing array according to the input data; The input counter is connected to the word lines of the memory and computing array, and is used to sum the input data, output and store the theoretical value of the error correction reference column; The bit line and plate line driving circuit is connected to the bit lines and plate lines of the memory and computing array; The integrating circuit is connected to the plate lines of each weight column in the memory and computing array, and is used to transfer the charge generated on the plate lines to the output end and output it in the form of a voltage during the operation process; The offset charge cancellation circuit is respectively connected to the plate line of the charge cancellation reference column and the plate line of the weight column, and is configured to read the negative charge of the charge cancellation reference column and generate a positive charge to cancel the offset charge generated by the plate line in the weight column; The analog-to-digital converter is connected to the integration circuit and is configured to convert the output voltage of the integration circuit into a digital signal; the digital signal includes the calculated value and the theoretical value of the error correction reference column and the calculated value of the weight column; The error correction circuit is connected to the analog-to-digital converter and is configured to obtain the theoretical value of the weight column according to the theoretical value and the calculated value of the error correction reference column and the calculated value of the weight column.

9. The accelerator according to claim 8, wherein, The offset charge cancellation circuit includes: a charge cancellation integration unit and a plurality of charge cancellation feedback capacitors; The input end of the offset charge cancellation integration unit is connected to the plate line of the charge cancellation reference column; One end of the charge cancellation feedback capacitor is connected to the output end of the charge cancellation integration unit, and the other end of the charge cancellation feedback capacitor is connected to the plate line of the weight column.

10. The accelerator according to claim 8, wherein, The integration circuit includes a first operational amplifier and a first feedback capacitor; the integration circuit further includes a first switch connected between the output end of the first operational amplifier and the ground; the offset charge cancellation unit includes a second operational amplifier and a second feedback capacitor, and the offset charge cancellation circuit further includes a second switch connected between the second operational amplifier and the ground.

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