MOS device and manufacturing method thereof
By forming an epitaxial layer locally on the semiconductor substrate and forming a gate using a maskless etching process, the problem that the development of MOS devices is limited by photolithography technology is solved, and smaller feature sizes and more flexible gate size control are achieved.
Patent Information
- Application Number
- CN202311667092.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-05
- Publication Date
- 2025-06-20
AI Technical Summary
The development of MOS devices is limited by lithography technology, and it is difficult to further limit their feature size.
By forming an epitaxial layer locally on the semiconductor substrate and forming a gate on the side wall of the epitaxial layer using a maskless etching process, a photolithography process is avoided, thereby achieving a smaller feature size.
This method effectively avoids the limitations of lithography technology, realizes further restriction of the characteristic size of the MOS device, and controls the size of the gate electrode by regulating the thickness of the gate conductive material layer.
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Figure CN120184007A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a MOS device and a manufacturing method thereof. Background Art
[0002] With the rapid development of integrated circuit technology, the feature size of MOS (Metal Oxide Semiconductor) devices is getting smaller and smaller. As the feature size of MOS devices continues to shrink, their development is restricted by lithography technology. How to further reduce the feature size of MOS devices under the conditions of existing lithography technology is a difficult problem faced by those skilled in the art. Summary of the Invention
[0003] The purpose of the present invention is to provide a MOS device and a manufacturing method thereof to solve the problem that the development of MOS devices in the prior art is restricted by lithography technology.
[0004] To solve the above technical problem, the present invention provides a manufacturing method of a MOS device, and the manufacturing method of the MOS device includes:
[0005] Provide a semiconductor substrate;
[0006] Form an epitaxial layer locally on the semiconductor substrate;
[0007] Form a gate dielectric material layer, and the gate dielectric material layer covers the epitaxial layer and the semiconductor substrate;
[0008] Form a gate conductive material layer on the gate dielectric material layer;
[0009] Perform a maskless etching process on the gate conductive material layer to form a gate on the sidewall of the epitaxial layer; and,
[0010] Form a first source / drain region and a second source / drain region in the semiconductor substrate, wherein the first source / drain region extends into the epitaxial layer.
[0011] Optionally, in the manufacturing method of the MOS device, forming the first source / drain region and the second source / drain region in the semiconductor substrate includes:
[0012] Perform a first ion implantation process on the semiconductor substrate and the epitaxial layer to form at least a first doped region in the semiconductor substrate; and,
[0013] A second ion implantation process is performed on the semiconductor substrate and the epitaxial layer to form a second doped region and a third doped region in the semiconductor substrate and the epitaxial layer, wherein the second doped region and the first doped region are joined to form the first source / drain region, and the third doped region forms the second source / drain region.
[0014] Optionally, in the method for manufacturing the MOS device, the first doped region is located in the semiconductor substrate, or the first doped region extends from the epitaxial layer into the semiconductor substrate; the second doped region extends from the surface of the epitaxial layer to join the first doped region; the third doped region extends from the surface of the semiconductor substrate into the semiconductor substrate.
[0015] Optionally, in the method for manufacturing the MOS device, the thickness of the epitaxial layer is between and the ion implantation energy of the first ion implantation process is between 40 keV and 180 keV.
[0016] Optionally, in the method for manufacturing the MOS device, the width of the gate is between and .
[0017] Optionally, in the method for manufacturing the MOS device, before forming the epitaxial layer locally on the semiconductor substrate, the method for manufacturing the MOS device further includes:
[0018] Performing a well region ion implantation process on the semiconductor substrate to form a well region in the semiconductor substrate.
[0019] Optionally, in the method for manufacturing the MOS device, after forming the first source / drain region and the second source / drain region in the semiconductor substrate, the method for manufacturing the MOS device further includes:
[0020] Etching the gate dielectric material layer to form a gate dielectric layer;
[0021] Forming a gate metal silicide, a first source / drain region metal silicide, and a second source / drain region metal silicide on the surfaces of the gate, the first source / drain region, and the second source / drain region respectively; and,
[0022] Forming a gate conductive pillar, a first source / drain region conductive pillar, and a second source / drain region conductive pillar, connecting the gate conductive pillar to the gate metal silicide, connecting the first source / drain region conductive pillar to the first source / drain region metal silicide, and connecting the second source / drain region conductive pillar to the second source / drain region metal silicide.
[0023] The present invention also provides a MOS device, which includes:
[0024] A semiconductor substrate;
[0025] An epitaxial layer covering a part of the semiconductor substrate;
[0026] A gate covering the sidewall of the epitaxial layer; and
[0027] A first source / drain region and a second source / drain region located in the semiconductor substrate, wherein the first source / drain region extends into the epitaxial layer.
[0028] Optionally, in the MOS device, the first source / drain region includes a first doped region and a second doped region connected to the first doped region, and the second source / drain region includes a third doped region; wherein the first doped region is located in the semiconductor substrate, or the first doped region extends from the epitaxial layer into the semiconductor substrate; the second doped region extends from the surface of the epitaxial layer to be connected to the first doped region; and the third doped region extends from the surface of the semiconductor substrate into the semiconductor substrate.
[0029] Optionally, in the MOS device, the MOS device further includes a gate dielectric layer, which is between the gate and the semiconductor substrate, and between the gate and the epitaxial layer.
[0030] Optionally, in the MOS device, the MOS device further includes a gate metal silicide, a first source / drain region metal silicide, and a second source / drain region metal silicide, which are respectively located on the gate, the first source / drain region, and the second source / drain region; a gate conductive pillar, a first source / drain region conductive pillar, and a second source / drain region conductive pillar, wherein the gate conductive pillar is connected to the gate metal silicide, the first source / drain region conductive pillar is connected to the first source / drain region metal silicide, and the second source / drain region conductive pillar is connected to the second source / drain region metal silicide.
[0031] Optionally, in the MOS device, the width of the gate is between and .
[0032] In the MOS device and its manufacturing method provided by the present invention, an epitaxial layer is formed on a part of the semiconductor substrate, and a gate is formed on the sidewall of the epitaxial layer through a maskless etching process, thereby avoiding the photolithography process and thus being free from the limitations of photolithography technology. Among them, the size of the gate can be controlled by adjusting the thickness of the gate conductive material layer deposited on the epitaxial layer. Description of the Drawings
[0033] Figure 1It is a schematic flow chart of a manufacturing method of a MOS device according to an embodiment of the present invention.
[0034] Figure 2 It is a schematic cross-sectional view of a device on a semiconductor substrate provided by an embodiment of the present invention.
[0035] Figure 3 It is a schematic cross-sectional view of a device after forming a first patterned mask layer provided by an embodiment of the present invention.
[0036] Figure 4 It is a schematic cross-sectional view of a device after forming an epitaxial layer provided by an embodiment of the present invention.
[0037] Figure 5 It is a schematic cross-sectional view of a device after forming a gate dielectric material layer provided by an embodiment of the present invention.
[0038] Figure 6 It is a schematic cross-sectional view of a device after forming a gate conductive material layer provided by an embodiment of the present invention.
[0039] Figure 7 It is a schematic cross-sectional view of a device after forming a gate provided by an embodiment of the present invention.
[0040] Figure 8 It is a schematic cross-sectional view of a device after forming a first doped region provided by an embodiment of the present invention.
[0041] Figure 9 It is a schematic cross-sectional view of a device after forming a second doped region and a third doped region provided by an embodiment of the present invention.
[0042] Figure 10 It is a schematic cross-sectional view of a device after forming a gate conductive column, a first source / drain region conductive column, and a second source / drain region conductive column provided by an embodiment of the present invention.
[0043] Among them, the reference numerals are explained as follows:
[0044] 100 - semiconductor substrate; 110 - well region; 120 - silicon dioxide layer; 130 - first patterned mask layer; 132 - first opening; 140 - epitaxial layer; 150 - gate dielectric material layer; 160 - gate conductive material layer; 170 - gate; 180 - second patterned mask layer; 182 - second opening; 190 - first doped region; 200 - second doped region; 210 - third doped region; 220 - first source / drain region; 230 - second source / drain region; 240 - gate dielectric layer; 250 - gate metal silicide; 260 - first source / drain region metal silicide; 270 - second source / drain region metal silicide; 280 - interlayer dielectric layer; 290 - gate conductive column; 300 - first source / drain region conductive column; 310 - second source / drain region conductive column.
[0045] Note that in the embodiments described below, the same reference numerals are sometimes used in different drawings to denote the same or functionally identical parts, and their repeated description is omitted. In some cases, similar reference numerals and letters are used to denote similar items, and thus, once an item is defined in one drawing, it is not necessary to discuss it further in subsequent drawings. Detailed Embodiments
[0046] The MOS device and its manufacturing method proposed by the present invention will be further described in detail below in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.
[0047] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. Unless otherwise defined in this application document, the technical terms or scientific terms used in the present invention should be the ordinary meanings understood by those with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar terms used in the specification and claims of the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a quantity limitation, but mean that there is at least one. "Plurality" or "several" means two or more. Unless otherwise specified, terms such as "upper / upper layer", "lower / lower layer" are only for convenience of description and are not limited to one position or a spatial orientation. The terms "comprising" or "including" and similar terms mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. The singular forms of "a", "the" and "said" used in the specification and appended claims of the present invention are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0048] Please refer to Figure 1 , which is a schematic flowchart of the manufacturing method of the MOS device according to an embodiment of the present invention. As Figure 1 shown, the manufacturing method of the MOS device mainly includes the following steps:
[0049] Step S10: Provide a semiconductor substrate;
[0050] Step S12: Form an epitaxial layer locally on the semiconductor substrate;
[0051] Step S14: Form a gate dielectric material layer that covers the epitaxial layer and the semiconductor substrate;
[0052] Step S16: Form a gate conductive material layer on the gate dielectric material layer;
[0053] Step S18: Perform a maskless etching process on the gate conductive material layer to form a gate on the sidewalls of the epitaxial layer; and,
[0054] Step S20: Form a first source / drain region and a second source / drain region in the semiconductor substrate, wherein the first source / drain region extends into the epitaxial layer.
[0055] Here, an epitaxial layer is formed locally on the semiconductor substrate, and a gate is formed on the sidewalls of the epitaxial layer through a maskless etching process, thus avoiding the photolithography process and being free from the limitations of photolithography technology. Among them, the size of the gate can be controlled by adjusting the thickness of the gate conductive material layer deposited on the epitaxial layer.
[0056] Further, please refer to Figures 2 to 10 , which is a schematic cross-sectional view of a device of the structure formed by performing the manufacturing method of the MOS device according to the embodiment of the present invention.
[0057] As Figure 2 shown, in the embodiment of the present application, a semiconductor substrate 100 is first provided. Among them, the material of the semiconductor substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, etc. Further, it can be a bulk structure, for example, it can be a bulk silicon structure, a bulk germanium structure, etc.; it can also be a structure on insulator, for example, it can be a silicon on insulator (SOI) structure, a germanium on insulator (GOI) structure, etc.
[0058] In one embodiment, a silicon oxide layer 120 is formed on the surface of the semiconductor substrate 100, and the thickness of the silicon oxide layer 120 is preferably greater than or equal to 75 angstroms. The silicon oxide layer 120 can protect the surface of the semiconductor substrate 100 and is also conducive to the control of subsequent processes.
[0059] In one embodiment, a well region ion implantation process is performed on the semiconductor substrate 100 to form a well region 110 in the semiconductor substrate 100. Specifically, a P-type ion implantation process or an N-type ion implantation process can be selected according to the type of MOS device to be formed.
[0060] Next, as Figure 3As shown, a first patterned mask layer 130 is formed on the silicon oxide layer 120. The material of the first patterned mask layer 130 can be, for example, a hard mask material, a photoresist material, etc. The first patterned mask layer 130 has a first opening 132 that exposes a part of the silicon oxide layer 120.
[0061] In the embodiment of the present application, then, the exposed silicon oxide layer 120 is removed to expose the semiconductor substrate 100, specifically exposing the well region 110. Specifically, an etching process, such as a wet etching process, can be used to remove the exposed silicon oxide layer 120. Further, the first patterned mask layer 130 is also removed to expose the remaining silicon oxide layer 120. Specifically, processes such as ashing can be used to remove the first patterned mask layer 130.
[0062] Next, as Figure 4 shown, an epitaxial growth process is performed on the exposed semiconductor substrate 100 to form an epitaxial layer 140 on the exposed semiconductor substrate 100. That is, an epitaxial layer 140 is formed locally on the semiconductor substrate 100. Among them, the thickness of the epitaxial layer 140 is preferably between and.
[0063] Further, after the epitaxial layer 140 is formed, the remaining silicon oxide layer 120 is also removed to expose the semiconductor substrate 100. In another embodiment, since the silicon oxide layer 120 and the subsequently formed gate dielectric material layer 150 can have the same material, the remaining silicon oxide layer 120 can also be retained.
[0064] Please refer to Figure 5 , next, a gate dielectric material layer 150 is formed. The gate dielectric material layer 150 covers the epitaxial layer 140 and the semiconductor substrate 100. Specifically, a furnace process can be used to form the gate dielectric material layer 150. The material of the gate dielectric material layer 150 is, for example, silicon oxide. Through the furnace process, the surface lattice damage of the epitaxial layer 140 and the semiconductor substrate 100 can also be repaired, improving the quality and reliability of the formed MOS device. In another embodiment, a thermal oxidation process can be used to form the gate dielectric material layer 150.
[0065] Next, as Figure 6As shown, a gate conductive material layer 160 is formed on the gate dielectric material layer 150. Among them, the material of the gate conductive material layer 160 can be, for example, metal, polysilicon, etc. In the embodiment of the present application, the material of the gate conductive material layer 160 is polysilicon, which can be formed by a deposition process. Among them, the thickness of the gate conductive material layer 160 can be determined according to the size of the gate to be formed. For example, the thickness of the gate conductive material layer 160 is between and , for example, it can be or etc. Further, the thickness of the gate conductive material layer 160 can also be larger than .
[0066] Next, as Figure 7 shown, a maskless etching (Blank Etch) process is performed on the gate conductive material layer 160 to form a gate 170 on the sidewall of the epitaxial layer 140, specifically a maskless dry etching in the vertical direction. Here, due to the use of the maskless etching process, the use of the photolithography process is avoided during the formation of the gate. Correspondingly, it can be free from the limitations of the photolithography technology. Specifically, a dry etching process can be used to perform maskless etching on the gate conductive material layer 160. Among them, the width of the gate 170 (i.e., the thickness of the gate conductive material layer 160) is the characteristic size of the formed MOS device, for example, between and . Here, since the deposition process can control the thickness of the formed gate conductive material layer 160, for example, its thickness can be as low as correspondingly, the width of the formed gate 170 can also be as low as thus avoiding the limitations of the photolithography technology and further reducing the characteristic size of the MOS device.
[0067] Next, please refer to Figure 8 , a second patterned mask layer 180 is formed, and the second patterned mask layer 180 covers the gate 170 and part of the gate dielectric material layer 150. Specifically, the second patterned mask layer 180 has a second opening 182, and the second opening 182 exposes the part of the gate dielectric material layer 150 that covers the epitaxial layer 140. Among them, the material of the second patterned mask layer 180 can be, for example, a hard mask material, a photoresist material, etc.
[0068] In an embodiment of the present application, then, a first ion implantation process is performed on the semiconductor substrate 100 and the epitaxial layer 140 to form a first doped region 190 in the semiconductor substrate 100 and the epitaxial layer 140, or to form a first doped region 190 in the semiconductor substrate 100. Herein, specifically, the first ion implantation process is performed on the well region 110 and the epitaxial layer 140 to form a first doped region 190 in the well region 110 and the epitaxial layer 140, or to form a first doped region 190 in the well region 110.
[0069] Preferably, the thickness of the epitaxial layer 140 is between and the ion implantation energy of the first ion implantation process is between 40 keV and 180 keV. Thus, the position of the formed first doped region 190 is relatively deep. In an embodiment of the present application, the first doped region 190 is located in the semiconductor substrate 100, and more specifically, in the well region 110. That is, the first doped region 190 extends from the surface of the well region 110 into the well region 110. In other embodiments of the present application, the first doped region 190 may also extend from the epitaxial layer 140 into the well region 110.
[0070] As Figure 9 shown, then, the second patterned mask layer 180 is removed to expose the gate 170 and the gate dielectric material layer 150.
[0071] Next, a second ion implantation process is performed on the semiconductor substrate 100 and the epitaxial layer 140 to form a second doped region 200 and a third doped region 210 in the semiconductor substrate 100 and the epitaxial layer 140. Among them, the second doped region 200 is connected to the first doped region 190 to form a first source / drain region 220, and the third doped region 210 forms a second source / drain region 230. Among them, the first source / drain region 220 may specifically be a source electrode, and the second source / drain region 230 may specifically be a drain electrode; or, the first source / drain region 220 may specifically be a drain electrode, and the second source / drain region 230 may specifically be a source electrode.
[0072] Preferably, the ion implantation energy of the second ion implantation process is between 10 keV and 40 keV. In an embodiment of the present application, the gate conductive material layer 160 is a polysilicon layer. When the second ion implantation process is performed on the semiconductor substrate 100 and the epitaxial layer 140, ion implantation is also performed on the gate 170.
[0073] In an embodiment of the present application, the second doped region 200 extends from the surface of the epitaxial layer 140 to contact the first doped region 190; the third doped region 210 extends from the surface of the semiconductor substrate 100 into the semiconductor substrate 100. Preferably, the depth of the third doped region 210 is the same as the depth of the first doped region 190, that is, the distance from the third doped region 210 to the surface of the semiconductor substrate 100 is the same as the distance from the first doped region 190 to the surface of the semiconductor substrate 100.
[0074] Please refer to Figure 10 , in an embodiment of the present application, further, it further includes: etching the gate dielectric material layer 150 to form a gate dielectric layer 240. Specifically, the exposed gate dielectric material layer 150 is etched away, and the portions of the gate dielectric material layer 150 between the gate 170 and the semiconductor substrate 100 and between the gate 170 and the epitaxial layer 140 are retained to form the gate dielectric layer 240.
[0075] After removing the exposed gate dielectric material layer 150, the surfaces of the first source / drain region 220 and the second source / drain region 230 are exposed. In an embodiment of the present application, further, a salicide process is performed to form a gate salicide 250, a first source / drain region salicide 260, and a second source / drain region salicide 270 on the surfaces of the gate 170, the first source / drain region 220, and the second source / drain region 230, respectively.
[0076] In an embodiment of the present application, then, an interlayer dielectric layer 280 is formed, and the interlayer dielectric layer 280 covers the gate salicide 250, the first source / drain region salicide 260, the second source / drain region salicide 270, and the gate dielectric layer 240, that is, here, the interlayer dielectric layer 280 covers the exposed surfaces of the device structure. Then, a third opening (not shown in the figure) exposing the gate salicide 250, a fourth opening (not shown in the figure) exposing the first source / drain region salicide 260, and a fifth opening (not shown in the figure) exposing the second source / drain region salicide 270 are formed in the interlayer dielectric layer 280. Further, a gate conductive pillar 290, a first source / drain region conductive pillar 300, and a second source / drain region conductive pillar 310 are respectively formed in the third opening, the fourth opening, and the fifth opening. The gate conductive pillar 290 is connected to the gate salicide 250, the first source / drain region conductive pillar 300 is connected to the first source / drain region salicide 260, and the second source / drain region conductive pillar 310 is connected to the second source / drain region salicide 270.
[0077] In Figure 10Two MOS transistors are shown, and the two MOS transistors share a first source / drain region 220. For example, if the first source / drain region 220 is a source electrode, then the second source / drain region 230 on the left serves as the drain electrode of the first MOS transistor, and the second source / drain region 230 on the right serves as the drain electrode of the second MOS transistor.
[0078] Please continue to refer to Figure 10 , correspondingly, an embodiment of the present application further provides a MOS device, where the MOS device includes: a semiconductor substrate 100; an epitaxial layer 140 covering a part of the semiconductor substrate 100; a gate electrode 170 covering the sidewalls of the epitaxial layer 140; and a first source / drain region 220 and a second source / drain region 230 located in the semiconductor substrate 100, where the first source / drain region 220 extends into the epitaxial layer 140.
[0079] Among them, the first source / drain region 220 extends from the surface of the epitaxial layer 140 into the semiconductor substrate 100, and the second source / drain region 230 extends from the surface of the semiconductor substrate 100 into the semiconductor substrate 100. Preferably, the depths of the first source / drain region 220 and the second source / drain region 230 are the same, that is, the distances from the first source / drain region 220 to the surface of the semiconductor substrate 100 and from the second source / drain region 230 to the surface of the semiconductor substrate 100 are the same.
[0080] In the embodiment of the present application, the first source / drain region 220 includes a first doping region 190 and a second doping region 200 connected to the first doping region 190, and the second source / drain region 230 includes a third doping region 210; among them, the first doping region 190 is located in the semiconductor substrate 100, or the first doping region 190 extends from the epitaxial layer 140 into the semiconductor substrate 100; the second doping region 200 extends from the surface of the epitaxial layer 140 to be connected to the first doping region 190; the third doping region 210 extends from the surface of the semiconductor substrate 100 into the semiconductor substrate 100.
[0081] Furthermore, the MOS device further includes a gate dielectric layer 240, and the gate dielectric layer 240 is located between the gate electrode 170 and the semiconductor substrate 100 and the epitaxial layer 140. Here, the gate dielectric layer 240 is in an "L" shape or a mirror image of the "L" shape.
[0082] In one embodiment, the MOS device further includes a gate metal silicide 250, a first source / drain region metal silicide 260, and a second source / drain region metal silicide 270, which are respectively located on the gate 170, the first source / drain region 220, and the second source / drain region 230; a gate conductive pillar 290, a first source / drain region conductive pillar 300, and a second source / drain region conductive pillar 310, where the gate conductive pillar 290 is connected to the gate metal silicide 250, the first source / drain region conductive pillar 300 is connected to the first source / drain region metal silicide 260, and the second source / drain region conductive pillar 310 is connected to the second source / drain region metal silicide 270.
[0083] In one embodiment, the width of the gate 170 is between and .
[0084] In summary, in the MOS device and its manufacturing method provided by the present invention, an epitaxial layer is formed locally on a semiconductor substrate, and a gate is formed on the sidewall of the epitaxial layer through a maskless etching process, thereby avoiding the photolithography process and thus being free from the limitations of photolithography technology. Among them, the size of the gate can be controlled by adjusting the thickness of the gate conductive material layer deposited on the epitaxial layer.
[0085] In this application, the reference to "one embodiment" or "some embodiments" means that the features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment or at least some embodiments of this application. Therefore, the appearances of the phrases "in one embodiment" and "in some embodiments" throughout this application are not necessarily referring to the same or the same set of embodiments. In addition, in one or more embodiments, the features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.
[0086] Although some specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The various embodiments of this application can be combined arbitrarily without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.
Claims
1. A manufacturing method of a MOS device, characterized in that, The manufacturing method of the MOS device includes: Providing a semiconductor substrate; Forming an epitaxial layer locally on the semiconductor substrate; Forming a gate dielectric material layer that covers the epitaxial layer and the semiconductor substrate; Forming a gate conductive material layer on the gate dielectric material layer; Performing a maskless etching process on the gate conductive material layer to form a gate on the sidewalls of the epitaxial layer; and Forming a first source / drain region and a second source / drain region in the semiconductor substrate, wherein the first source / drain region extends into the epitaxial layer.
2. The manufacturing method of the MOS device according to claim 1, characterized in that, Forming a first source / drain region and a second source / drain region in the semiconductor substrate includes: Performing a first ion implantation process on the semiconductor substrate and the epitaxial layer to form at least a first doped region in the semiconductor substrate; and Performing a second ion implantation process on the semiconductor substrate and the epitaxial layer to form a second doped region and a third doped region in the semiconductor substrate and the epitaxial layer, wherein the second doped region and the first doped region are joined to form the first source / drain region, and the third doped region forms the second source / drain region.
3. The manufacturing method of the MOS device according to claim 2, characterized in that, The first doped region is located in the semiconductor substrate, or the first doped region extends from the epitaxial layer into the semiconductor substrate; The second doped region extends from the surface of the epitaxial layer to join the first doped region; the third doped region extends from the surface of the semiconductor substrate into the semiconductor substrate.
4. The manufacturing method of the MOS device according to claim 2, characterized in that, The thickness of the epitaxial layer is between , and the ion implantation energy of the first ion implantation process is between 40 keV and 180 keV.
5. The manufacturing method of the MOS device according to claim 1, characterized in that, The width of the gate is between and .
6. The manufacturing method of the MOS device according to any one of claims 1 to 5, characterized in that, Before forming the epitaxial layer locally on the semiconductor substrate, the manufacturing method of the MOS device further includes: Performing a well region ion implantation process on the semiconductor substrate to form a well region in the semiconductor substrate.
7. The manufacturing method of the MOS device according to any one of claims 1 to 5, characterized in that, After forming the first source / drain region and the second source / drain region in the semiconductor substrate, the manufacturing method of the MOS device further includes: Etching the gate dielectric material layer to form a gate dielectric layer; Forming a gate metal silicide, a first source / drain region metal silicide, and a second source / drain region metal silicide on the surfaces of the gate, the first source / drain region, and the second source / drain region respectively; and Forming a gate conductive pillar, a first source / drain region conductive pillar, and a second source / drain region conductive pillar, wherein the gate conductive pillar is connected to the gate metal silicide, the first source / drain region conductive pillar is connected to the first source / drain region metal silicide, and the second source / drain region conductive pillar is connected to the second source / drain region metal silicide.
8. A MOS device, characterized in that, The MOS device includes: A semiconductor substrate; An epitaxial layer that covers a part of the semiconductor substrate; A gate that covers the sidewalls of the epitaxial layer; and A first source / drain region and a second source / drain region located in the semiconductor substrate, wherein the first source / drain region extends into the epitaxial layer.
9. The MOS device according to claim 8, characterized in that, The first source / drain region includes a first doped region and a second doped region connected to the first doped region, and the second source / drain region includes a third doped region; wherein, the first doped region is located in the semiconductor substrate, or the first doped region extends from the epitaxial layer into the semiconductor substrate; the second doped region extends from the surface of the epitaxial layer to be connected to the first doped region; the third doped region extends from the surface of the semiconductor substrate into the semiconductor substrate.
10. The MOS device according to claim 8, characterized in that, The MOS device further includes a gate dielectric layer, which is interposed between the gate and the semiconductor substrate, and between the gate and the epitaxial layer.
11. The MOS device according to claim 8, characterized in that, The MOS device further includes: A gate metal silicide, a first source / drain region metal silicide, and a second source / drain region metal silicide, which are respectively located on the gate, the first source / drain region, and the second source / drain region; a gate conductive pillar, a first source / drain region conductive pillar, and a second source / drain region conductive pillar, where the gate conductive pillar is connected to the gate metal silicide, the first source / drain region conductive pillar is connected to the first source / drain region metal silicide, and the second source / drain region conductive pillar is connected to the second source / drain region metal silicide.
12. The MOS device according to any one of claims 8-11, characterized in that, The width of the gate is between and .