Preparation method of semiconductor structure
By introducing a closed air gap structure into the metal interconnect layer of the semiconductor integrated circuit, the dielectric constant of the insulating medium is reduced, and the problem of RC delay between metal interconnect lines is solved, and the effect of reducing parasitic capacitance and improving chip speed is achieved.
Patent Information
- Application Number
- CN202311740438.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-18
- Publication Date
- 2025-06-20
AI Technical Summary
In the rear-stage process of semiconductor integrated circuits, the RC delay between metal interconnects has an increasingly greater impact on chip speed, and it is difficult for the prior art to effectively reduce parasitic capacitance.
By introducing a plurality of spaced and adjustable enclosed air gap structures in the insulating medium in the metal interconnect layer, the dielectric constant of the insulating medium is reduced, thereby forming a low dielectric constant film and metal interconnect layer, reducing parasitic capacitance and RC delay.
This achieves the reduction of parasitic capacitance and RC delay of the metal interconnect layer, and improves the chip's speed performance.
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Figure CN120184086A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for manufacturing a semiconductor structure. Background Art
[0002] Currently, in the back-end-of-line (BEOL) process of semiconductor devices, when manufacturing semiconductor integrated circuits, after the semiconductor device layer is formed, a metal interconnect layer needs to be formed on the semiconductor device layer. Each metal interconnect layer includes metal interconnect lines and insulating media.
[0003] With the iteration of semiconductor integrated circuit technology nodes, the resistance-capacitance delay (RC delay) caused by metal interconnect lines has an increasingly greater impact on the speed of integrated chips; for the RC delay, when the material and design specifications of the metal interconnect lines are fixed, reducing the parasitic capacitance (C) is an effective and feasible means. Since the parasitic capacitance C is proportional to the dielectric constant k (referred to as low-k) of the insulating medium in the metal interconnect layer, in the process of chip manufacturing, introducing a low-k material to replace traditional silicon dioxide as the insulating medium of the metal interconnect layer is a common solution in the industry. Summary of the Invention
[0004] The purpose of the present invention is to provide a method for manufacturing a semiconductor structure, so as to introduce a plurality of spaced and closed air gap structures with adjustable sizes and shapes into the insulating medium in the metal interconnect layer, reduce the dielectric constant of the insulating medium, that is, form a low dielectric constant thin film and a metal interconnect layer with the low dielectric constant thin film as the insulating medium, and also achieve the purpose of reducing the parasitic capacitance and RC delay of the metal interconnect layer.
[0005] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor structure, which at least includes the following steps:
[0006] Provide a substrate, on which a metal interconnect layer is formed, and the metal interconnect layer includes a plurality of metal interconnect lines;
[0007] Form a film layer structure to be patterned on the metal interconnect layer, and the film layer structure to be patterned includes an etch stop layer, a first insulating medium layer, a sacrificial medium layer, a second insulating medium layer, and an anti-reflection layer stacked in sequence from bottom to top;
[0008] Etch to form a plurality of first trenches in the film layer structure to be patterned, and the bottom of one of the first trenches exposes the top of one of the metal interconnect lines;
[0009] Form a third insulating medium layer, and the third insulating medium layer fills the plurality of first trenches and is horizontally connected to the first insulating medium layer and the second insulating medium layer located between adjacent first trenches respectively;
[0010] A plurality of second trenches are formed in a third insulating dielectric layer and a second insulating layer on a sacrificial dielectric layer located between adjacent ones of the first trenches, and in a vertical direction, projections of the second trenches do not overlap with projections of the first trenches;
[0011] The sacrificial dielectric layer is removed through the second trenches to form a plurality of semi-closed air gap structures with openings at the tops, which are separated by the first insulating dielectric layer, the second insulating dielectric layer, and the third insulating dielectric layer;
[0012] At least in the top openings of partial heights of each of the semi-closed air gap structures, a fourth insulating dielectric layer communicating with the third insulating dielectric layer and the second insulating dielectric layer is filled to form a low dielectric constant thin film containing a plurality of enclosed air gap structures arranged at intervals inside.
[0013] In some alternative examples, the process of removing the sacrificial dielectric layer through the second trenches includes an ashing process.
[0014] In some alternative examples, process conditions of the ashing process include: a temperature range of 250°C to 285°C, and a reaction gas being a mixed gas of oxygen and nitrogen.
[0015] In some alternative examples, each of the first insulating dielectric layer, the second insulating dielectric layer, the third insulating dielectric layer, and the fourth insulating dielectric layer includes at least one of a silicon oxide layer, a low dielectric constant material layer, or an ultra-low dielectric constant material layer.
[0016] In some alternative examples, the sacrificial dielectric layer includes a carbon-containing material layer.
[0017] In some alternative examples, the carbon-containing material layer includes at least one of an amorphous carbon layer or a spin-on carbon layer.
[0018] In some alternative examples, a thickness range of the carbon-containing material layer can be specifically 70 nm to 1500 nm.
[0019] In some alternative examples, the process of forming the carbon-containing material layer is a chemical vapor deposition process or a spin-on sol-gel method.
[0020] In some alternative examples, the etch stop film layer includes at least one of a silicon nitride layer or a silicon carbonitride layer.
[0021] In some alternative examples, after forming the low dielectric constant thin film containing a plurality of enclosed air gap structures arranged at intervals inside, the preparation method further includes:
[0022] A plurality of third trenches are formed in the fourth insulating dielectric layer, the third insulating dielectric layer, the second insulating dielectric layer, and the first insulating dielectric layer located between adjacent ones of the enclosed air gap structures, and the top of a metal interconnecting line is exposed at the bottom of one of the third trenches; and
[0023] A metal material layer is filled in the third trenches to form conductive plugs connecting the multi-layer metal interconnecting layers; wherein, in the vertical direction, the projection of the third trenches partially overlaps with the projection of the first trenches and does not overlap with the projection of the second trenches.
[0024] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:
[0025] In the method for preparing a semiconductor structure provided by the present invention, a film layer structure to be patterned including at least a first insulating dielectric layer, a sacrificial dielectric layer, and a second insulating dielectric layer can be first formed on a metal interconnecting layer, and then multiple enclosed air gap structures arranged at intervals are formed in the film layer structure to be patterned by using multiple semiconductor manufacturing process steps such as photolithography, etching, and deposition. After that, etching, filling, and other processes can be further used to form conductive plugs respectively for connecting a metal interconnecting line in the metal interconnecting layer in the film layer structure of the multiple enclosed air gap structures.
[0026] An unexpected effect is obtained: multiple enclosed air gap structures with intervals and adjustable sizes and shapes can be introduced into the insulating dielectric according to actual design requirements, that is, by introducing air with a smaller dielectric constant into the insulating dielectric, the dielectric constant of the insulating dielectric is reduced, that is, a preparation method for forming a low dielectric constant thin film is proposed; then, based on the low dielectric constant thin film formed by the present invention and containing multiple enclosed air gap structures with intervals and adjustable sizes and shapes, a metal interconnecting layer using the low dielectric constant thin film as the insulating dielectric or a metal interconnecting structure including multiple layers of the metal interconnecting layers is formed, and the purpose of reducing the parasitic capacitance and RC delay of the metal interconnecting layer is also achieved. Description of the Drawings
[0027] Figure 1 It is a schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present invention;
[0028] Figure 2 is Figure 1 a partial structural schematic diagram after at least forming a metal interconnecting layer 120 on a substrate in the corresponding preparation method;
[0029] Figure 3 is Figure 1 a partial structural schematic diagram after forming a film layer structure 130 to be patterned composed of multiple film layers on the metal interconnecting layer 120 in the corresponding preparation method;
[0030] Figure 4 For Figure 1 A partial structural schematic diagram after forming a plurality of first trenches 101 corresponding to the positions and sizes of the metal interconnect lines 121 in the film layer structure 130 to be patterned in the corresponding preparation method;
[0031] Figure 5 For Figure 1 A partial structural schematic diagram after filling a third insulating dielectric layer 140 in a plurality of first trenches 101 formed in the film layer structure 130 to be patterned in the corresponding preparation method;
[0032] Figure 6 For Figure 1 A partial structural schematic diagram after forming a plurality of second trenches 102 in the formed third insulating dielectric layer 140 and the second insulating dielectric layer 134 in the corresponding preparation method;
[0033] Figure 7 For Figure 1 A structural schematic diagram of a semi - enclosed air gap structure formed by removing the carbon - containing material block 133a through the opening direction of the second trench 102 in the corresponding preparation method;
[0034] Figure 8 For Figure 1 A structural schematic diagram of a low - dielectric - constant thin film formed with a plurality of closed air gap structures arranged at intervals inside in the corresponding preparation method;
[0035] Figures 9 - 10 A structural schematic diagram of the preparation process of further forming a metal interconnect layer after forming a low - dielectric - constant thin film with a plurality of closed air gap structures arranged at intervals inside in the preparation method of the semiconductor structure provided in an embodiment of the present invention;
[0036] Among them, the marks in the drawings are:
[0037] 100 - Substrate;
[0038] 110 - Device layer;
[0039] 120 - Metal interconnect layer;
[0040] 121 - Metal interconnect line;
[0041] 130 - Film layer structure to be patterned;
[0042] 131 - Etch stop layer;
[0043] 132 - First insulating dielectric layer;
[0044] 133 - Sacrificial dielectric layer;
[0045] 133a - Carbon - containing material block;
[0046] 133b - Semi - enclosed air - gap structure;
[0047] 133c - Enclosed air - gap structure;
[0048] 134 - Second insulating dielectric layer;
[0049] 135 - Anti - reflection layer;
[0050] 140 - Third insulating dielectric layer;
[0051] 150 - Fourth insulating dielectric layer;
[0052] CT - Conductive plug;
[0053] 251 - Low - dielectric - constant thin film;
[0054] 101 - First trench;
[0055] 102 - Second trench;
[0056] 103 - Third trench. Detailed implementation manners
[0057] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below in combination with the drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present invention and to be able to convey the scope of the present invention completely to those skilled in the art.
[0058] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the drawings. The advantages and features of the present invention will be clearer according to the following description and the claims. It should be noted that the drawings are all in a very simplified form and use non - precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "overhead...", etc. in the present invention should be interpreted in the broadest way, so that "on..." not only means "on" something without any intermediate features or layers (i.e., directly on something), but also includes the meaning of being "on" something with intermediate features or layers.
[0059] In addition, for ease of description, spatial relative terms such as "on", "above", "over", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another element or feature. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly.
[0060] In the embodiments of the present invention, terms such as "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.
[0061] According to the related art, in the process of chip manufacturing, introducing a low-k material to replace traditional silicon dioxide as the insulating medium of the metal interconnect layer is an effective and feasible solution commonly used in the industry to reduce the parasitic capacitance (C).
[0062] In the current prior art, the specific process of using the method for manufacturing a low dielectric constant thin film is as follows: using a CVD machine, a silicon source compound as a thin film liquid source, for example, DEMS (Diethoxy methylsilane), and an organic pore former, for example, ATRP (α-Terpinene), are used to form a low dielectric constant thin film through thin film deposition and crosslinking reaction, and then the pore former remaining after the crosslinking reaction is removed by heating with ultraviolet light.
[0063] Since the ratio of the thin film silicon source and the pore former used in the prior art needs to be adjusted, and the film formation also needs to be combined with the UV-cure process, obviously, the film-forming chemical materials and process are complex, the adjustable porosity range is limited, a large-porosity thin film system structure with controllable morphology cannot be obtained, and the organic pore former requires a large amount of electric power for PECVD, which is bound to cause problems such as high manufacturing cost of the low dielectric constant thin film, complex manufacturing system, and high process flow requirements.
[0064] Based on this, the inventors of the present invention propose a preparation method for forming a thin film with a low dielectric constant and a preparation method for a metal interconnect layer including the low dielectric constant thin film, so as to achieve the purpose of reducing the parasitic capacitance and RC delay of the metal interconnect layer.
[0065] The overall inventive concept of the preparation method proposed by the present invention is as follows: By introducing a plurality of enclosed air-gap structures with small dielectric constants and arranged at intervals in the insulating medium, the dielectric constant of the insulating medium in the low-dielectric-constant thin film or the metal interconnect layer (metal interconnect structure) is reduced. Specifically, based on different actual design requirements, the size, dimensions, and shape of each enclosed air-gap structure can be adjusted, that is, by specifically controlling the porosity and morphology of the enclosed air-gap structure, flexible control of the dielectric constant of the insulating medium in the low-dielectric-constant thin film or the metal interconnect layer can be achieved.
[0066] For ease of understanding, the horizontal direction and the vertical direction are defined hereinafter. The horizontal direction is the direction parallel to the surface of the substrate 100; the vertical direction is the direction perpendicular to the surface of the substrate 100; and in Figures 2 - 10 the X direction and the Y direction are also specifically defined. The X direction corresponds to the horizontal direction, the Y direction corresponds to the vertical direction, and the X direction and the Y direction are perpendicular to each other.
[0067] Referring to Figure 1 and combining with Figures 2 - 10 wherein the Figure 1 is a schematic flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present invention, and the Figures 2 - 10 is the structure schematic diagram in the preparation process of the method for preparing the semiconductor structure provided in an embodiment of the present invention as shown in Figure 1 .
[0068] As shown in Figure 1 , the method for preparing the semiconductor structure may include the following steps:
[0069] Step S101: Provide a substrate, on which a metal interconnect layer is formed, and the metal interconnect layer includes a plurality of metal interconnect lines.
[0070] Step S102: Form a film layer structure to be patterned on the metal interconnect layer. The film layer structure to be patterned includes an etch stop layer, a first insulating medium layer, a sacrificial medium layer, a second insulating medium layer, and an anti-reflection layer stacked in sequence from bottom to top.
[0071] Step S103: Etch to form a plurality of first trenches in the film layer structure to be patterned, and the top of one of the metal interconnect lines is exposed at the bottom of one of the first trenches.
[0072] Step S104: Form a third insulating medium layer, which fills the plurality of first trenches and is horizontally connected to the first insulating medium layer and the second insulating medium layer located between adjacent first trenches respectively.
[0073] Step S105: Form a plurality of second trenches in the third insulating dielectric layer and the second insulating layer on the sacrificial dielectric layer located between adjacent first trenches, and in the vertical direction, the projection of the second trenches does not overlap with that of the first trenches.
[0074] Step S106: Remove the sacrificial dielectric layer through the second trenches to form a plurality of semi-closed air gap structures with open tops separated by the first insulating dielectric layer, the second insulating dielectric layer, and the third insulating dielectric layer.
[0075] Step S107: Fill at least the top openings of the partial height of each semi-closed air gap structure with a fourth insulating dielectric layer communicating with the third insulating dielectric layer and the second insulating dielectric layer to form a low dielectric constant thin film containing a plurality of enclosed air gap structures arranged at intervals inside.
[0076] Refer to Figure 2 , Figure 2 is Figure 1 a partial structural schematic diagram after at least forming a metal interconnect layer 120 on a substrate in the corresponding manufacturing method. In the above step S101, a substrate 100 can be provided first, and then one or a combination of semiconductor manufacturing processes such as deposition, photolithography, etching, and chemical mechanical polishing are used to form a device layer 110 including one or more devices (such as MOS transistors, diodes) and a metal interconnect layer 120 stacked on the device layer 110 on the substrate 100. Among them, the metal interconnect layer 120 can include a plurality of metal interconnect lines 121, and the metal interconnect layer 120 can be any layer in the metal interconnect structure for electrically leading out the device layer 110. The present invention does not limit this.
[0077] In this embodiment, the material of the substrate 100 can be any suitable substrate well-known in the art. For example, it can be at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc., but not limited thereto.
[0078] It is understandable that the overall inventive concept of the present invention is to propose a method for preparing a thin film with a low dielectric constant and a method for preparing a metal interconnection layer including the thin film with a low dielectric constant. For the sake of simplicity of description, the inventive steps of the present invention are described in the process of forming an insulating medium for isolating a plurality of conductive plugs in the metal interconnection layer. In other embodiments, the film layer structure to be patterned and the subsequent preparation method proposed by the present invention can also be directly used to form a thin film structure with a low dielectric constant. Based on this theory, the metal interconnection layer 120 can be directly formed on the substrate 100, or the device layer 110 can be formed first and then the metal interconnection layer 120. The present invention does not make specific limitations on this.
[0079] Refer to Figure 3 , Figure 3 is Figure 1 a partial structural schematic diagram after forming a film layer structure 130 to be patterned composed of multiple film layers on the metal interconnection layer 120 in the corresponding preparation method. In the above step S102, a film layer structure 130 to be patterned including an etch stop layer 131, a first insulating dielectric layer 132, a sacrificial dielectric layer 133, a second insulating dielectric layer 134, and an anti-reflection layer 135 stacked in sequence from bottom to top can be deposited or coated on the surface of the metal interconnection layer 120.
[0080] Specifically, one or several of chemical vapor deposition (CVD), atomic layer deposition (ALD), and spin-on sol-gel method can be used to sequentially form an etch stop film layer 131 with a thickness of 10 nm - 200 nm and a material of silicon carbon phosphorus SiCN or silicon nitride SiN on the surface of the metal interconnection layer 120, but not limited thereto, a first insulating dielectric layer 132 with a thickness of 10 nm - 200 nm and a material of silicon oxide, low dielectric constant material, or ultra-low dielectric constant material, but not limited thereto, a sacrificial dielectric layer 133 with a thickness of 70 nm - 1500 nm and a material of amorphous carbon APF, spin-on carbon SOC (Spin on Carb on), or other carbon-containing materials, but not limited thereto, a second insulating dielectric layer 134 with a thickness of 10 nm - 200 nm and a material of silicon oxide, low dielectric constant material, or ultra-low dielectric constant material, but not limited thereto, and an anti-reflection layer 135 with a thickness of 10 nm - 30 nm and a material of organic or inorganic anti-reflection materials such as SiOC (NF DARC), DARC, BARC, etc., but not limited thereto.
[0081] It should be noted that since the materials of the multi-layer films of the to-be-patterned film layer structure 130 for preparing a plurality of enclosed air-gap structures arranged at intervals are all silicon oxide, low-k materials or ultra-low-k materials, the dielectric constant of the to-be-patterned film layer structure 130 is relatively low. Therefore, the dielectric constants of the insulating dielectric film layer or the metal interconnect layer (metal interconnect structure) formed based on the to-be-patterned film layer structure 130 are relatively low, and the parasitic capacitance and RC delay of the metal interconnect layer are also low.
[0082] See Figure 4 , Figure 4 is Figure 1 a partial structural schematic diagram corresponding to the preparation method after forming a plurality of first trenches 101 in the to-be-patterned film layer structure 130 that correspond one-to-one in position and size to the metal interconnect lines 121. In the above step S103, one or more of etching processes, such as dry etching process and wet etching process, can be further used to etch and form a plurality of first trenches 101 in the to-be-patterned film layer structure 130. Among them, the number and specific positions of the first trenches 101 can be the same as those of the metal interconnect lines 121 in the metal interconnect layer 120 located below the to-be-patterned film layer structure 130, that is, the plurality of first trenches 101 are respectively in one-to-one correspondence and communication with the plurality of metal interconnect lines 121. In other words, along the direction perpendicular to the surface of the substrate 100 (simply referred to as the vertical direction), the projection of one first trench 101 completely overlaps with the projection of the corresponding metal interconnect line.
[0083] It should be noted that after forming the plurality of first trenches 101, the anti-reflection layer 135 for improving the lithography process characteristics can be removed by using an etching process, and then the step S104 is performed.
[0084] See Figure 5 , Figure 5 is Figure 1Schematic diagram of the local structure after filling the third insulating dielectric layer 140 in a plurality of first trenches 101 formed in the film layer structure 130 to be patterned in the corresponding manufacturing method. In the above step S104, one or more of chemical vapor deposition (CVD) and atomic layer deposition (ALD) can be used to form the third insulating dielectric layer 140 on the substrate 100. Among them, the material of the third insulating dielectric layer 140 can be the same as that of the first insulating dielectric layer 132 and the second insulating dielectric layer 134, such as silicon oxide, low-k material or ultra-low-k material, but not limited thereto; the third insulating dielectric layer 140 fills at least a plurality of the first trenches 101 along the vertical direction, and is sequentially connected to the first insulating dielectric layer 132 and the second insulating dielectric layer 134 on both sides of each of the first trenches 101 in the surface direction parallel to the substrate 100 (abbreviated as the horizontal direction), so as to form carbon-containing material blocks 133a that divide the sacrificial dielectric layer 133 into a plurality of strips or blocks and are surrounded by an insulating dielectric material made of at least one of silicon oxide, low-k material or ultra-low-k material on all sides.
[0085] It should be noted that in this step, the third insulating dielectric layer 140 may only fill the first trenches 101, that is, the top surface of the third insulating dielectric layer 140 may be flush with the top surface of the second insulating dielectric layer 134. Of course, the third insulating dielectric layer 140 may not only fill the first trenches 101, but also synchronously extend and cover the surface of the second insulating dielectric layer 134, such as Figure 5 shown. Therefore, after forming the third insulating dielectric layer 140 in the manufacturing method provided in the embodiments of the present invention, chemical mechanical polishing (CMP) can also be performed on the third insulating dielectric layer 140 to planarize the connected third insulating dielectric layer 140 and the second insulating dielectric layer 134.
[0086] Refer to Figure 6 , Figure 6 is Figure 1 Schematic diagram of the local structure after forming a plurality of second trenches 102 in the formed third insulating dielectric layer 140 and second insulating dielectric layer 134 in the corresponding manufacturing method. In the above step S105, an etching process, such as a dry etching process, can be used to form a plurality of second trenches 102 arranged in sequence along the horizontal direction with the sacrificial dielectric layer 133 exposed at the bottom in the third insulating dielectric layer 140 and the second insulating layer 134 that are connected together on the sacrificial dielectric layer 133 located between adjacent first trenches 101, and the projection of the second trenches 102 in the vertical direction does not overlap with the projection of the first trenches 101 in the vertical direction. The purpose of forming the second trenches 102 at this time is to serve as openings for removing a plurality of the carbon-containing material blocks 133a in the subsequent step S106.
[0087] See Figure 7 , Figure 7 is Figure 1 a schematic structural view of a semi-closed air gap structure formed by removing the carbon-containing material block 133a through the opening direction of the second trench 102 in the corresponding preparation method. In the above step S106, an ashing process can be used to remove each carbon-containing material block 133a exposed at the bottom of the second trench 102 through the direction of the second trench 102, so as to form a plurality of separated semi-closed air gap structures 133b in the interconnected third insulating dielectric layer 140, second insulating dielectric layer 134, and first insulating dielectric layer 132, and the top of which is connected to the second trench 102. At this time, all of the sacrificial dielectric layer 133 in the film layer structure 130 to be patterned formed in step S102 is removed, and only the first insulating dielectric layer 132 and the second insulating dielectric layer 134 composed of silicon oxide, low-k material, or ultra-low-k material are retained.
[0088] As a preferred example, in the process of removing each carbon-containing material block 133a exposed at the bottom of the second trench 102 by using the ashing process, the process conditions of the ashing process may include: the temperature is 250°C to 285°C, and the reaction gas is a mixed gas of oxygen and nitrogen. The temperature may specifically be 250°C, 275°C, 285°C, and any value between any two of the above values, but is not limited thereto.
[0089] It can be understood that since the film layer structure 130 to be patterned for forming the low-k thin film in the present invention includes amorphous carbon APF, spin-on carbon SOC (Spin on Carbon), or other carbon-containing materials, the preparation method of the low-k thin film provided by the present invention or the preparation method of the metal interconnection layer including the low-k thin film can utilize the principle that the ashing process can remove amorphous carbon APF, spin-on carbon SOC (Spin on Carbon), or other carbon-containing materials without damaging other film layer structures such as the substrate 100 during the specific preparation process, so as to form the closed air gap structure, and further achieve the purpose of simplifying the process, reducing the process cost, and improving the manufacturing efficiency while ensuring the function of the formed semiconductor structure.
[0090] See Figure 8 , Figure 8 is Figure 1Schematic diagram of the structure of a low dielectric constant thin film with a closed air gap structure containing multiple spaced-apart internal portions formed in the corresponding preparation method. In the above step S107, a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), can be further used to fill, at least in the top openings of partial heights of each of the semi-closed air gap structures 133b, a fourth insulating dielectric layer 150 that communicates with the third insulating dielectric layer 140 and the second insulating dielectric layer 134, so as to form a low dielectric constant thin film 251 with a closed air gap structure 133c containing multiple spaced-apart internal portions. Among them, the fourth insulating dielectric layer 150 has the same material as the third insulating dielectric layer 140 and the second insulating dielectric layer 134, thereby achieving communication.
[0091] Obviously, the overall process of the above steps S102 to S107 is to form a low dielectric constant thin film 251 composed of silicon oxide, a low dielectric constant material or an ultra-low dielectric constant material, and a closed air gap structure with multiple spaced-apart internal portions within the film layer structure 130 to be patterned formed on the substrate 100. And this low dielectric constant thin film 251 has a lower dielectric constant due to its high porosity and the use of a low dielectric constant material.
[0092] It can be understood that in the process of forming the low dielectric constant thin film 251 with a closed air gap structure 133c containing multiple spaced-apart internal portions by using the above steps S102 to S107 in the embodiments of the present invention, according to the actual design requirements, by adjusting the depth and width of the first trench 101, the depth and width of the sacrificial dielectric layer 133, etc., a closed air gap structure with adjustable size and shape can be formed within the film layer structure 130 to be patterned, and thus the purpose of reducing the dielectric constant of the insulating dielectric by introducing air with a smaller dielectric constant into the insulating dielectric, that is, to propose a preparation method for forming a low dielectric constant thin film, can be achieved.
[0093] Moreover, in the embodiments of the present invention, according to the actual design requirements, the sizes and morphologies of the multiple spaced-apart closed air gap structures 133c can be set to be the same or different, and the present invention does not make specific limitations in this regard.
[0094] Refer to Figures 9 - 10 , the Figures 9 - 10 is a schematic diagram of the preparation process of further forming a metal interconnect structure after forming a low dielectric constant thin film 251 with a closed air gap structure 133c containing multiple spaced-apart internal portions in the preparation method of the semiconductor structure provided in an embodiment of the present invention.
[0095] Such as Figures 9 - 10As shown, after forming the low-k dielectric thin film with multiple enclosed air gap structures arranged at intervals therein in the above step S107, the manufacturing method further includes:
[0096] Step S108, forming a plurality of third trenches 103 in the fourth insulating dielectric layer, the third insulating dielectric layer, the second insulating dielectric layer, and the first insulating dielectric layer located between adjacent enclosed air gap structures, and the bottom of one third trench 103 exposes the top of one metal interconnection line 121.
[0097] Step S109, filling the third trenches 103 with a metal material layer to form conductive plugs CT for connecting multiple metal interconnection layers.
[0098] In this embodiment, the projection of the third trench 103 in the vertical direction overlaps partially with the projection of the first trench 101 in the vertical direction and does not overlap with the projection of the second trench 102 in the vertical direction. That is to say, steps S108 to S109 are steps of forming a plurality of conductive plugs respectively for electrically connecting multiple metal interconnection lines 121 in the metal interconnection layer 120 after using the low-k dielectric thin film 251 composed of multiple enclosed air gap structures arranged at intervals as the insulating dielectric in the metal interconnection layer.
[0099] It can be understood that in the embodiment of the present invention, only a film layer structure 130 to be patterned for forming the low-k dielectric thin film 251 composed of the enclosed air gap structure is exemplarily shown on the metal interconnection layer 120. In other embodiments, steps S102 to S109 can be repeated to form a metal interconnection structure including multiple metal interconnection layers on the substrate 100, and the insulating dielectric layer in each metal interconnection layer in the formed metal interconnection structure is the low-k dielectric thin film 251 with multiple enclosed air gap structures 133c arranged at intervals formed by steps S102 to S107, so as to achieve the purpose of reducing the parasitic capacitance and RC delay of the metal interconnection layer or the metal interconnection structure proposed by the present invention.
[0100] In summary, in the method for preparing a semiconductor structure provided by the present invention, a film layer structure to be patterned including at least a first insulating dielectric layer, a sacrificial dielectric layer, and a second insulating dielectric layer can be first formed on a metal interconnect layer, and then multiple closed air gap structures arranged at intervals are formed in the film layer structure to be patterned by using multiple semiconductor manufacturing process steps such as photolithography, etching, and deposition. After that, etching, filling, and other processes can be further used to form conductive plugs in the film layer structure located at the multiple closed air gap structures respectively for connecting a metal interconnect line in the metal interconnect layer, and the unexpected effect obtained is that multiple closed air gap structures with intervals and adjustable sizes and shapes can be introduced into the insulating dielectric according to actual design requirements, that is, the method for forming a low dielectric constant thin film is proposed by introducing air with a smaller dielectric constant into the insulating dielectric, thereby reducing the dielectric constant of the insulating dielectric. Then, based on the low dielectric constant thin film formed by the present invention and including multiple closed air gap structures with intervals and adjustable sizes and shapes inside, a metal interconnect layer using the low dielectric constant thin film as the insulating dielectric or a metal interconnect structure including multiple layers of the metal interconnect layer is formed, and the purpose of reducing the parasitic capacitance and RC delay of the metal interconnect layer is also achieved.
[0101] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the presence of additional identical elements in the process, method, article or device including the element.
[0102] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the embodiments of the device, electronic device, and computer-readable storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.
[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate on which a metal interconnect layer is formed, the metal interconnect layer including a plurality of metal interconnect lines; Forming a film layer structure to be patterned on the metal interconnect layer, the film layer structure to be patterned including an etch stop layer, a first insulating dielectric layer, a sacrificial dielectric layer, a second insulating dielectric layer, and an anti-reflection layer stacked in sequence from bottom to top; Etching to form a plurality of first trenches in the film layer structure to be patterned, and the top of one of the metal interconnect lines being exposed at the bottom of one of the first trenches; Forming a third insulating dielectric layer, the third insulating dielectric layer filling the plurality of first trenches and being horizontally connected to the first insulating dielectric layer and the second insulating dielectric layer located between adjacent first trenches respectively; Forming a plurality of second trenches in the third insulating dielectric layer and the second insulating layer on the sacrificial dielectric layer located between adjacent first trenches, and in the vertical direction, the projection of the second trenches not overlapping with the projection of the first trenches; Removing the sacrificial dielectric layer through the second trenches to form a plurality of semi-closed air gap structures with openings at the top separated by the first insulating dielectric layer, the second insulating dielectric layer, and the third insulating dielectric layer; Filling at least the top openings of the partial height of each semi-closed air gap structure with a fourth insulating dielectric layer communicating with the third insulating dielectric layer and the second insulating dielectric layer to form a low dielectric constant thin film containing a plurality of enclosed air gap structures arranged at intervals inside; 2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The process of removing the sacrificial dielectric layer through the second trenches includes an ashing process.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The process conditions of the ashing process include: the temperature range is 250°C to 285°C, and the reaction gas is a mixed gas of oxygen and nitrogen.
4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The first insulating dielectric layer, the second insulating dielectric layer, the third insulating dielectric layer, and the fourth insulating dielectric layer all include at least one of a silicon oxide layer, a low dielectric constant material layer, or an ultra-low dielectric constant material layer.
5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The sacrificial dielectric layer includes a carbon-containing material layer.
6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The carbon-containing material layer includes at least one of an amorphous carbon layer or a spin-on carbon layer.
7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The thickness range of the carbon-containing material layer is 70 nm to 1500 nm.
8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The process of forming the carbon-containing material layer is a chemical vapor deposition process or a spin-on sol-gel method.
9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The etch stop film layer includes at least one of a silicon nitride layer or a silicon carbonitride layer.
10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After forming the low dielectric constant thin film containing a plurality of enclosed air gap structures arranged at intervals inside, the preparation method further includes: Forming a plurality of third trenches in the fourth insulating dielectric layer, the third insulating dielectric layer, the second insulating dielectric layer, and the first insulating dielectric layer located between adjacent enclosed air gap structures, and the top of one of the metal interconnect lines being exposed at the bottom of one of the third trenches; and Filling a metal material layer in the third trenches to form conductive plugs connecting multiple metal interconnect layers; Wherein, in the vertical direction, the projection of the third trenches partially overlaps with the projection of the first trenches and does not overlap with the projection of the second trenches.