Manufacturing method of semiconductor structure
By forming an air gap around the substrate perforation on the back of the semiconductor structure, and a fill layer can be formed therein, the adverse effects of substrate perforation on the semiconductor device are solved, and the effect of reducing parasitic capacitance and preventing stress and radio frequency interference is achieved.
Patent Information
- Application Number
- CN202410623397.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-20
- Filing Date
- 2024-05-20
- Publication Date
- 2025-06-20
AI Technical Summary
As the size of the semiconductor structure continues to shrink, substrate perforation has adverse effects on the semiconductor devices in the semiconductor structure.
By performing a patterning process on the back of the substrate, an air gap surrounding the perforation of the substrate is formed, and a fill layer can be formed in the air gap to prevent adverse effects of the perforation of the substrate on the semiconductor device.
The formation of air gaps and fill layers can reduce parasitic capacitance, prevent stress from adversely affecting the electrical properties of semiconductor devices, and prevent radio frequency interference.
Smart Images
Figure CN120184087A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure including through-substrate vias (TSVs). Background Art
[0002] Some semiconductor structures have through-substrate vias (TSVs) that penetrate the substrate. The through-substrate vias can be used to electrically connect stacked integrated circuits together. However, as the size of semiconductor structures continues to shrink, the through-substrate vias can have an adverse effect on semiconductor devices in the semiconductor structure. Summary of the Invention
[0003] The present invention provides a method for manufacturing a semiconductor structure, which can prevent through-substrate vias from having an adverse effect on semiconductor devices in the semiconductor structure.
[0004] The present invention proposes a method for manufacturing a semiconductor structure, including the following steps. Provide a substrate. The substrate includes a front surface and a back surface opposite to each other. Form a device layer on the front surface of the substrate. Form through-substrate vias in the device layer and the substrate. The through-substrate vias extend from the front surface of the substrate into the substrate. Form a first dielectric layer between the through-substrate vias and the substrate. Perform a patterning process on the back surface of the substrate to form an air gap. The air gap surrounds the through-substrate vias.
[0005] Based on the above, in the method for manufacturing a semiconductor structure proposed by the present invention, a patterning process is performed on the back surface of the substrate to form an air gap. The air gap surrounds the through-substrate vias. In some embodiments, the air gap can be used to prevent through-substrate vias from having an adverse effect on semiconductor devices (such as transistor devices) in the semiconductor structure. In other embodiments, a filling layer can be formed in the air gap, and the filling layer can be used to prevent through-substrate vias from having an adverse effect on semiconductor devices (such as transistor devices) in the semiconductor structure.
[0006] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings
[0007] Figures 1A to 1L Is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention;
[0008] Figure 2 Is Figure 1L A top view of the semiconductor structure of;
[0009] Figures 3A to 3C Is a cross-sectional view of the manufacturing process of a semiconductor structure according to other embodiments of the present invention;
[0010] Figure 4 Upper view of a semiconductor structure Figure 3C for
[0011] Reference numerals in the attached drawings:
[0012] 10, 20: Semiconductor structure
[0013] 100: Substrate
[0014] 102: Device layer
[0015] 104: Termination layer
[0016] 106, 120: Patterened photoresist layer
[0017] 108: Dielectric material layer
[0018] 108a, 116, 122: Dielectric layer
[0019] 110: Barrier material layer
[0020] 110a: Barrier layer
[0021] 112: Substrate via material layer
[0022] 112a: Substrate via
[0023] 114: Protection layer
[0024] 118: Interconnection structure
[0025] 124: Redistribution layer
[0026] 126: Bump
[0027] 200: Filling material layer
[0028] 200a: Filling layer
[0029] AR: Air gap
[0030] OP: Opening
[0031] S1: Front side
[0032] S2: Back side Detailed implementation manners
[0033] Examples are listed below and described in detail in conjunction with the attached drawings. However, the provided examples are not intended to limit the scope covered by the present invention. For ease of understanding, the same components will be denoted by the same reference numerals in the following description. In addition, the attached drawings are for illustrative purposes only and are not drawn to the original scale. In fact, for the sake of clear discussion, the sizes of various features can be arbitrarily increased or decreased.
[0034] Figures 1A to 1L A manufacturing process cross-sectional view of a semiconductor structure according to some embodiments of the present invention. Figure 2 is Figure 1L a top view of the semiconductor structure of Figures 1A to 1L is Figure 2 a cross-sectional view along the I-I' cross-section line in Figure 2 In the top view of Figure 1L some components in Figure 2 are omitted to clearly illustrate the positional relationship between the components in
[0035] Please refer to Figure 1A , a substrate 100 is provided. The substrate 100 includes a front surface S1 and a back surface S2 that face each other. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. Next, a device layer 102 is formed on the front surface S1 of the substrate 100. In some embodiments, the device layer 102 may include components such as a dielectric layer and semiconductor devices (e.g., active devices and / or passive devices) located in the dielectric layer, and their description is omitted here. Then, a termination layer 104 can be formed on the device layer 102. The material of the termination layer 104 may include a nitride (e.g., silicon nitride). The formation method of the termination layer 104 may include chemical vapor deposition. Next, a patterned photoresist layer 106 can be formed on the termination layer 104. The patterned photoresist layer 106 can be formed by a lithography process.
[0036] Please refer to Figure 1B , the patterned photoresist layer 106 can be used as a mask to remove a part of the termination layer 104, a part of the device layer 102, and a part of the substrate 100. Thus, an opening OP can be formed in the termination layer 104, the device layer 102, and the substrate 100. The opening OP can extend from the front surface S1 of the substrate 100 into the substrate 100. The removal method of a part of the termination layer 104, a part of the device layer 102, and a part of the substrate 100 may include dry etching.
[0037] Next, the patterned photoresist layer 106 can be removed. The removal method of the patterned photoresist layer 106 may include dry stripping or wet stripping.
[0038] Please refer to Figure 1C , a dielectric material layer 108 can be formed on the termination layer 104 and in the opening OP. The material of the dielectric material layer 108 may include an oxide (e.g., silicon oxide). The formation method of the dielectric material layer 108 may include atomic layer deposition.
[0039] Then, a barrier material layer 110 can be formed on the dielectric material layer 108. The material of the barrier material layer 110 may include tantalum (Ta), tantalum nitride (TaN), or a combination thereof. The formation method of the barrier material layer 110 may include chemical vapor deposition.
[0040] Then, a substrate via material layer 112 can be formed on the barrier material layer 110. The material of the substrate via material layer 112 can include copper. The method of forming the substrate via material layer 112 can include an electroplating method.
[0041] Please refer to Figure 1D , the substrate via material layer 112, the barrier material layer 110, and the dielectric material layer 108 located outside the opening OP can be removed to form a substrate via 112a, a barrier layer 110a, and a dielectric layer 108a. Thus, a substrate via 112a can be formed in the device layer 102 and the substrate 100, a dielectric layer 108a can be formed between the substrate via 112a and the substrate 100, and a barrier layer 110a can be formed between the substrate via 112a and the dielectric layer 108a. The substrate via 112a extends from the front surface S1 of the substrate 100 into the substrate 100. The method of removing the substrate via material layer 112, the barrier material layer 110, and the dielectric material layer 108 located outside the opening OP can include a chemical mechanical polishing method.
[0042] Please refer to Figure 1E , a protective layer 114 can be formed on the termination layer 104, the substrate via 112a, the barrier layer 110a, and the dielectric layer 108a. The material of the protective layer 114 can include a nitride (e.g., silicon nitride). The method of forming the protective layer 114 can include a chemical vapor deposition method.
[0043] Please refer to Figure 1F , a dielectric layer 116 can be formed on the protective layer 114. In some embodiments, the dielectric layer 116 can be a multi-layer structure. The material of the dielectric layer 116 can include an oxide (e.g., silicon oxide). The method of forming the dielectric layer 116 can include a chemical vapor deposition method.
[0044] Next, an interconnect structure 118 can be formed in the dielectric layer 116. The interconnect structure 118 can electrically connect to the substrate via 112a through the protective layer 114. The interconnect structure 118 can include a wire, a via, or a combination thereof. The material of the interconnect structure 118 can include copper, aluminum, tungsten, or a combination thereof. In addition, the number of layers of the interconnect structure 118 is not limited to the number of layers in the figure. As long as the number of layers of the interconnect structure 118 is at least one layer, it falls within the scope covered by the present invention. The interconnect structure 118 can be formed by an interconnect process.
[0045] Please refer to Figure 1G , a thinning process can be performed on the back surface S2 of the substrate 100. The above-mentioned thinning process can include a chemical mechanical polishing process.
[0046] Please refer to Figure 1H, a patterned photoresist layer 120 can be formed on the back surface S2 of the substrate 100. The patterned photoresist layer 120 can be formed by a photolithography process.
[0047] Please refer to Figure 1I , the patterned photoresist layer 120 can be used as a mask to remove a part of the substrate 100. Thus, a patterning process can be performed on the back surface S2 of the substrate 100 to form an air gap AR. As Figure 2 shown, the air gap AR surrounds the substrate via 112a. The method for removing a part of the substrate 100 can include a dry etching method.
[0048] Next, the patterned photoresist layer 120 can be removed. The method for removing the patterned photoresist layer 120 can include a dry stripping method or a wet stripping method.
[0049] Please refer to Figure 1J , after the air gap AR is formed, a part of the substrate 100, a part of the dielectric layer 108a, and a part of the barrier layer 110a are removed from the back surface S2 of the substrate 100 to expose the substrate via 112a. After the substrate via 112a is exposed, the substrate via 112a can penetrate through the substrate 100. The air gap AR can extend into the device layer 102. The method for removing a part of the substrate 100, a part of the dielectric layer 108a, and a part of the barrier layer 110a can include an etching process, a chemical mechanical polishing process, or a combination thereof on the back surface S2 of the substrate 100. The above etching process can include a dry etching process.
[0050] Please refer to Figure 1K , a dielectric layer 122 can be formed on the back surface S2 of the substrate 100. The dielectric layer 122 can seal one end of the air gap AR. The dielectric layer 122 can be located on the substrate via 112a, the barrier layer 110a, and the dielectric layer 108a. The material of the dielectric layer 122 can include a nitride (e.g., silicon nitride). The method for forming the dielectric layer 122 can include a chemical vapor deposition method.
[0051] Please refer to Figure 1L , a redistribution layer (RDL) 124 is formed on the substrate via 112a. In some embodiments, the redistribution layer 124 can electrically connect to the substrate via 112a through the dielectric layer 122. A part of the redistribution layer 124 can be located on the dielectric layer 122. The material of the redistribution layer 124 can include a conductive material such as copper. Then, a bump 126 can be formed on the redistribution layer 124. The bump 126 can electrically connect to the redistribution layer 124. The material of the bump 126 can include copper, nickel, gold, or a combination thereof.
[0052] Based on the above embodiments, in the manufacturing method of the semiconductor structure 10, a patterning process is performed on the back surface S2 of the substrate 100 to form an air gap AR. The air gap AR surrounds the substrate via 112a. In this way, the substrate via 112a can be prevented from having an adverse effect on semiconductor devices (such as transistor devices) in the semiconductor structure 10 through the air gap AR. For example, the air gap AR can be used to reduce parasitic capacitance and prevent the stress caused by the substrate via 112a from having an adverse effect on the electrical performance of the semiconductor devices.
[0053] Figures 3A to 3C FIG. is a cross-sectional view of the manufacturing process of a semiconductor structure according to some other embodiments of the present invention. Figure 4 is Figure 3C a top view of the semiconductor structure. Figures 3A to 3C is a cross-sectional view along the II-II' section line in Figure 4 . In the top view of Figure 4 , some components in Figure 3C are omitted to clearly illustrate the positional relationship between the components in Figure 4 .
[0054] Please refer to Figure 3A , and provide a structure as shown in Figure 1I . In addition, Figure 1I the structure and its manufacturing method have been described in detail in the above embodiments and will not be described herein again.
[0055] After forming the air gap AR, a filler material layer 200 is formed on the back surface S2 of the substrate 100 and in the air gap AR. The material of the filler material layer 200 may include a dielectric material (such as silicon oxide) or a metal material (such as copper, tungsten). The forming method of the filler material layer 200 may include chemical vapor deposition or physical vapor deposition.
[0056] Please refer to Figure 3B , and remove a part of the filler material layer 200, a part of the substrate 100, a part of the dielectric layer 108a, and a part of the barrier layer 110a from the back surface S2 of the substrate 100 to form a filling layer 200a in the air gap AR and expose the substrate via 112a. As shown in Figure 4 , the filling layer 200a can surround the substrate via 112a. The material of the filling layer 200a may include a dielectric material (such as silicon oxide) or a metal material (such as copper, tungsten). After exposing the substrate via 112a, the substrate via 112a can penetrate the substrate 100. The removal method of a part of the filler material layer 200, a part of the substrate 100, a part of the dielectric layer 108a, and a part of the barrier layer 110a may include an etching process, a chemical mechanical polishing process, or a combination thereof on the back surface S2 of the substrate 100. The above etching process may include a dry etching process.
[0057] Please refer toFigure 3C , can perform steps similar to Figure 1K and Figure 1L to form the dielectric layer 122, the redistribution layer 124, and the bump 126. The dielectric layer 122 can be located on the substrate vias 112a, the barrier layer 110a, the dielectric layer 108a, and the filling layer 200a. For the detailed content of the dielectric layer 122, the redistribution layer 124, and the bump 126, reference can be made to Figure 1K and Figure 1L for the description, and the description thereof is omitted here.
[0058] Based on the above embodiments, it can be seen that in the manufacturing method of the semiconductor structure 20, a patterning process is performed on the back surface S2 of the substrate 100 to form the air gap AR. The air gap AR surrounds the substrate via 112a. In the above embodiments, a filling layer 200a can be formed in the air gap AR, and the filling layer 200a can be used to prevent the substrate via 112a from having an adverse effect on the semiconductor devices (such as transistor devices) in the semiconductor structure 20. For example, when the material of the filling layer 200a is a dielectric material, the filling layer 200a can be used to reduce the parasitic capacitance and prevent the stress caused by the substrate via 112a from having an adverse effect on the electrical performance of the semiconductor devices. In addition, when the material of the filling layer 200a is a metal material, radio frequency interference can be prevented.
[0059] Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the claims.
Claims
1. A method for manufacturing a semiconductor structure, comprising: Providing a substrate, wherein the substrate comprises a front side and a back side opposite to each other; forming a device layer on the front side of the substrate, forming a through-substrate via in the device layer and the substrate, wherein the through-substrate via extends from the front side of the substrate into the substrate; forming a first dielectric layer between the substrate through-hole and the substrate; as well as A patterning process is performed on the back side of the substrate to form an air gap, wherein the air gap is formed around the substrate through hole.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein the method of performing a patterning process on the back side of the substrate comprises: forming a patterned photoresist layer on the back side of the substrate; as well as The patterned photoresist layer is used as a mask to remove a portion of the substrate. The method for manufacturing a semiconductor structure according to claim 1 , wherein the air gap extends into the device layer.
4. The method for manufacturing a semiconductor structure according to claim 1, further comprising: A barrier layer is formed between the through substrate via and the first dielectric layer.
5. The method for manufacturing a semiconductor structure according to claim 4, further comprising: A termination layer is formed on the device layer.
6. The method for manufacturing a semiconductor structure according to claim 5, wherein a method for forming the substrate through hole, the barrier layer and the first dielectric layer comprises: forming an opening in the termination layer, the device layer, and the substrate, wherein the opening extends from the front side of the substrate into the substrate; forming a dielectric material layer on the termination layer and in the opening; forming a barrier material layer on the dielectric material layer; forming a substrate through-hole material layer on the barrier material layer; as well as The through-substrate via material layer, the barrier material layer and the dielectric material layer located outside the opening are removed to form the through-substrate via, the barrier layer and the first dielectric layer.
7. The method for manufacturing a semiconductor structure according to claim 5, further comprising: forming a protective layer on the stop layer, the substrate through-hole, the barrier layer and the first dielectric layer; forming a second dielectric layer on the protective layer; as well as An interconnection line structure is formed in the second dielectric layer, wherein the interconnection line structure passes through the protection layer and is electrically connected to the substrate through hole.
8. The method for manufacturing a semiconductor structure according to claim 1, further comprising: A thinning process is performed on the back side of the substrate.
9. The method for manufacturing a semiconductor structure according to claim 1, further comprising: After forming the air gap, a portion of the substrate and a portion of the first dielectric layer are removed from the back side of the substrate to expose the through-substrate via. 10 . The method for manufacturing a semiconductor structure according to claim 9 , wherein after the through substrate via is exposed, the through substrate via penetrates through the substrate.
11. The method for manufacturing a semiconductor structure according to claim 1, further comprising: A second dielectric layer is formed on the back side of the substrate, wherein the second dielectric layer seals one end of the air gap.
12. The method for manufacturing a semiconductor structure according to claim 11, further comprising: forming a redistribution layer on the substrate through-hole; as well as Bumps are formed on the redistribution layer. 13 . The method for manufacturing a semiconductor structure according to claim 12 , wherein a portion of the redistribution layer is located on the second dielectric layer.
14. The method for manufacturing a semiconductor structure according to claim 1, further comprising: A filling layer is formed in the air gap, wherein the filling layer is perforated around the substrate. 15 . The method for manufacturing a semiconductor structure according to claim 14 , wherein a material of the filling layer comprises a dielectric material or a metal material.
16. The method for manufacturing a semiconductor structure according to claim 1, further comprising: After forming the air gap, forming a filling material layer on the back side of the substrate and in the air gap; as well as A portion of the filling material layer, a portion of the substrate, and a portion of the first dielectric layer are removed from the back side of the substrate to form a filling layer in the air gap and expose the through-substrate hole.