Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming at least two gate structures on one side of the substrate; the at least two gate structures are distributed at intervals along a first direction parallel to the substrate; forming an etching stop layer covering the gate structure and the surface of the substrate; forming an interlayer dielectric layer on one side, deviating from the substrate, of the etching stop layer; at least etching the interlayer dielectric layer and the etching stop layer between any two adjacent gate structures to form a contact hole; forming a liner layer on the side wall of the contact hole; wherein the feature size of the contact hole is larger than the forming thickness of the etching stop layer and smaller than twice of the forming thickness of the etching stop layer. The parasitic capacitance between the adjacent gate structures of the semiconductor structure can be effectively reduced, so that the RC delay problem in an integrated circuit is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As semiconductor devices gradually tend to be miniaturized, the size of basic devices in integrated circuits continues to shrink, and the size and spacing of interconnects in integrated circuits will also shrink accordingly. Among them, since resistance (R) is inversely proportional to the cross-sectional area, the reduction in the size of the interconnect will cause the resistivity of the interconnect to increase; since capacitance (C) is inversely proportional to the spacing, the reduction in the spacing of the interconnect will cause the parasitic capacitance between adjacent interconnects to increase; thus, it is easy for the resistance-capacitance signal delay problem (i.e., RC delay problem) to exist in the integrated circuit, which has an adverse effect on the electrical performance of the semiconductor device.

[0003] Moreover, in the current conventional semiconductor structure, the contact etch stop layer (CESL) will inevitably grow on the sidewalls of the gate structure or the sidewalls of the sidewall structure during the formation process, which will easily cause the parasitic capacitance in the semiconductor structure to increase, thereby making the RC delay problem in the integrated circuit more serious, causing adverse effects on the response speed and signal integrity of the integrated circuit, and reducing the electrical performance of the integrated circuit. Summary of the invention

[0004] Based on this, an embodiment of the present application provides a semiconductor structure and a method for manufacturing the same, which can effectively reduce the parasitic capacitance between adjacent gate structures of the semiconductor structure, thereby improving the RC delay problem in the integrated circuit.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a method for manufacturing a semiconductor structure. The method for manufacturing the semiconductor structure includes: providing a substrate; forming at least two gate structures on one side of the substrate; at least two gate structures are spaced apart along a first direction parallel to the substrate; forming an etch stop layer covering the gate structure and the surface of the substrate; forming an interlayer dielectric layer on the side of the etch stop layer away from the substrate; etching at least the interlayer dielectric layer and the etch stop layer between any two adjacent gate structures to form a contact hole; forming a liner layer on the sidewall of the contact hole; wherein the characteristic size of the contact hole is greater than the formation thickness of the etch stop layer and less than twice the formation thickness of the etch stop layer.

[0006] In some embodiments, after forming at least two gate structures on one side of the substrate and before forming an etch stop layer covering the gate structures and the surface of the substrate, the method for manufacturing the semiconductor structure further includes: forming sidewall structures on both sides of each of the gate structures in the first direction; the sidewall structures are at least located on both sidewalls of each of the gate structures in the first direction; wherein, the etch stop layer covers the sidewall structures; there is no contact between the liner layer and the sidewall structures.

[0007] In some embodiments, forming the liner layer on the sidewall of the contact hole includes: forming a liner material layer covering the bottom and sidewalls of the contact hole and the surface of the interlayer dielectric layer; etching back the liner material layer to remove the liner material layer on the bottom of the contact hole and the surface of the interlayer dielectric layer, and the liner material layer remaining on the sidewalls of the contact hole correspondingly constitutes the liner layer.

[0008] In some embodiments, the dielectric constant of the liner layer is less than or equal to 6.

[0009] In some embodiments, after forming the liner layer on the sidewall of the contact hole, the method for manufacturing the semiconductor structure further includes: forming a conductive plug covering the liner layer and filling the contact hole.

[0010] On the other hand, according to some embodiments, the present application further provides a semiconductor structure; the semiconductor structure can be prepared by the method for manufacturing the semiconductor structure in the above-mentioned some embodiments.

[0011] In some embodiments, the semiconductor structure includes a substrate, at least two gate structures, an etch stop layer, an interlayer dielectric layer, a contact hole, and a liner layer. The at least two gate structures are spaced apart along a first direction parallel to the substrate; the etch stop layer covers the gate structures and at least a part of the surface of the substrate; the interlayer dielectric layer is located on a side of the etch stop layer away from the substrate; the contact hole is located in the interlayer dielectric layer and the etch stop layer between any two adjacent gate structures and extends along a second direction perpendicular to the substrate; the second direction intersects the first direction; the liner layer is located on the sidewall of the contact hole; wherein, the feature size of the contact hole is greater than the formation thickness of the etch stop layer and less than twice the formation thickness of the etch stop layer.

[0012] In some embodiments, the semiconductor structure further includes sidewall structures; the sidewall structures are at least located on both sidewalls of each of the gate structures in the first direction; wherein, the etch stop layer further covers the sidewall structures; there is no contact between the liner layer and the sidewall structures.

[0013] In some embodiments, the material of the liner layer includes silicon monoxide, silicon dioxide, or silicon oxycarbide.

[0014] In some embodiments, the semiconductor structure further includes a conductive plug; the conductive plug covers the liner layer and fills the contact hole.

[0015] In some embodiments, the semiconductor structure further includes a metal contact layer; the metal contact layer covers the surface of the substrate that is not covered by the gate structure and the sidewall structure; wherein, the etch stop layer further covers the metal contact layer; the surface of the liner layer close to the substrate is in contact with the surface of the metal contact layer facing away from the substrate.

[0016] The embodiments of the present application may / at least have the following advantages:

[0017] In the embodiments of the present application, by making the feature size of the contact hole between two adjacent gate structures greater than the formation thickness of the etch stop layer and less than twice the formation thickness of the etch stop layer, the contact hole penetrates through part of the etch stop layer and there is no contact with the gate structure; in addition, a liner layer is formed on the sidewall of the contact hole, realizing the isolation between the internal space of the contact hole and the gate structure and the etch stop layer, so that there is no contact between the filling material inside the contact hole and the gate structure and the etch stop layer in the subsequent process. In this way, the isolation between the gate structure and the internal space of the contact hole is realized through the liner layer, effectively reducing the parasitic capacitance between adjacent gate structures of the semiconductor structure, thereby effectively improving the resistance-capacitance signal delay problem (i.e., the RC delay problem) in the integrated circuit, and further improving the response speed and signal integrity of the integrated circuit, and improving the electrical performance of the integrated circuit.

[0018] Details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor structure provided in some embodiments;

[0021] Figure 2 It is a schematic flow chart of another method for manufacturing a semiconductor structure provided in some embodiments;

[0022] Figure 3 Schematic flow diagram of a manufacturing method of another semiconductor structure provided in some embodiments;

[0023] Figure 4 Schematic flow diagram of a manufacturing method of another semiconductor structure provided in some embodiments;

[0024] Figure 5 Schematic flow diagram of a manufacturing method of another semiconductor structure provided in some embodiments;

[0025] Figure 6 Schematic diagram of the structure obtained after forming a gate structure in some embodiments;

[0026] Figure 7 Schematic diagram of the structure obtained after forming a sidewall structure in some embodiments;

[0027] Figure 8 Schematic diagram of the structure obtained after forming an etch stop layer in some embodiments;

[0028] Figure 9 Schematic diagram of the structure obtained after forming an interlayer dielectric layer in some embodiments;

[0029] Figure 10 Schematic diagram of the structure obtained after forming a contact hole in some embodiments;

[0030] Figure 11 Schematic diagram of the structure obtained after forming a liner material layer in some embodiments;

[0031] Figure 12 Schematic diagram of the structure obtained after forming a liner layer in some embodiments;

[0032] Figure 13 Schematic diagram of a semiconductor structure provided in some embodiments.

[0033] Description of reference numerals:

[0034] 1 - Substrate, 2 - Gate structure, 3 - Insulating layer, 4 - Metal contact layer, 5 - Sidewall structure, 6 - Etch stop layer, 7 - Interlayer dielectric layer, C - Contact hole, 8 - Liner layer, 81 - Liner material layer, 9 - Conductive plug, 91 - Seed layer, 92 - Conductive material layer. Detailed implementation manners

[0035] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of the present application herein are for the purpose of describing specific embodiments only and are not intended to limit the present application.

[0037] It should be understood that when an element or layer is referred to as "on", "adjacent to", or "connected to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or part discussed below can be referred to as the second element, component, region, layer, or part.

[0038] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups may not be excluded. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0039] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, and such variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.

[0040] Based on this, an embodiment of the present application provides a semiconductor structure and a method for manufacturing the same, which can effectively reduce the parasitic capacitance between adjacent gate structures of the semiconductor structure, thereby improving the RC delay problem in the integrated circuit.

[0041] In some embodiments, see Figure 1 , the manufacturing method of the semiconductor structure includes the following steps S100~S600.

[0042] S100 , providing a substrate.

[0043] S200, forming at least two gate structures on one side of a substrate; the at least two gate structures are spaced apart and distributed along a first direction parallel to the substrate.

[0044] S300, forming an etching stop layer covering the gate structure and the surface of the substrate.

[0045] S400, forming an interlayer dielectric layer on a side of the etch stop layer facing away from the substrate.

[0046] S500, etching at least the interlayer dielectric layer and the etch stop layer between any two adjacent gate structures to form a contact hole; wherein the characteristic size of the contact hole is greater than the formed thickness of the etch stop layer and less than twice the formed thickness of the etch stop layer.

[0047] S600 , forming a liner layer on the sidewall of the contact hole.

[0048] In the embodiment of the present application, by making the characteristic size of the contact hole between two adjacent gate structures larger than the formation thickness of the etch stop layer and smaller than twice the formation thickness of the etch stop layer, the contact hole penetrates part of the etch stop layer and has no contact with the gate structure; in addition, a liner layer is formed on the sidewall of the contact hole to achieve isolation between the internal space of the contact hole and the gate structure and the etch stop layer, so that there is no contact between the filling material inside the contact hole and the gate structure and the etch stop layer in the subsequent process. In this way, the isolation of the gate structure and the internal space of the contact hole is achieved through the liner layer, which effectively reduces the parasitic capacitance between the adjacent gate structures of the semiconductor structure, thereby effectively improving the resistance-capacitance signal delay problem (i.e., RC delay problem) in the integrated circuit, thereby improving the response speed and signal integrity of the integrated circuit, and improving the electrical performance of the integrated circuit.

[0049] In some embodiments, see Figure 2 , after step S200 and before step S300, the method for manufacturing the semiconductor structure further includes the following step S210.

[0050] S210 , forming sidewall structures on both sides of each gate structure in the first direction; the sidewall structures are at least located on both side walls of each gate structure in the first direction.

[0051] Accordingly, the etch stop layer formed in step S300 covers the sidewall structure; there is no contact between the liner layer formed in step S600 and the sidewall structure.

[0052] In some embodiments, after step S200 and before step S210, the method for manufacturing a semiconductor structure further includes the following step S220.

[0053] S220, forming a metal contact layer on the surface of the substrate not covered by the gate structure and on the surface of the gate structure facing away from the substrate.

[0054] In some embodiments, referring to Figure 3 , step S600 includes the following steps S610 to S620.

[0055] S610, forming a liner material layer covering the bottom and sidewalls of the contact hole and the surface of the interlayer dielectric layer.

[0056] S620, etching back the liner material layer to remove the liner material layer on the bottom of the contact hole and the surface of the interlayer dielectric layer, and making the liner material layer remaining on the sidewalls of the contact hole correspondingly form a liner layer.

[0057] In some embodiments, the dielectric constant of the liner layer is less than or equal to 6.

[0058] In the embodiments of the present application, a low dielectric constant material (low-K material) is used to form the liner layer. Since the parasitic capacitance is positively correlated with the dielectric constant (K value) of the material; therefore, the liner layer in the embodiments of the present application can effectively reduce the parasitic capacitance between adjacent gate structures and conductive plugs in the semiconductor structure.

[0059] In some embodiments, referring to Figure 4 , after step S600, the method for manufacturing a semiconductor structure further includes the following step S700.

[0060] S700, forming a conductive plug covering the liner layer and filling the contact hole.

[0061] In some embodiments, the conductive plug includes a conductive material layer and a seed layer stacked in sequence from the inside to the outside; referring to Figure 5 , step S700 includes the following steps S710 to S720.

[0062] S710, forming a seed layer covering the liner layer and the bottom of the contact hole.

[0063] S720, forming a conductive material layer covering the seed layer and filling the contact hole.

[0064] In the embodiments of the present application, the liner layer realizes isolation between the gate structure, the sidewall structure, and the conductive plug, effectively reducing the parasitic capacitance between adjacent gate structures and conductive plugs in the semiconductor structure, thereby effectively improving the resistance-capacitance signal delay problem (i.e., the RC delay problem) in the integrated circuit, and further improving the response speed and signal integrity of the integrated circuit, and improving the electrical performance of the integrated circuit.

[0065] It should be understood that although Figures 1 to 5 the steps in the flowchart are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figures 1 to 5 at least a part of the steps in

[0066] may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of the steps or stages in other steps or other steps. Figures 6 to 13 To more clearly illustrate the manufacturing method of the semiconductor structure in some of the above embodiments, the following some embodiments are to be understood in conjunction with

[0067] In some embodiments, the manufacturing method of the semiconductor structure includes the following steps S100 to S600.

[0068] In step S100, a substrate 1 is provided.

[0069] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. Therefore, the type of the substrate 1 should not limit the protection scope of the present application.

[0070] In step S200, please refer to Figure 6 , at least two gate structures 2 are formed on one side of the substrate 1; the at least two gate structures 2 are spaced apart along a first direction (for example, the X direction) parallel to the substrate 1.

[0071] Exemplarily, the material of the gate structure 2 includes, but is not limited to, polysilicon (Poly).

[0072] In some examples, continue to refer to Figure 6 , both sidewalls of each gate structure 2 in the first direction parallel to the substrate 1 (for example, the X direction) have an insulating layer 3.

[0073] Exemplarily, the material of the insulating layer 3 includes, but is not limited to, oxides of silicon or nitrides of silicon, etc.

[0074] In some embodiments, after step S200 and before step S210, the manufacturing method of the semiconductor structure further includes the following step S220.

[0075] In step S220, continue to refer to Figure 6 , a metal contact layer 4 is formed on the surface of the substrate 1 not covered by the gate structure 2 and on the surface of the gate structure 2 facing away from the substrate 1.

[0076] In some examples, the metal contact layer 4 includes a source contact layer, a drain contact layer, and a gate contact layer; wherein, the source contact layer is located on the surface of the source region facing away from the substrate 1, the drain contact layer is located on the surface of the drain region facing away from the substrate 1, and the gate contact layer is located on the surface of the gate structure 2 facing away from the substrate 1.

[0077] Exemplarily, the material of the metal contact layer 4 includes, but is not limited to, metal silicides; the material of the metal contact layer 4 can be, for example, nickel silicide (NiSi), cobalt silicide (CoSi2), or titanium silicide (TiSi2), etc.

[0078] It should be noted that the function of the metal contact layer 4 is to reduce the contact resistance between the gate structure 2 and / or the active region and the conductive plug 9, thereby improving the electrical performance of the semiconductor structure.

[0079] In some embodiments, after step S200 and before step S300, the manufacturing method of the semiconductor structure further includes the following step S210.

[0080] In step S210, refer to Figure 7 , sidewall structures 5 are formed on both sides of each gate structure 2 in the first direction; the sidewall structures 5 are at least located on both sidewalls of each gate structure 2 in the first direction (for example, the X direction).

[0081] Exemplarily, the material of the sidewall structure 5 includes, but is not limited to, insulating materials; the material of the sidewall structure 5 can be, for example, oxides.

[0082] In step S300, refer to Figure 8 , an etch stop layer 6 covering the surface of the gate structure 2 and the substrate 1 is formed.

[0083] In some examples, the etch stop layer 6 formed in step S300 also covers the sidewall structure 5.

[0084] In some embodiments, the etch stop layer 6 may be a contact etch stop layer (CESL for short).

[0085] In some embodiments, the dielectric constant of the etch stop layer 6 is less than or equal to 6.

[0086] Exemplarily, the value of the dielectric constant (K value) of the etch stop layer 6 may be, for example, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6, etc.

[0087] Exemplarily, the material of the etch stop layer 6 includes, but is not limited to, silicon monoxide (SiO), silicon dioxide (SiO2), or silicon carbon oxide (SiCO), etc.

[0088] In step S400, please refer to Figure 9 , an interlayer dielectric layer 7 is formed on the side of the etch stop layer 6 away from the substrate 1.

[0089] Exemplarily, the material of the interlayer dielectric layer 7 includes, but is not limited to, insulating materials, and the material of the interlayer dielectric layer 7 may be, for example, an oxide.

[0090] In step S500, please refer to Figure 10 , at least the interlayer dielectric layer 7 and the etch stop layer 6 between any two adjacent gate structures 2 are etched to form a contact hole C; wherein, the characteristic dimension of the contact hole C is greater than the formation thickness of the etch stop layer 6 and less than twice the formation thickness of the etch stop layer 6.

[0091] Exemplarily, the etching process of the interlayer dielectric layer 7 and the etch stop layer 6 includes, but is not limited to, a dry etch process; the etching process of the interlayer dielectric layer 7 and the etch stop layer 6 may be, for example, a photolithography process, etc.

[0092] It should be noted that, please continue to refer to Figure 10 , the bottom of the contact hole C exposes a partial surface of the metal contact layer 4 between any two adjacent gate structures 2 away from the substrate 1.

[0093] It should be noted that the characteristic dimension of the contact hole C refers to: the dimension of the contact hole C in the first direction parallel to the substrate 1 (for example, the X direction). The formation thickness of the etch stop layer 6 refers to: the dimension of the etch stop layer 6 in the direction perpendicular to the sidewall structure 5.

[0094] Exemplarily, the characteristic dimension of the contact hole C is greater than the maximum value of the formation thickness of the etch stop layer 6 and less than twice the maximum value of the formation thickness of the etch stop layer 6.

[0095] In step S600, refer to Figure 12 , and a liner layer 8 is formed on the sidewall of the contact hole C.

[0096] In some embodiments, the dielectric constant (K value) of the liner layer 8 is less than or equal to 6.

[0097] Exemplarily, the value of the dielectric constant (K value) of the liner layer 8 can be, for example, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6, etc.

[0098] In some embodiments, the material of the liner layer 8 includes but is not limited to silicon monoxide (SiO), silicon dioxide (SiO2), or silicon carbon oxide (SiCO), etc.

[0099] There is no contact between the liner layer 8 formed in step S600 and the sidewall structure 5.

[0100] In some embodiments, step S600 includes the following steps S610 to S620.

[0101] In step S610, refer to Figure 11 , and a liner material layer 81 is formed to cover the bottom and sidewall of the contact hole C and the surface of the interlayer dielectric layer 7.

[0102] Exemplarily, the formation process of the liner material layer 81 includes but is not limited to the atomic layer deposition (ALD) process.

[0103] Exemplarily, the dielectric constant (K value) of the liner material layer 81 is less than or equal to 6. The value of the dielectric constant (K value) of the liner material layer 81 can be, for example, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6, etc.

[0104] Exemplarily, the material of the liner material layer 81 includes but is not limited to silicon monoxide (SiO), silicon dioxide (SiO2), or silicon carbon oxide (SiCO), etc.

[0105] In step S620, refer to Figure 12 , the liner material layer 81 is etched back to remove the liner material layer 81 on the bottom of the contact hole C and the surface of the interlayer dielectric layer 7, and the liner material layer 81 remaining on the sidewall of the contact hole C correspondingly constitutes the liner layer 8.

[0106] For example, the etching process used to etch back the liner material layer 81 includes, but is not limited to, a dry etching process; the etching process used to etch back the liner material layer 81 may be, for example, a photolithography process.

[0107] In some embodiments, after step S600 , the method for manufacturing a semiconductor structure further includes the following step S700 .

[0108] In step S700, refer to Figure 13 , a conductive plug 9 covering the liner layer 8 and filling the contact hole C is formed.

[0109] It should be noted that the bottom of the conductive plug 9 forms an ohmic contact with the surface of the metal contact layer 4 between any two adjacent gate structures 2 that faces away from the substrate 1 .

[0110] In some embodiments, the conductive plug 9 includes a conductive material layer 92 and a seed layer 91 stacked in sequence from inside to outside; step S700 includes the following steps S710 - S720 .

[0111] In step S710, please continue to refer to Figure 13 , a seed layer 91 (Seed Layer) covering the liner layer 8 and the bottom of the contact hole C is formed.

[0112] For example, the material of the seed layer 91 (Seed Layer) includes but is not limited to a conductive material; the material of the seed layer 91 may be, for example, a conductive metal.

[0113] By way of example, the material of the seed layer 91 may be copper (Cu).

[0114] For example, the formation process of the seed layer 91 includes, but is not limited to, an electrochemical copper plating (Electroplating) process, an atomic layer deposition (Atomic Layer Deposition, ALD for short) process, or a physical vapor deposition (Physical Vapor Deposition, PVD for short) process.

[0115] In step S720, please continue to refer to Figure 13 , a conductive material layer 92 covering the seed layer 91 and filling the contact hole C is formed.

[0116] By way of example, the material of the conductive material layer 92 includes, but is not limited to, a conductive material; the material of the conductive material layer 92 may be, for example, a conductive metal.

[0117] By way of example, the material of the conductive material layer 92 may be copper (Cu).

[0118] For example, the formation process of the conductive material layer 92 includes, but is not limited to, an electrochemical copper plating (Electroplating) process, a physical vapor deposition (Physical Vapor Deposition, PVD for short) process, or a chemical vapor deposition (Chemical Vapor Deposition, CVD for short) process.

[0119] The present application also provides a semiconductor structure according to some embodiments; the semiconductor structure can be prepared by the manufacturing method of the semiconductor structure in some of the above embodiments. The semiconductor structure also has the technical advantages of the manufacturing method of the above semiconductor structure. It should be noted that the parts that are the same or corresponding to the above embodiments can refer to the corresponding description of the above embodiments, and will not be described in detail below.

[0120] In some embodiments, see Figure 13 The semiconductor structure includes a substrate 1, at least two gate structures 2, an etch stop layer 6, an interlayer dielectric layer 7, a contact hole C and a liner layer 8. At least two gate structures 2 are spaced apart along a first direction parallel to the substrate 1; the etch stop layer 6 covers the gate structure 2 and at least a portion of the surface of the substrate 1; the interlayer dielectric layer 7 is located on the side of the etch stop layer 6 away from the substrate 1; the contact hole C is located in the interlayer dielectric layer 7 and the etch stop layer 6 between any two adjacent gate structures 2, and extends along a second direction perpendicular to the substrate 1; the second direction intersects with the first direction; the liner layer 8 is located on the sidewall of the contact hole C; wherein the characteristic size of the contact hole C is greater than the formed thickness of the etch stop layer 6 and less than twice the formed thickness of the etch stop layer 6.

[0121] For example, the substrate 1 can be made of semiconductor material, insulating material, conductor material or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 1 should not limit the scope of protection of the present application.

[0122] In some embodiments, the etch stop layer 6 may be a contact etch stop layer (Contact Etch Stop Layer, CESL for short).

[0123] In some embodiments, the dielectric constant of the etch stop layer 6 is less than or equal to 6.

[0124] Exemplarily, the value of the dielectric constant (K value) of the etch stop layer 6 can be, for example, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6, etc.

[0125] Exemplarily, the material of the etch stop layer 6 includes but is not limited to silicon monoxide (SiO), silicon dioxide (SiO2), or silicon carbon oxide (SiCO), etc.

[0126] In some embodiments, the dielectric constant (K value) of the liner layer 8 is less than or equal to 6.

[0127] Exemplarily, the value of the dielectric constant (K value) of the liner layer 8 can be, for example, 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6, etc.

[0128] In some embodiments, the material of the liner layer 8 includes but is not limited to silicon monoxide (SiO), silicon dioxide (SiO2), or silicon carbon oxide (SiCO), etc.

[0129] In some embodiments, there is no contact between the liner layer 8 and the spacer structure 5.

[0130] In the embodiments of the present application, by making the feature size of the contact hole C between two adjacent gate structures 2 greater than the formation thickness of the etch stop layer 6 and less than twice the formation thickness of the etch stop layer 6, the contact hole C penetrates through part of the etch stop layer 6 and has no contact with the gate structure 2; in addition, a liner layer 8 is formed on the sidewall of the contact hole C, realizing the isolation between the internal space of the contact hole C and the gate structure 2 and the etch stop layer 6, so that there is no contact between the filling material inside the contact hole C and the gate structure 2 and the etch stop layer 6 in subsequent processes. Thus, the isolation between the gate structure 2 and the internal space of the contact hole C is realized through the liner layer 8, effectively reducing the parasitic capacitance between adjacent gate structures 2 of the semiconductor structure, thereby effectively improving the resistance-capacitance signal delay problem (i.e., the RC delay problem) in the integrated circuit, and further improving the response speed and signal integrity of the integrated circuit, and improving the electrical performance of the integrated circuit.

[0131] In some embodiments, please continue to refer to Figure 13 , the semiconductor structure further includes a spacer structure 5; the spacer structure 5 is at least located on both sidewalls of each gate structure 2 in the first direction; wherein, the etch stop layer 6 further covers the spacer structure 5; there is no contact between the liner layer 8 and the spacer structure 5.

[0132] In some embodiments, the material of the liner layer 8 includes silicon monoxide (SiO), silicon dioxide (SiO2), or silicon carbon oxide (SiCO).

[0133] In some embodiments, please continue to refer to Figure 13 , the semiconductor structure further includes a conductive plug 9; the conductive plug 9 covers the liner layer 8 and fills the contact hole C.

[0134] In some examples, please continue to refer to Figure 13 , the conductive plug 9 includes a conductive material layer 92 and a seed layer 91 stacked in sequence from the inside to the outside.

[0135] In some embodiments, please continue to refer to Figure 13 , the semiconductor structure further includes a metal contact layer 4; the metal contact layer 4 covers the surface of the substrate 1 that is not covered by the gate structure 2 and the sidewall structure 5; wherein, the etch stop layer 6 also covers the metal contact layer 4; the surface of the liner layer 8 close to the substrate 1 is in contact with the surface of the metal contact layer 4 facing away from the substrate 1.

[0136] It should be noted that an ohmic contact is formed between the bottom of the conductive plug 9 and the surface of the metal contact layer 4 facing away from the substrate 1 between any two adjacent gate structures 2.

[0137] In the description of this specification, the descriptions referring to terms such as "some embodiments", "some examples", "exemplarily", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0138] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0139] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming at least two gate structures on one side of the substrate; At least two of the gate structures are spaced apart and distributed along a first direction parallel to the substrate; forming an etch stop layer covering the gate structure and the surface of the substrate; forming an interlayer dielectric layer on a side of the etch stop layer facing away from the substrate; At least etching the interlayer dielectric layer and the etching stop layer between any two adjacent gate structures to form a contact hole; forming a liner layer on the sidewall of the contact hole; The characteristic size of the contact hole is larger than the formed thickness of the etch stop layer and smaller than twice the formed thickness of the etch stop layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: After forming at least two gate structures on one side of the substrate and before forming an etch stop layer covering the gate structures and the surface of the substrate, the method for manufacturing the semiconductor structure further includes: A sidewall structure is formed on both sides of each gate structure in the first direction; the sidewall structure is at least located on two side walls of each gate structure in the first direction; Wherein, the etching stop layer covers the sidewall structure; and there is no contact between the liner layer and the sidewall structure.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of forming a liner layer on the sidewall of the contact hole comprises: forming a liner material layer covering the bottom and sidewalls of the contact hole and the surface of the interlayer dielectric layer; The liner material layer is etched back to remove the liner material layer at the bottom of the contact hole and the surface of the interlayer dielectric layer, and the liner material layer retained on the sidewall of the contact hole corresponds to the liner layer.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The dielectric constant of the liner layer is less than or equal to 6.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: After forming a liner layer on the sidewall of the contact hole, the method for manufacturing the semiconductor structure further includes: A conductive plug is formed covering the liner layer and filling the contact hole.

6. A semiconductor structure, characterized in that: include: substrate; At least two gate structures are spaced apart and distributed along a first direction parallel to the substrate; An etch stop layer, covering the gate structure and at least a portion of the surface of the substrate; an interlayer dielectric layer, located on a side of the etch stop layer away from the substrate; A contact hole, located in the interlayer dielectric layer and the etch stop layer between any two adjacent gate structures, and extending along a second direction perpendicular to the substrate; The second direction intersects the first direction; A liner layer, located on the sidewall of the contact hole; The characteristic size of the contact hole is larger than the formed thickness of the etch stop layer and smaller than twice the formed thickness of the etch stop layer.

7. The semiconductor structure according to claim 6, characterized in that: Also includes: A sidewall structure, at least located on two side walls of each of the gate structures in the first direction; Wherein, the etching stop layer also covers the sidewall structure; There is no contact between the liner layer and the sidewall structure.

8. The semiconductor structure according to claim 6, characterized in that: The material of the liner layer includes silicon monoxide, silicon dioxide or silicon oxycarbide.

9. The semiconductor structure according to claim 6, characterized in that: Also includes: A conductive plug covers the liner layer and fills the contact hole.

10. The semiconductor structure according to claim 7, characterized in that: Also includes: A metal contact layer, covering a surface of the substrate that is not covered by the gate structure and the spacer structure; Wherein, the etching stop layer also covers the metal contact layer; A surface of the liner layer close to the substrate contacts a surface of the metal contact layer facing away from the substrate.

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