Manufacturing method of semiconductor device

Abstract

The embodiment of the invention discloses a manufacturing method of a semiconductor device, which is characterized in that a first semiconductor structure is formed, and the forming method of the first semiconductor structure comprises the following steps: providing a first semiconductor layer, and forming a sacrificial structure penetrating through the semiconductor layer along a first direction; the sacrificial structures comprise a plurality of first sacrificial structures extending in the second direction and a plurality of second sacrificial structures extending in the third direction; the second direction intersects with the third direction, and a plane formed by the second direction and the third direction intersects with the first direction; at least forming device structures on the first semiconductor layer exposed between the first sacrificial structure and the second sacrificial structure, wherein the adjacent device structures are arranged at intervals; the manufacturing method comprises the following steps: removing a sacrificial structure to form a first groove, and separating a first semiconductor structure into a plurality of tube cores by at least utilizing the first groove; the die includes at least a device structure and a portion of the first semiconductor layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device. Background Art

[0002] Wafer dicing plays a crucial role in the semiconductor manufacturing process. A whole wafer is diced to separate multiple chips with independent electrical functions. After subsequent packaging, they are applied to various integrated circuits. The wafer dicing process can improve the utilization rate of the wafer and reduce the unit cost of each chip. It can also define the size and shape of the chips, and thus can affect the quality and performance of the product to a certain extent. In addition, advanced wafer dicing technology makes it possible to produce chips with smaller sizes and higher integration degrees, meeting the market's demand for diversified chips. By optimizing the dicing process and enhancing the equipment automation, wafer dicing can also significantly improve the production efficiency, reduce material losses, and ultimately increase the utilization rate of the wafer. The accuracy and consistency of wafer dicing are crucial for ensuring the yield and reliability of the chips.

[0003] In some wafer dicing processes, such as dicing processes using diamond blades, diamond-coated blades or scribing, the cost is relatively low, but they may generate frictional heat, debris and cracks, posing a risk of damaging the wafer; and the dicing lanes are wide. Some processes such as laser dicing, plasma dicing, laser stealth dicing, etc. produce narrow cuts, which can reduce silicon debris and cracks, reduce peeling and cracking phenomena, and are beneficial to improving the dicing yield; but they may not be suitable for cutting relatively thick wafers or wafers with a stacked structure of multiple wafers. In view of this, there is still some room for improvement in the wafer dicing process in terms of adapting to the cutting of larger thickness structures, reducing losses and narrowing the dicing lanes. Summary of the Invention

[0004] According to some aspects of the embodiments of the present disclosure, there is provided a method for manufacturing a semiconductor device, including forming a first semiconductor structure. The forming method of the first semiconductor structure includes: providing a first semiconductor layer, and forming a sacrificial structure that penetrates the first semiconductor layer along a first direction; the sacrificial structure includes a plurality of first sacrificial structures extending along a second direction and a plurality of second sacrificial structures extending along a third direction; the second direction intersects with the third direction, and the plane formed by the second direction and the third direction intersects with the first direction; forming device structures on at least the first semiconductor layer exposed between the first sacrificial structure and the second sacrificial structure, and adjacent device structures are spaced apart; the manufacturing method further includes: removing the sacrificial structure to form a first trench, and separating the first semiconductor structure into a plurality of die at least by using the first trench; the die includes at least the device structure and a part of the first semiconductor layer.

[0005] According to some aspects of embodiments of the present disclosure, a method for fabricating a semiconductor structure is provided, including: providing a first semiconductor structure, the first semiconductor structure including: a first semiconductor layer and a sacrificial structure penetrating the first semiconductor layer along a first direction, the sacrificial structure including a plurality of first sacrificial structures extending along a second direction and a plurality of second sacrificial structures extending along a third direction; the sacrificial structure being located at the edge of the device structure of the first semiconductor structure; the second direction intersecting the third direction, and the plane formed by the second direction and the third direction intersecting the first direction; bonding a second semiconductor structure to the side of the first semiconductor structure having the device structure; the second semiconductor structure including a second semiconductor layer and including a third sacrificial structure and a fourth sacrificial structure penetrating the second semiconductor layer along the first direction, the third sacrificial structure extending along the second direction and being aligned with the first sacrificial structure in the first direction; the fourth sacrificial structure extending along the third direction and being aligned with the second sacrificial structure in the first direction; the third sacrificial structure and the fourth sacrificial structure being located at the edge of the device structure of the second semiconductor structure; removing the first sacrificial structure and the second sacrificial structure to form a first trench in the first semiconductor structure; removing the third sacrificial structure and the fourth sacrificial structure to form a second trench in the second semiconductor structure; breaking at least along the first trench and the second trench the bonded structure formed by the first semiconductor structure and the second semiconductor structure to form die; the die including a part of the first semiconductor structure and a part of the second semiconductor structure.

[0006] Embodiments of the present disclosure provide a method for fabricating a semiconductor device, forming a first semiconductor structure, including providing a first semiconductor layer, forming a sacrificial structure penetrating the first semiconductor layer along a first direction, the sacrificial structure including a plurality of first sacrificial structures extending along a second direction and a plurality of second sacrificial structures extending along a third direction, the first sacrificial structures intersecting the second sacrificial structures; forming device structures at least on the first semiconductor layer exposed between the first sacrificial structures and the second sacrificial structures, with adjacent device structures spaced apart; removing the sacrificial structure to form a first trench, and separating the first semiconductor structure into a plurality of die at least by using the first trench, the die at least including the device structures and the first semiconductor layer; the sacrificial structure being located at the edge of the device structure and can be removed by an etching process instead of a cutting process, thereby reducing the damage to the device caused by the cutting process and avoiding the limitation of the cutting process by the device thickness, and being adaptable to the cutting of large-thickness devices and die separation; and the sacrificial structure can have a relatively small width dimension, which is beneficial to reducing the width of the cutting channel or notch, reducing the occupation of the device area, and being beneficial to improving the device integration. Description of the Drawings

[0007] Figure 1 and Figure 2 is a schematic diagram of a semiconductor structure shown according to an embodiment of the present disclosure;

[0008] Figure 3 is a schematic flow chart of a method for fabricating a semiconductor device shown according to an embodiment of the present disclosure;

[0009] Figures 4 to 25 is a schematic diagram of a method for fabricating a semiconductor device shown according to an embodiment of the present disclosure;

[0010] Figure 26 is another schematic flow chart of a method for fabricating a semiconductor device shown according to an embodiment of the present disclosure. Detailed implementation manners

[0011] Hereinafter, the exemplary embodiments disclosed in the present disclosure will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0012] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device during use and operation. For example, if the device in the figure is flipped, then the element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, the exemplary terms "under" and "below" can include both the upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptive terms used herein are correspondingly interpreted.

[0013] It should be understood that "some embodiments" or "an embodiment" mentioned throughout the specification means that a particular feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of "in some embodiments" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the magnitude of the serial numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure.

[0014] Embodiments of the present disclosure provide an exemplary semiconductor structure, which may be a semiconductor wafer or a semiconductor panel. For example, the first semiconductor structure 100 or the wafer may include a plurality of device structures 101, and at least a part of the device structures 101 is located on the front side of the wafer, or may be located on the back side of the wafer, or may be located within the wafer. Exemplary device structures 101 may include, but are not limited to: capacitors, inductors, resistors, memory structures, CMOS transistors, diodes, conductive interconnect layers, conductive contact structures, and conductive connection structures, etc. The device structures 101 may be various integrated circuits with electrical functions composed of a variety of semiconductor elements or metal structures. For example, taking a transistor as an example, the gate of the transistor may be located on the front side of the wafer or on the semiconductor layer on the front side of the wafer, and the source and drain of the transistor may be located within the wafer, formed by ion implantation of the wafer substrate. Some redistribution layers, backside lead structures, contacts, or pads, etc. may be located on the back side of the wafer and are electrically interconnected with the front side of the wafer through vertical connection structures such as through-silicon vias (TSVs). The device structures 101 may include integrated circuits with independent electrical functions and capable of independent operation. The wafer is cut and separated into multiple parts, and each part may include the device structures 101 and a part of the substrate as a die (such as the exemplary die 141 described later) or a chip, and then the die is packaged and applied in an integrated circuit. Before cutting, the back side of the wafer may be thinned to reduce the die thickness and facilitate cutting. Figure 13 In some embodiments,

[0015] An exemplary semiconductor structure or a schematic diagram of a wafer layout is provided, including a plurality of device structures 101 or dies to be cut, including the substrate provided by the bare wafer and the device structures 101 located on the substrate. The first direction mentioned in the embodiments of the present disclosure may be the z direction shown in the drawing examples, which may be the thickness direction or the vertical direction; the second direction may be the x direction, and the third direction may be the y direction. The x and y directions are horizontal directions, and the x and y directions may intersect or be perpendicular; the xoy plane may intersect or be perpendicular to the z direction, which will not be elaborated later. Figure 1

[0016] ​A sacrificial structure can be disposed between device structures 101. The cross-section of the sacrificial structure in the xoy plane is shown as a strip, extending along the x and y directions, and located at the edge of the device structure 101 or the die to be cut, such as the first sacrificial structure 121 and the second sacrificial structure 122. The sacrificial structure can extend at least in the substrate under the device structure 101. The material of the sacrificial structure has a large etching selectivity difference from the metal material and dielectric material in the device structure 101. For example, the sacrificial structure can include silicon, such as polysilicon, single-crystalline silicon or amorphous silicon. The sacrificial structure can be etched away to form trenches, gaps or slits extending in the thickness direction on the wafer; when the sacrificial structure penetrates the device structure 101 and the bottom substrate, that is, the sacrificial structure penetrates the entire wafer, or when the sacrificial structure in the substrate and the trench on its top penetrate the entire wafer, the wafer will be divided or separated into multiple independent dies after the sacrificial structure is removed.

[0017] In some embodiments, when the sacrificial structure only penetrates the substrate part and does not extend to the device structure 101 on the wafer, some remaining film layers can be left after removing the sacrificial structure, and the remaining film layers can be laser cut or laser stealth cut to separate the die. For example, when multiple wafers are bonded and arranged, after removing the sacrificial structure in the substrate, the film layers including the bonding layer between adjacent substrates can be laser cut or laser stealth cut. In the laser stealth cutting process, the laser beam is focused on the material to be cut to form a modified layer or crack inside the material. The molecular bonds at the position of the modified layer are broken, and the connection of the material becomes fragile and easy to separate. After cutting, the carrier film is stretched to expand the film, so that the wafer breaks at the position irradiated by the laser to separate the die. Stealth cutting does not contact the carrier film under the wafer, reducing damage to the carrier film or the carrier stage of the machine tool, reducing debris and heat melting, and is beneficial to narrowing the cutting channel 111.

[0018] In some embodiments, referring to Figure 2 As shown, for the convenience of cutting and separating the die, a cutting channel 111 can be provided on the wafer. The cutting channel 111 is a cutting or scribing path. The cutting channel 111 surrounds the edge of the device structure 101 or the die to be cut, and a sacrificial structure can be disposed along the position of the cutting channel 111. The width of the sacrificial structure is smaller than that of the cutting channel 111. Figure 2 The enlarged schematic diagram of a partial area of the wafer is also shown. The range of the width D1 of the sacrificial structure can include 0.5 μm to 10 μm; the sacrificial structure can be located at the center of the cutting channel 111, and the distance between the sacrificial structure and the edge of the device structure 101 is D2. D2 can be half or close to half of the width of the cutting channel 111. There can be no metal structure in the area where the sacrificial structure or the cutting channel 111 is located, such as no interconnect layer, or the interconnect layer is interrupted. The cutting channel 111 can include dielectric materials, such as silicon oxide, silicon nitride or silicon oxynitride, etc.

[0019] According to some aspects of the embodiments of the present disclosure, Figure 3 A method for manufacturing a semiconductor device is provided, including forming a first semiconductor structure, and the forming method of the first semiconductor structure includes: providing a first semiconductor layer, and forming a sacrificial structure penetrating the first semiconductor layer along a first direction; the sacrificial structure includes a plurality of first sacrificial structures extending along a second direction and a plurality of second sacrificial structures extending along a third direction; the second direction intersects the third direction, and a plane formed by the second direction and the third direction intersects the first direction.

[0020] Forming a device structure on at least the first semiconductor layer exposed between the first sacrificial structure and the second sacrificial structure, and adjacent device structures are spaced apart.

[0021] The manufacturing method further includes: removing the sacrificial structure to form a first trench, and separating the first semiconductor structure into a plurality of die at least by using the first trench; the die at least includes the device structure and a part of the first semiconductor layer. The semiconductor structure may be a wafer or a panel including the device structure 101, and there is no limitation on the size of the wafer. The semiconductor structure may be a product form at different process nodes of the wafer, and may be an intermediate product or a final product; the die 141 is a part obtained by cutting and separating the wafer, and may include a part of the wafer substrate or a thinned substrate; the semiconductor device may be the die 141, or a bonded structure formed by bonding a plurality of die 141, or a product structure obtained by packaging the die 141. The logical division of the structure in the embodiments of the present disclosure is only for ease of explanation and does not limit the product structure and the manufacturing process.

[0022] Specifically, as shown in Figure 4 , a first semiconductor layer 110 is provided, and a dielectric layer 112 is formed on a first side of the first semiconductor layer 110 in the z direction. The first semiconductor layer 110 may be a semiconductor substrate, a semiconductor wafer, or a semiconductor layer epitaxially grown on a wafer or a substrate. The first side may be the front side of the wafer, and the second side may be the back side of the wafer, and the back side of the wafer may be thinned. The first semiconductor layer 110 may include semiconductor materials such as silicon, germanium, or silicon carbide; the first semiconductor layer 110 may be doped, such as by diffusion or ion implantation, and different regions of the first semiconductor layer 110 may be doped with different types, and a part of the first semiconductor layer 110 may be grounded.

[0023] Exemplarily, the formation process of the dielectric layer may include a deposition process, which may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The constituent materials of the dielectric layer 112 may include but are not limited to insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The dielectric layer 112 can act as a buffer isolation between the first semiconductor layer 110 (or substrate) and other materials, such as isolation from the device structure 101.

[0024] In some embodiments, referring to Figure 5 and Figure 6 as shown, a sacrificial structure is formed that penetrates the first semiconductor layer 110 along the z direction; the sacrificial structure includes a plurality of first sacrificial structures 121 extending in the x direction and a plurality of second sacrificial structures 122 extending in the y direction; the x direction intersects the y direction, and the plane formed by the x direction and the y direction intersects the z direction. Figure 5 As shown, dielectric material and the first semiconductor layer 110 can be etched on the first side (front side) of the first semiconductor layer 110 to form trenches 131 extending in the x direction and the y direction. The trenches 131 may or may not penetrate the first semiconductor layer 110; Figure 6 As shown, a sacrificial structure is formed in the trenches 131. Taking the first sacrificial structure 121 extending in the x direction as an example, the second sacrificial structure 122 is not shown due to the cross-sectional angle and will not be described further hereinafter. When the trenches 131 penetrate the first semiconductor layer 110, the sacrificial structure penetrates the first semiconductor layer 110; when the trenches 131 do not penetrate the first semiconductor layer 110, the sacrificial structure does not penetrate the first semiconductor layer 110, and the second side (back side) of the first semiconductor layer 110 can be thinned to expose the bottom of the sacrificial structure so that the sacrificial structure penetrates the remaining first semiconductor layer 110 after thinning. The etching process may include but is not limited to: dry etching, wet etching, or a combination thereof; the thinning process may include but is not limited to: etching, chemical mechanical polishing, or a combination thereof. In some embodiments, the front side of the first semiconductor structure 100 in Figure 6 can be chemically mechanically polished to remove the dielectric layer 112 to provide a flatter surface; or the dielectric layer 112 may not be removed, and the sacrificial structure can extend into the dielectric layer 112.

[0025] Combined with Figure 1 and Figure 2As an example, the trench 131 is formed at the edge of the device structure 101, or at the preformed position of the device structure 101, or at the pre-cut position of the die 141, or at the position of the scribe line 111. The trench 131 is a structure extending in the x-direction and the y-direction, and after the trenches 131 intersect, they surround the edge of the device structure 101. The formed sacrificial structure is a structure extending in the x-direction and the y-direction, such as a plurality of first sacrificial structures 121 extending in the x-direction and a plurality of second sacrificial structures 122 extending in the y-direction. The first sacrificial structures 121 and the second sacrificial structures 122 intersect to form a plurality of meshes, and the inside of the meshes is the device structure 101 or the preformed area of the device structure 101.

[0026] In some embodiments, Figure 5 The width range of the shown trench 131 may include 0.5 um to 10 um, and the depth range of the trench 131 may include 30 um to 400 um. The width of the trench 131 may be compatible with the width of the scribe line 111 or the spacing distance between adjacent dies 141. A smaller width enables the subsequent process to be compatible with the clearance area within this width range. The clearance area is formed by interrupting metal layers such as the interconnect layer 102 between adjacent device structures 101, thereby avoiding the influence of uneven metal density caused by large-sized clearances on the process yield. A smaller width is beneficial for reducing the width of the scribe line 111 or the cut width, and is beneficial for increasing the utilization area of the wafer. The depth range of the trench 131 can be adapted to the final thickness requirements after cutting different dies 141, and the depth of the trench 131 is the thickness of the substrate after subsequent thinning.

[0027] In some embodiments, referring to Figure 6 As shown, filling Figure 5 the trench 131 in forms the first sacrificial structure 121 and the second sacrificial structure 122. The filling material can be selected according to the material of the first semiconductor layer 110, so that the sacrificial structure can have good high-temperature stability and can withstand a high temperature of 600 to 1000 °C; the sacrificial structure has good material compatibility with the first semiconductor layer 110, reduces contamination, and has a thermal expansion coefficient close to that of the first semiconductor layer 110; the sacrificial structure has a high etching selectivity ratio with other materials such as dielectric materials and conductive materials in the device structure 101, which is convenient for removal and can reduce the over-etching damage of other materials; the sacrificial structure has good adhesion to the first semiconductor layer 110 and has good stress dispersion and filling effects. As an example, the first semiconductor layer 110 may include silicon; the sacrificial structure may include the same or similar material as the first semiconductor layer 110, such as including silicon material, such as polysilicon; the crystal form of the sacrificial structure may be the same or different from that of the first semiconductor layer 110.

[0028] In some embodiments, referring to Figures 7 to 9 As shown, in Figure 2A device structure 101 is formed on the first semiconductor layer 110 exposed between the first sacrificial structure 121 and the second sacrificial structure 122 in the illustrated example, that is, the device structure 101 is formed within the grid region formed by the intersection of the first sacrificial structure 121 and the second sacrificial structure 122, in the exposed region of the first semiconductor layer 110; one device structure 101 can be located in one grid, and adjacent device structures 101 can be spaced by a dielectric material 103, or the conductive materials such as the dielectric material 103 and the interconnect layer 102 between adjacent device structures 101 are etched and interrupted, and are spaced by a first gap 132.

[0029] In Figure 7 the functional devices forming the device structure 101 include, but are not limited to, capacitors, inductors, resistors, memory structures, CMOS transistors, diodes, and in Figure 8 the interconnect layer 102 is formed and Figure 7 the functional devices in are electrically connected to lead out electrical signals; Figure 8 the interconnect layers 102 of the respective device structures 101 in are discontinuous, and the interconnect layer 102 is spaced above the sacrificial structure to form a clearance of the interconnect layer 102, and the device structures 101 belonging to different dies 141 are spaced by a dielectric material 103; the interconnect layer 102 can be a stack of multiple film layers, and adjacent layers can be interconnected by conductive plugs. Referring to Figure 9 as shown, the dielectric material 103 above the first sacrificial structure 121 and the second sacrificial structure 122 is etched to form a first gap 132 to expose the sacrificial structure.

[0030] In some embodiments, some components of the device structure 101 can be located in the first semiconductor layer 110, such as the source and drain of a transistor and the isolation structure between different transistors. The source and drain can be formed by ion implantation doping of different regions of the first semiconductor layer 110, and the ion implantation depth is less than the thickness of the first semiconductor layer 110; the isolation structure can include, but is not limited to, shallow trench isolation or deep trench isolation, and can extend in the z direction along the front surface of the first semiconductor layer 110 without penetrating the entire thickness of the first semiconductor layer 110. The isolation structure can include insulating materials such as silicon oxide. The sacrificial structure located in the first semiconductor layer 110 avoids and does not contact the source, drain, and isolation structure and other structures in the first semiconductor layer 110.

[0031] In some embodiments, during the fabrication process of the interconnect layer 102, the interconnect layers 102 of multiple device structures 101 can be fabricated integrally in the same process, and the interconnect layer 102 is a continuous wiring layer at the wafer level. In Figure 8The interconnect layer 102 is provided in the dielectric material 103 above the first sacrificial structure 121 and the second sacrificial structure 122. When forming the first gap 132, the interconnect layer 102 can be removed, and a clearance of the interconnect layer 102 is formed through the interconnect layer 102. For example, the dielectric material 103 and the interconnect layer 102 above the sacrificial structure can be removed by etching or laser grooving process to form Figure 9 the exemplified first gap 132. The distribution of the first gap 132 corresponds to Figure 1 and Figure 2 the first sacrificial structure 121 and the second sacrificial structure 122 therein. The first gap 132 can be a strip structure extending in the x direction and arranged in rows and columns in the y direction. The first gaps 132 intersect to form a grid, and the device structure 101 or the die 141 to be separated is exposed in the middle of the grid. After the first gaps 132 intersect, they surround the device structure 101 or the die 141 to be separated.

[0032] In some embodiments, as shown in reference to Figure 10 , the back surface of the first semiconductor layer 110 can be thinned to expose the first sacrificial structure 121 and the second sacrificial structure 122, Figure 11 and the first trench 133 is formed by removing the sacrificial structure on the back surface therein; the structure after removing the sacrificial structure is attached to the carrier film 320. For example, the back surface of the first semiconductor layer 110 can be pasted to the carrier film 320. At this time, the first gap 132 and the first trench 133 communicate through the entire first semiconductor structure 100, and the first semiconductor structure 100 has been divided into multiple dies 141 by using the first trench 133 and the first gap 132. After removing the carrier film 320, the independent dies 141 are separated. In some other embodiments, as shown in reference to Figure 12 , the back surface of the first semiconductor structure 100 after back thinning can be attached to the carrier film 320, Figure 13 the sacrificial structure can be removed along the first gap 132 on the front surface to form the first trench 133. The first trench 133 and the first gap 132 divide the first semiconductor structure 100 into multiple dies 141. The first trench 133 can be a strip structure extending in the x direction and arranged in rows and columns in the y direction. The first trenches 133 intersect to form a grid, and the device structure 101 or the die 141 to be separated is exposed in the middle of the grid. After the first trenches 133 intersect, they surround the device structure 101 or the die 141 to be separated.

[0033] In some embodiments, the carrier film 320 may include, but is not limited to: a UV film (blue film), an adhesive film, or other films, and the attachment method may be adhesive bonding or electrostatic adsorption. The etching process for removing the sacrificial structure may include, but is not limited to, wet etching to improve production efficiency; for example, the first semiconductor layer 110 may be single-crystalline silicon, the sacrificial structure may include polysilicon to improve the etching selectivity ratio, and the etchant may include, but is not limited to: hydrofluoric acid, phosphoric acid, or a mixed solution of phosphoric acid, hydrofluoric acid, and nitric acid to selectively etch the sacrificial structure. In some embodiments, a barrier layer may be formed between the sacrificial structure and the first semiconductor layer 110, and the barrier layer at least surrounds the sidewalls of the sacrificial structure to reduce over-etching damage to the first semiconductor layer 110; the barrier layer may include, but is not limited to: insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. Exemplarily, on the sidewalls and / or bottom of the trench 131 shown in Figure 5 a barrier layer is deposited and formed, and then the trench 131 is filled to form the sacrificial structure; the part of the barrier layer located at the bottom of the sacrificial structure may be removed in the back thinning process to expose the sacrificial structure.

[0034] In some embodiments, Figure 8 there is no interconnect layer 102 above the first sacrificial structure 121 and the second sacrificial structure 122 in Figure 8 but there is a dielectric material 103 for spacing; after the back thinning of the first semiconductor layer 110 in Figure 8 with the support of the carrier film 320, the sacrificial structure is removed to form a first trench 133, the bottom of the first trench 133 exposes the dielectric material 103, the dielectric material 103 at the bottom of the first trench 133 is laser stealth cut, and subsequently, the carrier film 320 is used to perform a film expansion process to fragment the first semiconductor structure 100 along the contour of the first trench 133, and a plurality of die 141 are separated.

[0035] In some embodiments, the first semiconductor layer 110 has a first side and a second side that are oppositely arranged in the z direction; the method for forming the first semiconductor structure 100 further includes: as shown in Figure 6 a sacrificial structure is formed along the first side of the first semiconductor layer 110, and the bottom of the sacrificial structure is located in the first semiconductor layer 110; the device structure 101 is located on the first side of the first semiconductor layer 110; as shown in Figure 10 the second side of the first semiconductor layer 110 is thinned to expose the bottom of the sacrificial structure. Exemplarily, the first side may be the front side of the first semiconductor layer 110, and the second side may be the back side of the first semiconductor layer 110.

[0036] Figure 6 As shown, the first sacrificial structure 121 and the second sacrificial structure 122 may be fabricated along the front side of the first semiconductor layer 110, and the sacrificial structure only penetrates through a partial thickness of the first semiconductor layer 110 and does not completely penetrate, so as to reduce the etching amount of the first semiconductor layer 110; Figure 10The first semiconductor structure 100 is temporarily bonded to the carrier wafer 310 or other film structures, and a bonding adhesive can be used for temporary bonding. With the aid of the carrier wafer 310, the first semiconductor structure 100 is turned over, and the second side of the first semiconductor layer 110 is back-thinned under the support of the carrier wafer 310 to expose the first sacrificial structure 121 and the second sacrificial structure 122. While reducing the overall thickness of the device to meet the packaging standard, it is possible to Figure 11 remove the sacrificial structures from the back side to form the first trench 133 as shown in Figure 13 . Subsequently, the second side of the first semiconductor layer 110 is adhered to the Figure 13 carrier film 320 for facilitating the picking and transferring of the die 141. The carrier wafer 310 can be removed under the support of the carrier film 320, and the removal method can include but is not limited to debonding. The carrier film 320 can prevent the die 141 from collapsing and shifting during the debonding process.

[0037] In some embodiments, the device structure 101 at least includes: as Figure 8 shown in the example, the first device structure 101 and the second device structure 101, and there is a dielectric material 103 between the first device structure 101 and the second device structure 101; the manufacturing method further includes: referring to Figure 9 shown, removing the dielectric material 103 above the first sacrificial structure 121 and the second sacrificial structure 122 to form a first gap 132 penetrating the dielectric material 103; the bottom of the first gap 132 exposes the sacrificial structures; wherein, Figure 11 after forming the first trench 133, the first gap 132 is in communication with the first trench 133 in the z direction. Figure 9 In , using the patterned photoresist layer as an etching mask, the dielectric material 103 above the sacrificial structures is etched to form the first gap 132, and the first gap 132 is located above the sacrificial structures.

[0038] In some embodiments, the interconnect layer 102 of the first device structure 101 is connected to the interconnect layer 102 of the second device structure 101; at least a part of the interconnect layer 102 of the first device structure 101 and at least a part of the interconnect layer 102 of the second device structure 101 are located in the dielectric material 103; the method for forming the first gap 132 further includes: also removing a part of the interconnect layer 102 located above the sacrificial structures, and the first gap 132 also penetrates the interconnect layer 102.

[0039] During the manufacturing process of the interconnect layer 102, the interconnect layers 102 of multiple device structures 101 can be integrally manufactured in the same process, and the interconnect layer 102 is a continuous wiring layer at the wafer level. For example, the dielectric material 103 is etched to form cavity structures such as trenches, grooves or openings, and the cavity structures are filled with a conductive material to form the interconnect layer 102; the filling process can include but is not limited to chemical deposition, physical deposition, and electroplating and other processes. Figure 9Etch the dielectric material 103 and the interconnect layer 102 on the first sacrificial structure 121 and the second sacrificial structure 122 to form a first gap 132 that penetrates the dielectric material 103 and the interconnect layer 102 until the sacrificial structure is exposed. During the etching process, the sacrificial structure may not be etched or partially over-etched. The distribution of the first gap 132 corresponds to Figure 1 and Figure 2 the sacrificial structures therein. The first gap 132 may be a strip-shaped structure extending in the x direction and arranged in rows and columns in the y direction. The first gaps 132 intersect to form a grid, and the device structure 101 or the die 141 to be separated is exposed in the middle of the grid. After the first gaps 132 intersect, they surround the device structure 101 or the die 141 to be separated.

[0040] Refer to Figure 10 As shown, temporarily bond the side with the first gap 132 to the carrier wafer 310 or other film structures, and thin the back surface (the second side of the first semiconductor layer 110) of the first semiconductor layer 110 until the sacrificial structure is exposed, so that the sacrificial structure penetrates the first semiconductor layer 110; refer to Figure 11 As shown, etch away the sacrificial structure to form a first trench 133 communicating with the first gap 132. At this time, the first trench 133 and the first gap 132 separate the first semiconductor structure 100 into multiple independent dies 141. Refer to Figure 13 As shown, attach the back surface (the second side) of the first semiconductor layer 110 having the first trench 133 to the carrier film 320, and debond the carrier wafer 310, and pick up multiple dies 141 for subsequent packaging or bonding and stacking with other semiconductor structures.

[0041] Alternatively, refer to Figure 12 As shown, attach the back surface of the thinned first semiconductor layer 110 in Figure 10 to the carrier film 320, and debond the carrier wafer 310 to expose the first gap 132; refer to Figure 13 As shown, use the first gap 132 to etch away the sacrificial structure and form a first trench 133 at the bottom of the first gap 132; at this time, the first trench 133 and the first gap 132 separate the first semiconductor structure 100 into multiple independent dies 141.

[0042] In some embodiments, the method for forming the first semiconductor structure 100 further includes: refer to Figure 14 As shown, form a first connection structure 104 extending in the z direction along the first side of the first semiconductor layer 110, and the bottom of the first connection structure 104 is located in the first semiconductor layer 110; when thinning the second side of the first semiconductor layer 110, the bottom of the first connection structure 104 is also exposed.

[0043] A first connection structure 104 is formed along the front surface of the first semiconductor layer 110. The first connection structure 104 does not penetrate the entire first semiconductor layer 110. A device structure 101 and a bonding layer can be formed on the first connection structure 104. The bonding layer has a plurality of first bonding contacts 151. The first bonding contacts 151 can be connected to the device structure 101, and the first connection structure 104 can be connected to the device structure 101. The device structure 101 can only include an interconnect layer 102, such as a redistribution layer. At this time, the first semiconductor structure 100 can be used as an interposer, such as a silicon interposer. Or, other functional devices such as transistors and interconnect layers 102 in the device structure 101 are not shown in Figure 14 . The first connection structure 104 can be used as a TSV and cooperate with the bonding contacts 150 for electrical signal interconnection on the front and back sides of the first semiconductor structure 100 or the die 141.

[0044] Referring to Figure 15 as shown, with the support of the carrier wafer 310, the back surface of the first semiconductor layer 110 can be thinned to expose the first connection structure 104, the first sacrificial structure 121, and the second sacrificial structure 122. Referring to Figure 16 as shown, a contact or pad is formed on the back surface of the first semiconductor layer 110 and connected to the first connection structure 104. The constituent materials of the first connection structure 104 and the contact can include, but are not limited to, conductive materials such as copper, aluminum, cobalt, gold, silver, platinum, tungsten, nickel, and titanium.

[0045] In some embodiments, the embodiments of the present disclosure can form sacrificial structures in the semiconductor layers of multiple semiconductor structures. The multiple semiconductor structures can be hybrid bonded in the z direction for electrical interconnection. The sacrificial structures in each semiconductor structure are removed to form trenches, and the bonding structure is cut using the trenches to form a plurality of dies 141. The die 141 can include a part of different semiconductor structures and can be regarded as a semiconductor device formed by bonding multiple sub-dies in the z direction. For example, a second semiconductor structure 200 is provided as shown in Figure 17 . The second semiconductor structure 200 and the first semiconductor structure 100 can have the same device structure 101 or different device structures. The second semiconductor structure 200 includes a second semiconductor layer 210, a third sacrificial structure 221 located in the second semiconductor layer 210, and a fourth sacrificial structure. The third sacrificial structure 221 extends in the x direction and Figure 17As shown, the fourth sacrificial structure extends in the y direction and is not shown. The sacrificial structure of the second semiconductor structure 200, like the third sacrificial structure 221, may penetrate the second semiconductor layer 210 or only penetrate a part of the thickness of the second semiconductor layer 210. Subsequently, the back surface of the second semiconductor layer 210 is thinned to expose the bottom of the third sacrificial structure 221, causing the third sacrificial structure 221 to penetrate the entire second semiconductor layer 210. Subsequently, the first semiconductor structure 100 and the second semiconductor structure 200 can be bonded so that the upper and lower sacrificial structures are aligned or substantially aligned.

[0046] In some embodiments, before removing the sacrificial structure in the first semiconductor structure 100, the manufacturing method further includes: referring to Figure 18 As shown, bonding the second semiconductor structure 200 to the side of the device structure 101 of the first semiconductor structure 100 away from the first semiconductor layer 110; the second semiconductor structure 200 includes: a second semiconductor layer 210, a third sacrificial structure 221 and a fourth sacrificial structure penetrating the second semiconductor layer 210, the third sacrificial structure 221 extending in the x direction and being aligned with the first sacrificial structure 121 in the z direction; the fourth sacrificial structure extending in the y direction and being aligned with the second sacrificial structure 122 in the z direction; the third sacrificial structure 221 and the fourth sacrificial structure do not overlap with the device structure 101 of the second semiconductor structure 200 in the z direction; Figure 18 As exemplified in, a first sacrificial structure 121 extending in the x direction and a third sacrificial structure 221 aligned or substantially aligned with it are shown. The third sacrificial structure 221 may completely penetrate the second semiconductor layer 210 or may be thinned through the back surface to completely penetrate the second semiconductor layer 210; the die 141 includes a part of the first semiconductor structure 100 and a part of the second semiconductor structure 200. The method of forming the die 141 further includes: as referring to the following text Figure 26 As shown, removing the third sacrificial structure 221 and the fourth sacrificial structure to form a second trench 135 in the second semiconductor structure 200; referring to Figure 24 and Figure 25 As shown, breaking the bonded structure formed by the first semiconductor structure 100 and the second semiconductor structure 200 at least along the first trench 133 and the second trench 135 to form the die 141.

[0047] Referring to Figure 18As shown, before bonding, a first bonding layer having a plurality of first bonding contacts 151 is formed on the bonding side of the first semiconductor structure 100, and a second bonding layer having a plurality of second bonding contacts 152 is formed on the bonding side of the second semiconductor structure 200; after the first bonding layer and the second bonding layer are bonded, there may be no physical boundary, and after the first bonding contacts 151 and the second bonding contacts 152 are bonded, there may be no physical boundary, which is shown as the bonding contact 150; the part of the bonding contact 150 located in the first semiconductor structure 100 is the first bonding contact 151 before bonding, and the part of the bonding contact 150 located in the second semiconductor structure 200 is the second bonding contact 152 before bonding. The first semiconductor structure 100 and the second semiconductor structure 200 are electrically interconnected through the bonding contact 150, including but not limited to power supply, data transmission, control signal transmission, etc.

[0048] Similar to Figure 1 and Figure 2 As shown in the exemplified first sacrificial structure 121 and second sacrificial structure 122, the third sacrificial structure 221 and the fourth sacrificial structure in the second semiconductor structure 200 are arranged in rows and columns along the x direction and y direction respectively to form a grid, and a device structure 101 is formed on or in the second semiconductor layer 210 exposed between the grids; the second semiconductor structure 200 and the first semiconductor structure 100 may have the same device structure 101 or different device structures. Figure 17 Among them, the third sacrificial structure 221 and the fourth sacrificial structure avoid and do not contact the source, drain, and isolation structures in the second semiconductor layer 210, and there is no device structure 101 above the third sacrificial structure 221 and the fourth sacrificial structure. For example, there is no interconnect layer 102, and there may be a dielectric material 103. Based on the cross-sectional schematic direction, Figure 18 only the aligned or substantially aligned first sacrificial structure 121 and third sacrificial structure 221 are shown.

[0049] In some embodiments, referring to Figure 19 As shown, the side of the first semiconductor layer 110 away from the bonding interface is etched to remove the dielectric material 103 and / or conductive material above the first sacrificial structure 121 and the second sacrificial structure 122, forming a second gap 134 exposing the sacrificial structure. The second gap 134 is conformally arranged with the sacrificial structure and forms a grid arranged in rows and columns in the x direction and y direction, facilitating the etching to remove the sacrificial structure.

[0050] In some embodiments, one end of the third sacrificial structure 221 and the fourth sacrificial structure away from the first semiconductor structure 100 is located in the second semiconductor layer 210; the manufacturing method further includes: referring to Figure 20As shown, bond the side of the first semiconductor layer 110 having the second gap 134 to the carrier wafer 310; thin the side of the second semiconductor layer 210 away from the first semiconductor structure 100 to expose the third sacrificial structure 221 and the fourth sacrificial structure.

[0051] In some embodiments, refer to Figure 21 As shown, remove the third sacrificial structure 221 and the fourth sacrificial structure to form a second trench 135 in the second semiconductor structure 200. The second trenches 135 are arranged in rows and columns in the x-direction and the y-direction, and the bottom of the second trench 135 exposes the dielectric material.

[0052] In some embodiments, after forming the second trench 135, the manufacturing method further includes: performing a laser irradiation process on the dielectric material exposed at the bottom of the second trench 135 along the z-direction for laser stealth dicing; in Figure 22 a modified layer, or cracks, or a weakened region is formed in the dielectric material at the bottom of the second trench 135. The laser irradiation region or the region where the modified layer is formed is shown at the curve position in the figure, and this part of the region does not include the device and the interconnect layer 102; refer to Figure 23 As shown, attach the side of the second semiconductor structure 200 having the second trench 135 to the carrier film 320; refer to Figure 24 As shown, remove the first sacrificial structure 121 and the third sacrificial structure 221 based on the second gap 134 to form a first trench 133; the second gap 134 may be formed in Figure 23 a step, and in Figure 19 if the second gap 134 is not formed and after forming the second trench 135, remove it again just before removing the first sacrificial structure 121 and the third sacrificial structure 221, and sequentially form the second gap 134 and the first trench 133; refer to Figure 25 As shown, after forming the first trench 133, perform a film expansion process on the carrier film 320 to break the bonded structure formed by the first semiconductor structure 100 and the second semiconductor structure 200.

[0053] During the film expansion process, a film expander can be used to stretch the carrier film 320, or the carrier film 320 can be fixed and the wafer can be lifted, so that the carrier film 320 is stretched to generate a radial tension and expand around, causing the film layer after laser stealth dicing to break along the first trench 133 and the second trench 135, separating out multiple die 141. The die 141 in the figure may include two bonded parts. Figure 25 In, the film layer broken by film expansion includes the part between the first trench 133 and the second trench 135, including some dielectric materials at the bonding interface.

[0054] According to some aspects of the embodiments of the present disclosure, Figure 26A method for fabricating a semiconductor structure is provided, including: providing a first semiconductor structure, the first semiconductor structure including: a first semiconductor layer and a sacrificial structure penetrating the first semiconductor layer along a first direction, the sacrificial structure including a plurality of first sacrificial structures extending along a second direction and a plurality of second sacrificial structures extending along a third direction; the sacrificial structure being located at the edge of the device structure of the first semiconductor structure; the second direction intersecting the third direction, and the plane formed by the second direction and the third direction intersecting the first direction;

[0055] Bonding a second semiconductor structure to the side of the first semiconductor structure having a device structure; the second semiconductor structure including a second semiconductor layer, and including a third sacrificial structure and a fourth sacrificial structure penetrating the second semiconductor layer along the first direction, the third sacrificial structure extending along the second direction and being aligned with the first sacrificial structure in the first direction; the fourth sacrificial structure extending along the third direction and being aligned with the second sacrificial structure in the first direction; the third sacrificial structure and the fourth sacrificial structure being located at the edge of the device structure of the second semiconductor structure;

[0056] Removing the first sacrificial structure and the second sacrificial structure to form a first trench in the first semiconductor structure;

[0057] Removing the third sacrificial structure and the fourth sacrificial structure to form a second trench in the second semiconductor structure;

[0058] Breaking at least along the first trench and the second trench the bonding structure formed by the first semiconductor structure and the second semiconductor structure to form a die; the die including a part of the first semiconductor structure and a part of the second semiconductor structure.

[0059] Specifically, referring to Figure 16 As shown, a first semiconductor structure 100 is provided. The first semiconductor structure 100 includes a first semiconductor layer 110 and a sacrificial structure penetrating the first semiconductor layer 110 along the z direction. The sacrificial structure includes a plurality of first sacrificial structures 121 extending along the x direction and a plurality of second sacrificial structures 122 extending along the y direction; As Figure 1 And Figure 2 Illustratively, the sacrificial structure is located at the edge of the device structure 101 of the first semiconductor structure 100 or at the scribe line 111. Figure 16 In, the first semiconductor structure 100 includes a first connection structure 104 penetrating the first semiconductor layer 110, such as a TSV. The first semiconductor structure 100 also has a first bonding contact 151, and other device structures 101 can be provided between the first bonding contact 151 and the first connection structure 104. Figure 16The first sacrificial structure 121 illustrated in [the figure] is located between two adjacent partial device structures 101 or a portion to be cut (die to be cut 141). The device structure 101 may include only an interconnect layer 102, such as a redistribution layer. At this time, the first semiconductor structure 100 may be used as an interposer, such as a silicon interposer.

[0060] Referring to Figure 17 As shown, a second semiconductor structure 200 is provided. The second semiconductor structure 200 may have a third sacrificial structure 221 and a fourth sacrificial structure located in the second semiconductor layer 210. The second semiconductor structure 200 may be arranged with reference to Figure 8 the first semiconductor structure 100 shown. The third sacrificial structure 221 and the fourth sacrificial structure are arranged in a grid in the x-direction and y-direction rows and columns. A device structure 101 is provided in the region where the second semiconductor layer 210 is exposed between the grids. The third sacrificial structure 221 and the fourth sacrificial structure may have a dielectric material 103 thereon without providing an interconnect layer 102 or other functional devices.

[0061] Referring to Figure 18 As shown, the first semiconductor structure 100 and the second semiconductor structure 200 are bonded to form a bonded structure. The first bonding contact 151 of the first semiconductor structure 100 and the second bonding contact 152 of the second semiconductor structure 200 are electrically connected after bonding. There may be no physical demarcation after the first bonding contact 151 and the second bonding contact 152 are bonded, which is shown by the bonding contact 150. As shown later Figure 24 As shown, the first sacrificial structure 121 and the second sacrificial structure 122 are etched away to form a first trench 133; the third sacrificial structure 221 and the fourth sacrificial structure are removed to form a second trench 135; the row- and column-arranged first trenches 133 and the row- and column-arranged second trenches 135 are aligned or substantially aligned in the z-direction. There is no residual film layer and no interconnect layer 102 and other functional devices between the two trenches 131; a laser is used to irradiate the residual dielectric material between the two trenches 131 along the first trench 133 or the second trench 135, and laser cutting or laser stealth cutting is performed to separate the bonded structure into dies 141, and the dies 141 include two bonded parts.

[0062] In some embodiments, before removing the first sacrificial structure 121 and the second sacrificial structure 122, the manufacturing method further includes: referring to Figure 19 As shown, on the side of the first semiconductor layer 110 away from the second semiconductor structure 200, the dielectric material 103 above the first sacrificial structure 121 and the second sacrificial structure 122 is removed to form a second gap 134 penetrating the dielectric material 103; the bottom of the second gap 134 exposes the first sacrificial structure 121 and the second sacrificial structure 122; wherein, as Figure 24After forming the first trench 133 of the example, the second gap 134 communicates with the first trench 133 in the z direction.

[0063] In some embodiments, when Figure 19 There is also an interconnect layer 102 in the dielectric material 103 above the first sacrificial structure 121 and the second sacrificial structure 122. The method of forming the second gap 134 further includes: removing the conductive material above the first sacrificial structure 121 and the second sacrificial structure 122, and the second gap 134 also penetrates the conductive material.

[0064] In some embodiments, Figure 19 The bottom of the third sacrificial structure 221 and the bottom of the fourth sacrificial structure are located in the second semiconductor layer 210; the manufacturing method further includes: referring to Figure 20 As shown, before forming the second trench 135, bond the side of the first semiconductor layer 110 having the second gap 134 to the carrier wafer 310; thin the side of the second semiconductor layer 210 away from the first semiconductor structure 100, that is, perform back thinning on the side of the second semiconductor layer 210 away from the first semiconductor layer 110 to expose the third sacrificial structure 221 and the fourth sacrificial structure. Referring to Figure 21 As shown, remove the third sacrificial structure 221 and the fourth sacrificial structure to form the second trench 135 in the second semiconductor structure 200. The second trenches 135 are arranged in rows and columns in the x direction and the y direction, and the bottom of the second trenches 135 exposes the dielectric material.

[0065] In some embodiments, the manufacturing method further includes: referring to Figure 22 As shown, after forming the second trench 135, perform laser irradiation treatment on the dielectric material exposed at the bottom of the second trench 135 in the z direction for laser stealth dicing; in Figure 22 A modified layer, or crack, or weakened area is formed in the dielectric material at the bottom of the second trench 135. The laser irradiation area or the area where the modified layer is formed is shown at the curve position in the figure, and this part of the area does not include the device and the interconnect layer 102; referring to Figure 23 As shown, attach the side of the second semiconductor structure 200 having the second trench 135 to the carrier film 320; referring to Figure 24 As shown, based on the second gap 134, remove the first sacrificial structure 121 and the third sacrificial structure 221 to form the first trench 133; the second gap 134 can or can be formed in Figure 23 In the step, in Figure 19 The second gap 134 is not formed, and after forming the second trench 135, it is removed again just before removing the first sacrificial structure 121 and the third sacrificial structure 221, and the second gap 134 and the first trench 133 are formed in sequence; referring to Figure 25As shown, after the first groove 133 is formed, the carrier film 320 is expanded, causing the bonding structure formed by the first semiconductor structure 100 and the second semiconductor structure 200 to break.

[0066] During the film expansion process, the carrier film 320 is stretched to generate a radial tension that expands around, causing the film layer after laser stealth cutting to break along the first groove 133 and the second groove 135, separating multiple dies 141. In the figure, the die 141 may include two bonded parts.

[0067] As described above, this is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises forming a first semiconductor structure, wherein the method of forming the first semiconductor structure comprises: Providing a first semiconductor layer, forming a sacrificial structure penetrating the first semiconductor layer along a first direction; the sacrificial structure includes a plurality of first sacrificial structures extending along a second direction, and a plurality of second sacrificial structures extending along a third direction; the second direction intersects with the third direction, and a plane formed by the second direction and the third direction intersects with the first direction; forming a device structure at least on the first semiconductor layer exposed between the first sacrificial structure and the second sacrificial structure, with adjacent device structures being arranged at intervals; The production method further comprises: The sacrificial structure is removed to form a first trench, and the first semiconductor structure is separated into a plurality of dies at least by using the first trench; the dies at least include the device structure and a portion of the first semiconductor layer.

2. The method according to claim 1, characterized in that: The first semiconductor layer has a first side and a second side which are arranged opposite to each other in the first direction; The method for forming the first semiconductor structure further includes: The sacrificial structure is formed along the first side of the first semiconductor layer, and the bottom of the sacrificial structure is located in the first semiconductor layer; the device structure is located on the first side of the first semiconductor layer; The second side of the first semiconductor layer is thinned to expose the bottom of the sacrificial structure.

3. The method according to claim 1, characterized in that: The device structure at least comprises: A first device structure and a second device structure, wherein a dielectric material is disposed between the first device structure and the second device structure; and the manufacturing method further comprises: Removing the dielectric material on the sacrificial structure to form a first gap penetrating the dielectric material; the sacrificial structure is exposed at the bottom of the first gap; After the first groove is formed, the first gap is connected to the first groove in the first direction.

4. The method according to claim 3, characterized in that: The interconnect layer of the first device structure is connected to the interconnect layer of the second device structure; at least a portion of the interconnect layer of the first device structure and at least a portion of the interconnect layer of the second device structure are located in the dielectric material; The method of forming the first gap further includes: A portion of the interconnection layer located above the sacrificial structure is also removed, and the first gap also penetrates the interconnection layer.

5. The method according to claim 2, characterized in that: The method for forming the first semiconductor structure further includes: A first connection structure extending along the first direction is formed along the first side of the first semiconductor layer, and the bottom of the first connection structure is located in the first semiconductor layer; when the second side of the first semiconductor layer is thinned, the bottom of the first connection structure is also exposed.

6. The method according to claim 5, characterized in that: Before removing the sacrificial structure in the first semiconductor structure, the manufacturing method further includes: A second semiconductor structure is bonded to a side of the device structure away from the first semiconductor layer; the second semiconductor structure comprises: a second semiconductor layer, and a third sacrificial structure and a fourth sacrificial structure penetrating the second semiconductor layer, the third sacrificial structure extending along the second direction and aligned with the first sacrificial structure in the first direction; the fourth sacrificial structure extending along the third direction and aligned with the second sacrificial structure in the first direction; the third sacrificial structure and the fourth sacrificial structure do not overlap with the device structure of the second semiconductor structure in the first direction; The die includes a portion of the first semiconductor structure and a portion of the second semiconductor structure, and the method of forming the die further includes: removing the third sacrificial structure and the fourth sacrificial structure to form a second trench in the second semiconductor structure; The bonding structure formed by the first semiconductor structure and the second semiconductor structure is broken at least along the first trench and the second trench to form the tube core.

7. The manufacturing method according to claim 6, characterized in that: The third sacrificial structure and the fourth sacrificial structure are located in the second semiconductor layer at one end away from the first semiconductor structure; The production method further comprises: The side of the second semiconductor layer away from the first semiconductor structure is thinned to expose the third sacrificial structure and the fourth sacrificial structure.

8. The method according to claim 7, characterized in that: After forming the second groove, the manufacturing method further includes: Performing laser irradiation processing on the dielectric material exposed at the bottom of the second groove along the first direction; Attaching a side of the second semiconductor structure having the second trench to a carrier film; After forming the first groove, the carrier film is expanded to break the bonding structure formed by the first semiconductor structure and the second semiconductor structure.

9. A method for manufacturing a semiconductor device, characterized in that: include: A first semiconductor structure is provided, the first semiconductor structure comprising: a first semiconductor layer and a sacrificial structure penetrating the first semiconductor layer along a first direction, the sacrificial structure comprising a plurality of first sacrificial structures extending along a second direction, and a plurality of second sacrificial structures extending along a third direction; the sacrificial structure is located at an edge of a device structure of the first semiconductor structure; the second direction intersects with the third direction, and a plane formed by the second direction and the third direction intersects with the first direction; A second semiconductor structure is bonded to a side of the first semiconductor structure having a device structure; the second semiconductor structure comprises a second semiconductor layer, and comprises a third sacrificial structure and a fourth sacrificial structure penetrating the second semiconductor layer along the first direction, the third sacrificial structure extends along the second direction and is aligned with the first sacrificial structure in the first direction; the fourth sacrificial structure extends along the third direction and is aligned with the second sacrificial structure in the first direction; the third sacrificial structure and the fourth sacrificial structure are located at the edge of the device structure of the second semiconductor structure; removing the first sacrificial structure and the second sacrificial structure to form a first trench in the first semiconductor structure; removing the third sacrificial structure and the fourth sacrificial structure to form a second trench in the second semiconductor structure; The bonding structure formed by the first semiconductor structure and the second semiconductor structure is broken at least along the first trench and the second trench to form a tube core; the tube core includes a portion of the first semiconductor structure and a portion of the second semiconductor structure.

10. The manufacturing method according to claim 9, characterized in that: The bottom of the third sacrificial structure and the bottom of the fourth sacrificial structure are located in the second semiconductor layer; The production method further comprises: Before forming the second trench, the side of the second semiconductor layer away from the first semiconductor structure is thinned to expose the third sacrificial structure and the fourth sacrificial structure.

11. The manufacturing method according to claim 10, characterized in that: The production method further comprises: After forming the second groove, performing laser irradiation treatment on the dielectric material exposed at the bottom of the second groove along the first direction; Attaching a side of the second semiconductor structure having the second trench to a carrier film; After forming the first groove, the carrier film is expanded to break the bonding structure formed by the first semiconductor structure and the second semiconductor structure.

12. The manufacturing method according to claim 9, characterized in that: Before removing the first sacrificial structure and the second sacrificial structure, the manufacturing method further includes: On a side of the first semiconductor layer away from the second semiconductor structure, the dielectric material on the first sacrificial structure and the second sacrificial structure is removed to form a second gap penetrating the dielectric material; the bottom of the second gap exposes the first sacrificial structure and the second sacrificial structure; wherein, after the first groove is formed, the second gap is connected to the first groove in the first direction.

13. The manufacturing method according to claim 12, characterized in that: The method of forming the second gap further includes: The conductive material on the first sacrificial structure and the second sacrificial structure is removed, and the second gap also penetrates the conductive material.

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