Semiconductor structure and preparation method thereof, and preparation method of bonding structure

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and a preparation method of a bonding structure. The semiconductor structure comprises a substrate which comprises a wiring layer; the first dielectric layer is located on the side, provided with the wiring layer, of the substrate and covers the wiring layer; the interconnection hole structure penetrates through the first dielectric layer, extends to the wiring layer and is provided with at least two conductive interconnection parts with different key sizes; the second dielectric layer covers the interconnection hole structure and the first dielectric layer; the bonding pads are located in the second dielectric layer and are in one-to-one correspondence with the interconnection hole structures, the bonding pads cover the corresponding interconnection hole structures, and the surfaces, away from the interconnection hole structures, of the bonding pads are sunken; wherein in the at least two conductive interconnection parts of the same interconnection hole structure, the larger the concave depth of the surfaces of the bonding pads opposite to the conductive interconnection parts is, the larger the key size of the conductive interconnection parts is. According to the embodiment of the invention, the bonding effect can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technologies, and particularly to a semiconductor structure, a preparation method thereof, and a preparation method of a bonding structure. Background Art

[0002] With the development of semiconductor technologies, hybrid bonding processes are often used for wafer bonding or chip bonding. In hybrid bonding processes, there are both intermolecular bonds between dielectric layers and electrical connections between metal layers on the bonding surfaces, so high requirements are imposed on the bonding surfaces.

[0003] However, in existing bonding processes, problems such as gaps between bonding pads or extrusion of bonding pads between bonding pads after bonding annealing are likely to occur. These will affect the bonding effect. Summary of the Invention

[0004] Based on this, embodiments of this application provide a semiconductor structure that can improve the bonding effect and a preparation method thereof.

[0005] A semiconductor structure includes:

[0006] a substrate including a wiring layer;

[0007] a first dielectric layer located on one side of the substrate where the wiring layer is provided and covering the wiring layer;

[0008] an interconnect via structure penetrating the first dielectric layer and extending to the wiring layer, having at least two conductive interconnect portions with different critical dimensions;

[0009] a second dielectric layer covering the interconnect via structure and the first dielectric layer;

[0010] bonding pads located in the second dielectric layer, arranged in one-to-one correspondence with the interconnect via structure, and the bonding pads covering the corresponding interconnect via structures, with the surfaces of the bonding pads away from the interconnect via structures being recessed;

[0011] wherein, among the at least two conductive interconnect portions of the same interconnect via structure, the greater the surface recess depth of the corresponding bonding pad, the greater the critical dimension of the conductive interconnect portion.

[0012] In one embodiment, the ratio of the critical dimensions of any two conductive interconnect portions of the same interconnect via structure is equal to the ratio of the surface recess depths of two positions of the corresponding bonding pad opposite to the two conductive interconnect portions.

[0013] In one embodiment, at positions where the recess depths of the corresponding bonding pads are the same, the critical dimensions of the conductive interconnect portions are the same.

[0014] In one embodiment, the at least two conductive interconnect portions of the same interconnect via structure include a central interconnect portion and at least one edge interconnect portion that are concentrically distributed. The central interconnect portion is cylindrical, the edge interconnect portion is annular, a critical dimension of the edge interconnect portion is smaller than a central dimension of the central interconnect portion, the at least one edge interconnect portion is sequentially disposed around the central interconnect portion, and the critical dimensions of the at least two conductive interconnect portions decrease sequentially from the inside to the outside.

[0015] In one embodiment, the bonding pad is cylindrical, a central axis of the bonding pad coincides with a central axis of the central interconnect portion, and a radius of the central interconnect portion is 1 / 4 to 1 / 6 of a radius of the bonding pad.

[0016] In one embodiment, the first dielectric layer includes a first etch stop layer and a first insulating dielectric layer sequentially disposed on the substrate, and / or the second dielectric layer includes a second etch stop layer, a second insulating dielectric layer, and a bonding dielectric layer sequentially disposed on the first dielectric layer.

[0017] A method for manufacturing a semiconductor structure includes:

[0018] Providing a substrate, the substrate including a wiring layer;

[0019] Forming a first dielectric layer covering the wiring layer on a side of the substrate where the wiring layer is provided;

[0020] Forming an interconnect via structure penetrating the first dielectric layer and extending to the wiring layer, the interconnect via structure having at least two conductive interconnect portions with different critical dimensions;

[0021] Forming a second dielectric layer covering the interconnect via structure and the first dielectric layer;

[0022] Forming, within the second dielectric layer, bonding pads corresponding to the interconnect via structures one by one, the bonding pads covering the corresponding interconnect via structures, and a surface of the bonding pad away from the interconnect via structure being recessed. Among the at least two conductive interconnect portions of the same interconnect via structure, the greater the recess depth of the surface of the bonding pad opposite thereto, the greater the critical dimension of the conductive interconnect portion.

[0023] In one embodiment, before forming, within the second dielectric layer, bonding pads corresponding to the interconnect via structures one by one, it further includes:

[0024] Forming a sacrificial layer on the second dielectric layer;

[0025] Within the second dielectric layer, bonding pads corresponding one-to-one to the interconnect via structures are formed, including:

[0026] Etch the sacrificial layer and the second dielectric layer to form a bonding groove exposing the interconnect via structures;

[0027] Form a bonding material layer within the bonding groove and on the upper surface of the sacrificial layer;

[0028] Using the sacrificial layer as a polishing stop layer, perform a first polishing process on the bonding material layer;

[0029] Using the second dielectric layer as a polishing stop layer, perform a second polishing process on the bonding material layer and the sacrificial layer to remove the sacrificial layer and form the bonding pads.

[0030] In one embodiment, the polishing rate of the first polishing process is greater than that of the second polishing process.

[0031] A method for preparing a bonding structure includes:

[0032] Provide two structures to be bonded, where at least one structure to be bonded is the semiconductor structure described above;

[0033] Bond the two structures to be bonded through the bonding pads and the second dielectric layer.

[0034] In the above semiconductor structure, its preparation method, and the preparation method of the bonding structure, the interconnect via structures are provided with at least two conductive interconnect portions. And among at least two conductive interconnect portions of the same interconnect via structure, the greater the depression depth of the surface of the corresponding bonding pad, the greater the critical dimension of the conductive interconnect portion. At this time, the expansion of the bonding pad can be made complementary to the expansion of the conductive interconnect portion, which is conducive to achieving or approaching filling the depression on the surface of the bonding pad without voids but not extruding the bonding pad after bonding annealing, and thus can effectively improve the bonding effect. Description of the Drawings

[0035] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment;

[0037] Figure 2 It is a top view schematic diagram of an interconnect via structure provided in an embodiment;

[0038] Figure 3 A top view schematic diagram of the interconnect via structure provided in another embodiment;

[0039] Figure 4 A flowchart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0040] Figures 5 - 12 A schematic diagram of the structure obtained during the manufacturing process of a semiconductor structure provided in an embodiment, wherein, in Figure 5 、 Figure 7 and Figure 8 Figure (a) is a top view schematic diagram, and the remaining drawings are cross-sectional schematic diagrams;

[0041] Figure 13 A cross-sectional schematic diagram of a bonding structure provided in an embodiment.

[0042] Explanation of reference numerals:

[0043] 100 - Substrate, 110 - Wiring layer, 120 - Substrate, 130 - Insulating dielectric layer, 200 - First dielectric layer, 210 - First etch stop layer, 220 - First insulating dielectric layer, 300 - Interconnect via structure, 310 - Central interconnect portion, 320 - Edge interconnect portion, 400 - Second dielectric layer, 410 - Second etch stop layer, 420 - Second insulating dielectric layer, 430 - Bonding dielectric layer, 500 - Bonding pad, 5001 - Bonding material layer, 610 - First patterned photoresist, 620 - Second patterned photoresist, 630 - Third patterned photoresist, 700 - Sacrificial layer, 10 - Central interconnect via, 20 - Edge interconnect via, 30 - Bonding groove. Detailed implementation manners

[0044] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion.

[0047] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0048] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be ascertained, but one or more other features, integers, steps, operations, elements, components and / or groups are not precluded from existence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0049] As described in the background art, in the existing bonding process, problems are likely to occur where either there will be a gap between the bonding pads after bonding annealing, or the bonding pads between the bonding pads will be extruded out after bonding annealing.

[0050] For example, before hybrid bonding a wafer or the like, it is necessary to perform chemical mechanical polishing on its surface to form bonding pads in the dielectric layer. Chemical mechanical polishing will produce a dishing effect, causing the surface of the bonding pads to sink. If the degree of the dishing effect is too large, there is a problem that there will be a gap between the bonding pads after bonding annealing. If the degree of the dishing effect is too small, there is a problem that the bonding pads between the bonding pads will be extruded out after bonding annealing.

[0051] Based on this, an embodiment of the present application provides a semiconductor structure and a manufacturing method thereof, and also provides a bonding structure.

[0052] In one embodiment, please refer to Figure 1 , a semiconductor structure is provided for hybrid bonding. The semiconductor structure can be a wafer structure or a chip structure, and no specific limitation is imposed on its specific form here.

[0053] The semiconductor structure includes a substrate 100, a first dielectric layer 200, an interconnect via structure 300, a second dielectric layer 400, and bonding pads 500.

[0054] The substrate 100 includes a wiring layer 110. In addition, the substrate 100 may include a semiconductor substrate 120, semiconductor device structures (not shown) formed on the substrate 120, an insulating dielectric layer 130, etc.

[0055] The substrate 120 may include a silicon (Si) substrate 120, a silicon germanium (SiGe) substrate 120, a silicon germanium carbon (SiGeC) substrate 120, a silicon carbide (SiC) substrate 120, a gallium arsenide (GaAs) substrate 120, an indium arsenide (InAs) substrate 120, an indium phosphide (InP) substrate 120, or other III / V semiconductor substrates 120 or II / VI semiconductor substrates 120. Or, for another example, the substrate 120 may also include substrates 120 such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0056] The semiconductor device structures may include, for example, a memory array and / or peripheral circuits, etc.

[0057] The wiring layer 110 may be disposed in the insulating dielectric layer on the surface of the substrate 100 and is electrically connected to semiconductor device structures such as a memory array and / or peripheral circuits, so as to introduce or lead out the signals of the semiconductor device structures. The material of the wiring layer 110 may include metal materials (such as copper, aluminum), etc.

[0058] The first dielectric layer 200 is located on the side of the substrate 100 where the wiring layer 110 is provided and covers the wiring layer 110. The first dielectric layer 200 may be a single-layer structure or a multi-layer structure.

[0059] As an example, the first dielectric layer 200 may include a first etch stop layer 210 and a first insulating dielectric layer 220 sequentially disposed on the substrate 100. The material of the first etch stop layer 210 may include, but is not limited to, silicon nitride. The material of the first insulating dielectric layer 220 may include, but is not limited to, silicon oxide.

[0060] The interconnect via structure 300 penetrates through the first dielectric layer 200 and extends to the wiring layer 110, thereby being electrically connected to the wiring layer 110. The interconnect via structure 300 may be a single-layer structure or a multi-layer structure.

[0061] As an example, the interconnect via structure 300 may include a first diffusion barrier layer and a first metal layer. The first diffusion barrier layer is located between the first metal layer and the first dielectric layer 200, thereby preventing the metal in the first metal layer from diffusing into the first dielectric layer 200.

[0062] The material of the first diffusion barrier layer may include, but is not limited to, tantalum (Ta), and its thickness may be 20 nm - 40 nm. The material of the first metal layer may include, but is not limited to, copper (Cu).

[0063] At the same time, the interconnect via structure 300 has at least two conductive interconnect portions with different critical dimensions. The conductive interconnect portions may be columnar and / or tubular, etc.

[0064] The second dielectric layer 400 covers the interconnect via structure 300 and the first dielectric layer 200. At the same time, the second dielectric layer 400 may be a single-layer structure or a multi-layer structure.

[0065] As an example, the second dielectric layer 400 includes a second etch stop layer 410, a second insulating dielectric layer 420, and a bonding dielectric layer 430 sequentially disposed on the first dielectric layer 200. The bonding dielectric layer 430 can be used for dielectric layer bonding in subsequent hybrid bonding. The material of the second etch stop layer 410 may include, but is not limited to, silicon nitride. The material of the second insulating dielectric layer 420 may include, but is not limited to, silicon oxide. The material of the bonding dielectric layer 430 may include, but is not limited to, silicon carbonitride.

[0066] The bonding pads 500 are located in the second dielectric layer 400 and are arranged in one-to-one correspondence with the interconnect via structure 300. And the bonding pads 500 cover the corresponding interconnect via structure 300, so that the bonding pads 500 are electrically connected to each conductive interconnect portion of the corresponding interconnect via structure 300, and further electrically connected to the wiring layer 110.

[0067] The bonding pad 500 can be a single-layer structure or a multi-layer structure. As an example, the bonding pad 500 includes a second metal diffusion barrier layer and a second metal layer. The second diffusion barrier layer is located between the second metal layer and the second dielectric layer 400 to prevent the metal in the second metal layer from diffusing into the second dielectric layer 400. The material of the second diffusion barrier layer can include, but is not limited to, tantalum (Ta), and its thickness can be 20nm - 40nm. The material of the second metal layer can include, but is not limited to, copper (Cu).

[0068] At the same time, the surface of the bonding pad 500 away from the interconnect via structure 300 is recessed. The recess on the surface of the bonding pad 500 can be, but is not limited to, caused by the dishing effect of chemical mechanical polishing during the formation of the bonding pad 500. For example, the recess of the bonding pad 500 can be formed by an etching process.

[0069] Among at least two conductive interconnect portions of the same interconnect via structure 300, the greater the recess depth of the surface of the bonding pad 500 opposite thereto, the greater the critical dimension of the conductive interconnect portion.

[0070] When the semiconductor structure is hybrid-bonded to the bonding pad 500 through the second dielectric layer 400, after the bonding annealing, at least two conductive interconnect portions of the interconnect via structure 300 and the bonding pad 500 above them expand simultaneously. At the position where the recess depth of the bonding pad 500 is greater, the thickness of the bonding pad 500 is smaller, and it can be large.

[0071] Therefore, among at least two conductive interconnect portions of the same interconnect via structure 300, the greater the recess depth of the surface of the bonding pad 500 opposite thereto, the smaller the expansion height of the conductive interconnect. And the greater the critical dimension of the conductive interconnect portion, the greater the expansion height of the conductive interconnect portion. The greater the critical dimension of the conductive interconnect portion can make the expansion of the bonding pad 500 and the expansion of the conductive interconnect portion complementary, which is beneficial to achieving or approaching filling the recess on the surface of the bonding pad 500 without voids after the bonding annealing but not extruding the bonding pad 500. At this time, the bonding effect can be effectively improved. At the same time, the requirement for the dishing degree can be reduced at this time, so the requirement for chemical mechanical polishing can be reduced, and then the process window of chemical mechanical polishing can be enlarged.

[0072] In one embodiment, the ratio of the critical dimensions of any two conductive interconnect portions of the same interconnect via structure 300 is equal to the ratio of the recess depths of the surfaces of the corresponding bonding pad 500 at the two positions opposite to the two conductive interconnect portions.

[0073] At this time, after the bonding annealing, it is convenient to make the expansion of the bonding pad 500 and the expansion of the conductive interconnect portion reach or approach balance, which is more beneficial to filling the recess on the surface of the bonding pad 500 without voids but not extruding the bonding pad 500.

[0074] In one embodiment, at positions where the recess depths of the corresponding bonding pads 500 are the same, the critical dimensions of the conductive interconnects are the same.

[0075] At this time, after bonding annealing, the conductive interconnects at positions with the same recess depth can be uniformly expanded, thereby more uniformly reducing the depth of the recessed area of the bonding pad 500, which is more conducive to filling the surface recess of the bonding pad 500 without voids but not extruding the bonding pad 500.

[0076] In one embodiment, please refer to Figure 2 or Figure 3 , at least two conductive interconnects of the same interconnect hole structure 300 include a central interconnect 310 and at least one peripheral interconnect 320 that are concentrically distributed. The central interconnect 310 is cylindrical, and the peripheral interconnect 320 is annular. The critical dimension of the peripheral interconnect 320 is smaller than the central dimension of the central interconnect 310. At least one peripheral interconnect 320 is sequentially arranged around the central interconnect 310, and the critical dimensions of at least two conductive interconnects decrease sequentially from the inside to the outside.

[0077] When the recess on the surface of the bonding pad 500 far from the interconnect hole structure 300 is caused by the dishing effect of chemical mechanical polishing during the formation of the bonding pad 500, the recessed area is usually bowl-shaped. The shape formed by connecting the positions with the same recess depth of the bonding pad 500 is approximately circular, and the circular lines formed by different recess depths are approximately concentric circles.

[0078] Therefore, the cylindrical central interconnect 310 and the annular peripheral interconnects 320 are concentrically distributed, and the critical dimensions of at least two conductive interconnects decrease sequentially from the inside to the outside, so that each conductive interconnect can better expand complementarily with the recessed area of the bonding pad 500, thereby more uniformly and effectively reducing the depth of the bowl-shaped recessed area of the bonding pad 500.

[0079] As an example, while arranging the cylindrical interconnect and the annular peripheral interconnects 320 to be concentrically distributed, the bonding pad 500 can also be arranged to be cylindrical. And the central axis of the bonding pad 500 coincides with the central axis of the central interconnect 310. At the same time, the radius of the central interconnect 310 is set to be 1 / 4 to 1 / 6 of the radius of the bonding pad 500. For example, the radius of the central interconnect 310 is set to be 1 / 5 of the radius of the bonding pad 500.

[0080] At this time, the combined expansion effect of the bonding pad 500 and the conductive interconnects can be more uniform, ensuring that each area of the recess in the bonding pad 500 can be filled by the expanded bonding pad 500, which is conducive to subsequent bonding.

[0081] Of course, in other embodiments, the circular edge interconnecting portion 320 may also be separated into multiple parts, and the intervals are set as multiple sub-interconnecting parts with the same critical dimensions and distributed in a ring shape.

[0082] In one embodiment, please refer to Figure 4 , a method for manufacturing a semiconductor structure is provided, including the following steps:

[0083] Step S10, please refer to Figure 5 , a substrate 100 is provided, and the substrate 100 includes a wiring layer 110;

[0084] Step S20, please continue to refer to Figure 5 , a first dielectric layer 200 covering the wiring layer 110 is formed on one side of the substrate 100 where the wiring layer 110 is provided;

[0085] Step S30, please refer to Figure 8 , an interconnect via structure 300 penetrating the first dielectric layer 200 and extending to the wiring layer 110 is formed, and the interconnect via structure 300 has at least two conductive interconnecting parts with different critical dimensions;

[0086] Step S40, please refer to Figure 10 , a second dielectric layer 400 covering the interconnect via structure 300 and the first dielectric layer 200 is formed;

[0087] Step S60, please refer to Figure 12 , within the second dielectric layer 400, bonding pads 500 corresponding to the interconnect via structure 300 one by one are formed. The bonding pads 500 cover the corresponding interconnect via structure 300, and the surface of the bonding pads 500 away from the interconnect via structure 300 is recessed. Among at least two conductive interconnecting parts of the same interconnect via structure 300, the greater the recessed depth of the surface of the corresponding bonding pad 500, the greater the critical dimension of the conductive interconnecting part.

[0088] In step S10, please refer to Figure 5 , the substrate 100 may include a semiconductor substrate 120, a semiconductor device structure formed on the substrate 120, an insulating dielectric layer 130, etc.

[0089] The substrate 120 may include a silicon (Si) substrate 120, a silicon germanium (SiGe) substrate 120, a silicon germanium carbon (SiGeC) substrate 120, a silicon carbide (SiC) substrate 120, a gallium arsenide (GaAs) substrate 120, an indium arsenide (InAs) substrate 120, an indium phosphide (InP) substrate 120, or other III / V semiconductor substrates 120 or II / VI semiconductor substrates 120. Or, for another example, the substrate 120 may also include substrates 120 such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0090] A semiconductor device structure may include, for example, a memory array and / or peripheral circuits, etc.

[0091] Moreover, the substrate 100 includes a wiring layer 110. The wiring layer 110 may be disposed within an insulating dielectric layer on the surface of the substrate 100 and is electrically connected to semiconductor device structures such as a memory array and / or peripheral circuits, thereby introducing or extracting signals of the semiconductor device structures.

[0092] The material of the wiring layer 110 may include metal materials (such as copper, aluminum), etc., which may be formed on the surface of the substrate 100 through a damascene process or a patterning etching process.

[0093] In step S20, please continue to refer to Figure 5 , a first dielectric layer 200 may be formed on the substrate 100 through a deposition process. The deposition process may include, but is not limited to, one or more of processes such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, plasma enhanced deposition process, and Spin-on Dielectric (SOD) process.

[0094] The first dielectric layer 200 may be a single-layer structure or a multi-layer structure. There is no limitation here.

[0095] As an example, the first dielectric layer 200 may include a first etch stop layer 210 and a first insulating dielectric layer 220. At this time, the first etch stop layer 210 and the first insulating dielectric layer 220 may be sequentially formed on one side of the substrate 100 provided with the wiring layer 110 through a deposition process.

[0096] The material of the first etch stop layer 210 may include, but is not limited to, silicon nitride. The material of the first insulating dielectric layer 220 may include, but is not limited to, silicon oxide.

[0097] In step S30, please refer to Figure 8 , at least two interconnected holes with different critical dimensions may be formed by first etching the first dielectric layer 200. Then, a conductive material is formed within the interconnected holes, thereby forming at least two conductive interconnecting portions with different critical dimensions, that is, an interconnect hole structure 300 is formed. Among them, each conductive interconnecting portion may be formed synchronously or step by step, and there is no limitation here.

[0098] Meanwhile, the interconnect via structure 300 can be a single-layer structure or a multi-layer structure. For example, the interconnect via structure 300 can include a first diffusion barrier layer (not shown) and a first metal layer (not shown) formed in sequence. The material of the first diffusion barrier layer can include, but is not limited to, tantalum (Ta), and its thickness can be 20 nm - 40 nm. The material of the first metal layer can include, but is not limited to, copper (Cu).

[0099] Moreover, when the first dielectric layer 200 can include the first etch stop layer 210 and the first insulating dielectric layer 220, the etching process of the first dielectric layer 200 can be to first etch the first insulating dielectric layer 220 and stop at the first etch stop layer 210, and then etch the first etch stop layer 210 to form an interconnect via exposing the wiring layer 110. At this time, the first etch stop layer 210 can effectively protect the wiring layer 110 during the process of etching the first dielectric layer 200 to form an interconnect via, preventing the wiring layer 110 from being damaged due to over-etching.

[0100] In step S40, the second dielectric layer 400 can also be formed by a deposition process. Meanwhile, the second dielectric layer 400 can be a single-layer structure or a multi-layer structure. There is no limitation here.

[0101] As an example, the second dielectric layer 400 can include a second etch stop layer 410, a second insulating dielectric layer 420, and a bonding dielectric layer 430.

[0102] At this time, please refer to Figure 9 , the second etch stop layer 410 can be first formed on the interconnect via structure 300 and the first dielectric layer 200. Please refer to Figure 10 , then the second insulating dielectric layer 420 is formed on the second etch stop layer 410, and then the bonding dielectric layer 430 is formed on the second insulating dielectric. The bonding dielectric layer 430 can be used for subsequent dielectric layer bonding.

[0103] The material of the second etch stop layer 410 can include, but is not limited to, silicon nitride. The material of the second insulating dielectric layer 420 can include, but is not limited to, silicon oxide. The material of the bonding dielectric layer 430 can include, but is not limited to, silicon carbonitride.

[0104] In step S60, please refer to Figure 10 , the second dielectric layer 400 can be first etched to form a bonding groove 30 exposing the interconnect via structure 300.

[0105] When the second dielectric layer 400 includes a second etch stop layer 410, a second insulating dielectric layer 420, and a bonding dielectric layer 430, the bonding dielectric layer 430 and the second insulating dielectric layer 420 can be etched first, and the etching stops at the second etch stop layer 410. After that, the etch gas or liquid is replaced, and the second etch stop layer 410 is etched. At this time, the second etch stop layer 410 can protect the interconnect hole structure 300 during the etching process of forming the bonding groove 30, preventing over-etching from damaging the interconnect hole structure 300. The thickness of the second etch stop layer 410 can be 60 nm to 100 nm.

[0106] Please refer to Figure 11 , after forming the bonding groove 30, a bonding material layer 5001 can be formed on the upper surface of the structure inside and outside the bonding groove 30. After that, please refer to Figure 12 , the bonding material layer 5001 is subjected to chemical mechanical polishing to remove the bonding material layer 5001 located outside the bonding groove 30, thereby forming a bonding pad 500. At this time, the surface of the bonding pad 500 away from the interconnect hole structure 300 will be recessed due to the Dishing effect of the chemical mechanical polishing.

[0107] As an example, the bonding material layer 5001 includes a second diffusion barrier material layer and a second metal material layer. When forming the bonding pad 500, the second diffusion barrier material layer can be formed first, and then the second metal material layer can be formed by processes such as electroplating. The second metal material layer fills the bonding groove 30. After that, through chemical mechanical polishing, the second diffusion barrier material layer and the second metal material layer located outside the bonding groove 30 are removed to form a second metal diffusion barrier layer and a second metal layer.

[0108] The material of the second diffusion barrier layer can include but is not limited to tantalum (Ta), and its thickness can be 20 nm - 40 nm. The material of the second metal layer can include but is not limited to copper (Cu).

[0109] At this time, the bonding pad 500 includes a second metal diffusion barrier layer and a second metal layer. In other examples, the bonding pad 500 can also be a single-layer structure, which is not limited here.

[0110] Since the bonding material layer 5001 needs to be subjected to chemical mechanical polishing during the formation of the bonding pad 500, the surface of the bonding pad 500 away from the interconnect hole structure 300 will be recessed due to the Dishing effect.

[0111] Of course, the depression on the surface of the bonding pad 500 can also be formed by other means, for example, by etching the bonding pad 500.

[0112] Meanwhile, in this embodiment, among at least two conductive interconnect portions provided in the same interconnect via structure 300, the greater the surface depression depth of the bonding pad 500 opposite thereto, the greater the critical dimension of the conductive interconnect portion.

[0113] When the semiconductor structure is hybrid-bonded to the bonding pad 500 through the second dielectric layer 400, after the bonding annealing, at least two conductive interconnect portions of the interconnect via structure 300 and the bonding pad 500 above them expand simultaneously. At the position where the depression depth of the bonding pad 500 is greater, the thickness of the bonding pad 500 is smaller, and the height by which it can expand is smaller. While the greater the critical dimension of the conductive interconnect portion, the greater the height by which the conductive interconnect portion expands.

[0114] Therefore, among at least two conductive interconnect portions provided in the same interconnect via structure 300, the greater the surface depression depth of the bonding pad 500 opposite thereto, the greater the critical dimension of the conductive interconnect portion, which can make the expansion of the bonding pad 500 complementary to the expansion of the conductive interconnect portion, thus facilitating filling the surface depression of the bonding pad 500 without voids or approaching this state after the bonding annealing without extruding the bonding pad 500. At this time, the bonding effect can be effectively improved. Meanwhile, at this time, the requirement for the Dishing degree can be reduced, thereby reducing the requirement for chemical mechanical polishing, and further enlarging the process window of chemical mechanical polishing.

[0115] In one embodiment, step S30 may include:

[0116] Step S31, please refer to Figure 5 , form a first patterned photoresist 610 on the first dielectric layer 200;

[0117] Step S32, please continue to refer to Figure 5 , based on the first patterned photoresist 610, etch the first dielectric layer 200 to form a central interconnect via 10 in an annular shape;

[0118] Step S33, please refer to Figure 6 , remove the first patterned photoresist 610, and fill the central interconnect via 10 with a central interconnect portion 310;

[0119] Step S34, please refer to Figure 7 , form a second patterned photoresist 620 on the first dielectric layer 200 and the central interconnect portion 310;

[0120] Step S35, please refer to Figure 7 , based on the second patterned photoresist 620, etch the first dielectric layer 200 to form an edge interconnect via 20 in an annular shape surrounding the central interconnect via 10. The edge interconnect via 20 and the central interconnect via 10 are concentrically distributed, and the critical dimension of the edge interconnect via 20 is smaller than the critical dimension of the central interconnect via 10;

[0121] Step S36, please refer to Figure 8 , remove the second patterned photoresist 620, and fill the central interconnect hole 10 with the edge interconnect portion 320.

[0122] In step S31, please refer to Figure 5 , a first photoresist layer can be first coated on the first dielectric layer 200. Then, the first photoresist layer can be exposed and developed to form a first patterned photoresist 610. The first patterned photoresist 610 can have a circular opening, and the circular opening defines the position and shape of the central interconnect hole 10, etc.

[0123] In step S32, please continue to refer to Figure 5 , when the first dielectric layer 200 includes a first etch stop layer 210 and a first insulating dielectric layer 220 sequentially disposed on the substrate 100, the first insulating dielectric layer 220 can be first etched and stopped at the first etch stop layer 210; then the first etch stop layer 210 can be etched to form the central interconnect hole 10 exposing the wiring layer 110. At this time, the first etch stop layer 210 can effectively protect the wiring layer 110 during the process of etching the first dielectric layer 200 to form the central interconnect hole 10, preventing the wiring layer 110 from being damaged due to over-etching.

[0124] As an example, one or more (such as two) central interconnect holes 10 can be formed on the same wiring pattern of the wiring layer 110, so as to form one or more interconnect hole structures 300.

[0125] In step S33, please refer to Figure 6 , the first patterned photoresist 610 can be first removed. Then, a first diffusion barrier material layer is formed on the sidewall, bottom of the central interconnect hole 10, and the upper surface of the first dielectric layer 200 outside the central interconnect hole 10. Then, a first metal material layer is formed on the surface of the first diffusion barrier material layer by an electroplating process or the like, and the first metal material layer fills the remaining area of the central interconnect hole 10. After that, the first diffusion barrier material layer and the first metal material layer outside the central interconnect hole 10 can be removed by a chemical mechanical polishing process to form a first diffusion barrier layer and a first metal layer. At this time, the central interconnect portion 310 includes the first diffusion barrier layer and the first metal layer.

[0126] In step S34, please refer to Figure 7 , a second photoresist layer can be first coated on the upper surface of the first dielectric layer 200 and the upper surface of the central interconnect portion 310. Then, the second photoresist layer can be exposed and developed to form a second patterned photoresist 620. The second patterned photoresist 620 can have an annular opening, and the circular opening defines the position and shape of the edge interconnect hole 20, etc.

[0127] In step S35, referring to Figure 7 , when the first dielectric layer 200 includes a first etch stop layer 210 and a first insulating dielectric layer 220 sequentially disposed on the substrate 100, the first insulating dielectric layer 220 can be etched first and stopped at the first etch stop layer 210; then the first etch stop layer 210 can be etched to form an edge interconnect hole 20 exposing the wiring layer 110. At this time, the first etch stop layer 210 can effectively protect the wiring layer 110 during the process of etching the first dielectric layer 200 to form the edge interconnect hole 20, preventing the wiring layer 110 from being damaged due to over-etching.

[0128] In step S36, referring to Figure 8 , the second patterned photoresist 620 can be removed first. Then, a first diffusion barrier material layer is formed on the sidewalls of the edge interconnect hole 20, the bottom of the edge interconnect hole 20, the upper surface of the first dielectric layer 200 outside the edge interconnect hole 20, and the upper surface of the central interconnect portion 310. Then, a first metal material layer is formed on the surface of the first diffusion barrier material layer by electroplating or other processes, and the first metal material layer fills the remaining area of the edge interconnect hole 20. After that, the first diffusion barrier material layer and the first metal material layer located outside the edge interconnect hole 20 can be removed by chemical mechanical polishing to form a first diffusion barrier layer and a first metal layer. At this time, the edge interconnect portion 320 includes a first diffusion barrier layer and a first metal layer.

[0129] At this time, at least two conductive interconnect portions of the same interconnect hole structure 300 include a central interconnect portion 310 and an edge interconnect portion 320 distributed in concentric circles. And since the critical dimension of the edge interconnect hole 20 is smaller than the critical dimension of the central interconnect hole 10, the critical dimension of the edge interconnect portion 320 is smaller than the critical dimension of the central interconnect portion 310.

[0130] As an example, the critical dimension of the central interconnect portion 310 can be set to be twice the critical dimension of the edge interconnect portion 320. Among them, the critical dimension of the central interconnect portion 310 can be the radius value of the central interconnect portion 310, and the critical dimension of the edge interconnect portion 320 can be its line width value.

[0131] In other embodiments, after forming the central interconnect portion 310, one or more (such as two) edge interconnect portions 320 sequentially disposed around the central interconnect portion 310 can also be formed by lithography, etching and other processes. The sizes of the edge interconnect portions 320 can gradually decrease from the direction close to the central interconnect portion 310 to the direction far from the central interconnect portion 310. And each conductive interconnect portion (including the central interconnect portion 310 and the edge interconnect portion 320) can be, but is not limited to, arranged at equal intervals.

[0132] Each conductive interconnect portion (including the central interconnect portion 310 and the edge interconnect portion 320) that is concentrically distributed and has sequentially changing critical dimensions can better expand and complement the depression of the bonding pad 500 caused by the dishing effect, thereby more uniformly and effectively reducing the depth of the bowl-shaped depression area of the bonding pad 500. At the same time, each conductive interconnect portion (including the central interconnect portion 310 and the edge interconnect portion 320) with different critical dimensions is formed by performing photolithography and etching processes step by step, so as to effectively reduce the etching load effect and prevent damage to the wiring layer 110 during the formation of the interconnect hole structure 300.

[0133] Of course, each conductive interconnect portion with different critical dimensions can also be formed synchronously through a single photomask process, and there is no limitation here.

[0134] In one embodiment, before step S60, please refer to Figure 10 , further including:

[0135] Step S50, forming a sacrificial layer 700 on the second dielectric layer 400.

[0136] The material of the sacrificial layer 700 may include, but is not limited to, silicon oxide.

[0137] At the same time, step S60 includes:

[0138] Step S61, please continue to refer to Figure 10 , etching the sacrificial layer 700 and the second dielectric layer 400 to form a bonding groove 30 exposing the interconnect hole structure 300;

[0139] Step S62, please refer to Figure 11 , forming a bonding material layer 5001 in the bonding groove 30 and on the upper surface of the sacrificial layer 700;

[0140] Step S63, please refer to Figure 12 , using the sacrificial layer 700 as a polishing stop layer, performing a first polishing process on the bonding material layer 5001;

[0141] Step S64, please continue to refer to Figure 12 , using the second dielectric layer 400 as a polishing stop layer, performing a second polishing process on the bonding material layer 5001 and the sacrificial layer 700 to remove the sacrificial layer 700 and form a bonding pad 500.

[0142] In step S61, a third photoresist layer can be first coated on the upper surface of the sacrificial layer 700. Then, the third photoresist layer can be exposed and developed to form a third patterned photoresist 630. The third patterned photoresist 630 can have an opening with a preset shape (such as a circle), and the opening defines the position and shape of the bonding groove 30, etc.

[0143] Then, based on the third patterned photoresist 630, the sacrificial layer 700 and the second dielectric layer 400 are etched to form a bonding groove 30 exposing the interconnect hole structure 300. After that, the third patterned photoresist 630 is removed.

[0144] In step S62, the bonding material layer 5001 can be a single-layer structure or a multi-layer structure.

[0145] As an example, the bonding material layer 5001 includes a second diffusion barrier material layer and a second metal material layer. At this time, the second diffusion barrier material layer can be formed first, and then the second metal material layer can be formed by processes such as electroplating. The second metal material layer fills the remaining space of the bonding groove 30.

[0146] In step S63, the first polishing process on the bonding material layer 5001 can stop on the sacrificial layer 700, so as to prevent the first polishing process from damaging the second dielectric layer 400.

[0147] In step S64, through the second polishing process, the bonding material layer 5001 and the sacrificial layer 700 are polished simultaneously. While forming the bonding pad 500, the sacrificial layer 700 is removed, thus simplifying the process steps.

[0148] In this embodiment, through the setting of the sacrificial layer 700, the chemical mechanical polishing is carried out in two steps. At this time, it is convenient to control the polishing effect. For example, the dishing degree can be adjusted through two polishing processes.

[0149] In one embodiment, it is set that the polishing rate of the first polishing process is greater than the polishing rate of the second polishing process.

[0150] At this time, on the one hand, the polishing efficiency is improved through the first polishing process, and on the other hand, through the second polishing process, the subsequent polishing can be slow and the surface flatness of the second dielectric layer 400 after polishing is high, which is convenient for bonding.

[0151] In one embodiment, please refer to Figure 13 , and a method for preparing a bonding structure is also provided, including:

[0152] Step S1, providing two bonding structures to be bonded, where at least one bonding structure to be bonded is the semiconductor structure of any of the above embodiments;

[0153] Step S2, through the bonding pad 500 and the second dielectric layer 400, the two bonding structures to be bonded are hybrid-bonded.

[0154] In step S1, the forms of the two structures to be bonded may be the same or different. For example, both of the two structures to be bonded are wafer structures. Alternatively, one structure to be bonded is a wafer structure and the other is a chip structure.

[0155] Both of the two structures to be bonded may be semiconductor structures of any of the above embodiments. Or only one of the two structures to be bonded is a semiconductor structure of any of the above embodiments.

[0156] In step S2, during the bonding process, the second dielectric layer 400 can be bonded at room temperature and under atmospheric conditions. Subsequently, the bonding pads 500 are bonded by annealing and metal diffusion. The bonding temperature can be 300°C to 400°C, and the bonding time can be 5h to 10h.

[0157] Since at least one of the two structures to be bonded is a semiconductor structure of any of the above embodiments, that is, at least one semiconductor structure can have a relatively flat surface after bonding annealing, the bonding effect can be effectively improved.

[0158] It should be understood that although Figure 4 the steps in the flowchart are shown sequentially in the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 at least a part of the steps in

[0159] may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0160] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0160] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate including a wiring layer; A first dielectric layer located on a side of the substrate where the wiring layer is provided and covering the wiring layer; An interconnect via structure extending through the first dielectric layer to the wiring layer and having at least two conductive interconnect portions with different critical dimensions; A second dielectric layer covering the interconnect via structure and the first dielectric layer; Bonding pads located within the second dielectric layer, provided in one-to-one correspondence with the interconnect via structure, and the bonding pads covering the corresponding interconnect via structures, with the surface of the bonding pads away from the interconnect via structures being recessed; Wherein, among the at least two conductive interconnect portions of the same interconnect via structure, the greater the surface recess depth of the corresponding bonding pad, the greater the critical dimension of the conductive interconnect portion.

2. The semiconductor structure according to claim 1, characterized in that, The ratio of the critical dimensions of any two conductive interconnect portions of the same interconnect via structure is equal to the ratio of the surface recess depths of two positions of the corresponding bonding pad opposite to the two conductive interconnect portions.

3. The semiconductor structure according to claim 1, characterized in that, At positions where the recess depths of the corresponding bonding pads are the same, the critical dimensions of the conductive interconnect portions are the same.

4. The semiconductor structure according to claim 1, characterized in that, The at least two conductive interconnect portions of the same interconnect via structure include a central interconnect portion and at least one edge interconnect portion arranged in concentric circles. The central interconnect portion is cylindrical, the edge interconnect portion is annular, the critical dimension of the edge interconnect portion is smaller than the central dimension of the central interconnect portion, the at least one edge interconnect portion is sequentially arranged around the central interconnect portion, and the critical dimensions of at least two of the conductive interconnect portions decrease sequentially from the inside to the outside.

5. The semiconductor structure according to claim 4, characterized in that, The bonding pads are cylindrical, the central axis of the bonding pads coincides with the central axis of the central interconnect portion, and the radius of the central interconnect portion is 1 / 4 to 1 / 6 of the radius of the bonding pads.

6. The semiconductor structure according to claim 1, characterized in that, The first dielectric layer includes a first etch stop layer and a first insulating dielectric layer sequentially provided on the substrate, and / or the second dielectric layer includes a second etch stop layer, a second insulating dielectric layer, and a bonding dielectric layer sequentially provided on the first dielectric layer.

7. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a wiring layer; Forming a first dielectric layer covering the wiring layer on a side of the substrate where the wiring layer is provided; Forming an interconnect via structure extending through the first dielectric layer and reaching the wiring layer, the interconnect via structure having at least two conductive interconnect portions with different critical dimensions; Forming a second dielectric layer covering the interconnect via structure and the first dielectric layer; Forming, within the second dielectric layer, bonding pads in one-to-one correspondence with the interconnect via structure, the bonding pads covering the corresponding interconnect via structures, and the surface of the bonding pads away from the interconnect via structures being recessed, wherein, among the at least two conductive interconnect portions of the same interconnect via structure, the greater the surface recess depth of the corresponding bonding pad, the greater the critical dimension of the conductive interconnect portion.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, Before forming, within the second dielectric layer, bonding pads in one-to-one correspondence with the interconnect via structure, further comprising: Forming a sacrificial layer on the second dielectric layer; Forming, within the second dielectric layer, bonding pads in one-to-one correspondence with the interconnect via structure, including: Etch the sacrificial layer and the second dielectric layer to form a bonding groove exposing the interconnect via structure; Form a bonding material layer in the bonding groove and on the upper surface of the sacrificial layer; Using the sacrificial layer as a polishing stop layer, perform a first polishing process on the bonding material layer; Using the second dielectric layer as a polishing stop layer, perform a second polishing process on the bonding material layer and the sacrificial layer to remove the sacrificial layer and form the bonding pad.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, The polishing rate of the first polishing process is greater than the polishing rate of the second polishing process.

10. A method for manufacturing a bonding structure, characterized in that, Comprising: Provide two structures to be bonded, wherein at least one structure to be bonded is the semiconductor structure according to any one of claims 1-6; Bond the two structures to be bonded through the bonding pad and the second dielectric layer by hybrid bonding.

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