Test structure and test method

Abstract

The invention discloses a test structure and a test method, and the structure comprises a substrate which comprises a cutting channel region; the test signal loading unit is located at the top of the substrate in the cutting channel area, the test signal loading unit comprises a plurality of test signal loading ends, the plurality of test signal loading ends are arranged in a matrix at intervals along a first direction and a second direction, and the first direction is perpendicular to the second direction; and the to-be-tested device structure is located at the top of the substrate in the peripheral area of the test signal loading unit, and the to-be-tested device structure is electrically connected with the test signal loading unit. The effective area utilization rate of the test structure is improved, and the test performance of the test structure is further improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a test structure and a test method. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are developing towards higher element density and higher integration, and semiconductor process nodes are continuously decreasing following Moore's Law. As the most basic semiconductor transistors, transistors are currently widely used. Therefore, with the increase in the element density and integration of semiconductor transistors, in order to adapt to the reduction of process nodes, the channel length of transistors has to be continuously shortened.

[0003] The size of the back-end metal lines is getting smaller and smaller, and the failures caused by metal line breakage or short circuit are numerous, which will greatly delay the R & D efficiency.

[0004] Currently, the test performance of the back-end metal lines still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improving the performance of the semiconductor structure.

[0006] To solve the above problems, embodiments of the present invention provide a test structure, including: a substrate, the substrate includes a dicing street area; a test signal loading unit, located on the top of the substrate in the dicing street area, the test signal loading unit includes a plurality of test signal loading ends, and the plurality of test signal loading ends are arranged at matrix intervals along a first direction and a second direction, and the first direction and the second direction are perpendicular to each other; a device under test structure, located on the top of the substrate in the peripheral area of the test signal loading unit, and the device under test structure is electrically connected to the test signal loading unit.

[0007] Optionally, along the first direction, the plurality of test signal loading ends include first test signal loading ends in odd columns and second test signal loading ends in even columns; or, along the second direction, the plurality of test signal loading ends include first test signal loading ends in odd columns and second test signal loading ends in even columns.

[0008] Optionally, the distance between the plurality of test signal loading ends along the first direction is 10 micrometers to 20 micrometers.

[0009] Optionally, the distance between the plurality of test signal loading ends along the second direction is 20 micrometers to 40 micrometers.

[0010] Optionally, the device under test structure includes a plurality of sub-device under test structures, and the plurality of sub-device under test structures are arranged on both sides of the test signal loading unit; or, the device under test structure includes a plurality of sub-device under test structures, and the plurality of sub-device under test structures are arranged on one side of the test signal loading unit.

[0011] Optionally, the plurality of sub-device under test structures are arranged in parallel at intervals along a first direction, and the size of the sub-device under test structure in the first direction is consistent with the size of the test signal loading end in the first direction; or, the plurality of sub-device under test structures are arranged in parallel at intervals along the first direction, and the size of the sub-device under test structure in the first direction is greater than the size of the test signal loading end in the first direction.

[0012] Optionally, the sub-device under test structure includes one or more metal layers stacked longitudinally, and the multiple metal layers are electrically connected.

[0013] Optionally, the distance between the device under test structure and the test signal loading unit in a second direction is 2 micrometers to 10 micrometers.

[0014] Optionally, the test structure further includes: a first metal wire located between the test signal loading end and the device under test structure, and the test signal loading end is electrically connected to the device under test structure through the first metal wire.

[0015] Correspondingly, an embodiment of the present invention provides a test method, including: providing the test structure provided by the embodiment of the present invention; loading a test electrical signal on the test signal loading unit to form a test path between the test signal loading unit and the device under test structure; and acquiring test data of the device under test structure under the test path.

[0016] Optionally, along the first direction, the plurality of test signal loading ends include odd-numbered first test signal loading ends and even-numbered second test signal loading ends; or, along the second direction, the plurality of test signal loading ends include odd-numbered first test signal loading ends and even-numbered second test signal loading ends.

[0017] Optionally, the step of loading a test electrical signal on the test signal loading unit includes: loading a first test electrical signal on the first test signal loading end; after loading the first test electrical signal, loading a second test electrical signal on the second test signal loading end; or, loading a first test electrical signal on the second test signal loading end; after loading the first test electrical signal, loading a second test electrical signal on the first test signal loading end.

[0018] Optionally, the step of loading a first test electrical signal on the first test signal loading end includes: loading a first test electrical signal on some of the first test signal loading ends simultaneously; or, loading a first test electrical signal on all of the first test signal loading ends simultaneously.

[0019] Optionally, the steps of obtaining the test data of the device structure under test in the test path include: obtaining the electrical signal test value of the test path; and determining the test data of the device structure under test based on the electrical signal test value.

[0020] Optionally, the electrical signal test value includes a current value or a resistance value.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0022] The embodiment of the present invention provides a test structure. The test signal loading unit is located on the top of the substrate in the scribe lane area. The test signal loading unit includes a plurality of test signal loading ends, and the plurality of test signal loading ends are arranged at matrix intervals along a first direction and a second direction, and the first direction and the second direction are perpendicular to each other. The device structure under test is located on the top of the substrate in the peripheral area of the test signal loading unit, and the device structure under test is electrically connected to the test signal loading unit. Compared with the solution of arranging the device structure under test between adjacent test signal loading ends, in the embodiment of the present invention, the device structure under test is arranged in the peripheral area of the test signal loading unit. During the process of setting the test signal loading ends, the distance between adjacent test signal loading ends can be further reduced, which means that the number of test signal loading ends that can be set per unit area becomes more. Correspondingly, during the process of setting the device structure under test, the distance between adjacent device structures under test can be further reduced, which means that the number of device structures under test that can be set per unit area also becomes more. That is to say, the number of test signal loading ends and the number of device structures under test that can be set per unit area both become more, so that the effective area utilization rate of the test structure is improved, and further the test performance of the test structure is improved. Description of the Drawings

[0023] Figures 1 to 3 is a schematic structural diagram corresponding to an embodiment of the test structure of the present invention;

[0024] Figure 4 is a flowchart of the steps of an embodiment of the test method of the present invention. Detailed Embodiments

[0025] As can be seen from the background art, during the current electrical reliability test of the device structure under test (such as the back-end metal wire), in the solution of arranging the device structure under test between adjacent test signal loading ends, the distance between adjacent test signal loading ends is too large, so that the effective area utilization rate of the test structure cannot be improved, thus affecting the test performance of the test structure.

[0026] In order to solve the technical problem, an embodiment of the present invention provides a test structure, including: a substrate, the substrate including a cutting path area; a test signal loading unit, located on the top of the substrate in the cutting path area, the test signal loading unit including a plurality of test signal loading terminals, the plurality of test signal loading terminals are arranged in a matrix along a first direction and a second direction, and the first direction and the second direction are perpendicular to each other; a device to be tested structure, located on the top of the substrate in the peripheral area of ​​the test signal loading unit, the device to be tested structure is electrically connected to the test signal loading unit.

[0027] The embodiment of the present invention provides a test structure, wherein a test signal loading unit is located at the top of a substrate in a cutting path area, the test signal loading unit includes a plurality of test signal loading terminals, the plurality of test signal loading terminals are arranged in a matrix along a first direction and a second direction, the first direction and the second direction are perpendicular to each other, a device to be tested structure is located at the top of the substrate in a peripheral area of ​​the test signal loading unit, the device to be tested structure is electrically connected to the test signal loading unit, and compared with a solution in which the device to be tested structure is arranged between adjacent test signal loading terminals, the embodiment of the present invention arranges the device to be tested structure in the peripheral area of ​​the test signal loading unit, and in the process of setting the test signal loading terminals, the distance between adjacent test signal loading terminals can be further reduced, which means that the number of test signal loading terminals that can be set within a unit area is increased, and accordingly, in the process of setting the device to be tested structure, the distance between adjacent device to be tested structures can be further reduced, which means that the number of device to be tested structures that can be set within a unit area is also increased, that is, the number of test signal loading terminals that can be set within a unit area and the number of device to be tested structures are both increased, thereby improving the effective area utilization rate of the test structure, and further improving the test performance of the test structure.

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figures 1 to 3 is a schematic diagram of a structure corresponding to an embodiment of a test structure of the present invention, wherein: Figure 3 yes Figure 2 Cross-sectional view along the AA direction.

[0030] The test structure includes: a substrate (not shown), the substrate includes a cutting path area 100A; a test signal loading unit 106, located on the top of the substrate in the cutting path area 100A, the test signal loading unit 106 includes a plurality of test signal loading terminals 100, and the plurality of test signal loading terminals 100 are arranged along a first direction (such as Figure 1 X direction) and the second direction (as shown in Figure 1They are arranged at matrix intervals in the Y direction shown in the figure, and the first direction and the second direction are perpendicular to each other; the device under test structure 102 is located at the top of the substrate in the peripheral area of the test signal loading unit 106, and the device under test structure 102 is electrically connected to the test signal loading unit 106.

[0031] It should be noted that the test signal loading unit is located at the top of the substrate in the dicing street area 100A. The test signal loading unit 106 includes a plurality of test signal loading terminals 100. The plurality of test signal loading terminals 100 are arranged at matrix intervals along the first direction and the second direction, and the first direction and the second direction are perpendicular to each other. The device under test structure 102 is located at the top of the substrate in the peripheral area of the test signal loading unit 106, and the device under test structure 102 is electrically connected to the test signal loading unit 106. Compared with the solution of arranging the device under test structure 102 between adjacent test signal loading terminals 100, in the embodiment of the present invention, the device under test structure 102 is arranged in the peripheral area of the test signal loading unit 106. During the process of setting the test signal loading terminals 100, the distance between adjacent test signal loading terminals 100 can be further reduced, which means that the number of test signal loading terminals 100 that can be set per unit area becomes larger. Correspondingly, during the process of setting the device under test structure 102, the distance between adjacent device under test structures 102 can be further reduced, which means that the number of device under test structures 102 that can be set per unit area also becomes larger. That is to say, the number of test signal loading terminals 100 and the number of device under test structures 102 that can be set per unit area both become larger, so that the effective area utilization rate of the test structure is improved, and further the test performance of the test structure is improved.

[0032] The substrate provides a process platform for setting the test structure.

[0033] In this embodiment, the substrate includes a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0034] The dicing street area 100A is the area for setting the test structure. At the same time, during the subsequent process of dicing the wafer, the wafer is diced along the dicing street area 100A.

[0035] The test signal loading unit 106 is used as the loading terminal for loading the test electrical signal to the device under test structure 102. During the subsequent process of testing the test structure, the test electrical signal is loaded to the test signal loading unit 106 through the test probe.

[0036] As an example, the test signal loading unit 106 is located at the top of the substrate in the dicing street area 100A. The test signal loading unit 106 includes a plurality of test signal loading terminals 100, and the plurality of test signal loading terminals 100 are arranged at matrix intervals in the first direction and the second direction, and the first direction and the second direction are perpendicular to each other.

[0037] It should be noted that by setting a plurality of test signal loading terminals 100, the test signal loading unit 106 can load test electrical signals on a plurality of device structures 102 to be tested at the same time. That is to say, two test signal loading terminals 100 (one end is a positive voltage signal terminal and the other end is a zero potential signal terminal) are used for a single device structure 102 to be tested, so that the test structure can load test electrical signals on a plurality of device structures 102 to be tested.

[0038] As an example, along the first direction, the plurality of test signal loading terminals 100 include first test signal loading terminals 150 in odd columns and second test signal loading terminals 151 in even columns.

[0039] Specifically, in the subsequent process of testing the test structure, when loading test electrical signals on the test signal loading unit 106 through test probes, limited by the minimum distance between adjacent test probes, it is necessary to first load test electrical signals on the first test signal loading terminals 150 in odd columns through the test probes, and then load test electrical signals on the second test signal loading terminals 151 in even columns.

[0040] In other embodiments, along the second direction, the plurality of test signal loading terminals 100 may also include first test signal loading terminals 150 in odd columns and second test signal loading terminals 151 in even columns.

[0041] It should be noted that the distance between the plurality of test signal loading terminals 100 spaced apart in the first direction should not be too large or too small. If the distance between the plurality of test signal loading terminals 100 spaced apart in the first direction is too large, it is easy to cause too few test signal loading terminals 100 placed per unit area, reducing the available utilization rate of the effective area of the test structure, thus affecting the test efficiency of the test structure; if the distance between the plurality of test signal loading terminals 100 in the first direction is too small, during the formation process of the test signal loading terminals 100, the formation process difficulty of the test signal loading terminals 100 is increased, and at the same time, the probability of short circuit between adjacent test signal loading terminals 100 is increased. In the subsequent process of testing the test structure, it is easy to cause a decrease in the accuracy of the test results, thus affecting the performance of the test structure. Therefore, in this embodiment, the distance between the plurality of test signal loading terminals 100 spaced apart in the first direction is 10 micrometers to 20 micrometers.

[0042] It should also be noted that the distance between multiple test signal loading terminals 100 spaced apart in the second direction should not be too large or too small. If the distance between multiple test signal loading terminals 100 spaced apart in the second direction is too large, it is likely to result in too few test signal loading terminals 100 placed per unit area, reducing the available utilization rate of the effective area of the test structure, thereby affecting the test efficiency of the test structure. If the distance between multiple test signal loading terminals 100 in the second direction is too small, during the formation process of the test signal loading terminals 100, the formation process difficulty of the test signal loading terminals 100 increases. At the same time, the probability of short - circuit between adjacent test signal loading terminals 100 also increases. During the subsequent testing process of the test structure, it is likely to lead to a decrease in the accuracy of the test results, thereby affecting the performance of the test structure. Therefore, in this embodiment, the distance between multiple test signal loading terminals 100 spaced apart in the second direction is 20 micrometers to 40 micrometers.

[0043] As Figure 1 and Figure 2 shown, multiple test signal loading terminals 100 are arranged in an m - row * n - column layout. Specifically, m is 4 and n is 12.

[0044] In other embodiments, m and n can also be other natural numbers.

[0045] Specifically, the device - under - test structure 102 is arranged in the peripheral area of the test signal loading unit 106. During the process of setting the test signal loading terminals 100, the distance between adjacent test signal loading terminals 100 can be further reduced, which means that the number of test signal loading terminals 100 that can be set per unit area becomes more. Correspondingly, during the process of setting the device - under - test structure 102, the distance between adjacent device - under - test structures 102 can be further reduced, which means that the number of device - under - test structures 102 that can be set per unit area also becomes more. That is to say, the number of test signal loading terminals 100 and the number of device - under - test structures 102 that can be set per unit area both become more, thereby improving the available utilization rate of the effective area of the test structure, and further improving the test performance of the test structure.

[0046] As an example, the device - under - test structure 102 is located at the top of the substrate in the peripheral area of the test signal loading unit 106, and the device - under - test structure 102 is electrically connected to the test signal loading unit 106.

[0047] It should be noted that the electrical connection between the device - under - test structure 102 and the test signal loading unit 106 enables the test signal loading unit 106 to form a test path with the device - under - test structure 102, so that a test signal can be applied to the device - under - test structure 102 through the test signal loading terminal 100, thereby judging the test data of the device - under - test structure 102.

[0048] Specifically, the test data refers to the electrical reliability of the device structure to be tested.

[0049] As an example, the device structure 102 to be tested includes a plurality of sub-device structures 101 to be tested, and the plurality of sub-device structures 101 to be tested are arranged on both sides of the test signal loading unit 106.

[0050] Specifically, by arranging the plurality of sub-device structures 101 to be tested on both sides of the test signal loading unit 106, the number of sub-device structures 101 to be tested placed per unit area of the test structure can be made large enough, further improving the utilization rate of the effective area of the test structure.

[0051] In other embodiments, the device structure 102 to be tested includes a plurality of sub-device structures 101 to be tested, and the plurality of sub-device structures 101 to be tested are arranged on one side of the test signal loading unit 106.

[0052] In this embodiment, the plurality of sub-device structures 101 are arranged at intervals and in parallel in the first direction, and the size of the sub-device structure 101 in the first direction is consistent with the size of the test signal loading end 100 in the first direction.

[0053] It should be noted that the plurality of sub-device structures 101 are arranged at intervals and in parallel in the first direction, reducing the probability of short circuit between adjacent sub-device structures 101, thereby affecting the test results of the test structure.

[0054] It should also be noted that the size of the sub-device structure 101 in the first direction is consistent with the size of the test signal loading end 100 in the first direction, that is to say, the sub-device structure 101 and the plurality of test signal loading ends 100 are on the same horizontal line in the second direction. Correspondingly, in the second direction, adjacent sub-device structures 101 share the plurality of test signal loading ends 100, so that the test signal loading ends 100 in the test signal loading unit 106 can be maximally utilized by the plurality of sub-device structures 101.

[0055] In this embodiment, the plurality of sub-device structures 101 are arranged at intervals and in parallel in the first direction, and the size of the sub-device structure 101 in the first direction is greater than the size of the test signal loading end 100 in the first direction.

[0056] Specifically, the size of the sub-device structure 101 in the first direction is greater than the size of the test signal loading end 100 in the first direction, so that the area occupied by the sub-device structure 101 is large enough, which can reduce the process difficulty of forming the sub-device structure 101. At the same time, it is also beneficial to set the sub-device structure 101 as a multi-layer metal layer, and during the subsequent test of the test structure, the test data (i.e., electrical reliability) of each metal layer can be tested.

[0057] As Figure 3 shown, as an example, the sub-device-under-test structure 101 includes one or more metal layers 120 stacked longitudinally, and the multiple metal layers 120 are electrically connected to each other.

[0058] Specifically, by setting the sub-device-under-test structure 101 as one or more metal layers 120 stacked longitudinally, during the subsequent test of the sub-device-under-test structure 101, that is, testing the test data (i.e., electrical reliability) of the metal layer 120 to determine the electrical reliability of the metal layer 120.

[0059] In other embodiments, the sub-device-under-test structure 101 can also be other film layer structures to be tested (such as the contact resistance between M0 and the source / drain doping layer).

[0060] It should be noted that the distance between the device-under-test structure 102 and the test signal loading unit 106 in the second direction should not be too large or too small. If the distance between the device-under-test structure 102 and the test signal loading unit 106 in the second direction is too large, it will waste too much of the effective area of the test structure and reduce the utilization rate of the effective area of the test structure; if the distance between the device-under-test structure 102 and the test signal loading unit 106 in the second direction is too small, it will increase the probability of short circuit between the device-under-test structure 102 and the test signal loading unit 106, thereby increasing the probability of the test structure failing, and further affecting the accuracy of the test result of the test structure. Therefore, in this embodiment, the distance between the device-under-test structure 102 and the test signal loading unit 106 in the second direction is 2 micrometers to 10 micrometers.

[0061] In this embodiment, the test structure further includes: a first metal wire (not shown in the figure), located between the test signal loading end 100 and the device-under-test structure 102, and the test signal loading end 100 is electrically connected to the device-under-test structure 102 through the first metal wire.

[0062] Specifically, the first metal wire is used to realize the electrical connection between the test signal loading end 100 and the device-under-test structure 102.

[0063] As an example, the material of the first metal wire includes copper.

[0064] Correspondingly, the present invention also provides a test method. Figure 4 It is a flowchart of the steps of an embodiment of the test method of the present invention.

[0065] In this embodiment, the test method includes the following basic steps:

[0066] Step S1: Provide the test structure provided in the foregoing embodiment;

[0067] Step S2: Apply a test electrical signal to the test signal loading unit to form a test path between the test signal loading unit and the device under test structure.

[0068] Step S3: Obtain the test data of the device under test structure under the test path.

[0069] In the test method provided by the embodiments of the present invention, the device under test structure is arranged in the peripheral area of the test signal loading unit. During the process of setting the test signal loading terminals, the distance between adjacent test signal loading terminals can be further reduced, which means that the number of test signal loading terminals that can be set per unit area increases. Correspondingly, during the process of setting the device under test structure, the distance between adjacent devices under test structures can be further reduced, which means that the number of devices under test structures that can be set per unit area also increases. That is to say, the number of test signal loading terminals and the number of devices under test structures that can be set per unit area both increase, thereby improving the utilization rate of the effective area of the test structure. During the process of testing the device under test structure, the number of devices under test structures that can be tested per unit time can be increased, thereby further improving the test efficiency of the test structure.

[0070] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following combines Figure 4 to make a detailed description of the specific embodiments of the present invention.

[0071] Refer to Figure 4 , and execute Step S1: Provide the test structure provided in the foregoing embodiments.

[0072] For the detailed description of the foregoing embodiments of the invention, refer to the description of the test structure, which will not be elaborated here.

[0073] As an example, along the first direction, the multiple test signal loading terminals include the first test signal loading terminals in odd columns and the second test signal loading terminals in even columns.

[0074] Specifically, during the subsequent testing process of the test structure, when applying a test electrical signal to the test signal loading unit through the test probe, limited by the minimum distance between adjacent test probes, it is necessary to first apply the test electrical signal to the first test signal loading terminals in odd columns through the test probe, and then apply the test electrical signal to the second test signal loading terminals in even columns.

[0075] In other embodiments, along the second direction, the multiple test signal loading terminals may also include the first test signal loading terminals in odd columns and the second test signal loading terminals in even columns.

[0076] Execute step S2: Apply a test electrical signal to the test signal loading unit so that the test signal loading unit and the device structure under test form a test path.

[0077] Specifically, by forming a test path with the test signal loading unit and the device structure under test, after applying a test electrical signal to the test signal loading unit in the subsequent process, the electrical signal test value in the test path can be obtained, and then the test data (i.e., electrical reliability) of the device structure under test can be judged through the electrical signal test value.

[0078] In this embodiment, the step of applying a test electrical signal to the test signal loading unit includes: applying a first test electrical signal to the first test signal loading terminal; after applying the first test electrical signal, applying a second test electrical signal to the second test signal loading terminal.

[0079] Specifically, during the process of testing the test structure, when applying a test electrical signal to the test signal loading unit through a test probe, limited by the minimum distance between adjacent test probes, it is necessary to first apply a test electrical signal to the first test signal loading terminals of the odd columns through the test probe, and then apply a test electrical signal to the second test signal loading terminals of the even columns.

[0080] In other embodiments, the step of applying a test electrical signal to the test signal loading unit may further include: applying a first test electrical signal to the second test signal loading terminal; after applying the first test electrical signal, applying a second test electrical signal to the first test signal loading terminal.

[0081] As an example, the step of applying a first test electrical signal to the first test signal loading terminal includes: applying a first test electrical signal to some of the first test signal loading terminals simultaneously.

[0082] In other embodiments, the step of applying a first test electrical signal to the first test signal loading terminal may further include: applying a first test electrical signal to all of the first test signal loading terminals simultaneously.

[0083] Execute step S3: Obtain the test data of the device structure under test under the test path.

[0084] It should be noted that the test data refers to the electrical reliability of the device structure under test.

[0085] Specifically, by obtaining the electrical reliability of the device structure under test under the test path, the product yield of the device structure under test can be judged.

[0086] As an example, the step of obtaining the test data of the device structure under test under the test path includes: obtaining the electrical signal test value of the test path; judging the test data of the device structure under test through the electrical signal test value.

[0087] The test data refers to the electrical reliability of the device structure to be tested.

[0088] Specifically, by obtaining the electrical signal test value of the test path, the electrical signal test value can be compared with the ideal electrical signal test value. When the difference between the electrical signal test value and the ideal electrical signal test value is too large, it can be determined that the electrical reliability of the device structure to be tested is low. When the difference between the electrical signal test value and the ideal electrical signal test value is too small or equal, it can be determined that the electrical reliability of the device structure to be tested is high.

[0089] In this embodiment, the electrical signal test value includes a current value or a resistance value.

[0090] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A test structure, characterized in that, Comprising: A substrate, the substrate including a scribing lane area; A test signal loading unit, located on top of the substrate in the scribing lane area, the test signal loading unit including a plurality of test signal loading terminals, the plurality of test signal loading terminals being arranged at matrix intervals along a first direction and a second direction, the first direction and the second direction being perpendicular to each other; A device under test structure, located on top of the substrate in the peripheral area of the test signal loading unit, the device under test structure being electrically connected to the test signal loading unit.

2. The test structure according to claim 1, characterized in that, Along the first direction, the plurality of test signal loading terminals include first test signal loading terminals in odd-numbered columns and second test signal loading terminals in even-numbered columns; Alternatively, along the second direction, the plurality of test signal loading terminals include first test signal loading terminals in odd-numbered columns and second test signal loading terminals in even-numbered columns.

3. The test structure according to claim 1, characterized in that, The distance between adjacent ones of the plurality of test signal loading terminals along the first direction is 10 micrometers to 20 micrometers.

4. The test structure according to claim 1, characterized in that, The distance between adjacent ones of the plurality of test signal loading terminals along the second direction is 20 micrometers to 40 micrometers.

5. The test structure according to claim 1, characterized in that, The device under test structure includes a plurality of sub-devices under test structures, the plurality of sub-devices under test structures being arranged on both sides of the test signal loading unit; Alternatively, the device under test structure includes a plurality of sub-devices under test structures, the plurality of sub-devices under test structures being arranged on one side of the test signal loading unit.

6. The test structure according to claim 5, characterized in that, The plurality of sub-devices under test structures are arranged in parallel at intervals along the first direction, and the size of the sub-device under test structure in the first direction is the same as the size of the test signal loading terminal in the first direction; Or, The plurality of sub-devices under test structures are arranged in parallel at intervals along the first direction, and the size of the sub-device under test structure in the first direction is greater than the size of the test signal loading terminal in the first direction.

7. The test structure according to claim 5, characterized in that, The sub-device under test structure includes one or more metal layers stacked longitudinally, and the plurality of metal layers are electrically connected to each other.

8. The test structure according to claim 1, characterized in that, The distance between the device under test structure and the test signal loading unit in the second direction is 2 micrometers to 10 micrometers.

9. The test structure according to claim 1, characterized in that, The test structure further includes: a first metal wire, located between the test signal loading terminal and the device under test structure, the test signal loading terminal being electrically connected to the device under test structure through the first metal wire.

10. A test method, characterized in that, Comprising: Providing the test structure according to any one of claims 1 to 9; Loading a test electrical signal on the test signal loading unit to form a test path between the test signal loading unit and the device under test structure; Obtaining test data of the device under test structure under the test path.

11. The test method according to claim 10, characterized in that, Along the first direction, the plurality of test signal loading terminals include first test signal loading terminals in odd-numbered columns and second test signal loading terminals in even-numbered columns; Alternatively, along the second direction, the plurality of test signal loading terminals include first test signal loading terminals in odd-numbered columns and second test signal loading terminals in even-numbered columns.

12. The test method according to claim 11, characterized in that, The step of loading a test electrical signal on the test signal loading unit includes: loading a first test electrical signal on the first test signal loading terminal; after loading the first test electrical signal, loading a second test electrical signal on the second test signal loading terminal; Alternatively, apply a first test electrical signal to the second test signal loading terminal; after applying the first test electrical signal, apply a second test electrical signal to the first test signal loading terminal.

13. The test method according to claim 12, characterized in that, The step of applying a first test electrical signal to the first test signal loading terminal includes: simultaneously applying a first test electrical signal to some of the first test signal loading terminals; alternatively, simultaneously apply a first test electrical signal to all of the first test signal loading terminals.

14. The test method according to claim 10, wherein, The step of obtaining test data of the device structure under test in the test path includes: obtaining an electrical signal test value of the test path; judging the test data of the device structure under test based on the electrical signal test value.

15. The test method according to claim 14, wherein, The electrical signal test value includes a current value or a resistance value.

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