Semiconductor structure and overlay error measurement method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and an overlay error measurement method thereof, relates to the technical field of semiconductors, and aims to more easily detect the parallel side edge contours of a first identifier and a second identifier, facilitate the improvement of the precision of measuring the distance between two adjacent sides of the first identifier and the second identifier, and improve the alignment precision of the two semiconductor structures. The first semiconductor structure comprises a first identifier; the material of the first identifier comprises a conductive material. The second semiconductor structure is arranged on one side of the first semiconductor structure and comprises a plurality of second marks. The second identifier extends along the stacking direction of the first semiconductor structure and the second semiconductor structure, and one end of the second identifier is exposed from the surface of the second semiconductor structure. At least part of the second identifiers are located on at least one side of the first identifier in the direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure, and a gap is formed between the second identifiers and the first identifier. And at least one side edge of the second identifier is parallel to the side edge of the first identifier.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor technology, including but not limited to a semiconductor structure and a method for measuring overlay error thereof. Background Art

[0002] Typical overlay measurement refers to detecting the offset degree between an upper layer mark and a lower layer mark by using marks prepared in advance on the top surface of a wafer for overlay measurement.

[0003] With the development of large-scale integrated circuits, the feature size of circuits is continuously miniaturized, and integrated chips are developing in three dimensions. In a structure where multiple chips are stacked, based on the structures of the upper layer mark and the lower layer mark, the method of measuring the offset degree between the two cannot meet the requirements for the alignment accuracy of the integrated structure of multiple stacked chips. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a semiconductor structure and a method for measuring overlay error thereof to solve at least one problem in the prior art, which can more easily detect the side profiles where the first mark and the second mark are parallel to each other, and can improve the alignment accuracy of adjacent semiconductor structures.

[0005] The technical solution of the embodiments of the present application is implemented as follows:

[0006] In a first aspect, embodiments of the present application provide a semiconductor structure. The semiconductor structure includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first mark; the material of the first mark includes a conductive material. The second semiconductor structure is disposed on one side of the first semiconductor structure and includes a plurality of second marks; the second marks extend along the stacking direction of the first semiconductor structure and the second semiconductor structure, and one end thereof is exposed from the surface of the second semiconductor structure.

[0007] Wherein, along the direction perpendicular to the stacking of the first semiconductor structure and the second semiconductor structure, at least some of the plurality of second marks are located on at least one side of the first mark and have a gap with the first mark; at least one side edge of the second mark is parallel to the side edge of the first mark.

[0008] In some examples, the plurality of second marks are arranged at intervals along a first direction; the first direction is parallel to the extending direction of the first mark and perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure.

[0009] Among the side edges on the same side of three adjacent second identifiers along the first direction, the side edge of the third second identifier is on the side where the side edge of the second second identifier is away from the side edge of the first second identifier along the second direction. The second direction is perpendicular to the first direction and perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure.

[0010] In some examples, a plurality of the second identifiers arranged at intervals along the first direction among the plurality of second identifiers form a group. The dimension of a group of second identifiers along the second direction is greater than twice the dimension of the first identifier along the second direction.

[0011] In some examples, along the first direction, the spacing between two adjacent second identifiers is equal. Along the second direction, the spacing between two adjacent second identifiers is equal.

[0012] In some examples, along the first direction, the spacing between a plurality of the second identifiers and the first identifier along the second direction increases and / or decreases.

[0013] In some examples, along the extending direction of the first identifier, the spacing between two adjacent second identifiers is greater than or equal to the dimension of the second identifier.

[0014] In some examples, along the direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure, the shape of the second identifier includes a quasi-square.

[0015] In some examples, a plurality of the second identifiers on the same side of the first identifier form a group. Two groups of second identifiers are arranged symmetrically or centrosymmetrically along the extending direction of the first identifier.

[0016] In some examples, along the direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure, a plurality of the first identifiers are arranged at intervals and enclose an annular region. A plurality of the second identifiers are located within the annular region and on one side of at least one of the first identifiers.

[0017] In some examples, the first identifier includes a main body portion, a protruding portion extending along a first direction, and a protruding portion extending along a third direction; the first direction intersects the third direction and is perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure. A plurality of the second identifiers are located on one side of at least one of the protruding portions.

[0018] In some examples, the first semiconductor structure further includes a first conductive structure that extends along the stacking direction of the first semiconductor structure and the second semiconductor structure, and one end of which is coupled to the first identifier; the shape of the first identifier is related to the number and position of the coupled first conductive structures.

[0019] The second semiconductor structure further includes a second conductive structure that extends along the stacking direction of the first semiconductor structure and the second semiconductor structure; along the stacking direction of the first semiconductor structure and the second semiconductor structure, the size of the second identifier is the same as the size of the second conductive structure.

[0020] Along the direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure, the size of the second identifier is 50% - 80% of the size of the second conductive structure.

[0021] In some examples, the extending direction of the first identifier is parallel to the extending direction of the first reference identifier of the first semiconductor structure. The arrangement direction of the plurality of second identifiers is parallel to the extending direction of the second reference identifier of the second semiconductor structure. The extending direction of the first reference identifier is parallel to the extending direction of the second reference identifier.

[0022] In the above semiconductor structure, in some of the second identifiers having a gap with the first identifier, at least one side of this part of the second identifiers is parallel to the side of the first identifier. For the overlay structure determined based on their relative position relationship, it is easier to detect the parallel side profiles of the first identifier and the second identifier, which is beneficial to improving the accuracy of measuring the distance between the two parallel adjacent sides. Moreover, based on the multiple distances between the plurality of second identifiers parallel to the extending direction of the first identifier and the first identifier respectively, the offset between the first semiconductor structure and the second semiconductor structure can be determined through the multiple distances, further improving the alignment accuracy of adjacent semiconductor structures.

[0023] In a second aspect, an embodiment of the present application provides a method for measuring a semiconductor structure. The overlay error measurement method includes: forming a first identifier on a first semiconductor structure; forming a plurality of second identifiers on a second semiconductor structure; aligning the first semiconductor structure and the second semiconductor structure; at least one side of the plurality of second identifiers is parallel to the side of the first identifier; respectively collecting the distances between the side of the first identifier and the sides of the plurality of second identifiers; and measuring the position offset between the first identifier and the plurality of second identifiers based on the values of the multiple distances to obtain the overlay error between the first semiconductor structure and the second semiconductor structure.

[0024] In some examples, measuring the position offset between the first identifier and the plurality of second identifiers based on the values of the plurality of spacings includes:

[0025] The plurality of second identifiers are arranged at intervals along a first direction; the first direction is parallel to the extension direction of the first identifier; the reference spacings of the plurality of second identifiers along a second direction are equal; the second direction is perpendicular to the first direction;

[0026] Based on the differences between the plurality of first spacings between the plurality of second identifiers and the first identifier and the reference spacing, obtain the position offset between the first identifier and the plurality of second identifiers along the second direction.

[0027] In some examples, measuring the position offset between the first identifier and the plurality of second identifiers based on the values of the plurality of spacings includes: the plurality of second identifiers are arranged at intervals along a second direction; the second direction is parallel to the extension direction of the first identifier; the reference spacings of the plurality of second identifiers along a first direction are equal; the first direction is perpendicular to the second direction.

[0028] Based on the differences between the plurality of second spacings between the plurality of second identifiers and the first identifier and the reference spacing, obtain the position offset between the first identifier and the plurality of second identifiers along the first direction.

[0029] In some examples, measuring the position offset between the first identifier and the plurality of second identifiers based on the values of the plurality of spacings includes: the plurality of second identifiers are arranged at intervals along a first direction; the first direction is parallel to the extension direction of the first identifier; the spacings between the plurality of second identifiers and the first identifier along the second direction first decrease and then increase.

[0030] Collect two first spacings between two second identifiers that are symmetrically distributed among the plurality of second identifiers and the first identifier respectively.

[0031] Based on the difference between the average value of the two first spacings and the reference spacing, obtain the position offset between the first identifier and the plurality of second identifiers along the second direction.

[0032] In some examples, measuring the position offset between the first identifier and the plurality of second identifiers based on the values of the plurality of spacings includes: a plurality of the first identifiers are arranged at intervals and enclose an annular region; a plurality of the second identifiers are located within the annular region and on one side of at least one of the first identifiers.

[0033] The two first identifiers symmetric along the second direction include a first type of first identifier and a second type of first identifier. A plurality of the second identifiers parallel to the extending direction of the first type of first identifier are a first group of second identifiers; a plurality of the second identifiers parallel to the extending direction of the second type of first identifier are a second group of second identifiers.

[0034] Obtain a first second identifier to be detected in the first group of second identifiers and a second second identifier to be detected in the second group of second identifiers, where the first second identifier to be detected and the second second identifier to be detected are centrosymmetric.

[0035] Collect a first type of distance between the first second identifier to be detected and the first type of first identifier, and a second type of distance between the second second identifier to be detected and the second type of first identifier.

[0036] Determine the position offset between the first identifier and the plurality of second identifiers based on the average value of the first type of distance and the second type of distance.

[0037] In some examples, the step of respectively collecting the distances between the side edges of the first identifier and the side edges of the plurality of second identifiers includes: obtaining the side edges of the second identifiers parallel to the side edge of the first identifier. Respectively measure the distances between the side edge of the first identifier and the side edges of the plurality of second identifiers.

[0038] In some examples, the overlay error measurement method includes: setting a first reference identifier on the first semiconductor structure, and forming the first identifier based on the position of the first reference identifier; the extending direction of the first identifier is parallel to the extending direction of the first reference identifier.

[0039] Set a second reference identifier on the second semiconductor structure, and form the plurality of second identifiers based on the position of the second reference identifier; the arrangement direction of the second identifiers is parallel to the extending direction of the second reference identifier; wherein, the extending direction of the first reference identifier is parallel to the extending direction of the second reference identifier.

[0040] Align the first semiconductor structure and the second semiconductor structure according to the first reference identifier and the second reference identifier.

[0041] In the above-mentioned overlay error measurement method, by setting at least one side of a plurality of second marks parallel to the side of the first mark, it is easier to detect the side profiles of the first mark and the second mark that are parallel to each other, which is beneficial to improving the accuracy of measuring the distance between two adjacent sides that are parallel to each other. Moreover, a plurality of distances between the second marks and the first mark can be collected respectively, and the offset between the first semiconductor structure and the second semiconductor structure can be determined through the plurality of distances, further improving the alignment accuracy of the first semiconductor structure and the second semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In the drawings, like reference numerals may describe like components in different views. Like reference numerals with different letter suffixes may represent different examples of like components. The drawings generally illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0043] Figure 1 Schematic structural diagram of a semiconductor structure provided by an embodiment of the present application;

[0044] Figure 2 Schematic structure of a first mark and a second mark provided by an embodiment of the present application Figure 1 ;

[0045] Figure 3 Schematic structure of a first mark and a second mark provided by an embodiment of the present application Figure 2 ;

[0046] Figure 4 Schematic structure of a first mark and a second mark provided by an embodiment of the present application Figure 3 ;

[0047] Figure 5 Schematic structure of a first mark and a second mark provided by an embodiment of the present application Figure 4 ;

[0048] Figure 6 Schematic structure of a first mark and a second mark provided by an embodiment of the present application Figure 5 ;

[0049] Figure 7 Schematic structure of a first mark and a second mark provided by an embodiment of the present application Figure 6 ;

[0050] Figure 8 Schematic structure of a first mark and a second mark provided by an embodiment of the present application Figure 7 ;

[0051] Figure 9 Schematic structure of a first mark and a second mark provided by an embodiment of the present application Figure 8 ;

[0052] Figure 10 Flow schematic of the overlay error measurement method provided for the implementation of this application Figure 1 ;

[0053] Figure 11 Flow schematic of the overlay error measurement method provided for the implementation of this application Figure 2 ;

[0054] Figure 12 Flow schematic of the overlay error measurement method provided for the implementation of this application Figure 3 ;

[0055] Figure 13 Flow schematic of the overlay error measurement method provided for the implementation of this application Figure 4 。 Detailed implementation manners

[0056] The technical solution of this application will be further elaborated in detail below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0057] In the embodiments of this application, terms such as "first", "second", etc. are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0058] In the embodiments of this application, the term "A contacts B" includes the situation where A directly contacts B, or the situation where other components are interposed between A and B and A indirectly contacts B.

[0059] It should be understood that "some embodiments" or "some examples" mentioned throughout the specification mean that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of this application. Therefore, "in some embodiments" or "in some examples" that appear throughout the specification do not necessarily refer to the same embodiments. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of this application, the magnitude of the serial numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application. The serial numbers of the embodiments of this application above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0060] It should be noted that, in this document, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising such element.

[0061] It can be understood that the meanings of "on...", "above..." and "overhead..." in this application should be interpreted in the broadest manner, such that "on..." not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0062] It should be noted that although this specification is described in terms of embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments understandable to those skilled in the art.

[0063] With the development of large-scale integrated circuits, the feature size of circuits has been continuously miniaturized, and the chips are developing in three dimensions and entering the post-Moore era to meet the requirements of high integration, fast transmission speed, low power consumption, etc. Among them, the three-dimensional direction mainly reflects the high integration of the circuit distribution within the chip, as well as the stacking of multiple chips through bonding.

[0064] It should be noted that the wafer bonding technology does not limit the specific type of bonding object, which can be selected and set according to actual needs. For example, in the wafer bonding technology, the bonding process can be distinguished according to the bonding object, including carrier wafer and wafer, wafer-to-wafer (W2W) bonding, chip-to-wafer (C2W) bonding, die-to-wafer (C2C) bonding, and chip-to-chip (C2C) bonding. It can be understood that a chip (Chip) and a die (Die) can refer to the same structure (the names can be interchanged), or a die is an unencapsulated chip. Different levels of chip structures can be set according to requirements. For example, chip Chip, die Die, and wafer Wafer are three different levels of chip structures. The examples provided in this application do not specifically limit the structures of Chip and Wafer.

[0065] Exemplarily, in a semiconductor structure implementing multi-wafer stacking, a carrier wafer can be used for fusion bonding with a device wafer; and, the back surface of the device wafer can be thinned, perforated, and a redistribution layer can be made to lead out wires, multiple wafers can be stacked on the wafer, and bonding can be performed separately.

[0066] For example, after the carrier wafer and the device wafer are fusion bonded, during the process of stacking and bonding multiple wafers on the device wafer, a conductive structure of the Through Silicon Via (TSV) type formed in the wafer can be used for alignment measurement.

[0067] However, in the lithography process of forming a conductive structure of the Through Silicon Via (TSV) type in each stacked wafer, since the opening of the TSV is circular, it is difficult to grasp the outermost edge of the circular contour, and it is very difficult to confirm the alignment and overlay accuracy between the TSV and the previous layer (such as the previous wafer).

[0068] To solve the above problems, as Figures 1 - 8 shown, an embodiment of the present application provides a semiconductor structure 100, which can more easily detect the side profiles where the first identifier and the second identifier are parallel to each other, is beneficial to improving the accuracy of measuring the distance between two adjacent sides that are parallel to each other, and can improve the alignment accuracy of adjacent semiconductor structures.

[0069] In some examples, as Figure 1 shown, the semiconductor structure 100 includes a first semiconductor structure 110 and a second semiconductor structure 120.

[0070] Exemplarily, the first semiconductor structure 110 may include a chip having an integrated circuit, and the first semiconductor structure 110 includes a first identifier 111. The material of the first identifier 111 includes a conductive material.

[0071] Exemplarily, the first identifier 111 may include an interconnection structure that couples internal electronic components of the first semiconductor structure 110 to external devices. For example, the first identifier may be a TSV landing metal bar that transmits the electrical signal of the TSV to the metal layer on the chip surface, thereby realizing electrical connection between different chips or layers. It can be understood that the first identifier 111 is multiplexed as an identification pattern while having its exclusive function.

[0072] In this way, the structure of the first identifier 111 is multiplexed, which can, without affecting the function and circuit layout of the first semiconductor structure 110, eliminate the need for additional marking structures, is beneficial to reducing the size of the first semiconductor structure 110, and improving the performance of the bonding and alignment operation of multiple semiconductor structures.

[0073] Continue to refer toFigure 1 In addition, the first semiconductor structure 110 further includes a first conductive structure 112 that extends along the stacking direction Z of the first semiconductor structure 110 and the second semiconductor structure 120, and one end of the first conductive structure 112 is coupled to the first identifier 111. The shape of the first identifier 111 is related to the number and position of the coupled first conductive structures 112.

[0074] In some examples, as Figure 1 shown, the second semiconductor structure 120 is disposed on one side of the first semiconductor structure 110 and includes a plurality of second identifiers 121.

[0075] Exemplarily, the second semiconductor structure 120 may include a chip with an integrated circuit. When the second semiconductor structure 120 and the first semiconductor structure 110 are stacked, the alignment adjustment and bonding of the two are realized through the second identifier 121 and the first identifier 111.

[0076] The second identifier 121 extends along the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120, and one end of the second identifier 121 is exposed from the surface of the second semiconductor structure 120.

[0077] It can be understood that the material used for the second identifier 121 may include a conductive material or a dielectric material. For example, when the second identifier 121 uses a conductive material, the second identifier 121 can be fabricated synchronously with the TSV structure in the second semiconductor structure 120 using the same process. For example, the second conductive structure 122 may be a through-silicon via type conductive structure (TSV) in the second semiconductor structure 120, which is used to realize the electrical connection between the internal electronic components of the second semiconductor structure 120 and external devices. The second identifier 121 may be a conductive structure similar to the second conductive structure 122, which can be used to transfer circuits of different layers in the second semiconductor structure 120 and at the same time be multiplexed as an identification pattern.

[0078] Exemplarily, as Figure 1 shown, the second semiconductor structure 120 further includes a second conductive structure 122 that extends along the stacking direction Z of the first semiconductor structure 110 and the second semiconductor structure 120. Among them, along the stacking direction Z of the first semiconductor structure 110 and the second semiconductor structure 120, the size of the second identifier 121 is the same as the size of the second conductive structure 122.

[0079] Based on the structures of the first semiconductor structure 110 and the second semiconductor structure 120 in the semiconductor structure 100 provided in the above examples, as Figures 2 - 9As shown, along the direction perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120 (direction X or direction Y), at least some of the plurality of second identifiers 121 are located on at least one side of the first identifier 111 and have a gap therebetween. At least one side of the second identifier 121 is parallel to the side of the first identifier 111.

[0080] Exemplarily, the first identifier 111 on the first semiconductor structure 110 and the second identifier 121 on the second semiconductor structure 120 are prepared separately. After aligning and bonding the first semiconductor structure 110 and the second semiconductor structure 120 through the first identifier 111 and the second identifier 121, the semiconductor structure 100 is obtained. Based on this, the condition for aligning and bonding the first semiconductor structure 110 and the second semiconductor structure 120 is that at least some of the plurality of second identifiers 121 are located on at least one side of the first identifier 111 and have a gap therebetween. At least one side of the second identifier 121 is parallel to the side of the first identifier 111.

[0081] In this way, the alignment degree of the first semiconductor structure 110 and the second semiconductor structure 120 is determined through the parallel sides of some of the second identifiers 121 and the first identifier 111, and alignment and bonding are achieved under the condition that the alignment accuracy of the two is reached. Among them, through the structure of the first identifier 111, the structure of the second identifier 121, and the structure determined by their relative position relationship, it is easier to detect the side profiles of the first identifier 111 and the second identifier 121 that are parallel to each other, which is beneficial to improving the accuracy of measuring the distance between the two parallel adjacent sides and improving the alignment accuracy of the adjacent first semiconductor structure 110 and the second semiconductor structure 120.

[0082] It should be noted that in some examples, the extension direction of the first identifier 111 is parallel to the extension direction of the first reference identifier of the first semiconductor structure 110. The arrangement direction of the plurality of second identifiers 121 is parallel to the extension direction of the second reference identifier of the second semiconductor structure 120. The extension direction of the first reference identifier is parallel to the extension direction of the second reference identifier.

[0083] The examples provided in this application do not specifically limit the setting positions and structures of the first reference identifier and the second reference identifier, which can be set according to actual needs.

[0084] In this way, the extending direction of the first identifier 111 fabricated on the first semiconductor structure 110 is obtained based on the arrangement and functional implementation conditions of the electronic components within the first semiconductor structure 110 (i.e., the extending direction of the first reference identifier is determined). Moreover, the extending direction of the second identifier 121 fabricated on the second semiconductor structure 120 can be determined based on the extending direction of a second reference identifier parallel to the extending direction of the first reference identifier, thereby meeting the detection condition that "at least one side of the second identifier 121 is parallel to the side of the first identifier 111". At this time, it is not necessary for the region where the electronic components are arranged within the first semiconductor structure 110 to be directly opposite the region where the electronic components are arranged within the second semiconductor structure 120.

[0085] In addition, in the case where the region where the electronic components are arranged within the first semiconductor structure 110 is directly opposite the region where the electronic components are arranged within the second semiconductor structure 120, the first reference identifier and the second reference identifier may not be provided. By rotating the first semiconductor structure 110 or the second semiconductor structure 120, the detection condition that "at least one side of the second identifier 121 is parallel to the side of the first identifier 111" can also be met without affecting the performance of the semiconductor structure 100.

[0086] In some examples, along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120, the size of the second identifier 121 is 50% - 80% of the size of the second conductive structure 122.

[0087] Exemplarily, the size of the second conductive structure (i.e., TSV) along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120 is 2 μm - 12 μm. For example, the size of the second conductive structure (i.e., TSV) along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120 is 2 μm, 3 μm, 5 μm, 7 μm or 12 μm.

[0088] For example, the size of the second identifier 121 along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120 is 50% of 2 μm, i.e., 1 μm. Or, the size of the second identifier 121 along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120 is 70% of 2 μm, i.e., 1.4 μm. Or, the size of the second identifier 121 along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120 is 80% of 2 μm, i.e., 1.6 μm. The examples provided in this application do not specifically limit the size of the second identifier 121, the size of the second conductive structure 122, and the specific relationship between the sizes of the two, which can be adjusted according to actual requirements.

[0089] In this way, when the first identifier 111 is multiplexed as an identification pattern, multiple alignment situations between the first identifier 111 and the second identifier 121 can be provided by setting the arrangement, position, shape, etc. of the multiple second identifiers 121, so as to improve the alignment accuracy of adjacent semiconductor structures.

[0090] In the following examples, in order to more clearly illustrate the alignment situation between the first identifier 111 and the second identifier 121, along the directions X and Y perpendicular to the stacking direction Z of the first semiconductor structure 110 and the second semiconductor structure 120, different examples of the positional relationship and structural features of both the first identifier 111 and the second identifier 121 are exemplarily shown, without restricting that both are located in the same plane in the semiconductor structure 100.

[0091] In some examples, as Figure 2 shown, multiple second identifiers 121 are arranged at intervals along the first direction X. The first direction X is parallel to the extension direction of the first identifier 111 and perpendicular to the stacking direction Z of the first semiconductor structure 110 and the second semiconductor structure 120.

[0092] And among three adjacent second identifiers 121 along the first direction X, the side of the third second identifier 121 is located on the side away from the side of the first second identifier 121 along the second direction Y1 of the side of the second second identifier 121. The second direction Y1 is perpendicular to the first direction X and perpendicular to the stacking direction Z of the first semiconductor structure 110 and the second semiconductor structure 120.

[0093] Exemplarily, as Figure 2 shown, multiple second identifiers 121 are arranged at intervals along the first direction X, and along the second direction Y1, multiple second identifiers 121 are arranged in sequence along the direction away from the first second identifier 121, that is, multiple second identifiers 121 are arranged obliquely. Among them, the extension directions of the sides of multiple second identifiers 121 on the same side are parallel to each other.

[0094] In this way, when adjusting the alignment degree of the first semiconductor structure 110 and the second semiconductor structure 120 through the relative position relationship between the second identifier 121 and the first identifier 111, along the direction perpendicular to the stacking direction Z of the first semiconductor structure 110 and the second semiconductor structure 120, even if some of the second identifiers 121 are located inside the first identifier 111 or overlap with the first identifier 111, there are still other parts of the second identifiers 121 having an interval from the first identifier 111, and at least one side of the second identifier 121 is parallel to the side of the first identifier 111. In this way, it is easier to detect the side contours parallel to each other between the first identifier 111 and the second identifier 121, which is beneficial to improving the accuracy of measuring the distance between two adjacent sides parallel to each other, and can improve the alignment accuracy of adjacent semiconductor structures.

[0095] It can be understood that, in order to ensure that among multiple second identifiers 121 arranged obliquely, along the stacking direction Z perpendicular to the first semiconductor structure 110 and the second semiconductor structure 120, even if some of the second identifiers 121 are located within the first identifier 111 or overlap with the first identifier 111, there is still a gap between the remaining second identifiers 121 and the first identifier 111. This is related to the number of the obliquely arranged second identifiers 121 and the gap between two adjacent second identifiers 121. The following examples illustrate the number of the obliquely arranged second identifiers 121 and the gap between two adjacent second identifiers 121.

[0096] In some examples, as Figure 2 shown, multiple second identifiers 121 arranged at intervals in the first direction X are grouped together. The dimension L1 of a group of second identifiers 121 along the second direction Y1 is greater than twice the dimension L2 of the first identifier 111 along the second direction Y1.

[0097] Exemplarily, the dimension L1 of a group of second identifiers 121 along the second direction Y1 is greater than twice the dimension L2 of the first identifier 111 along the second direction Y1. For example, if the dimension L2 of the first identifier 111 along the second direction Y1 is 2 micrometers, the dimension L1 of a group of second identifiers 121 along the second direction Y1 can be 4.5 micrometers.

[0098] It can be understood that the dimension L1 of a group of second identifiers 121 along the second direction Y1 refers to the distance between the relatively far - apart two side edges of the two second identifiers 121 that are farthest apart along the second direction Y1. That is, L1 includes the sum of the dimensions of at least two second identifiers 121 along the second direction Y1 and the gap between two adjacent second identifiers 121 along the second direction Y1.

[0099] For example, a group of second identifiers 121 includes two second identifiers 121. Along the stacking direction Z perpendicular to the first semiconductor structure 110 and the second semiconductor structure 120, when one second identifier 121 at least partially overlaps with the first identifier 111, the dimension L1 of a group of second identifiers 121 along the second direction Y1 being greater than twice the dimension L2 of the first identifier 111 along the second direction Y1 can ensure that there is a gap between the remaining one second identifier 121 and the first identifier 111, facilitating the measurement of the distance between this one second identifier 121 and the first identifier 111 and determining the alignment degree of the first semiconductor structure 110 and the second semiconductor structure 120.

[0100] For another example, a group of second marks 121 includes three, four, five, ... second marks 121. By measuring the spacing between the plurality of second marks 121 and the first mark 111, the amount of effective data used to determine the alignment degree between the first mark 111 and the second mark 121 is increased, and the alignment accuracy between the first semiconductor structure 110 and the second semiconductor structure 120 can be improved.

[0101] The example provided in this application does not impose any specific restriction on the number of second identifiers in a group of second identifiers 121, and can be adjusted according to factors such as the size of the first identifier 111, the size of the second identifier 121, the spacing between two adjacent second identifiers 121, and the relative position relationship between the first identifier 111 and the second identifier 121.

[0102] In some examples, when a second mark 121 at least partially overlaps with a first mark 111 along a stacking direction Z perpendicular to the first semiconductor structure 110 and the second semiconductor structure 120, a size L2 of the first mark 111 and a size L3 of the second mark 121 along an extending direction perpendicular to the first mark 111 may be set as close as possible. Figure 2 As shown, along the extension direction perpendicular to the first mark 111, the size L2 of the first mark 111 can be the same as the size L3 of the second mark 121, or the size L2 of the first mark 111 is about 0.15 microns larger than the size L3 of the second mark 121. Alternatively, the overlay accuracy of the first mark 111 and the second mark 121 is greater than 0.15 microns.

[0103] In this way, while ensuring that the first mark functions as a transfer structure for the TSV type conductive structure, the amount of overlap between the second mark 121 and the first mark 111 can be reduced, and the effective data that can be used to measure the distance between the first mark 111 and the second mark 121 can be increased, which is beneficial to improving the alignment accuracy of adjacent semiconductor structures.

[0104] In some examples, such as Figure 2 As shown, along the first direction X, the intervals M between two adjacent second marks 121 are equal. Along the second direction Y1, the intervals N between two adjacent second marks 121 are equal.

[0105] For example, Figure 2 As shown, along the first direction X, the spacing M between two adjacent second marks 121 is equal, and multiple second marks 121 are evenly arranged, which is beneficial to reducing the number of second marks 121 and reducing the difficulty of measuring the alignment of the second mark 121 and the first mark 111 under the condition that there is a gap between the second mark 121 and the first mark 111 along the second direction Y1.

[0106] For example, Figure 2As shown, along the second direction Y1, the spacing N between two adjacent second identifiers 121 is equal. It can be that the spacing N between adjacent second identifiers 121 located on the same side (or center) of the side is the same. This is beneficial for facilitating the adjustment of the alignment area between the second identifier 121 and the first identifier 111 under the condition that there is a gap between the second identifier 121 and the first identifier 111 along the second direction Y1, and reducing the difficulty of measuring the alignment of the second identifier 121 and the first identifier 111.

[0107] Moreover, as Figure 2 shown, along the second direction Y1, the spacing N between two adjacent second identifiers 121 is equal, which also means that under the conditions of higher process conditions and alignment accuracy, the spacing between the second identifier 121 and the first identifier 111 satisfies the condition of increasing or decreasing. In this way, it is possible to further verify the alignment degree of the first identifier 111 and the second identifier 121, adjust the positions of the first semiconductor structure 110 and the second semiconductor structure 120, and improve the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120.

[0108] Furthermore, based on the size, quantity, and the spacing between two adjacent second identifiers 121 of the second identifier 121, as Figure 3 and Figure 4 shown, the length H1 of the first identifier 111 along its extending direction can be set to be less than or equal to the size of a plurality of second identifiers 121 having a gap with the first identifier 111 along their arrangement direction, which is beneficial for increasing the effective data that can be used to measure the spacing between the first identifier 111 and the second identifier 121, and is beneficial for improving the alignment accuracy of adjacent semiconductor structures.

[0109] In some examples, as Figures 2 - 9 shown, along the first direction X, the spacing between a plurality of second identifiers 121 and the first identifier 111 along the second direction Y1 increases and / or decreases.

[0110] For example, as Figure 2 shown, along the first direction X, the spacing between a plurality of second identifiers 121 and the first identifier 111 along the second direction Y1 increases.

[0111] As Figure 3As shown, along the first direction X, the distances between multiple second identifiers 121 and the first identifier 111 along the second direction Y1 first decrease and then increase. Among them, the increasing part of the second identifiers 121 and the decreasing part of the second identifiers 121 can be symmetrically arranged with respect to a second identifier 121 located in the middle position. For example, 15 second identifiers 121 are arranged at intervals along the first direction X. The distances between the first to seventh second identifiers 121 and the first identifier 111 along the second direction Y1 decrease respectively, and the distances between the seventh to fifteenth second identifiers 121 and the first identifier 111 along the second direction Y1 increase respectively. Among them, the first to sixth second identifiers 121 and the eighth to fifteenth second identifiers 121 are symmetrically arranged with respect to the seventh second identifier 121.

[0112] In this way, the change in the distance between the second identifier 121 and the first identifier 111 can measure the alignment degree of different regions of the first identifier 111, which is beneficial to improving the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120. And under the conditions of relatively high process conditions and alignment accuracy, the distance between the second identifier 121 and the first identifier 111 meets the conditions of increase or decrease. In this way, it is possible to further verify the alignment degree of the first identifier 111 and the second identifier 121, adjust the positions of the first semiconductor structure 110 and the second semiconductor structure 120, and improve the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120.

[0113] It can be understood that one direction includes two orientations, and different orientations represent different increase or decrease situations of the distance change. That is, along one orientation of one direction, if the distance change is an increase, then along the other orientation of this direction, the distance change is a decrease. The present application does not make specific restrictions on the increasing and decreasing orientations, and only the change situation of the distances between multiple second identifiers 121 and the first identifier 111 needs to be reflected.

[0114] Another example is Figure 4 As shown, along the stacking direction Z perpendicular to the first semiconductor structure 110 and the second semiconductor structure 120, the shape of the first identifier 111 includes a shape similar to an "L". The arranged shape of multiple second identifiers 121 can also be set to a shape similar to an "L".

[0115] Among them, the first identifier 111 includes a first part extending along the first direction X and a second part extending along the second direction Y1. Some second identifiers 121 are arranged at intervals along the first direction X, and the distance between them and the first part of the first identifier 111 increases. Another part of the second identifiers 121 are arranged at intervals along the second direction Y1, and the distance between them and the second part of the first identifier 111 increases.

[0116] In this way, according to the structure of the first identifier 111, the arrangement directions of multiple second identifiers 121 can be adjusted to measure the alignment degree of different regions of the first identifier 111, which is beneficial to improving the alignment accuracy between the first semiconductor structure 110 and the second semiconductor structure 120.

[0117] In some examples, such as Figure 2 As shown, along the extension direction X of the first identifier 111, the distance M between two adjacent second identifiers 121 is greater than or equal to the size P of the second identifier 121.

[0118] For example, along the extension direction X of the first identifier 111, the distance M between two adjacent second identifiers 121 is 1.5 micrometers. The size P of the second identifier 121 is 1.5 micrometers.

[0119] The second identifier 121 can be made with the minimum size that meets the process conditions. Under the condition of forming the second identifier 121, the distance M between two adjacent second identifiers 121 is greater than or equal to the size P of the second identifier 121, which can reduce the probability of cracks occurring in the chip after annealing due to the too small distance M between two adjacent second identifiers 121.

[0120] In some examples, such as Figure 2 As shown, along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120, the shape of the second identifier 121 includes a quasi-square.

[0121] Along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120, a structure with an aspect ratio (see the ratio of the size P to the size L3 of the second identifier 121 shown in Figure 2 is formed to be close to 1, which is beneficial to reducing the size of the second identifier 121 while reducing the process difficulty of forming the second identifier 121 by depositing conductive materials and the structural stability of the second identifier structure 121; further, the shape of the second identifier 121 is a square with sides parallel to the first identifier 111, which is beneficial to improving the edge contour detection accuracy of subsequent measurements based on the structure of the second identifier 121.

[0122] In some examples, such as Figures 5 - 7 As shown, multiple second identifiers 121 located on the same side of the first identifier 111 form a group. The two groups of second identifiers 121 are arranged symmetrically or centrosymmetrically along the extension direction X of the first identifier 111.

[0123] For example, such as Figure 5As shown, along the first direction X, multiple second identifiers 121 located to the left of the first identifier 111 form a first group, and multiple second identifiers 121 located to the right of the first identifier 111 form a second group. The two groups of second identifiers 121 are arranged symmetrically about the center along the extension direction X of the first identifier 111.

[0124] Another example is, as Figure 6 shown, along the first direction X, multiple second identifiers 121 located to the left of the first identifier 111 form a first group, and multiple second identifiers 121 located to the right of the first identifier 111 form a second group. The two groups of second identifiers 121 are arranged symmetrically along the extension direction X of the first identifier 111.

[0125] Another example is, as Figure 7 shown, along the first direction X, multiple second identifiers 121 located above the first identifier 111 form a first group, and multiple second identifiers 121 located below the first identifier 111 form a second group. The two groups of second identifiers 121 are arranged symmetrically along the extension direction X of the first identifier 111. In each group of second identifiers 121, the increasing part of the second identifiers 121 can be symmetrically arranged with respect to the decreasing part of the second identifiers 121 about a second identifier 121 located at the middle position.

[0126] In this way, through the two groups of second identifiers 121 located on the opposite sides of the first identifier 111, the alignment accuracy between the first semiconductor structure 110 and the second semiconductor structure 120 can be further improved.

[0127] It should be noted that, based on being able to be located on the opposite sides of the first identifier 111 along its extension direction, it does not include the part of the second identifiers 121 that overlap with the first identifier 111 along the stacking direction Z of the first semiconductor structure 110 and the second semiconductor structure 120. In the examples provided in this application, the part of the second identifiers 121 that overlap with the first identifier 111 is not described in detail, which does not limit that all the second identifiers 121 on the second semiconductor structure 120 are located on one side or the opposite sides of the first identifier 111 along its extension direction. The relative position relationship between the first identifier 111 and the second identifiers 121 can be adjusted according to the actual situation.

[0128] In addition, the distances between the multiple second identifiers 121 and the first identifier 111 respectively may not be increasing or decreasing, and can be set according to actual requirements. For example, the distances between the multiple second identifiers 121 and the first identifier 111 respectively can vary in a staggered manner.

[0129] In some examples, such as Figure 5As shown, multiple second identifiers 121 arranged at intervals in the first direction X among the multiple second identifiers 121 form a group. The spacing Q of a group of second identifiers 121 increases along the second direction Y1. For example, the spacing Q1 is 40 nm, the spacing Q2 is 60 nm, the spacing Q3 is 80 nm, the spacing Q4 is 100 nm, the spacing Q5 is 120 nm, the spacing Q6 is 140 nm, and the spacing Q7 is 160 nm. The size L1 of another group of second identifiers 121 decreases along the second direction Y1. For example, the spacing Q'1 is 40 nm, the spacing Q'2 is 60 nm, the spacing Q3 is 80 nm, the spacing Q'4 is 100 nm, the spacing Q'5 is 120 nm, the spacing Q'6 is 140 nm, and the spacing Q'7 is 160 nm.

[0130] In this way, the relative positional relationship (or overlay accuracy) between the first identifier 111 and the second identifier 121 can be 1 / 2(Q i +Q' i ), where i = 1, 2... 7.

[0131] In some examples, as Figure 8 shown, along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120, multiple first identifiers 111 are arranged at intervals and enclose an annular region.

[0132] Multiple second identifiers 121 are located within the annular region and are located on one side of at least one first identifier 111.

[0133] Exemplarily, as Figure 8 shown, along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120, four first identifiers 111 are arranged at intervals and enclose an annular region.

[0134] Multiple second identifiers 121 are located within the annular region. Among them, a part of the second identifiers 121 close to one first identifier 111 forms a group, and four groups of second identifiers 121 are arranged at intervals and enclose an annular region.

[0135] Among them, the arrangement direction of a group of second identifiers 121 intersects with the extension direction of the corresponding first identifier 111.

[0136] In this way, the multiple second identifiers 121 located within the annular region enclosed by the multiple first identifiers 111 can not only improve the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120 according to the nested positional relationship between the second identifiers 121 and the first identifiers 111; moreover, the measurement of the spacing between a group of second identifiers 121 and the corresponding first identifier 111 can further improve the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120.

[0137] As another example, along the direction Z perpendicular to the stacking of the first semiconductor structure 110 and the second semiconductor structure 120, four first identifiers 111 are arranged at intervals and enclose an annular region.

[0138] Part of the second identifiers 121 may be located within the annular region enclosed by the multiple first identifiers 111, and another part of the second identifiers 121 may also be located outside the annular region enclosed by the multiple first identifiers 111. That is, one first identifier 111 may correspond to two sets of second identifiers 121, and the two sets of second identifiers 121 may be located on opposite sides of the first identifier 111 along its extending direction (see Figure 5 and Figure 6 for the relative positional relationship between the second identifier 121 and the first identifier 111 shown). This example does not make specific restrictions on this, and the relative positional relationship between the second identifier 121 and the first identifier 111 can be adjusted according to the position of the second identifier 121, so as to improve the accuracy of measuring the distance between two adjacent sides parallel to each other, and can improve the alignment accuracy of adjacent semiconductor structures.

[0139] For example, as Figure 8 shown, for a set of second identifiers 121 corresponding to a first identifier 111 extending along the first direction X, the distances between the multiple second identifiers 121 and the first identifier 111 along the second direction Y1 can increase. For example, the distance Q1 is 40 nm, the distance Q2 is 60 nm, the distance Q3 is 80 nm, the distance Q4 is 100 nm, the distance Q5 is 120 nm, the distance Q6 is 160 nm, and the distance Q7 is 180 nm.

[0140] In addition, for a set of second identifiers 121 corresponding to a first identifier 111 extending along the second direction Y1, the distances between the multiple second identifiers 121 and the first identifier 111 along the first direction X can increase. For example, the distance O1 is 40 nm, the distance O2 is 60 nm, the distance O3 is 80 nm, the distance O4 is 100 nm, the distance O5 is 120 nm, the distance O6 is 140 nm, and the distance O7 is 160 nm.

[0141] The relative positions of the multiple second identifiers 121 arranged in this increasing manner and the first identifier 111 can further improve the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120.

[0142] In the above first identification 111 of the annular structure, among the two first identifications 111 extending in the same direction, the relative position relationship between one first identification 111 and the corresponding set of second identifications 121 changes with an increasing spacing, and the relative position relationship between the other first identification 111 and the corresponding set of second identifications 121 changes with a decreasing spacing. In addition, in the first identification 111 of the annular structure of the present application, for the two sets of second identifications 121 respectively corresponding to the two first identifications 111 extending in the same direction, the relative position relationship between a set of second identifications 121 and the corresponding first identification 111 may also be increasing, and the relative position relationships between the two sets of second identifications 121 and the two first identifications 111 are both increasing. The examples provided in the present application do not make specific restrictions on this, and can be adjusted according to actual needs.

[0143] In some examples, such as Figure 9 shown, the first identification 111 includes a main body portion 111a, a protruding portion 111b extending along the first direction X, and a protruding portion 111c extending along the third direction Y2. The first direction X intersects with the third direction Y2, and both are perpendicular to the stacking direction Z of the first semiconductor structure 110 and the second semiconductor structure 120. It can be understood that when the third direction Y2 is perpendicular to the first direction X, the third direction Y2 and the second direction Y1 may refer to the same direction. When the included angle between the third direction Y2 and the first direction X is an acute angle, the third direction Y2 and the second direction Y1 are not the same direction. Here, the directions with different included angles with the first direction X are described by different names to facilitate clearly explaining the structures of the first identification 111 and the second identification 121 in different cases.

[0144] The above-mentioned multiple second identifications 121 are located on one side of at least one of the protruding portions 111b or 111c.

[0145] For example, as Figure 9 shown, along the direction Z perpendicular to the stacking of the first semiconductor structure 110 and the second semiconductor structure 120, the shape of the first identification 111 is cross-like. In the area between adjacent protruding portions 111b and 111c, multiple second identifications 121 are arranged at intervals along the connecting direction of the protruding portion 111b, the main body portion 111a, and the protruding portion 111c; and along the direction from the protruding portion 111b or 111c to the main body portion 111a, the spacing between the multiple second identifications 121 and the first identification 111 increases.

[0146] For example, as Figure 9 shown, the cross-like first identification 111 divides into 4 areas. The second identifications 121 in one area are a set, and the different sets of second identifications 121 in the 4 areas are arranged in central symmetry with respect to the first identification 111. Or, there may be a set of second identifications 121 in at least one of the 4 areas.

[0147] Among them, as Figure 9 shown, along the direction from the protruding part 111b to the main body part 111a, the distance between some of the second identifiers 121 in a group of second identifiers 121 and the first identifier 111 increases. For example, the distance Q1 is 40 nm, the distance Q2 is 60 nm, the distance Q3 is 80 nm, the distance Q4 is 100 nm, the distance Q5 is 120 nm, and the distance Q6 is 140 nm. And, along the direction from the protruding part 111c to the main body part 111a, the distance between another part of the second identifiers 121 in a group of second identifiers 121 and the first identifier 111 increases. For example, the distance O1 is 40 nm, the distance O2 is 60 nm, the distance O3 is 80 nm, the distance O4 is 100 nm, the distance O5 is 120 nm, and the distance O6 is 140 nm.

[0148] In this way, according to the accuracy of the distance between the protruding part 111b (or 111c) of the first identifier 111 and two parallel adjacent sides of the plurality of second identifiers 121, the alignment accuracy of adjacent semiconductor structures can be improved. Moreover, through the nested positional relationship between the second identifier 121 and the first identifier 111, the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120 can be further improved.

[0149] Along the direction Z perpendicular to the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120, the sizes of the above-mentioned protruding parts 111b and 111c can be the same or different. For example, the size of the protruding part 111b along the first direction X can be the same as the size of the protruding part 111c along the second direction Y1; the size of the protruding part 111b along the second direction Y1 can be the same as the size of the protruding part 111c along the first direction X. Or, the size of the protruding part 111b along the first direction X is greater than the size of the protruding part 111c along the second direction Y1; the size of the protruding part 111b along the second direction Y1 can be the same as the size of the protruding part 111c along the first direction X. The examples provided in this application do not make specific limitations on this.

[0150] Based on the structure and positional relationship between the first identifier 111 and the second identifier 121 provided in the above examples, as Figures 10 - 13 shown, this application also provides a method for measuring overlay error. Based on the side profiles of the first identifier 111 and the second identifier 121 that are easier to detect and are parallel to each other, the accuracy of measuring the distance between two parallel adjacent sides of the two is improved, and the alignment accuracy of adjacent semiconductor structures can be improved.

[0151] In some examples, as Figure 10 shown, the method for measuring overlay error includes S100 to S500.

[0152] S100: Form a first identifier 111 on the first semiconductor structure 110.

[0153] For example, as Figure 1 shown, the first semiconductor structure 110 may include a chip with an integrated circuit, and the first semiconductor structure 110 includes the first identifier 111. The material of the first identifier 111 includes a conductive material.

[0154] For example, the first identifier 111 may include an interposer structure that couples the electronic components inside the first semiconductor structure 110 to external devices. In this way, the formed first identifier 111 is multiplexed as an identification pattern while having its exclusive function, so there is no need for an additional design solution to fabricate the first identifier 111, which is beneficial to improving the process efficiency and reducing the size of the first semiconductor structure 110.

[0155] S200: Form a plurality of second identifiers 121 on the second semiconductor structure 120.

[0156] For example, the second semiconductor structure 120 may include a chip with an integrated circuit. A plurality of vias extending along the stacking direction of the first semiconductor structure 110 and the second semiconductor structure 120 are formed on the second semiconductor structure 120. For example, the opening shape of the via includes a square. A conductive material or a dielectric material is deposited in the via to form the second identifier 121, and one end is exposed from the surface of the second semiconductor structure 120.

[0157] For example, if the second identifier 121 uses a conductive material, the second identifier 121 can be fabricated synchronously with the TSV structure in the second semiconductor structure 120 using the same process. In this way, it is beneficial to reduce the process steps and improve the preparation efficiency.

[0158] S300: Align the first semiconductor structure 110 and the second semiconductor structure 120; at least one side of the plurality of second identifiers 121 is parallel to the side of the first identifier 111.

[0159] For example, the first semiconductor structure 110 and the second semiconductor structure 120 are aligned according to the same reference conditions, so that the aligned semiconductor structure 100 satisfies the functional implementation of the internal circuit structure. Among them, the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120 can be judged according to the relative position relationship between the first identifier 111 and the second identifier 121 whether it meets the functional implementation (the specific judgment process is exemplified in the subsequent steps).

[0160] S400: Collect the distances between the side of the first identifier 111 and the sides of the plurality of second identifiers 121 respectively.

[0161] Exemplarily, obtain the side of the second identifier 121 that is parallel to the side of the first identifier 111. Since the side of the first identifier 111 is parallel to the side of the second identifier 121, it is easier to collect the sides of both, improving the accuracy of the collected information, and being able to obtain the distance between the side of the first identifier 111 and the sides of multiple second identifiers 121, and the accuracy of the obtained values of multiple distances is relatively high.

[0162] S500: Based on the values of multiple distances, measure the position offset between the first identifier 111 and multiple second identifiers 121 to obtain the overlay error between the first semiconductor structure 110 and the second semiconductor structure 120.

[0163] Exemplarily, based on the values of multiple distances, the average value of multiple distance values can be obtained, and then the magnitude relationship between the average value and a reference value can be compared to obtain the position offset between the first identifier 111 and multiple second identifiers 121. Alternatively, the changing trend of multiple distance values, such as the difference between the distance values measured for every two adjacent second identifiers, can be compared with the reference value to obtain the position offset between the first identifier 111 and multiple second identifiers 121.

[0164] In the above overlay error measurement method, by setting at least one side of multiple second identifiers 121 to be parallel to the side of the first identifier 111, it is easier to detect the side profiles of the first identifier 111 and the second identifier 121 that are parallel to each other, which is beneficial to improving the accuracy of measuring the distance between two adjacent sides that are parallel to each other. Moreover, multiple distances between multiple second identifiers 121 and the first identifier 111 respectively can be collected, and the offset between the first semiconductor structure 110 and the second semiconductor structure 120 can be determined through the multiple distances, further improving the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120.

[0165] Considering that the structure and shape of the first identifier 111 are related to the number and position of the first conductive structure 112 coupled thereto. When the extending direction of the first identifier 111 includes at least one of the first direction X, the second direction Y1, and the third direction Y2, the position offset between the second identifier 121 and the first identifier 111 can be measured according to multiple second identifiers 121 arranged in different directions, and the alignment errors of the first semiconductor structure 110 and the second semiconductor structure 120 in different directions can be obtained. The specific measurement method will be described in subsequent examples.

[0166] In some examples, as Figure 11 shown, the above step S500: Based on the values of multiple distances, measure the position offset between the first identifier 111 and multiple second identifiers 121, includes S510.

[0167] Exemplarily, as Figures 2 - 9As shown, a plurality of second identifiers 121 are arranged at intervals along a first direction X; the first direction X is parallel to the extending direction of the first identifier 111.

[0168] Moreover, the reference pitch N of the plurality of second identifiers 121 along a second direction Y is equal; the second direction Y is perpendicular to the first direction X.

[0169] S510: Based on the differences between the plurality of first pitches Q between the plurality of second identifiers 121 and the first identifier 111 and the reference pitch N, obtain the position offset of the first identifier 111 and the plurality of second identifiers 121 along the second direction Y.

[0170] Exemplarily, as Figure 2 shown, the plurality of second identifiers 121 are arranged along a direction away from the first identifier 111. Collect the plurality of first pitches Q between the plurality of second identifiers 121 and the first identifier 111 respectively. For example, collect the first pitches Q1, Q2, Q3, Q4, Q5, Q6... Then, judge the magnitude relationship between the difference between two adjacent first pitches Q measured by two second identifiers 121 and the reference pitch N; if it is 0, the position offset of the first identifier 111 and the plurality of second identifiers 121 along the second direction Y is 0, that is, the first semiconductor structure 110 and the second semiconductor structure 120 are accurately aligned; otherwise, obtain the value of the position offset of the first identifier 111 and the plurality of second identifiers 121 along the second direction Y, and adjust the displacement of the first semiconductor structure 110 or the second semiconductor structure 120.

[0171] For example, as Figure 4 shown, among the first pitches Q1, Q2, Q3, Q4, and Q5 collected, the difference between each adjacent two first pitches Q is the same as the value of the reference pitch N, and the first semiconductor structure 110 and the second semiconductor structure 120 are accurately aligned.

[0172] In addition, it is also possible to collect the plurality of first pitches Q between 4 second identifiers 121 (having a pitch from the first identifier 111) shown in Figure 2 , etc. The examples provided in this application are not limited to this, and can be adjusted according to the positional relationship between the plurality of second identifiers 121 and the first identifier 111. For the specific method, refer to the above examples and will not be elaborated here.

[0173] In some other examples, as Figure 4 shown, the above step S500: Measure the position offset of the first identifier 111 and the plurality of second identifiers 121 based on the values of the plurality of pitches, including S520.

[0174] Exemplarily, as Figure 4As shown, a plurality of second identifiers 121 are arranged at intervals along the second direction Y1; the second direction Y1 is parallel to the extending direction of the first identifier 111. The reference pitch N of the plurality of second identifiers 121 along the first direction X is equal; the first direction X is perpendicular to the second direction Y1.

[0175] S520: Based on the differences between the plurality of second pitches O between the plurality of second identifiers 121 and the first identifier 111 and the reference pitch N, obtain the position offset of the first identifier 111 and the plurality of second identifiers 121 along the first direction X.

[0176] Exemplarily, as Figure 4 shown, the plurality of second identifiers 121 are arranged along the direction away from the first identifier 111. Collect the plurality of second pitches O between the plurality of second identifiers 121 and the first identifier 111 respectively. For example, collect a plurality of second pitches O1, O2, O3, O4, O5, O6, and O7. Then, judge the magnitude relationship between the difference between the two first pitches Q measured by two adjacent second identifiers 121 and the reference pitch N; if it is 0, the position offset of the first identifier 111 and the plurality of second identifiers 121 along the second direction Y is 0, that is, the first semiconductor structure 110 and the second semiconductor structure 120 are accurately aligned; otherwise, obtain the position offset of the first identifier 111 and the plurality of second identifiers 121 along the second direction Y, and adjust the displacement of the first semiconductor structure 110 or the second semiconductor structure 120 based on this.

[0177] For example, among the second pitches O1, O2, O3, O4, O5, O6, and O7, the difference between each adjacent two second pitches O is the same as the value of the reference pitch N, and the first semiconductor structure 110 and the second semiconductor structure 120 are accurately aligned.

[0178] Based on this, the first identifier 111 may include a part extending along the first direction X and another part extending along the second direction Y. For the part of the first identifier 111 with different extending directions and the plurality of second identifiers 121 arranged in its extending direction, it is possible to measure the position offset of the plurality of second identifiers 121 and the first identifier 111 in the first direction X, or the position offset in the second direction Y, or measure the position offset in the first direction X and the second direction Y, improve the overlay accuracy of the first identifier 111 and the second identifier 121, and improve the accurate alignment of the first semiconductor structure 110 and the second semiconductor structure 120.

[0179] In still some other examples, as Figure 11 shown, the above step S500: Based on the values of the plurality of pitches, measure the position offset of the first identifier 111 and the plurality of second identifiers 121, including S530.

[0180] Exemplarily, as Figure 3 and Figure 7As shown, a plurality of second identifiers 121 are arranged at intervals along the first direction X; the first direction X is parallel to the extending direction of the first identifier 111. The distances between the plurality of second identifiers 121 and the first identifier 111 along the second direction Y first decrease and then increase.

[0181] S530: Collect two first distances Q between two symmetrically distributed second identifiers 121 among the plurality of second identifiers 121 and the first identifier 111 respectively;

[0182] Based on the difference between the average value of the two first distances Q and the reference distance N, obtain the position offset of the first identifier 111 and the plurality of second identifiers 121 along the second direction Y1.

[0183] Exemplarily, as Figure 3 shown, a plurality of second identifiers are symmetrically structured along the first direction X. In this way, when measuring the overlay error between the plurality of second identifiers 121 and the first identifier 111, by collecting the two first distances Q between two symmetric second identifiers 121 and the first identifier 111 respectively, judge the magnitude relationship between the average value of the two first distances Q and the reference distance N, and obtain the position offset of the first identifier 111 and the plurality of second identifiers 121 along the second direction Y1. In this way, the amount of data collected can be reduced, which is beneficial to simplifying the measurement operation and improving the measurement efficiency.

[0184] Another example is, as Figure 7 shown, a plurality of second identifiers 121 located below the first identifier 111 are the second group. A plurality of the second identifiers 121 are the first group, and a plurality of second identifiers 121 located below the first identifier 111 are the second group.

[0185] The position offset between the second identifiers 121 of the first group and the first identifier 111 can be measured respectively, and the position offset between the second identifiers 121 of the second group and the first identifier 111 can be measured, and the measurement accuracy of the overlay error can be improved by judging the two groups of measurement results.

[0186] In some other examples, as Figure 11 shown, the above step S500: Based on the values of a plurality of distances, measure the position offset of the first identifier 111 and the plurality of second identifiers 121, including S540.

[0187] Exemplarily, as Figure 8 shown, a plurality of first identifiers 111 are arranged at intervals and enclose an annular region. A plurality of second identifiers 121 are located within the annular region and on one side of at least one first identifier 111.

[0188] Two first identifiers 111 symmetric along the second direction Y1 include a first type of first identifier 111m and a second type of first identifier 111n.

[0189] A plurality of second identifiers 121 parallel to the extending direction of the first identifier 111m of the first type are the first group of second identifiers. A plurality of second identifiers 121 parallel to the extending direction of the first identifier 111n of the second type are the second group of second identifiers.

[0190] S540: Obtain a first second identifier 121A to be detected in the first group of second identifiers and a second second identifier 121B to be detected in the second group of second identifiers. The first second identifier 121A and the second second identifier 121B are centrosymmetric.

[0191] Collect a first type of distance between the first second identifier 121A to be detected and the first identifier 111m of the first type, and a second type of distance between the second second identifier 121B to be detected and the first identifier 111n of the second type.

[0192] Based on the average value of the first type of distance and the second type of distance, determine the position offset of the first identifier 111 and the plurality of second identifiers 121.

[0193] Exemplarily, such as Figure 8 As shown, collect a first type of distance Q1 between the first second identifier 121A to be detected and the first identifier 111m of the first type, and a second type of distance Q'1 between the second second identifier 121B to be detected and the first identifier 111n of the second type. Based on the average value of the first type of distance Q1 and the second type of distance Q'1, determine the position offset of the first identifier 111 and the plurality of second identifiers 121.

[0194] For example, by calculating the value of 1 / 2(Q i +Q' i ), where i = 1, 2... 7, determine the position offset of the first identifier 111 and the plurality of second identifiers 121.

[0195] In this way, for the plurality of second identifiers 121 located in the annular region surrounded by the plurality of first identifiers 111, not only can the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120 be improved according to the nested position relationship between the second identifier 121 and the first identifier 111; moreover, the measurement of the distance between a group of second identifiers 121 and the corresponding first identifier 111 can further improve the alignment accuracy of the first semiconductor structure 110 and the second semiconductor structure 120.

[0196] In some examples, such as Figure 12 As shown, the above step S400: respectively collect the distances between the side edges of the first identifier 111 and the side edges of the plurality of second identifiers 121, including S410 and S420.

[0197] S410: Obtain the side edge of the second identifier 121 parallel to the side edge of the first identifier 111.

[0198] S420: Measure the distances between the side edges of the first identifier 111 and the side edges of the multiple second identifiers 121 respectively.

[0199] Exemplarily, among the multiple second identifiers 121, obtain the second identifier 121 that has a distance from the first identifier 111 and whose side edges are parallel to those of the first identifier 111 as the measurement target. Then measure the distances between the side edges of the filtered multiple second identifiers 121 and the side edges of the first identifier 111.

[0200] In some examples, as Figure 13 shown, the overlay error measurement method includes: S110, S210, and S310.

[0201] The above step S100 includes S110: Set a first reference identifier on the first semiconductor structure 110, and form a first identifier 111 based on the position of the first reference identifier. The extension direction of the first identifier 111 is parallel to the extension direction of the first reference identifier.

[0202] Exemplarily, the first reference identifier can be set according to the subsequent alignment and detectable regions of the first semiconductor structure 110 first.

[0203] Then, considering that the shape and structure of the first identifier 111 can be related to the arrangement of the first conductive structure 112 in the first semiconductor structure 110, under the condition of satisfying the electrical connection performance of the first identifier 111, the extension area of the first identifier 111 can be increased to adjust the shape of the first identifier 111 so that the extension direction of the first identifier 111 can be parallel to the first reference identifier.

[0204] The above step S200 includes S210: Set a second reference identifier on the second semiconductor structure 120, and form multiple second identifiers 121 based on the position of the second reference identifier. The arrangement direction of the multiple second identifiers 121 is parallel to the extension direction of the second reference identifier. Among them, the extension direction of the first reference identifier is parallel to the extension direction of the second reference identifier.

[0205] Exemplarily, the second reference identifier can be set according to the subsequent alignment and detectable regions of the second semiconductor structure 120 first. For example, set the second reference identifier in combination with the position and extension direction of the first reference identifier.

[0206] Then, after the second reference identifier is formed, form multiple second identifiers 121 based on the position of the second reference identifier, so as to meet the detection condition that "at least one side edge of the second identifier 121 is parallel to the side edge of the first identifier 111".

[0207] The above-mentioned step S300 includes S310: Align the first semiconductor structure 110 and the second semiconductor structure 120 according to the first reference identifier and the second reference identifier.

[0208] Exemplarily, by setting the first reference identifier and the second reference identifier, the detection condition that "at least one side of the second identifier 121 is parallel to the side of the first identifier 111" after the alignment of the first semiconductor structure 110 and the second semiconductor structure 120 can be satisfied.

[0209] The examples provided in this application do not specifically limit the setting positions and structures of the first reference identifier and the second reference identifier, and can be set according to actual needs.

[0210] In addition, in the case where the area where the electronic components are arranged in the first semiconductor structure 110 faces the area where the electronic components are arranged in the second semiconductor structure 120, the first reference identifier and the second reference identifier may not be set. By rotating the first semiconductor structure 110 or the second semiconductor structure 120, the detection condition that "at least one side of the second identifier 121 is parallel to the side of the first identifier 111" can also be satisfied without affecting the performance of the semiconductor structure 100.

[0211] As described above, only the embodiments of the present application are provided, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first semiconductor structure includes a first mark; the material of the first mark includes a conductive material; A second semiconductor structure is disposed on one side of the first semiconductor structure, and includes a plurality of second marks; the second marks extend along a stacking direction of the first semiconductor structure and the second semiconductor structure, and one end of the second marks is exposed from a surface of the second semiconductor structure; Among them, along the direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure, at least some of the multiple second marks are located on at least one side of the first mark and are spaced apart from the first mark; and at least one side edge of the second mark is parallel to a side edge of the first mark.

2. The semiconductor structure according to claim 1, characterized in that: A plurality of the second marks are arranged at intervals along a first direction; the first direction is parallel to an extension direction of the first marks and is perpendicular to a stacking direction of the first semiconductor structure and the second semiconductor structure; Three second marks adjacent along the first direction are located on the side of the same side, and the side of the third second mark is located on the side of the second second mark away from the side of the first second mark along the second direction; the second direction is perpendicular to the first direction and perpendicular to the direction in which the first semiconductor structure and the second semiconductor structure are stacked.

3. The semiconductor structure according to claim 2, characterized in that: A plurality of the second identifications arranged at intervals in the first direction among the plurality of second identifications constitute a group; A size of a group of the second marks along the second direction is greater than twice a size of the first marks along the second direction.

4. The semiconductor structure according to claim 2, characterized in that: Along the first direction, the distances between two adjacent second marks are equal; Along the second direction, the intervals between two adjacent second marks are equal.

5. The semiconductor structure according to claim 4, characterized in that: Along the first direction, the intervals between the plurality of second marks and the first mark along the second direction increase and / or decrease.

6. The semiconductor structure according to claim 1, characterized in that Along the extension direction of the first mark, the distance between two adjacent second marks is greater than or equal to the size of the second mark.

7. The semiconductor structure according to claim 1, characterized in that: Along a direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure, the shape of the second mark includes a quasi-square.

8. The semiconductor structure according to claim 1, characterized in that: A plurality of the second marks located on the same side of the first mark are grouped together; The two groups of the second marks are arranged symmetrically or centrosymmetrically along the extension direction of the first mark.

9. The semiconductor structure according to claim 1, characterized in that: Along a direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure, a plurality of the first marks are arranged at intervals and surround an annular area; A plurality of the second marks are located in the annular area and are located on one side of at least one of the first marks.

10. The semiconductor structure according to claim 1, characterized in that The first mark includes a main body, a protruding portion extending along a first direction, and a protruding portion extending along a third direction; the first direction intersects the third direction and is perpendicular to a direction in which the first semiconductor structure and the second semiconductor structure are stacked; A plurality of the second marks are located on one side of at least one of the protruding portions.

11. The semiconductor structure according to claim 1, characterized in that: The first semiconductor structure further includes a first conductive structure, which extends along the stacking direction of the first semiconductor structure and the second semiconductor structure, and one end of which is coupled to the first mark; the shape of the first mark is related to the number and position of the coupled first conductive structures; The second semiconductor structure further includes a second conductive structure, the second conductive structure extends along the stacking direction of the first semiconductor structure and the second semiconductor structure; along the stacking direction of the first semiconductor structure and the second semiconductor structure, the second mark size is the same as the size of the second conductive structure; Along a direction perpendicular to the stacking direction of the first semiconductor structure and the second semiconductor structure, a size of the second mark is 50% to 80% of a size of the second conductive structure.

12. The semiconductor structure according to claim 1, characterized in that An extending direction of the first mark is parallel to an extending direction of the first reference mark of the first semiconductor structure; An arrangement direction of the plurality of second marks is parallel to an extension direction of the second reference mark of the second semiconductor structure; An extending direction of the first reference mark is parallel to an extending direction of the second reference mark.

13. A method for measuring overlay error of a semiconductor structure, characterized in that: include: forming a first mark on the first semiconductor structure; forming a plurality of second marks on the second semiconductor structure; Aligning the first semiconductor structure and the second semiconductor structure; At least one side of the plurality of second marks is parallel to a side of the first mark; respectively collecting the distances between the side edges of the first mark and the side edges of the plurality of second marks; Based on the values ​​of the plurality of intervals, the position offset between the first mark and the plurality of second marks is measured to obtain an overlay error between the first semiconductor structure and the second semiconductor structure.

14. The overlay error measurement method according to claim 13, characterized in that: The measuring, based on the values ​​of the plurality of intervals, the position offsets between the first mark and the plurality of second marks comprises: The plurality of second marks are arranged at intervals along a first direction; the first direction is parallel to an extension direction of the first marks; the reference spacings of the plurality of second marks along the second direction are equal; the second direction is perpendicular to the first direction; Based on the difference between a plurality of first intervals between the plurality of second marks and the first mark and the reference interval, the position offset between the first mark and the plurality of second marks along the second direction is obtained.

15. The overlay error measurement method according to claim 13 or 14, characterized in that: The measuring, based on the values ​​of the plurality of intervals, the position offsets between the first mark and the plurality of second marks comprises: The plurality of second marks are arranged at intervals along a second direction; the second direction is parallel to an extension direction of the first mark; the reference spacings of the plurality of second marks along the first direction are equal; the first direction is perpendicular to the second direction; Based on the difference between a plurality of second intervals between the plurality of second marks and the first mark and the reference interval, the position offset between the first mark and the plurality of second marks along the first direction is obtained.

16. The overlay error measurement method according to claim 13, characterized in that: The measuring, based on the values ​​of the plurality of intervals, the position offsets between the first mark and the plurality of second marks comprises: The plurality of second marks are arranged at intervals along a first direction; the first direction is parallel to an extension direction of the first mark; and the spacings between the plurality of second marks and the first mark along the second direction first decrease and then increase; Collecting two first distances between two second identifiers symmetrically distributed among the plurality of second identifiers and the first identifier respectively; Based on the difference between the average value of the two first intervals and the reference interval, a position offset between the first mark and the plurality of second marks along the second direction is obtained.

17. The overlay error measurement method according to claim 13, characterized in that: The measuring, based on the values ​​of the plurality of intervals, the position offsets between the first mark and the plurality of second marks comprises: A plurality of the first marks are arranged at intervals and form an annular area; a plurality of the second marks are located in the annular area and are located on one side of at least one of the first marks; The two first marks symmetrical along the second direction include a first-category first mark and a second-category first mark; A plurality of the second marks parallel to the extending direction of the first mark of the first category are a first group of second marks; a plurality of the second marks parallel to the extending direction of the second mark of the second category are a second group of second marks; Acquire a first second identifier to be detected in the first group of second identifiers and a second second identifier to be detected in the second group of second identifiers, wherein the first second identifier to be detected is centrally symmetrical with the second second identifier to be detected; Collecting a first type of distance between the first second mark to be detected and the first type of first mark, and a second type of distance between the second second mark to be detected and the second type of first mark; Based on an average value of the first type of spacing and the second type of spacing, a position offset between the first marker and the plurality of second markers is determined.

18. The overlay error measurement method according to claim 13, characterized in that: The respectively collecting the distances between the side edges of the first mark and the side edges of the plurality of second marks includes: Acquire a side edge of the second mark that is parallel to a side edge of the first mark; The distances between the side edges of the first mark and the side edges of the plurality of second marks are measured respectively.

19. The overlay error measurement method according to claim 13, characterized in that: The overlay error measurement method comprises: A first reference mark is provided on the first semiconductor structure, and the first mark is formed based on the position of the first reference mark; an extension direction of the first mark is parallel to an extension direction of the first reference mark; A second reference mark is arranged on the second semiconductor structure, and the plurality of second marks are formed based on the position of the second reference mark; the arrangement direction of the second marks is parallel to the extension direction of the second reference mark; wherein the extension direction of the first reference mark is parallel to the extension direction of the second reference mark; The first semiconductor structure and the second semiconductor structure are aligned according to the first reference mark and the second reference mark.

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