Chip packaging structure and packaging method thereof, circuit board assembly and terminal

Abstract

The embodiment of the invention provides a chip packaging structure and a packaging method thereof, a circuit board assembly and a terminal, relates to the technical field of semiconductors, and is used for reducing the size of the chip packaging structure. The chip packaging structure comprises a substrate, a first rewiring layer, a first device, a second rewiring layer and at least one deep groove capacitor. A plurality of containing cavities are formed in the first side of the substrate, the deep groove capacitors are arranged on the first side of the substrate and extend into at least two containing cavities, and each protrusion of each deep groove capacitor extends into one containing cavity. The first rewiring layer and the second rewiring layer are arranged on two opposite sides of the substrate; the first rewiring layer is directly coupled with the deep groove capacitor, and the first device is arranged on the side, away from the substrate, of the first rewiring layer and is coupled with the deep groove capacitor through the first rewiring layer. According to the chip packaging structure, the deep groove capacitor is directly formed in the substrate, so that the layout area originally required for placing an independent capacitor device is reduced, the size of the chip packaging structure is reduced, the requirement on the process precision is relatively low, and the yield is high.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a chip packaging structure, a packaging method thereof, a circuit board assembly, and a terminal. Background Art

[0002] With the rapid increase in the popularity of electronic devices and the booming development of the electronic device market, there is an increasing requirement for electronic products to evolve towards miniaturization and thinning while having high performance, multi-functionality, high reliability, and convenience. Such requirements pose higher demands for chip packaging in terms of being better, lighter, thinner, higher packaging density, better electrical and thermal performance, higher reliability, and higher cost performance.

[0003] In some application scenarios, it is inevitable to integrate some passive devices such as capacitors in the chip packaging structure. And how to minimize the size of the chip packaging structure while integrating capacitors in the chip packaging structure remains a key issue continuously studied by those skilled in the art. Summary of the Invention

[0004] Embodiments of the present application provide a chip packaging structure, a packaging method thereof, a circuit board assembly, and a terminal, which are used to reduce the size of the chip packaging structure while taking into account the yield.

[0005] To achieve the above object, the present application adopts the following technical solutions:

[0006] In a first aspect of embodiments of the present application, a chip packaging structure is provided, including a substrate, a first redistribution layer, a first device, a second redistribution layer, and at least one deep trench capacitor. A plurality of receiving cavities are formed on a first side of the substrate, the deep trench capacitor is disposed on the first side of the substrate and extends into at least two of the receiving cavities; the first redistribution layer is disposed on the first side of the substrate and is directly coupled to the deep trench capacitor; the first device is disposed on a side of the first redistribution layer away from the substrate, and the first device is coupled to the deep trench capacitor through the first redistribution layer; the second redistribution layer is disposed on a second side of the substrate away from the first redistribution layer.

[0007] The chip packaging structure provided by the embodiment of the present application has a trench capacitor encapsulated inside, but the trench capacitor extends into the substrate, and there is no need to reserve space for the deep groove capacitor separately in the thickness direction. Therefore, the trench capacitor is arranged in the substrate to reduce the size of the chip packaging structure along the thickness direction. Moreover, the number of devices arranged inside the substrate is usually relatively small, and there is a sufficient spare position inside the substrate to accommodate the deep groove capacitor, and the size in the horizontal direction will not be increased separately. Therefore, the trench capacitor is arranged in the substrate to reduce the size of the chip packaging structure in the horizontal direction. In other words, the trench capacitor is arranged in the substrate, which reduces the layout area originally required for placing independent capacitor devices, thereby reducing the size of the chip packaging structure. On this basis, a accommodating cavity is provided on the substrate, and a deep groove capacitor is directly formed on the surface of the substrate and is accommodated by the accommodating cavity. In the chip packaging structure of the present application, when preparing the deep groove capacitor, the shape of the deep groove capacitor matches the shape of the accommodating cavity, and each accommodating cavity accommodates a protrusion of a deep groove capacitor, and there is no requirement for the dimensional accuracy of the accommodating cavity, and the product yield is high. Moreover, a first redistribution layer directly coupled to the deep trench capacitor can be formed directly on the surface of the deep trench capacitor, without the need to perform the steps of pre-processing of the external device packaging, and without the need to form other transfer structures, which can reduce the process. If the prepared capacitor device is integrated and packaged in the substrate, the entire capacitor device is placed in a accommodating cavity, and the size of the accommodating cavity formed on the substrate needs to be strictly matched with the capacitor device, the precision requirement is relatively high, and the yield loss is large. Moreover, after the capacitor device is integrated in the substrate, it is still necessary to perform pre-processing of packaging to prepare the first redistribution layer, and the process is complicated. Therefore, the chip packaging structure provided in the embodiment of the present application can reduce the size of the chip packaging structure on the basis of taking into account the yield.

[0008] In a possible implementation, the deep trench capacitor fits the inner surface of the accommodating cavity, which can improve the problem caused by the gap between the deep trench capacitor and the inner surface of the accommodating cavity.

[0009] In a possible implementation, the deep trench capacitor includes a first electrode and a second electrode, wherein the first electrode is coupled to the first device, and the second electrode is coupled to the first ground network of the first redistribution layer. The first electrode is coupled to the first device, and the second electrode is coupled to the ground network, and the deep trench capacitor can act as a filter capacitor.

[0010] In a possible implementation, the deep trench capacitor includes a first electrode and a second electrode, wherein the first electrode is coupled to the first device, and the second electrode is coupled to the second ground network of the second redistribution layer. The first electrode is coupled to the first device, and the second electrode is coupled to the ground network, and the deep trench capacitor can act as a filter capacitor.

[0011] In a possible implementation, the deep trench capacitor includes a first electrode and a second electrode. The first electrode is coupled to a first device, and the second electrode is coupled to both the first ground network of the first rewiring layer and the second ground network of the second rewiring layer. The second electrode is respectively coupled to the first rewiring layer and the second rewiring layer. That is, the first rewiring layer and the second rewiring layer are coupled through the second electrode. The second electrode can act as a via hole in the substrate, playing a role in interconnecting the first ground network and the second ground network, which can reduce the number of via holes in the substrate, so as to reduce the area of the chip packaging structure and lower the cost at the same time.

[0012] In a possible implementation, the first electrode and the second electrode form at least two protruding portions. The deep trench capacitor extending into at least two receiving cavities specifically means that the protruding portions extend into the receiving cavities. The protruding portions and the receiving cavities are in one-to-one correspondence, which can reduce the process difficulty.

[0013] In a possible implementation, the second electrode is directly coupled to the first ground network. In this application, the trench capacitor is formed in the substrate by a preparation and integration method. Compared with placing the capacitor in the substrate by an integration method, it can reduce the process steps and the thickness of the chip packaging structure.

[0014] In a possible implementation, the receiving cavity penetrates the substrate, and the second electrode is directly coupled to the second ground network. In this application, the trench capacitor is formed in the substrate by a preparation and integration method. Compared with placing the capacitor in the substrate by an integration method, it can reduce the process steps and the thickness of the chip packaging structure.

[0015] In a possible implementation, the deep trench capacitor is disposed along the edge of the substrate. By disposing the deep trench capacitor at the edge of the substrate, it does not affect the layout of the central area, and the change in the overall layout of the chip packaging structure is relatively small. Moreover, when the second electrode T2 of the deep trench capacitor is coupled to both the first ground network and the second ground network, on the basis of its own capacitance function, the deep trench capacitor can also perform electromagnetic shielding on the external radiation of the devices in the packaging intermediate layer. That is, the deep trench capacitor has an external radiation suppression effect. At the position where the deep trench capacitor is disposed, the chip packaging structure can avoid using a special process to sputter a conformal shielding layer on the side surface, reducing the packaging cost and simplifying the packaging steps.

[0016] In a possible implementation, the chip packaging structure further includes a second device and a third device; the second device and the third device are disposed in the substrate, and at least one deep trench capacitor is located between the second device and the third device. In this way, the deep trench capacitor can play a role in cavity partitioning and internal isolation, and the deep trench capacitor can shield the electromagnetic interference between the internal second device and the third device. For example, if the second device is a source of interference and the third device is a victim, the electromagnetic interference of the second device on the third device can be shielded by the deep trench capacitor.

[0017] In a possible implementation, the magnetic field intensities of the second device and the third device are different. Electromagnetic interference will occur between two devices with different magnetic fields, and the presence of the deep trench capacitor can shield the electromagnetic interference of the second device on the third device.

[0018] In a possible implementation, the second device includes a radio frequency transmitting device, and the third device includes a radio frequency receiving device. This is a common scenario.

[0019] In a possible implementation, the second device includes a digital circuit device, and the third device includes an analog circuit device. This is a common scenario.

[0020] In a possible implementation, the magnetic field intensity of the second device is greater than or equal to 50 dBμV / m, and the magnetic field intensity of the third device is less than 50 dBμV / m. Electromagnetic interference will be generated when the magnetic field intensity is above 50 dBμV / m. In this application, grounding capacitors are arranged between the devices where electromagnetic interference may occur, which can optimize the performance of the chip package structure.

[0021] In a possible implementation, the magnetic field intensity of the first device is less than 50 dBμV / m. By arranging non-strong radiation devices on the side of the first wiring layer away from the substrate, a shielding layer does not need to be provided on the surface of the chip package structure where the first device is located, simplifying the structure and manufacturing process.

[0022] In a possible implementation, the first device includes a radio frequency receiving device or an analog circuit device. This is a common scenario.

[0023] In a possible implementation, the magnetic field intensity of the first device is greater than or equal to 50 dBμV / m. The chip package structure further includes a shielding cover and a plastic encapsulation layer. The shielding cover is buckled on the first wiring layer, the first device is located inside the shielding cover, and the plastic encapsulation layer covers the shielding cover and the first wiring layer. Even if a strong radiation device needs to be arranged above the first wiring layer, by arranging a shielding cover with a local shielding function above the strongly radiating first device, the first device is electromagnetically protected by the shielding cover, and still no shielding layer needs to be provided on the outer surface of the chip package structure, and the overall external radiation degree of the package can still be controlled.

[0024] In a possible implementation, the first device includes a radio frequency transmitting device or a digital circuit device; the chip package structure further includes a shielding cover and a plastic encapsulation layer. The shielding cover is buckled on the first wiring layer, the first device is located inside the shielding cover, and the plastic encapsulation layer covers the shielding cover and the first wiring layer. Even if a strong radiation device needs to be arranged above the first wiring layer, by arranging a shielding cover with a local shielding function above the strongly radiating first device, the first device is electromagnetically protected by the shielding cover, and still no shielding layer needs to be provided on the outer surface of the chip package structure, and the overall external radiation degree of the package can still be controlled.

[0025] In a possible implementation, the shielding cover includes bonding wires arranged crosswise, and the bonding wires are coupled to the first ground network of the first redistribution layer. This is a shielding cover structure with a simple structure and a mature manufacturing process.

[0026] In a possible implementation, the capacitance value of the deep trench capacitor is greater than or equal to 500 pF. Since the capacitors above 500 pF in the chip packaging structure will have relatively large dimensions in the thickness direction and the horizontal direction, the impact on the packaging area is relatively obvious. Therefore, integrating the capacitors above 500 pF in the substrate can significantly save the packaging area of the chip packaging structure.

[0027] In a possible implementation, the chip packaging structure further includes a fourth device and / or solder balls, and both the fourth device and the solder balls are disposed on the side of the second redistribution layer away from the substrate and are both coupled to the second redistribution layer. Devices can also be arranged on the side of the second redistribution layer away from the substrate, which is applicable to various scenarios.

[0028] In a second aspect of the embodiments of the present application, there is provided a circuit board assembly, including a circuit board and a chip packaging structure. The chip packaging structure is disposed on the circuit board, and the chip packaging structure includes the chip packaging structure according to any one of the first aspect.

[0029] The circuit board assembly provided in the second aspect of the embodiments of the present application includes the chip packaging structure of the first aspect, and its beneficial effects are the same as those of the chip packaging structure, which will not be elaborated herein.

[0030] In a third aspect of the embodiments of the present application, there is provided a terminal, including a rear case and a circuit board assembly. The circuit board assembly is disposed inside the rear case, and the circuit board assembly includes the circuit board assembly of the second aspect.

[0031] The terminal provided in the third aspect of the embodiments of the present application includes the circuit board assembly of the second aspect, and its beneficial effects are the same as those of the circuit board assembly, which will not be elaborated herein.

[0032] In a fourth aspect of the embodiments of the present application, there is provided a packaging method for a chip packaging structure, including: forming a plurality of accommodation cavities on a first side of the substrate; forming a deep trench capacitor on the first side of the substrate, and the deep trench capacitor extends into at least two of the accommodation cavities; forming a first redistribution layer on the first side, and the first redistribution layer is directly coupled to the deep trench capacitor; forming a second redistribution layer on a second side of the substrate away from the first redistribution layer; bonding a first device on a side of the first redistribution layer away from the substrate, and the first device is coupled to the deep trench capacitor through the first redistribution layer.

[0033] The packaging method for the chip packaging structure provided in the fourth aspect of the embodiments of the present application has the same beneficial effects as those of the chip packaging structure of the first aspect, which will not be elaborated herein.

[0034] In a possible implementation, a deep trench capacitor is formed on a first side of a substrate, including: forming a second electrode on the first side of the substrate, the second electrode extending into the accommodation cavity and fitting with the inner surface of the accommodation cavity; forming a capacitor dielectric layer on the surface of the second electrode; and forming a first electrode on the surface of the capacitor dielectric layer. The process is simple and has relatively low requirements for precision. Description of the Drawings

[0035] Figure 1 A schematic structural diagram of a terminal provided by an embodiment of the present application;

[0036] Figure 2 A cross-sectional view of a chip package structure provided by an embodiment of the present application;

[0037] Figure 3 A cross-sectional view of a chip package structure provided by an embodiment of the present application;

[0038] Figure 4A A cross-sectional view of a chip package structure provided by an embodiment of the present application;

[0039] Figure 4B A cross-sectional view of a chip package structure provided by an embodiment of the present application;

[0040] Figure 4C A topological circuit diagram of a deep trench capacitor provided by an embodiment of the present application;

[0041] Figure 5 A cross-sectional view of a chip package structure provided by an embodiment of the present application;

[0042] Figure 6 A top view of the arrangement of deep trench capacitors provided by an embodiment of the present application;

[0043] Figure 7A A cross-sectional view of a chip package structure provided by an embodiment of the present application;

[0044] Figure 7B A cross-sectional view of a chip package structure provided by an embodiment of the present application;

[0045] Figure 7C A layout diagram of a device and deep trench capacitors provided by an embodiment of the present application;

[0046] Figure 8 A cross-sectional view of a chip package structure provided by an embodiment of the present application;

[0047] Figure 9 A cross-sectional view of a chip package structure provided by an embodiment of the present application;

[0048] Figure 10A flowchart of a chip packaging method provided by an embodiment of the present application;

[0049] Figures 11A - 11G A preparation process diagram of a chip packaging structure provided by an embodiment of the present application. Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0051] Hereinafter, terms such as "second" and "first" are only for convenience of description, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "second", "first", etc. may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0052] In addition, in the embodiments of the present application, orientation terms such as "upper", "lower", "left", and "right" may include, but are not limited to, being defined relative to the schematic placement of components in the accompanying drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly with the change of the orientation of the components in the accompanying drawings.

[0053] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" may be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" may be direct contact or indirect contact through an intermediate medium.

[0054] In the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0055] Embodiments of the present application provide a terminal. The terminal can be, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product. Among them, consumer electronic products include, for example, mobile phones, tablets, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, servers, etc. Home electronic products include, for example, smart door locks, TVs, remote controls, refrigerators, small household appliances for charging (such as soybean milk makers, floor cleaning robots), switches, etc. Vehicle-mounted electronic products include, for example, vehicle-mounted navigators, vehicle-mounted DVDs, etc. Financial terminal products include, for example, ATMs, terminals for self-service business handling, etc. The terminal can also be products such as radio frequency front-ends, application processors, power supplies, etc. Embodiments of the present application do not impose special restrictions on the specific form of the above terminal. For the convenience of description, the following embodiments are all exemplified by taking the terminal as a mobile phone.

[0056] Figure 1 It is a schematic structural diagram of a terminal provided by an embodiment of the present application.

[0057] As Figure 1 shown, the terminal 1 mainly includes a cover plate 10, a display module 20, a middle frame 30, and a rear shell (or called a battery cover, a housing) 40.

[0058] The display module 20 has a light-emitting side where the display screen can be seen and a back surface opposite to the light-emitting side. The cover plate 10 is located on the light-emitting side of the display module 20, and the rear shell 40 is located on the back surface of the display module 20. The display module 20 includes an active area (AA), and the active area is used to display images. The active area includes a plurality of subpixels (SP).

[0059] In a possible embodiment, the display module 20 is a liquid crystal display (LCD). Based on this, the terminal 1 further includes a backlight module (BLU) located on the back of the liquid crystal display. The backlight module can provide light sources for the liquid crystal display so that each subpixel in the liquid crystal display can emit light to achieve image display.

[0060] In another possible embodiment, the display module 20 is a self-luminous display module such as an organic light-emitting diode (OLED) display module, an active-matrix organic light-emitting diode (AMOLED) display module, a mini organic light-emitting diode (Mini-OLED) display module, a micro light-emitting diode (Micro-LED) display module, a micro organic light-emitting diode (Micro-OLED) display module, or a quantum dot light emitting diodes (QLED) display module. At this time, the display module 20 can be a rigid display module or a flexible display module.

[0061] The middle frame 30 is located between the display module 20 and the rear housing 40. An installation space is formed between the middle frame 30 and the rear housing 40 to accommodate electronic devices such as a printed circuit board (PCB), a battery, a receiver, a speaker, and a camera. The PCB can integrate electronic components such as the main controller, the storage unit, the antenna module, and the power management module of the terminal, and the battery can supply power to electronic components such as the display module 20, the circuit board, the receiver, the speaker, and the camera.

[0062] The cover plate 10 is located on the side of the display module 20 away from the middle frame 30. The cover plate 10 is a light-transmitting structure and covers the display surface of the display module 20 as a protective layer. In this way, the light transmitted through the display surface of the display module 20 can pass through the cover plate 10 and be received by the user. The display surface of the display module 20 involved in the embodiment of the present application is the side of the display module 20 for displaying a picture to the user. The display surface of the display module 20 and the light-emitting side of the display module 20 are on the same side, and the back surface of the display module 20 refers to the surface opposite to the display surface of the display module 20. After the display module 20 and components such as the cover plate 10 are assembled, the display module provided by the embodiment of the present application can be formed.

[0063] In some embodiments, the terminal 1 further includes a central processing unit (CPU) chip, a dynamic random access memory (DRAM) chip, a radio frequency chip, a radio frequency power amplifier (PA) chip, a system on a chip (SOC), a power management integrated circuits (PMIC), a memory chip (such as high bandwidth memory (HBM)), an audio processor chip, a touch screen control chip, a NAND flash, an image sensor chip, etc., which are disposed on a printed circuit board (PCB). The PCB is used to carry the above chips and complete signal interaction with the above chips.

[0064] Since the chips in current terminals are developing towards a greater degree of deep trench capacitor (DTC) and miniaturization, in order to meet the development trends of terminal miniaturization, integration, ultra-thinness, and functional diversification, the chips in the terminal 1 are mostly integrated in the form of system in a package (SiP). In order to achieve a higher DTC degree in the current system-level packaging, it is necessary to continuously improve the packaging and chip integration technologies. For example, integrated passive devices (IPD) with higher integration degrees are used to replace discrete surface mounted devices (SMD) resistors, capacitors, and inductors, thinner re-distributed layer (RDL) interconnections are used to replace organic substrates, and multi-layer packaging stacking technologies, etc.

[0065] Figure 2 This is a cross-sectional view of a chip packaging structure provided by an embodiment of the present application.

[0066] In some embodiments, as Figure 2 shown, the chip packaging structure includes a first re-distributed layer RDL1, a second re-distributed layer RDL2, a substrate, a chip D, discrete passive devices (such as capacitors, resistors, inductors), solder balls, and a shielding layer.

[0067] The first re-distributed layer RDL1 and the second re-distributed layer RDL2 are vertically interconnected through vias, and the vias may include, for example, through molding vias (TMV), through glass vias (TGV), and through silicon vias (TSV).

[0068] A chip D may be disposed on a side of the first redistribution layer RDL1 away from the substrate, a chip D may also be disposed on a side of the second redistribution layer RDL2 away from the substrate, and a chip D may also be disposed inside the substrate. The chip D is coupled to the solder ball through the first redistribution layer RDL1 and / or the second redistribution layer RDL2.

[0069] Discrete passive devices may be disposed on a side of the first redistribution layer RDL1 away from the substrate, discrete passive devices may also be disposed on a side of the second redistribution layer RDL2 away from the substrate, and discrete passive devices may also be disposed inside the substrate. The passive devices are coupled to the redistribution layer through the SMD process.

[0070] The solder ball is used for electrical connection with the PCB in the terminal 1 to realize the electrical interconnection between the chip package structure and the PCB. A shielding layer is formed on the side and top surfaces of the chip package structure through the sputtering process, and the shielding layer is used for electromagnetic shielding of external radiation.

[0071] Figure 2 In the shown chip package structure, the capacitors for filtering and matching are generally ceramic capacitors. The ceramic capacitors have a high height and cannot be thinned, resulting in a large overall thickness of the chip package structure. Moreover, a special process needs to be adopted in the chip package structure to form the conformal shielding layer on the surface, increasing the packaging cost.

[0072] Figure 3 This is a cross-sectional view of a chip package structure provided by an embodiment of the present application.

[0073] As Figure 3 shown, the passive devices mounted through the SMD process in the chip package structure are replaced with thinner integrated product development (IPD) devices. The IPD planar plate (metal insulator metal, MIM) capacitor can realize the capacitance function at the pF level. And a thinner DTC can be used to replace the SMD capacitor above the nF level to realize the filtering function.

[0074] The MIM capacitor includes a lower planar electrode, an insulating layer, and an upper planar electrode which are sequentially stacked in a direction away from the substrate. The DTC includes a lower electrode, an insulating layer, and an upper electrode which are sequentially stacked in a direction away from the substrate. Both the lower electrode and the upper electrode are bent out in a groove shape.

[0075] After using the DTC to replace the SMD capacitor (above the nF level), although the height of the chip package structure can be reduced, the layout area occupied by the DTC in the horizontal direction will increase, resulting in an increase in the packaging area. Moreover, a special process needs to be adopted in the chip package structure to form the conformal shielding layer on the surface, increasing the packaging cost.

[0076] Figure 4A and Figure 4B is a cross-sectional view of a chip packaging structure provided by an embodiment of the present application, Figure 4C is a topological circuit diagram of a deep trench capacitor provided by an embodiment of the present application.

[0077] An embodiment of the present application provides a chip packaging structure, as Figure 4A shown, the chip packaging structure includes: a substrate, a first redistribution layer RDL1, a first device D1, a second redistribution layer RDL2, and at least one deep trench capacitor DTC.

[0078] The substrate may be a glass substrate, a silicon substrate, a ceramic substrate, etc. The present application does not limit the material of the substrate, and the substrates in the related art are applicable to the embodiments of the present application.

[0079] The first redistribution layer (re distribution layer) RDL1 is disposed on the first side of the substrate, and the second redistribution layer RDL2 is disposed on the second side of the substrate away from the first redistribution layer RDL, that is, the first redistribution layer RDL1 and the second redistribution layer RDL2 are disposed on opposite sides of the substrate.

[0080] The first redistribution layer RDL1 includes at least one metal interconnect layer, and the second redistribution layer RDL2 may also include at least one metal interconnect layer. Figure 4A In this embodiment, an example is given in which both the first redistribution layer RDL1 and the second redistribution layer RDL2 include multiple metal interconnect layers, and an insulating dielectric layer is disposed between adjacent metal interconnect layers. The present application does not limit the structures of the first redistribution layer RDL1 and the second redistribution layer RDL2, and the structures in the related art are applicable to the embodiments of the present application.

[0081] In some embodiments, the chip packaging structure further includes a via hole that penetrates the substrate and is respectively coupled to the first redistribution layer RDL1 and the second redistribution layer RDL2. According to the different substrate materials, the via hole may be, for example, TMV, TSV, TGV, etc. The present application does not limit the structure of the via hole, and it is only necessary to realize the interconnection of the first redistribution layer RDL1 and the second redistribution layer RDL2 through the via hole.

[0082] The first device D1 is disposed on the side of the first redistribution layer RDL1 away from the substrate, and the first device D1 is coupled to the first redistribution layer RDL1. Of course, one or more first devices D1 may be disposed on the side of the first redistribution layer RDL1 away from the substrate. In the case where multiple first devices D1 are disposed on the side of the first redistribution layer RDL1 away from the substrate, the functions of the multiple first devices D1 may be the same, may not be completely the same, or may be completely different.

[0083] The first device D1 can be a digital chip, or an analog chip, or a chip with any function in the terminal 1. For example, at least one transistor is integrated on the first device D1. The transistor here can be, for example, a field effect transistor (FET). The field effect transistor can include planar transistors such as metal-oxide-semiconductor field-effect transistor (MOSFET) or junction field-effect transistor (JFET), and can also include three-dimensional transistors such as fin field-effect transistor (FinFET), gate all around field effect transistor (GAAFET), or fork sheet field effect transistor (fork sheet FET or FSFET). The embodiments of the present application do not limit this.

[0084] Of course, in the embodiments of the present application, the first device D1 can be a bare die, or a packaged chip, or a co-packaged chip component, or a device element.

[0085] Exemplarily, the first device D1 can be a radio frequency transmitting device (such as a power amplifier, etc.), a radio frequency receiving device (such as a low noise amplifier, etc.), a digital circuit device (such as an application processor, a memory chip, etc.), or an analog circuit device (such as an operational amplifier, a sensor, etc.).

[0086] The chip packaging structure further includes a first molding layer disposed on a side of the first redistribution layer RDL1 away from the substrate, and the first molding layer covers the first device D1. The material of the first molding layer can be, for example, molding compound or insulating material.

[0087] In some embodiments, a plurality of receiving cavities are formed on a first side of the substrate, and the deep trench capacitor DTC is disposed on the first side of the substrate and extends into at least two of the receiving cavities. The first redistribution layer RDL1 is disposed on the first side of the substrate and is directly coupled to the deep trench capacitor DTC, and the deep trench capacitor DTC is coupled to the first device D1 through the first redistribution layer RDL1.

[0088] By adjusting the capacitance value of the deep trench capacitor DTC, the deep trench capacitor DTC can provide functions such as filtering and radio frequency impedance matching for the first device D1. For example, the deep trench capacitor DTC with a capacitance value in the pF range is mostly used for radio frequency impedance matching, and the deep trench capacitor DTC with a capacitance value in the nF and uF ranges is often placed near the power network to filter out power supply noise.

[0089] Exemplarily, the deep trench capacitor DTC has a raised portion formed by bending, and the accommodating cavity is used to accommodate the raised portion of the deep trench capacitor DTC (the part of the deep trench capacitor DTC located in the accommodating cavity). Each deep trench capacitor DTC has a plurality of raised portions, each raised portion occupies an accommodating cavity on the substrate, and each accommodating cavity contains a raised portion. This can reduce the process difficulty.

[0090] In some embodiments, the deep trench capacitor DTC includes a first electrode T1, a second electrode T2, and a capacitive dielectric layer T3 located between the first electrode T1 and the second electrode T2.

[0091] Exemplarily, as Figure 4A shown, the second electrode T2 forms at least two raised portions, and the raised portions extend into the accommodating cavity to enable the deep trench capacitor DTC to extend into the accommodating cavity.

[0092] In some embodiments, the first electrode T1 and the second electrode T2 are stacked to jointly form the above-mentioned raised portion. As Figure 4A shown, the portion of the first electrode T1 located in the substrate encloses a groove, and the groove is filled with an insulating dielectric layer. In other embodiments, the portion of the first electrode T1 located in the substrate is a solid structure and does not fill the insulating dielectric layer inside. Of course, the deep trench capacitor DTC provided in the embodiments of the present application is only an illustration and is not limited in any way. The deep trench capacitor DTC in the related art is applicable to the embodiments of the present application.

[0093] The materials of the capacitive dielectric layer T3 include, for example, polyimide (PI), tetraethyl orthosilicate (C8H20O4Si), silicon oxycarbide (SiOCH), silicon oxynitride (SiON), silicon carbide (SiC), or silicon nitride (SiN), silicon dioxide (SiO2), benzocyclobutene (BCB), polybenzoxazole (PBO), etc. The materials of the capacitive dielectric layer T3 may also include undoped silicon glass (USG) materials, phosphor silicate glass (PSG), fluorinated silica glass (FSG), boron phosphor silicate glass (BPSG), etc. silicon glasses (*SG). The material of the first electrode T1 includes conductive materials such as titanium nitride (TiN), and the material of the second electrode T2 includes conductive materials such as nitrogen-doped silicon, phosphorus-doped silicon, arsenic-doped silicon, boron-doped silicon, aluminum-doped silicon, etc.

[0094] The first electrode T1 is coupled to the first device D1 through the first redistribution layer RDL1, as Figure 4C shown, the second electrode T2 can be coupled to the ground network GND in the chip package structure. At this time, the deep trench capacitor DTC can be used as a filter capacitor, for example.

[0095] Exemplarily, as Figure 4A shown, the second electrode T2 is coupled to the first ground network GND1 in the first redistribution layer RDL1. For example, the accommodating cavity is in a groove shape, and a part of the structure of the deep trench capacitor DTC is accommodated in the groove, and the second electrode T2 is directly coupled to the first ground network GND1.

[0096] Or, exemplarily, as Figure 4B shown, the second electrode T2 is coupled to the second ground network GND2 in the second redistribution layer RDL2. For example, the accommodating cavity penetrates the substrate, and the second electrode T2 is directly coupled to the second ground network GND2 in the second redistribution layer RDL2.

[0097] Or, exemplarily, the second electrode T2 of the deep trench capacitor DTC can also be coupled to other devices in the chip package structure. For example, the second electrode T2 can be coupled to devices such as chips, capacitors, resistors, inductors, microstrip lines, etc. in the chip package structure. The embodiments of the present application do not limit this, and the enumeration in the embodiments of the present application is only for illustration.

[0098] In some embodiments, as Figure 4AAs shown, the chip packaging structure further includes solder balls, and the chip packaging structure can be coupled to the PCB through the solder balls. The materials of the solder balls can include, for example, copper, tin, silver, etc.

[0099] Exemplarily, as Figure 4A shown, the solder balls are disposed on the side of the second redistribution layer RDL2 away from the substrate. Alternatively, exemplarily, the solder balls are disposed on the side of the first redistribution layer RDL1 away from the substrate.

[0100] In the chip packaging structure provided by the embodiments of the present application, a trench capacitor DTC is internally packaged. However, the trench capacitor DTC is located within the substrate, and no separate space needs to be reserved for the deep trench capacitor DTC in the thickness direction. Therefore, disposing the trench capacitor DTC within the substrate can reduce the size of the chip packaging structure in the thickness direction. Moreover, the number of devices arranged within the substrate is usually relatively small, and there is relatively sufficient free space within the substrate to accommodate the deep trench capacitor DTC, without separately increasing the size in the horizontal direction. Therefore, disposing the trench capacitor DTC within the substrate can reduce the size of the chip packaging structure in the horizontal direction. That is to say, disposing the trench capacitor DTC within the substrate reduces the layout area originally required for placing independent capacitor devices, thereby reducing the size of the chip packaging structure. On this basis, a receiving cavity is formed on the substrate, and the deep trench capacitor DTC is directly formed on the surface of the substrate and is received by the receiving cavity. The shape of the deep trench capacitor DTC in the chip packaging structure of the present application matches the shape of the receiving cavity, and there is no requirement for the dimensional accuracy of the receiving cavity, and the product yield is high. Moreover, the first redistribution layer RDL1 can be directly formed on the surface of the deep trench capacitor DTC, without performing the steps of pre-processing for external device packaging, which can reduce the process. If the prepared capacitor device is integrally packaged within the substrate, the size of the receiving cavity formed on the substrate needs to match the capacitor device, with relatively high accuracy requirements and a large loss of yield. Moreover, after integrating the capacitor device into the substrate, pre-processing before packaging is also required to prepare the first redistribution layer RLD1, and the process is complex. Therefore, the chip packaging structure provided by the embodiments of the present application can reduce the size of the chip packaging structure while taking into account the yield.

[0101] Figure 5 This is a cross-sectional view of a chip packaging structure provided by an embodiment of the present application.

[0102] In some embodiments, as Figure 5 shown, the second electrode T2 of the deep trench capacitor DTC is coupled to the first ground network GND1 of the first redistribution layer RDL1, and the second electrode T2 is also coupled to the second ground network GND2 of the second redistribution layer RDL2.

[0103] The second electrode T2 is coupled to the first redistribution layer RDL1 and the second redistribution layer RDL2 respectively. It is equivalent to that the first redistribution layer RDL1 and the second redistribution layer RDL2 are coupled through the second electrode T2. The second electrode T2 can act as a via hole in the substrate, playing the role of interconnecting the first ground network GND1 and the second ground network GND2. It can reduce the number of via holes in the substrate to reduce the area of the chip package structure and simultaneously reduce the cost.

[0104] Regarding the coupling manner between the second electrode T2 and the first ground network GND1 of the first redistribution layer RDL1, for example, as Figure 4A shown, it can be that the second electrode T2 is spliced and coupled to the first ground network GND1. In this way, the first redistribution layer RDL1 can be fabricated after the deep trench capacitor DTC is fabricated, which can simplify the process steps.

[0105] Or, for example, as Figure 5 shown, it can also be that the second electrode T2 overlaps with the first ground network GND1, and the first ground network GND1 is located below the second electrode T2. During fabrication, first fabricate the layer where the first ground network GND1 of the first redistribution layer RDL1 is located, then fabricate the deep trench capacitor DTC, and then fabricate the other wiring layers of the first redistribution layer RDL1. In this way, the requirement for process precision can be reduced and the product yield can be improved.

[0106] In some embodiments, the capacitance value of the deep trench capacitor DTC is greater than or equal to 500 pF.

[0107] Since the capacitors with capacitance above 500 pF in the chip package structure will have relatively large dimensions in the thickness direction and the horizontal direction, the influence on the package area is relatively obvious. Therefore, integrating the capacitors with capacitance above 500 pF in the substrate can significantly save the package area of the chip package structure.

[0108] Figure 6 It is a top view of the arrangement of deep trench capacitors provided by the embodiments of the present application.

[0109] In some embodiments, for example, as Figure 6 shown, the deep trench capacitor DTC is arranged along the edge of the substrate.

[0110] For example, as Figure 5 shown, the edge of the deep trench capacitor DTC can coincide with the edge of the substrate. Or, for example, as Figure 6 shown, there is a gap between the edge of the deep trench capacitor DTC and the edge of the substrate.

[0111] Figure 6 Only the setting position of the deep trench capacitor DTC is schematically shown by a block diagram in

[0112] By arranging the deep trench capacitor DTC at the edge of the substrate, the layout of the central region can be unaffected, and the overall layout change of the chip packaging structure is relatively small. Moreover, when the second electrode T2 of the deep trench capacitor DTC is coupled to both the first ground network GND1 and the second ground network GND2, on the basis of its own capacitance function, the deep trench capacitor DTC can also perform electromagnetic shielding on the external radiation of the intermediate layer devices of the package, that is, the deep trench capacitor DTC has an external radiation suppression effect. Then, at the position where the deep trench capacitor DTC is arranged, there is no need to adopt a special process to sputter a conformal shielding layer on the side surface, reducing the packaging cost and simplifying the packaging steps.

[0113] In some embodiments, the deep trench capacitor DTC is arranged in a circle around the edge of the substrate.

[0114] In this way, on the one hand, with the same occupied area, the capacitance value of the deep trench capacitor DTC can be made relatively large. On the other hand, the conformal shielding layer can be completely not arranged on the side surface of the chip packaging structure.

[0115] Exemplarily, the deep trench capacitor DTC is a ring structure. In this way, the shielding effect is good.

[0116] Or, exemplarily, as Figure 6 shown, the deep trench capacitor DTC is arranged in a discontinuous and intermittent circle around the edge of the substrate.

[0117] In this way, by controlling the size of the gap between two adjacent parts of the capacitor, the deep trench capacitor DTC can still shield the entire side surface of the chip packaging structure. Moreover, the process difficulty is relatively low and it is easy to implement.

[0118] Or, exemplarily, the deep trench capacitor DTC is arranged in a circle around the edge of the substrate in a staggered overlapping manner. The embodiments of the present application do not limit the setting manner of the deep trench capacitor DTC, and generally shows a ring shape, as long as it can shield the entire side surface of the chip packaging structure.

[0119] Figure 7A and Figure 7B is a cross-sectional view of a chip packaging structure provided by an embodiment of the present application, Figure 7C is a layout diagram of a device and a deep trench capacitor provided by an embodiment of the present application.

[0120] In some embodiments, as Figure 7A shown, the chip packaging structure further includes a second device D2 and a third device D3. The second device D2 and the third device D3 are arranged in the substrate, and at least one deep trench capacitor DTC is arranged between the second device D2 and the third device D3.

[0121] Exemplarily, the second device D2 is coupled to the first redistribution layer RDL1 and / or the second redistribution layer RDL2, and the third device D3 is coupled to the first redistribution layer RDL1 and / or the second redistribution layer RDL2. Figure 7A Taking the case where both the second device D2 and the third device D3 are coupled to the second redistribution layer RDL2 as an example for illustration.

[0122] That is to say, in the embodiments of the present application, deep trench capacitors DTC are provided along the edge of the substrate, and deep trench capacitors DTC can also be provided in the middle region of the substrate.

[0123] In some embodiments, the second electrode T2 of the deep trench capacitor DTC is coupled to both the first ground network GND1 and the second ground network GND2. In this way, the deep trench capacitor DTC can play the role of cavity shielding and internal isolation, and the deep trench capacitor DTC can shield the electromagnetic interference between the internal second device D2 and the third device D3. For example, if the second device D2 is a source of interference and the third device D3 is a device being disturbed, the electromagnetic interference of the second device D2 on the third device D3 can be shielded by the deep trench capacitor DTC.

[0124] Exemplarily, the second device D2 and the third device D3 are devices with different magnetic field intensities.

[0125] For example, the second device D2 includes a device with a magnetic field intensity greater than or equal to 50 dBμV / m. The second device D2 is a strong radiation type device and belongs to the interference source. The third device D3 includes a device with a magnetic field intensity less than 50 dBμV / m. The third device D3 is a radiation sensitive type device and belongs to the device being disturbed.

[0126] Exemplarily, the second device D2 includes a radio frequency transmitting device (such as a power amplifier, etc.), and the third device D3 includes a radio frequency receiving device (such as a low noise amplifier, etc.). Or, the second device D2 includes a digital circuit device (such as an application processor, a memory chip, etc.), and the third device D3 includes an analog circuit device (such as an operational amplifier, a sensor, etc.).

[0127] In the present application, the interfering device and the device being disturbed are isolated by the deep trench capacitor DTC, and a dedicated shielding structure can be dispensed with, simplifying the structure.

[0128] In some embodiments, as Figure 7B shown, the chip package structure includes deep trench capacitors DTC disposed around the substrate, and also includes deep trench capacitors DTC disposed between the second device D2 and the third device D3.

[0129] As Figure 7C shown, from a top view, the second device D2 and the third device D3 are located in the isolation area surrounded by the deep trench capacitor DTC, and there is a deep trench capacitor DTC between the second device D2 and the third device D3.

[0130] In this way, there is no need to separately provide a shielding layer on the side surface or the side and top surfaces of the chip packaging structure, nor is there a need to separately provide a shielding layer between adjacent interference sources and radiation-sensitive bodies. The structure is simple and the radiation shielding effect is good.

[0131] Figure 8 The figure is a cross-sectional view of a chip packaging structure provided by an embodiment of the present application.

[0132] In some embodiments, as Figure 8 shown, the chip packaging structure further includes a fourth device D4. The fourth device D4 is disposed on a side of the second redistribution layer RDL2 away from the substrate, and the fourth device D4 is coupled to the second redistribution layer RDL2.

[0133] Exemplarily, the chip packaging structure further includes a second encapsulation layer. The second encapsulation layer is disposed on a side of the second redistribution layer RDL2 away from the substrate. The second encapsulation layer covers the fourth device D4 and exposes the solder balls.

[0134] In some embodiments, the solder balls are located on the periphery of the fourth device D4. In this way, the solder balls can play a shielding role and reduce the radiation interference of the fourth device D4.

[0135] In some embodiments, the magnetic field intensity of the first device D1 is less than 50 dBμV / m, belonging to a non-strong radiation type device.

[0136] By disposing a non-strong radiation type device on a side of the first redistribution layer RDL1 away from the substrate, there is no need to provide a shielding layer on the surface of the side where the first device D1 of the chip packaging structure is located, simplifying the structure and manufacturing process.

[0137] In some embodiments, the magnetic field intensity of the first device D1 is less than the magnetic field intensities of the second device D2, the third device D3, and the fourth device D4.

[0138] There are the first redistribution layer RDL1, the second redistribution layer RDL2, the deep trench capacitor DTC, and the solder balls around the second device D2, the third device D3, and the fourth device D4 as electromagnetic shielding protection layers. A shielding layer can be specifically formed on the side surface of the chip packaging structure through a sputtering process. After the first device D1 is a non-strong radiation type device, there is no need to specifically form a shielding layer on the top surface of the chip packaging structure either. Then, there is no need to provide a shielding layer on the outer surface of the entire chip packaging structure, and the overall external radiation level of the package can still be controlled, simplifying the process and reducing costs.

[0139] Figure 9 The figure is a cross-sectional view of a chip packaging structure provided by an embodiment of the present application.

[0140] In other embodiments, as Figure 9As shown, the magnetic field strength of the first device D1 is greater than or equal to 50 dBμV / m, and it belongs to the category of strong radiation devices.

[0141] In this case, for example, a shielding layer can be provided on the surface of the chip packaging structure on the side where the first device D1 is located to form electromagnetic shielding.

[0142] Or, for example, as Figure 9 shown, the chip packaging structure further includes a shielding cover, the shielding cover is buckled on the first redistribution layer RDL1, and the first device D1 is located inside the shielding cover. The first encapsulation layer covers the shielding cover and the first redistribution layer RDL1, so that the shielding cover is encapsulated inside the chip packaging structure.

[0143] For example, the shielding cover is an open cavity, and the open cavity is buckled on the first redistribution layer RDL1.

[0144] Or, for example, as Figure 9 shown, the shielding cover includes bonding wires arranged crosswise, and the bonding wires are coupled to the first ground network GND1 of the first redistribution layer RDL1. For example, the shielding cover is a wire cage formed by crosswise surrounding of bonding wires.

[0145] Even if a strong radiation device needs to be provided above the first redistribution layer RDL1, by providing a shielding cover with a local shielding function above the strongly radiating first device D1, the first device D1 is electromagnetically protected by the shielding cover, and there is still no need to provide a shielding layer on the outer surface of the chip packaging structure, and the overall external radiation level of the package can still be controlled.

[0146] Next, a schematic description of the packaging process of the chip packaging structure provided in the embodiments of the present application is given.

[0147] The embodiments of the present application provide a packaging method for a chip packaging structure, taking Figure 9 the chip packaging structure shown as an example, as Figure 10 shown, the packaging method includes:

[0148] S1, as Figure 11A shown, drill holes on the second side of the substrate, and embed the second device D2 and the third device D3.

[0149] As Figure 11A shown, the second device D2 and the third device D3 are arranged inside the substrate, and the active surfaces of the second device D2 and the third device D3 are exposed on the second side surface of the substrate.

[0150] S2, as Figure 11B shown, form a plurality of accommodation cavities on the first side of the substrate.

[0151] Of course, the accommodation cavity can be a groove-like structure, and the accommodation cavity can also penetrate the substrate. Figure 11BThis is only a schematic illustration and is not subject to any limitation.

[0152] S3. As Figure 11C shown, a deep trench capacitor DTC is formed on the first side of the substrate, and the deep trench capacitor DTC extends from the first side of the substrate into at least two accommodation cavities.

[0153] For example, the deep trench capacitor DTC includes a first electrode T1, a second electrode T2, and a capacitive dielectric layer T3 located between the first electrode T1 and the second electrode T2.

[0154] Step S3 includes:

[0155] S31. Form the second electrode T2 on the first side of the substrate. The second electrode T2 extends into the accommodation cavity and fits with the inner surface of the accommodation cavity.

[0156] S32. Form the capacitive dielectric layer T3 on the surface of the second electrode T2.

[0157] S33. Form the first electrode T1 on the surface of the capacitive dielectric layer T3.

[0158] Exemplarily, if the deep trench capacitor DTC is located above the first ground network GND1 and is lapped with the first ground network GND1, then the first ground network GND1 is formed before the deep trench capacitor DTC is formed. If the deep trench capacitor DTC is spliced and connected with the first ground network GND1, then the deep trench capacitor DTC can be formed first, and then the first ground network GND1 is formed.

[0159] The first electrode T1 of the deep trench capacitor DTC is coupled to other networks of the first redistribution layer RDL1, and the second electrode T2 is coupled to the first ground network GND1 of the first redistribution layer RDL1. The deep trench capacitor DTC can, for example, penetrate the substrate so that the second side of the substrate exposes the second electrode T2, and subsequently, the second ground network GND2 in the second redistribution layer RDL2 is coupled to the second electrode T2.

[0160] S4. As Figure 11D shown, a temporary bonding carrier is placed on the second side of the substrate, and a first redistribution layer RDL1 is formed on the first side of the substrate. The first redistribution layer RDL1 is directly coupled to the deep trench capacitor DTC.

[0161] The embodiments of the present application do not limit the process of forming the first redistribution layer RDL1 and the structure of the first redistribution layer RDL1. The redistribution layers in the related art are all applicable to the embodiments of the present application.

[0162] S5. As Figure 11E shown, the temporary bonding carrier on the second side of the substrate is removed, a temporary bonding carrier is re-placed on the surface of the first redistribution layer RDL1, and a second redistribution layer RDL2 is formed on the second side of the substrate.

[0163] S6. As shown in Figure 11F Figure [not provided], remove the temporary bonding carrier, bond the first device D1 on the side of the first redistribution layer RDL1 away from the substrate, form a shielding cover, and form a first encapsulation layer.

[0164] S7. As shown in Figure 11G Figure [not provided], bond the fourth device D4 on the surface of the second redistribution layer RDL2, and form a second encapsulation layer.

[0165] S8. As shown in Figure 9 Figure [not provided], implant solder balls.

[0166] In the case where the chip packaging structure does not include a shielding cover, the step of forming the shielding cover can be omitted. In the case where the chip packaging structure does not include the fourth device D4, the steps of forming the fourth device D4 and the second encapsulation layer can be omitted, and solder balls can be directly implanted on the surface of the second redistribution layer RDL2. In the case where the chip packaging structure does not include the second device D2 and the third device D3, the steps of embedding the second device D2 and the third device D3 in the substrate can be omitted, and a deep trench capacitor DTC can be directly formed.

[0167] After coupling the chip packaging structure provided in the embodiment of the present application to a circuit board through solder balls, a circuit board assembly provided in the embodiment of the present application can be formed. Of course, the chip packaging structure can also be coupled to other chips or device structures through solder balls, which all fall within the application scope of the chip packaging structure provided in the embodiment of the present application. The chip packaging structure or the circuit board assembly provided in the embodiment of the present application can be applied to any of the above-mentioned terminals provided in the embodiment of the present application.

[0168] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that, Comprising: A substrate, on the first side of which a plurality of receiving cavities are formed; At least one deep trench capacitor, which is disposed on the first side of the substrate and extends into at least two of the receiving cavities; A first rewiring layer, disposed on the first side of the substrate and directly coupled to the deep trench capacitor; A first device, disposed on the side of the first rewiring layer away from the substrate and coupled to the deep trench capacitor through the first rewiring layer; A second rewiring layer, disposed on the second side of the substrate away from the first rewiring layer.

2. The chip packaging structure according to claim 1, characterized in that, The deep trench capacitor is in contact with the inner surface of the receiving cavity.

3. The chip packaging structure according to claim 1 or 2, characterized in that, The deep trench capacitor includes a first electrode and a second electrode, the first electrode is coupled to the first device, and the second electrode is coupled to both the first ground network of the first rewiring layer and the second ground network of the second rewiring layer.

4. The chip packaging structure according to claim 3, characterized in that, The first electrode and the second electrode form at least two protruding portions, and the deep trench capacitor extending into at least two of the receiving cavities specifically means: the protruding portions extend into the receiving cavities.

5. The chip packaging structure according to any one of claims 1-4, characterized in that, The second electrode is directly coupled to the first ground network.

6. The chip packaging structure according to any one of claims 1-5, characterized in that, The receiving cavity penetrates the substrate, and the second electrode is directly coupled to the second ground network.

7. The chip packaging structure according to any one of claims 2-6, characterized in that, The deep trench capacitor is disposed along the edge of the substrate.

8. The chip packaging structure according to any one of claims 1-7, characterized in that, The chip package structure further includes a second device and a third device; The second device and the third device are disposed in the substrate, and at least one deep trench capacitor is located between the second device and the third device.

9. The chip packaging structure according to claim 8, characterized in that, The magnetic field intensities of the second device and the third device are different.

10. The chip packaging structure according to claim 8 or 9, characterized in that, The second device includes a radio frequency transmitting device, and the third device includes a radio frequency receiving device; Or, The second device includes a digital circuit device, and the third device includes an analog circuit device; Or, The magnetic field intensity of the second device is greater than or equal to 50 dBμV / m, and the magnetic field intensity of the third device is less than 50 dBμV / m.

11. The chip packaging structure according to any one of claims 1-10, characterized in that, The magnetic field intensity of the first device is less than 50 dBμV / m; Or, The first device includes a radio frequency receiving device or an analog circuit device.

12. The chip packaging structure according to any one of claims 1-10, characterized in that, The magnetic field intensity of the first device is greater than or equal to 50 dBμV / m; or, the first device includes a radio frequency transmitting device or a digital circuit device; The chip package structure further includes a shielding cover and a plastic encapsulation layer, the shielding cover is buckled on the first rewiring layer, and the first device is located inside the shielding cover; the plastic encapsulation layer covers the shielding cover and the first rewiring layer.

13. The chip package structure according to claim 12, wherein, The shielding cover includes bonding wires disposed crosswise, and the bonding wires are coupled to the first ground network of the first rewiring layer.

14. The chip package structure according to any one of claims 1-13, wherein, The capacitance value of the deep trench capacitor is greater than or equal to 500 pF.

15. A circuit board assembly, wherein, Comprising a circuit board and a chip package structure, the chip package structure is disposed on the circuit board, and the chip package structure includes the chip package structure according to any one of claims 1-14.

16. A terminal, wherein, Comprising a rear shell and a circuit board assembly, the circuit board assembly is disposed inside the rear shell, and the circuit board assembly includes the circuit board assembly according to claim 15.

17. A packaging method for a chip package structure, wherein, Comprising: Forming a plurality of receiving cavities on the first side of the substrate; A deep trench capacitor is formed on a first side of the substrate, and the deep trench capacitor extends into at least two of the accommodation cavities; A first metal wiring layer is formed on the first side of the substrate, and the first metal wiring layer is directly coupled to the deep trench capacitor; A second metal wiring layer is formed on a second side of the substrate away from the first metal wiring layer; A first device is bonded to a side of the first metal wiring layer away from the substrate, and the first device is coupled to the deep trench capacitor through the first metal wiring layer.

18. The packaging method according to claim 17, wherein, Forming a deep trench capacitor on a first side of the substrate, comprising: Forming a second electrode on the first side of the substrate, the second electrode extending into the accommodation cavity and fitting with an inner surface of the accommodation cavity; Forming a capacitor dielectric layer on a surface of the second electrode; Forming a first electrode on a surface of the capacitor dielectric layer.

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