Thin film attenuator design method and thin film attenuator

Abstract

The invention provides a thin film attenuator design method. The thin film attenuator design method comprises the following specific steps: S1, establishing a sheet-type thin film attenuator model through an HFSS; s2, exporting a CAD file from the thin film attenuator model, and processing the CAD file into a photoetching plate processing layout; s3, processing according to the processing layout by using a thin film process to obtain a thin film attenuator entity; s4, testing the thin film attenuator object by using the vector network analyzer to obtain corresponding test data; s5, constructing a parasitic parameter compensation circuit model, and importing test data for high-frequency parasitic parameter analysis to obtain a compensation parasitic parameter value; s6, converting the compensation parasitic parameter value into a micro-strip model, substituting the micro-strip model into the HFSS to obtain a new attenuator model, and optimizing simulation; and S7, manufacturing and testing the new attenuator model again. According to the design method provided by the invention, the influence of the high-frequency parasitic effect is analyzed, so that the high-frequency deterioration of the attenuation is reduced, and the performance of the attenuator is remarkably improved.

Description

Technical Field

[0001] This application relates to the field of attenuator structure design, and particularly to a design method for thin-film attenuators and thin-film attenuators. Background Art

[0002] Attenuators are widely used in various scenarios where power levels need to be adjusted, such as controlling the levels at the input / output of amplifiers, controlling the branch attenuation amount, etc. The performance of attenuators affects the stability of signal levels. Traditional attenuator design methods include: index analysis, software modeling, plate making and processing, physical testing, and error analysis, etc. Although thin-film processes have the advantage of miniaturization, due to the limitation of key dimensions, the attenuation fluctuations designed by ordinary design methods deteriorate severely as the frequency increases, and often cannot meet the high-frequency usage requirements. Through comparative analysis, the main factors causing the performance deterioration of thin-film attenuators are: at high frequencies, there are parasitic inductance and parasitic capacitance effects, and the parasitic effects of the devices severely deteriorate the performance of the attenuators. Summary of the Invention

[0003] To solve the above problems, this application provides a design method for thin-film attenuators, which compensates for the parasitic inductance and parasitic capacitance caused by high frequencies to avoid the deterioration effect of parasitic effects on the performance of attenuators.

[0004] To achieve the above purpose, the technical solutions adopted in this application are as follows:

[0005] A design method for thin-film attenuators includes the following specific steps:

[0006] S1: Establish a chip-type thin-film attenuator model;

[0007] S2: Process the thin-film attenuator model into a lithography plate processing layout;

[0008] S3: Process according to the processing layout using thin-film processes to obtain a physical thin-film attenuator;

[0009] S4: Use a vector network analyzer to test the physical thin-film attenuator to obtain corresponding test data;

[0010] S5: Construct a parasitic parameter compensation circuit model, import the test data for high-frequency parasitic parameter analysis, and obtain the compensated parasitic parameter values;

[0011] S6: Convert the compensated parasitic parameter values into a microstrip model, bring them into HFSS to obtain a new version of the attenuator model and optimize the simulation;

[0012] S7: Remake and test the new version of the attenuator model.

[0013] Further, the thin-film attenuator model includes a T-shaped structure.

[0014] Furthermore, the relationship between the attenuation of the thin-film attenuator and the resistance value is as follows:

[0015] S 21 = 10 -A / 20 ;

[0016]

[0017]

[0018] where: S 21 is the transmission coefficient, A is the attenuation in dB (insertion loss), Z0 is the characteristic impedance of the input and output ports, and R T1 , R T2 and R T3 are the resistance values of resistor R1, resistor R2, and resistor R3 in the attenuator.

[0019] Furthermore, the thin-film attenuator model includes a π-type architecture.

[0020] Furthermore, the relationship between the attenuation of the thin-film attenuator and the resistance value is as follows:

[0021] S 21 = 10 -A / 20 ;

[0022]

[0023]

[0024] where: S 21 is the transmission coefficient, A is the attenuation in dB (insertion loss), Z0 is the characteristic impedance of the input and output ports, and R π1 , R π2 and R π3 are the resistance values of resistor R1, resistor R2, and resistor R3 in the attenuator.

[0025] Furthermore, the calculation formula for the resistance value in the thin-film attenuator is:

[0026]

[0027] where Rs is the sheet resistivity of the thin-film resistor, with the unit of Ω / square, abbreviated as sheet resistance; L is the length of the film resistor; W is the width of the film resistor; according to the above formula, the external dimensions of the thin-film resistor can be calculated, and then the processing layout can be obtained based on the thin-film attenuator model.

[0028] Furthermore, to construct a parasitic parameter compensation circuit model, import test data for high-frequency parasitic parameter analysis, and obtain the compensated parasitic parameter values, the following steps are included:

[0029] Establish a parasitic parameter compensation circuit model using ADS software;

[0030] Import the test data into the parasitic parameter compensation circuit model for parasitic parameter compensation, and fit out the compensated parasitic parameter values.

[0031] Furthermore, the compensated parasitic parameter values include compensated parasitic inductance values and compensated parasitic capacitance values.

[0032] Furthermore, the thin film process includes cleaning, sputtering, electroplating, photolithography, development, etching, resistance value screening, heat treatment, scribing, and special inspection processing procedures.

[0033] A thin film attenuator is designed according to the thin film attenuator design method described above.

[0034] Beneficial effects:

[0035] 1. By compensating for the parasitic inductance and parasitic capacitance caused by high frequencies, the deterioration effect of parasitic effects on the performance of the attenuator is avoided. Description of the Drawings

[0036] Figure 1 It is a schematic flow chart of a thin film attenuator design method;

[0037] Figure 2 It is a schematic circuit architecture diagram of a thin film attenuator;

[0038] Figure 3 It is a schematic diagram of the first thin film attenuator model structure;

[0039] Figure 4 It is a schematic diagram of the attenuation curve of the first thin film attenuator;

[0040] Figure 5 It is a schematic diagram of the parasitic parameter compensation circuit model structure;

[0041] Figure 6 It is a schematic diagram of the second thin film attenuator model structure;

[0042] Figure 7 It is a schematic diagram of the attenuation curve of the second thin film attenuator.

[0043] Description of the reference numerals: Substrate 1, Metal Conductor 2, Resistance Layer 3. Detailed Embodiments

[0044] The following describes the embodiments of the present disclosure in detail with reference to the drawings.

[0045] The following uses specific specific examples to illustrate the implementation manners of the present disclosure. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The present disclosure can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0046] Embodiment 1

[0047] As Figure 1 shown is a flow schematic diagram of a thin film attenuator design method, including the following specific steps:

[0048] S1: Establish a chip thin film attenuator model through HFSS;

[0049] S2: Export the thin film attenuator model to a CAD file and process it into a lithography plate processing layout;

[0050] S3: Process according to the processing layout using a thin film process to obtain a physical thin film attenuator;

[0051] S4: Use a vector network analyzer to test the physical thin film attenuator to obtain corresponding test data;

[0052] S5: Construct a parasitic parameter compensation circuit model, import the test data for high-frequency parasitic parameter analysis, and obtain the compensated parasitic parameter values;

[0053] S6: Convert the compensated parasitic parameter values into a microstrip model, bring them into HFSS to obtain a new version of the attenuator model and optimize the simulation;

[0054] S7: Remake and test the new version of the attenuator model.

[0055] In specific implementation, in this embodiment, the chip thin film attenuator model established through HFSS is as Figure 2 (a) shows the adoption of a T-type circuit architecture, and the corresponding physical model is as Figure 3 shown. In the physical model, the attenuator includes a metal conductor 2, a resistor layer 3, and a substrate 1. Among them, the upper parts of the left and right resistor layers 3 are the resistors R1 and R2 in the circuit architecture, and the lower parts of the resistor layer 3 are the resistor R3 in the circuit architecture. That is, the resistor R3 in the physical object is composed of two parallel parts to enable the attenuator to achieve a large attenuation effect.

[0056] In specific implementation, the relationship between the attenuation of the thin film attenuator and the resistance value is as follows:

[0057] S 21 =10 -A / 20 ;

[0058]

[0059]

[0060] Wherein: S 21 is the transmission coefficient, A is the attenuation in dB (insertion loss), Z0 is the characteristic impedance of the input and output ports, and R T1 , R T2 and R T3 are the resistance values of resistor R1, resistor R2, and resistor R3 in the attenuator.

[0061] According to the above formula, when Z0 is a certain value, such as 50 Ω, the resistance values R T1 , R T2 and R T3 of each resistor of the attenuator can be calculated.

[0062] In specific implementation, after calculating the resistance values of each resistor according to the above formula based on the attenuation, and then according to the calculation formula of the resistance value and its shape and size in the thin film attenuator:

[0063]

[0064] Wherein, Rs is the surface resistivity of the thin film resistor, with the unit of Ω / square, simply called sheet resistance; L is the length of the film resistor; W is the width of the film resistor.

[0065] The external dimensions of the thin film resistor can be calculated. After obtaining the dimensions of the thin film resistor, combined with the thin film attenuator model, the specific dimensions of each component can be obtained; then the thin film attenuator model is exported as a CAD file, processed into a photolithography plate processing layout, and processed using the thin film process according to the processing layout to obtain the physical object of the thin film attenuator; further, the thin film process includes cleaning, sputtering, electroplating, photolithography, development, etching, resistance value screening, heat treatment, dicing, and special inspection processing procedures.

[0066] In specific implementation, after manufacturing the physical object of the thin film attenuator, use a vector network analyzer to test the physical object of the thin film attenuator, and obtain the corresponding test data and form a test result file S2P. The main parameter of the test data in the test result file S2P is the attenuation (insertion loss). Then import the test result file S2P into the ADS software to obtain Figure 4 the attenuation curve shown as follows. It can be seen that the attenuation deteriorates rapidly in the high-frequency state.

[0067] In specific implementation, a parasitic parameter compensation circuit model is constructed, and test data is imported for high-frequency parasitic parameter analysis to obtain compensated parasitic parameter values, including the following steps:

[0068] After obtaining the test result file, use ADS software to establish a parasitic parameter compensation circuit model as Figure 5 shown;

[0069] Import the test data (or the test result file S2P) into the parasitic parameter compensation circuit model for parasitic parameter compensation, and fit the compensated parasitic parameter values for input, output, and ground as shown in the model. Further, the compensated parasitic parameter values include compensated parasitic inductance values and compensated parasitic capacitance values. Since the parasitic inductance is large and the parasitic capacitance is small, the parasitic effects brought by the parasitic inductance should be compensated emphatically. Due to the large parasitic inductance, the attenuation of the circuit at high frequencies becomes smaller. Circuit matching design is carried out at the input and output ends, and capacitance compensation is carried out at the ground end. The calculation formula for the capacitance value of the chip capacitor is as follows:

[0070]

[0071] In the formula, C is the capacitance value, ε is the dielectric constant, S is the plate area, and d is the plate spacing.

[0072] Then convert the compensated parasitic parameter values into a microstrip model, substitute the calculated chip capacitor size into HFSS to obtain a new version of the attenuator model, and perform size fine-tuning and optimization simulation according to the actual situation to obtain a new version of the attenuator model as Figure 6 shown; where Figure 5 the parasitic parameter values of the left and right compensation inductors L1, L2 and capacitors C1, C2 correspond to adding metal conductor 2 bumps on the middle substrate 1 in Figure 6 ; Figure 5 the parasitic parameter values of the compensation inductor L3 and capacitor C3 in the middle and lower parts correspond to adding metal conductor 2 bumps on the two side substrates 1 in Figure 6 ;

[0073] After remaking the new version of the attenuator model and testing the thin-film attenuator physical object using a vector network analyzer, import the test result file S2P into ADS software to obtain a new version of the attenuation curve graph as Figure 7 shown; compared with Figure 4 , it can be seen that the new version of the attenuator can still maintain good attenuation performance at high frequencies.

[0074] Embodiment 2

[0075] The difference from Embodiment 1 is that, as Figure 2 (b) shown, the thin-film attenuator model in this embodiment adopts a π-type architecture.

[0076] In a specific implementation, the relationship between the attenuation and resistance of the thin film attenuator is:

[0077] S 21 =10 -A / 20 ;

[0078]

[0079]

[0080] Where: S 21 Transmission coefficient, A is the attenuation (insertion loss) in dB, Z0 is the input and output port characteristic impedance, R T1 , R T2 and R T3 is the resistance value of resistors R1, R2 and R3 in the attenuator. According to the above formula, when Z0 is a certain value, the resistance value of each resistor of the attenuator can be calculated.

[0081] Embodiment 3

[0082] A thin film attenuator, such as Figure 6 As shown, it is designed according to the thin film attenuator design method as described above, including a metal conductor 2, a resistor layer 3, and a substrate 1; the resistor layer 3 is provided with two parallel ones, and a metal conductor 2 is provided between the upper parts of the resistor layer 3 as a connecting wire of the resistor layer 3, and a metal conductor 2 is provided on the outer side of the upper part of the resistor layer 3 as the input and output ports of the attenuator; the lower end of the resistor layer 3 is provided with a metal conductor 2 as a grounding wire; a substrate 1 is provided between the upper and lower metal conductors 2 to prevent the upper and lower metal conductors 2 from being connected and short-circuited; metal conductor 2 bumps are provided on the substrates 1 on both sides as the inductance and capacitance compensation values ​​on the grounding side; a metal conductor 2 bump is provided on the middle substrate 1 as the inductance and capacitance compensation values ​​between resistors. Compared with the uncompensated state, the film attenuator with compensation design can maintain better attenuation performance at high frequencies.

[0083] The present application provides a design method for a thin-film attenuator, including the following specific steps: S1: Establish a chip-type thin-film attenuator model through HFSS; S2: Export the thin-film attenuator model as a CAD file and process it into a lithography plate processing layout; S3: Process the thin-film attenuator in kind using a thin-film process according to the processing layout; S4: Use a vector network analyzer to test the thin-film attenuator in kind to obtain corresponding test data; S5: Construct a parasitic parameter compensation circuit model, import the test data for high-frequency parasitic parameter analysis, and obtain the compensated parasitic parameter values; S6: Convert the compensated parasitic parameter values into a microstrip model, bring them into HFSS to obtain a new version of the attenuator model and optimize the simulation; S7: Remake and test the new version of the attenuator model. For an attenuator with deteriorated test performance, this method estimates the values of high-frequency parasitic parameters (inductance value / capacitance value) through parameter analysis of the software model and fitting analysis of simulation data and test data, substitutes the estimated parasitic parameters into the simulation model for analysis to explore the causal relationship, substitutes the clearly analyzed high-frequency parasitic parameters into the model for compensation, anticipates the deterioration of attenuation fluctuations, and corrects the error in advance during design. The design method for a thin-film attenuator proposed by the present invention reduces the high-frequency deterioration of the attenuation amount by analyzing the influence of high-frequency parasitic effects, and significantly improves the performance of the attenuator.

[0084] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "middle", "length", "upper", "lower", "front", "rear", "vertical", "horizontal", "inner", "outer", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0085] In the present invention, unless otherwise clearly specified and limited, the first feature being "on" the second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. The meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise clearly specifically limited.

[0086] In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or communicable with each other; it may be directly connected, or indirectly connected through an intermediate medium, and may be the internal communication of two components or the interaction relationship between two components, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0087] The above are only illustrative of the embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc. made without creative efforts within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for designing a thin-film attenuator, characterized in that, It includes the following specific steps: S1: Establish a chip thin-film attenuator model; S2: Process the thin-film attenuator model into a lithography plate processing layout; S3: Process according to the processing layout using thin-film technology to obtain a physical thin-film attenuator; S4: Use a vector network analyzer to test the physical thin-film attenuator to obtain corresponding test data; S5: Construct a parasitic parameter compensation circuit model, import the test data for high-frequency parasitic parameter analysis, and obtain the compensated parasitic parameter values; S6: Convert the compensated parasitic parameter values into a microstrip model, bring it into HFSS to obtain a new version of the attenuator model and optimize the simulation; S7: Remake and test the new version of the attenuator model.

2. The method for designing a thin-film attenuator according to claim 1, characterized in that, The thin-film attenuator model includes a T-type architecture.

3. The method for designing a thin-film attenuator according to claim 2, characterized in that, The relationship between the attenuation amount and the resistance value of the thin-film attenuator is: S 21 ＝10 -A / 20 ； Where: S 21 is the transmission coefficient, A is the attenuation in dB (insertion loss), Z0 is the characteristic impedance of the input and output ports, R T1 , R T2 and R T3 are the resistances of resistor R1, resistor R2, and resistor R3 in the attenuator.

4. The method for designing a thin-film attenuator according to claim 1, characterized in that, The thin-film attenuator model includes a π-type architecture.

5. The method for designing a thin-film attenuator according to claim 4, characterized in that, The relationship between the attenuation amount and the resistance value of the thin-film attenuator is: S 21 ＝10 -A / 20 ； Where: S 21 is the transmission coefficient, A is the attenuation in dB (insertion loss), Z0 is the characteristic impedance of the input and output ports, R π1 , R π2 and R π3 are the resistances of resistor R1, resistor R2 and resistor R3 in the attenuator.

6. The method for designing a thin-film attenuator according to claim 3 or 5, characterized in that, The calculation formula for the resistance value in the thin-film attenuator is: In the formula, Rs is the surface resistivity of the thin-film resistor, with the unit of Ω / square, abbreviated as sheet resistance; L is the length of the film resistor; W is the width of the film resistor; according to the above formula, the external dimensions of the thin-film resistor can be calculated, and then the processing layout can be obtained based on the thin-film attenuator model.

7. The method for designing a thin-film attenuator according to claim 1, characterized in that, Construct a parasitic parameter compensation circuit model, import the test data for high-frequency parasitic parameter analysis, and obtain the compensated parasitic parameter values, including the following steps: Use ads software to establish a parasitic parameter compensation circuit model; Import the test data into the parasitic parameter compensation circuit model for parasitic parameter compensation, and fit out the compensated parasitic parameter values.

8. The method for designing a thin-film attenuator according to claim 7, characterized in that, The compensated parasitic parameter values include compensated parasitic inductance values and compensated parasitic capacitance values.

9. The method for designing a thin-film attenuator according to claim 1, characterized in that, The thin-film technology includes cleaning, sputtering, electroplating, lithography, development, etching, resistance value screening, heat treatment, dicing, and special inspection processing procedures.

10. A thin-film attenuator, characterized in that,It is designed according to the thin-film attenuator design method described in any one of claims 1 to 9.

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