Fault detection system and method for switched capacitor converter

Abstract

Fault detection systems and methods for switched capacitor converters are provided. A system includes a switched capacitor converter and fault detection circuitry. The switched capacitor converter is configured to perform direct current (DC) to DC conversion at a predefined conversion ratio, and includes a first power stage having a first switch, and includes a first capacitor having a first end and a second end. The fault detection circuitry is coupled to a second end of the first capacitor and is configured to monitor a second terminal voltage of the first capacitor and assert at least one fault signal in response to determining that any of the second terminal voltages is indicative of a fault during a start-up sequence of the switched capacitor converter.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to switched capacitor converters, including a fault detection system for a switched capacitor converter. Background Art

[0002] The increase in the number of features and functions in smart handheld devices such as smartphones has led to an increase in the total power consumption requirements, which in turn has led to faster battery discharge and more frequent charging of such devices. Many such devices have both inductive and "fast" charging capabilities, where fast charging is intended to provide increased power while charging in an attempt to reduce the time spent by the end user in charging the device. Additionally, such devices typically require reverse power transfer from the battery to support, for example, phone-to-phone or phone-to-device charging, thus requiring the direct current (DC) to DC converter of the device to be bidirectional (supporting both forward step-down conversion and reverse step-up conversion). Such requirements may make it complex and / or impractical to apply conventional fault detection techniques to identify short circuits or other faults in the DC to DC converter. Summary of the Invention

[0003] A brief overview of various exemplary embodiments is presented below. Some simplifications and omissions may have been made in the following overview, with the aim of highlighting and introducing some aspects of the various exemplary embodiments, rather than limiting the scope. A detailed description of the exemplary embodiments sufficient to allow a person of ordinary skill in the art to make and use these concepts will be given in later sections.

[0004] In an example embodiment, a system includes a switched capacitor converter configured to perform direct current (DC) to DC conversion at a predefined conversion ratio. The switched capacitor converter includes: a first power stage including a first switch; and a first capacitor coupled to the first power stage and having a first end and a second end. The system further includes a fault detection circuitry coupled to the second end of the first capacitor of the switched capacitor converter, where the fault detection circuitry is configured to monitor the voltage at the second end of the first capacitor and assert at least one fault signal in response to determining that any of the voltages at the second end indicates a fault during a startup sequence of the switched capacitor converter.

[0005] In one or more embodiments, the fault detection circuitry is further configured to deactivate the switched capacitor converter in response to the assertion of at least one fault signal.

[0006] In one or more embodiments, the fault detection circuitry is further configured to assert at least one fault signal in response to determining that at least one of the second terminal voltages of the first capacitor is less than a first threshold voltage during a first time period, during which the first terminal of the first capacitor is coupled to the output voltage of the battery of the system and the second terminal is floating.

[0007] In one or more embodiments, the fault detection circuitry is further configured to assert at least one fault signal in response to determining that at least one of the second terminal voltages is greater than a second threshold voltage during a second time period, during which the second terminal is coupled to a reference potential and the first terminal of the first capacitor is coupled to the output voltage of the battery of the system.

[0008] In one or more embodiments, the fault detection circuitry further includes an analog-to-digital converter (ADC), and wherein the fault detection circuitry is further configured to obtain a sampled output voltage value by sampling the output voltage of the battery prior to the first time period using the ADC and store the sampled output voltage value.

[0009] In one or more embodiments, the fault detection circuitry is further configured to: compare, after the first time period of a startup sequence, the voltage at an overvoltage protection node coupled to a switched-capacitor converter with a third threshold voltage, wherein the third threshold voltage is based on the sampled output voltage value; and deactivate the switched-capacitor converter in response to determining that the voltage at the overvoltage protection node is less than the third threshold voltage.

[0010] In one or more embodiments, the fault detection circuitry is further configured to: compare, during a third time period of a startup sequence, the voltage at an overvoltage protection node coupled to a switched-capacitor converter with a fourth threshold voltage, wherein the fourth threshold voltage is based on the sampled output voltage value; and deactivate the switched-capacitor converter in response to determining that the voltage at the overvoltage protection node is less than the third threshold voltage during the third time period, wherein the third time period corresponds to a half-synchronous switching state of the switched-capacitor converter and the third threshold voltage is greater than the output voltage of the battery.

[0011] In one or more embodiments, the first capacitor includes a flying capacitor configured to provide energy storage for a switched-capacitor converter.

[0012] In one or more embodiments, the switched-capacitor converter further includes: a second power stage including a second switch; and a second capacitor coupled to the first power stage and to the fault detection circuitry.

[0013] In an example embodiment, a method includes, during a startup sequence of a switched-capacitor converter: detecting, by a fault detection circuitry coupled to the switched-capacitor converter, a fault in the switched-capacitor converter based on a second terminal voltage of a flying capacitor of the switched-capacitor converter, the flying capacitor having a first terminal and a second terminal; and deactivating, in response to detecting the fault, the switched-capacitor converter by the fault detection circuitry.

[0014] In one or more embodiments, detecting the fault includes determining, by the fault detection circuitry, that at least one of the second terminal voltages indicates a pin fault based on a comparison of each of the second terminal voltages of the flying capacitor with a threshold voltage when the first terminal is coupled to an output voltage of a battery and the second terminal is floating.

[0015] In one or more embodiments, detecting the fault includes determining, by the fault detection circuitry, that at least one of the second terminal voltages indicates a short circuit of a capacitor plate based on a comparison of each of the second terminal voltages of the flying capacitor with a threshold voltage when the second terminal is coupled to a reference potential and the first terminal is coupled to an output voltage of a battery.

[0016] In one or more embodiments, a system includes a fault detection circuitry configured to receive voltages from a plurality of capacitors of a switched-capacitor converter, the plurality of capacitors having a first terminal and a second terminal, and the fault detection circuitry includes a logic circuitry configured to: monitor the voltages in a first state of a startup sequence and a second state of the startup sequence; assert a first fault signal in response to determining that any of the voltages is greater than a first threshold voltage when in the first state; and assert a second fault signal in response to determining that any of the voltages is less than a second threshold voltage when in the second state.

[0017] In one or more embodiments, the capacitor includes a flying capacitor of the switched-capacitor converter, and wherein the voltage received by the fault detection circuitry includes a second terminal voltage of the second terminal of the flying capacitor.

[0018] In one or more embodiments, the fault detection circuitry further includes a finite state machine (FSM) configured to receive the first fault signal and the second fault signal from the logic circuitry and deactivate the switched-capacitor converter in response to an assertion of either the first fault signal or the second fault signal.

[0019] In one or more embodiments, the fault detection circuitry further includes an analog-to-digital converter (ADC) configured to sample voltages from each of an overvoltage protection node coupled to the switched-capacitor converter and an output node of a battery coupled to the switched-capacitor converter and provide the sampled voltages to the FSM.

[0020] In one or more embodiments, the FSM is further configured to transition to a first state of a startup sequence of the switched-capacitor converter in response to determining that the voltage at the overvoltage protection node is less than a third threshold voltage.

[0021] In one or more embodiments, the FSM is further configured to compare the voltage at the overvoltage protection node with a fourth threshold voltage after the first state of the startup sequence, where the fourth threshold voltage is based on a sampled output voltage value obtained and stored by the fault detection circuitry prior to the first state.

[0022] In one or more embodiments, the FSM is further configured to compare the voltage at the overvoltage protection node with a fifth threshold voltage during a third state of the startup sequence corresponding to a half-synchronous switching state of the switched-capacitor converter, where the fifth threshold voltage is greater than the output voltage of the battery.

[0023] In one or more embodiments, the FSM is further configured to deactivate the switched-capacitor converter in response to determining that: after the first state, the voltage at the overvoltage protection node is less than the fourth threshold voltage; or at the end of the third state, the voltage at the overvoltage protection node is less than the fifth threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] A more complete understanding of the subject matter may be obtained by reference to the detailed description and claims when considered in conjunction with the following drawings, in which like reference numerals refer to like elements throughout. For simplicity and clarity, elements in the figures are shown, and these elements are not necessarily drawn to scale. The figures are incorporated into the specification and form a part of the specification, and are further used to illustrate examples, embodiments, etc., and to explain various principles and advantages in accordance with the present disclosure, where:

[0025] Figure 1 is a block diagram showing an example system including a switched-capacitor converter and fault detection circuitry configured to detect faults in the switched-capacitor converter according to one or more embodiments;

[0026] Figure 2 is a block diagram showing an example of a switched-capacitor converter arranged according to the Dickson topology according to one or more embodiments.

[0027] Figure 3 is a graph showing the overvoltage protection voltage (OVPOUT) and the voltage at the second end of the flying capacitor over time during a startup sequence of a switched-capacitor converter (e.g., Figure 1 the switched-capacitor converter) according to one or more embodiments;

[0028] Figure 4is a description of a method that can be used in a switched capacitor converter (e.g., Figure 1 The switched capacitor converter) is detected during startup by the fault detection circuit system (e.g., Figure 1 A process flow chart of a fault detection method executed by a fault detection circuit system. DETAILED DESCRIPTION

[0029] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. In addition, it is not intended to be bound by any explicit or implicit theory presented in the foregoing technical field, background technology or the following detailed description.

[0030] For simplicity and clarity of explanation, the drawings illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted for brevity. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the size of some elements or regions in the drawings may be enlarged relative to other elements or regions to help improve the understanding of the embodiments described herein.

[0031] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims may be used to distinguish similar elements and are not necessarily used to describe a specific sequential order or time order. It should be understood that the terms used in this manner are interchangeable in appropriate circumstances, so that the embodiments described herein can, for example, operate in an order different from that shown or otherwise described herein. In addition, the terms "comprise", "include", "have" and any variations thereof are intended to cover non-exclusive inclusions, so that processes, methods, products or devices including a series of elements are not necessarily limited to those elements, but may include other elements that are not explicitly listed or inherent to such processes, methods, products or devices. The term "coupled" as used herein is defined as being connected directly or indirectly in an electrical or non-electrical manner. As used herein, the terms "substantially" and "substantially" mean sufficient to achieve the purpose of the statement in a practical manner, and minor defects (if any) are not important for the purpose of the statement. As used herein, the words "exemplary" and "example" mean "serving as an example, an example or an illustration". Any implementation described herein as exemplary or example is not necessarily to be construed as preferred or advantageous over other implementations.In addition, certain terminology may also be used herein for reference only, and thus are not intended to be limiting.

[0032] Unless otherwise stated, directional references such as "top", "bottom", "left", "right", "above", "below", etc. are not intended to require any preferred orientation, but are made for illustration purposes with reference to the orientation of the corresponding figure or figures.

[0033] The various embodiments described herein relate to systems and methods for detecting faults in a switched-capacitor converter (e.g., which may be implemented to provide DC-to-DC conversion in an electronic device such as a mobile phone, a tablet computer, etc.) and particularly for detecting during the startup sequence of such a switched-capacitor converter. A switched-capacitor converter uses capacitors (sometimes referred to as "flying capacitors") as energy storage elements. Faults may occur in a switched-capacitor converter due to an electrical short circuit between the plates of an individual flying capacitor or due to an electrical short circuit between adjacent pins of such a switched-capacitor converter (e.g., a pin connected to a reference potential (e.g., ground; 0V) and a pin connected to a flying capacitor (e.g., if the flying capacitor is implemented outside the package)). Such an electrical short circuit may undesirably damage the switched-capacitor converter.

[0034] In one or more embodiments, the system may include a switched-capacitor converter and fault detection circuitry configured to detect faults in the switched-capacitor converter. For example, the fault detection circuitry may be coupled to an overvoltage protection node of the switched-capacitor converter and to a second end of the flying capacitor, and may monitor the voltages at these locations during the startup sequence of the switched-capacitor converter. Herein, the "second end" of the flying capacitor of the switched-capacitor converter is considered to be the end of the flying capacitor that is coupled to ground in the pre-charge state of the startup sequence of the switched-capacitor converter, and the "first end" of such a flying capacitor is considered to be the end of the flying capacitor that is coupled to the input or output of the switched-capacitor converter in the pre-charge state of the startup sequence of the switched-capacitor converter. In the bias state of the startup sequence, the voltage of the first end of the flying capacitor may be biased to a voltage VOUT corresponding to the output voltage of the battery of the system coupled to the output of the switched-capacitor converter, and then, the voltage of the second end of the flying capacitor may float to VOUT. In the bias state, the fault detection circuitry may monitor the voltage of the second end of the flying capacitor to determine whether the second end voltage is less than a threshold VTH1 (e.g., as a non-limiting example, about 200 mV). If the fault detection circuitry determines that the second end voltage is less than VTH1, this indicates that a pin short circuit (i.e., a short circuit between adjacent pins of the switched-capacitor converter) has occurred, in response to which the fault detection circuitry may be configured to deactivate or turn off the switched-capacitor converter.

[0035] In a pre-charge state of the startup sequence, after the bias state, the second terminal of the flying capacitor may be connected to a reference potential (e.g., ground; 0V), while the first terminal of the flying capacitor may be connected to VOUT. In the pre-charge state, the fault detection circuitry may monitor the voltage at the second terminal of the flying capacitor to determine whether the second terminal voltage is greater than a threshold VTH2 (e.g., as a non-limiting example, about 0V or 100 mV). If the fault detection circuitry determines that the second terminal voltage is greater than about VTH2, this indicates that a capacitor plate short circuit has occurred (i.e., a short circuit between the capacitor plates of the respective flying capacitors of the switched capacitor converter), in response to which the fault detection circuitry may be configured to deactivate or turn off the switched capacitor converter.

[0036] Figure 1 FIG. shows a block diagram of a system 100 including a battery 104, an inductive charger 148, system components 150, and a fast charger 103. The fast charger 103 includes a fault detection circuitry 101, a switched capacitor converter 102, and a control circuitry 110. In one or more embodiments, as a non-limiting example, the system 100 may be a mobile device, such as a smart phone or a tablet computer.

[0037] As a non-limiting example, the system components 150 may include one or more processor cores, memory, and / or peripheral components, such as one or more cameras, speakers, or displays. The inductive charger 148 is coupled to an input node 124, an output node 142, and the system components 150. As a non-limiting example, the inductive charger 148 may be implemented as a conventional charger, such as a buck converter, that provides power from the battery 104 to the system components 150. In one or more embodiments, as a non-limiting example, the battery 104 may be a single-cell lithium battery. An output capacitor 146 may be coupled between the output node 142 and a reference node 144 (e.g., configured to provide a ground voltage or other suitable reference potential).

[0038] The input node 124 may be configured to couple to either an external power source (not shown) or a receiver device (not shown; e.g., another mobile device, such as another tablet computer, smart phone, smart watch, etc. to be charged by the system 100), such that power may be provided to the system 100 from the external power source when coupled to the node 124, and such that power may be provided from the system 100 to the receiver device when the receiver device is coupled to the node 124.

[0039] The inductive charger 148 can be configured to charge the battery 104 at a first rate when an external power source is connected to the input node 124. The fast charger 103 can be configured to charge the battery 104 at a second rate when an external power source is connected to the input node 124, where the second rate is higher than the first rate. For example, the fast charger 103 can have a relatively higher charging rate than the inductive charger 148 because the fast charger 103 is configured to supply a higher current to the battery 104 than the inductive charger 148.

[0040] A higher charging current may have a greater impact on battery life, especially when the battery 104 is relatively close to 100% state of charge (SoC) (i.e., close to fully charged) or relatively close to 0% SoC. In one or more embodiments, in response to determining that the battery is within a first predetermined SoC (e.g., as a non-limiting example, a range between 30% and 80% of the charging capacity of the battery 104), the fast charger 103 can be selected to charge the battery 104. In other predetermined SoC ranges (e.g., as a non-limiting example, a range between 0% and 30% or a range between 80% and 100%), the inductive charger 148 can be selected to charge the battery 104.

[0041] The switched capacitor converter 102 of the fast charger 103 is coupled between the output node 142 and the input node 124. The switched capacitor converter 102 can be coupled to the input node 124 via a switch 126, and the switch 126 can be an overvoltage protection field effect transistor (FET). An overvoltage protection node 128 can be provided between the switched capacitor converter 102 and the switch 126, where OVPOUT is the voltage at the node 128. The switched capacitor converter 102 can be configured to provide DC-to-DC conversion between the voltage VIN at the input node 124 and the voltage VOUT at the output node 142. In one or more embodiments, the switched capacitor converter 102 implements a Dickson topology and can provide multiple conversion ratios, including both a forward conversion ratio (e.g., 4:1, 2:1, 1:1, etc.) and a reverse conversion ratio (e.g., 1:4, 1:2, 1:1, etc.). For example, if configured to provide a forward conversion ratio of 4:1, given an input voltage VIN = 20V at the input node 124, the switched capacitor converter 102 steps down the input voltage VIN to provide an output voltage VOUT = 5V at the output node 142. As another example, if configured to provide a reverse conversion ratio of 1:2, given a voltage VIN = 5V at the input node 124, the switched capacitor converter steps up the input voltage VIN to provide a voltage VOUT = 2.5V at the output node 142.

[0042] The switched capacitor converter 102 may include power stages 106 and 108. Power stage 106 is coupled to flying capacitors 130, 134, and 138. Power stage 108 is coupled to flying capacitors 132, 136, and 140. As used herein, the term "flying capacitor" refers to a capacitor that serves as an energy storage element for storing and transferring energy associated with voltage conversion applications. In one or more embodiments, flying capacitors 130, 132, 134, 136, 138, and 140 are separate from the integrated circuit including power stages 106 and 108 of the switched capacitor converter 102. In one or more other embodiments, flying capacitors 130, 132, 134, 136, 138, and 140 are formed on the same integrated circuit die as power stages 106 and 108 and / or are disposed in the same package as power stages 106 and 108. During normal operation of the switched capacitor converter 102, each of power stages 106 and 108 may implement a Dickson topology in combination with flying capacitors 130, 132, 134, 136, 138, and 140, which provide DC-to-DC conversion between VIN and VOUT at one or more predefined conversion ratios (e.g., by way of non-limiting example, 4:1, 2:1, 1:1, 1:2, or 1:4) when controlled by control circuitry 110. Prior to initiating normal operation, the switched capacitor converter 102 may execute a startup sequence that is controlled by control circuitry 110 and the finite state machine (FSM) 112 of the fault detection circuitry 101. During this startup sequence, the switches of the switched capacitor converter 102 may be controlled by control circuitry 110 to bias or charge the terminals of flying capacitors 130, 132, 134, 136, 138, and 140 to various predetermined voltage levels relative to a predefined sequence of states, while the fault detection circuitry 101 monitors the voltage OVPOUT at node 128 and the voltages C1A_2, C1B_2, C2A_2, C2B_2, C3A_2, and C3B_2 at the second terminals of the flying capacitors (sometimes referred to herein as "second terminal voltages") to detect faults, as explained in more detail below.

[0043] Although the switched capacitor converter 102 is shown in this example as including two power stages 106 and 108 each coupled to three flying capacitors, it should be understood that this is intended to be illustrative and not limiting. For example, in one or more other embodiments, more or fewer than three flying capacitors may be coupled to each power stage and / or more or fewer than two power stages may be included in the switched capacitor converter. In one or more such other embodiments, the second terminal of each flying capacitor will be coupled to an input of the logic circuitry 116 for detecting pin shorts and capacitor plate shorts.

[0044] The fault detection circuit system 101 is configured to detect faults that may occur during the startup sequence of the switched capacitor converter 102 (e.g., as a non-limiting example, a short circuit between the pins of the switched capacitor converter 102 or between the flying capacitor plates). The fault detection circuit system 101 includes a digital FSM 112 (sometimes referred to as the "FSM 112"), a multi-input analog-to-digital converter (ADC) 122, and a fault detection module 114. The ADC 122 may have inputs coupled to nodes 128 and 142 such that the ADC 122 samples the voltages OVPOUT and VOUT. The FSM 112 may receive the OVPUT and VOUT measurements from the ADC 122. In one or more embodiments, the FSM 112 may be configured to initiate the startup sequence of the switched capacitor converter 102, discharge the flying capacitor of the switched capacitor converter 102 in an initial state, and then transition from the initial state to a subsequent state of the startup sequence in response to determining that OVPOUT is significantly less than a threshold voltage OVPOUT_TH1 (e.g., as a non-limiting example, 200 mV), where this condition may indicate that the flying capacitor of the switched capacitor converter 102 is sufficiently discharged.

[0045] The FSM 112 may control the switched capacitor converter 102 via communication with the control circuit system 110. The FSM 112 may include a plurality of timers 113 that may define the time periods of one or more states of the startup sequence of the switched capacitor converter 102. The FSM 112 may receive the threshold voltages OVPOUT_TH1, OVPOUT_TH2, and OVPOUT_TH3 and may be configured to compare the voltage OVPOUT (sampled by the ADC 122) with any or each of the threshold voltages OVPOUT_TH1, OVPOUT_TH2, and OVPOUT_TH3 during various states of the startup sequence of the switched capacitor converter 102, as further described below. The FSM 112 may be configured to selectively enable the pin short circuit detection performed by the fault detection module 114 via the assertion of an enable signal EN_PIN_SHORT. Herein, a "pin short circuit" refers to an electrical short circuit between two or more adjacent pins of a device, e.g., an electrical short circuit between one or more ground or reference pins and one or more pins coupled to the ends of the flying capacitors 130, 132, 134, 136, 138, and 140 of the switched capacitor converter 102. The FSM 112 may be configured to selectively enable the capacitor plate short circuit detection performed by the fault detection module 114 via the assertion of an enable signal EN_CAP_SHORT. Herein, a "capacitor plate short circuit" refers to an electrical short circuit between the two plates of a capacitor, such as the flying capacitors 130, 132, 134, 136, 138, and 140.

[0046] The fault detection module 114 may include logic circuitry 116 having inputs coupled to the second ends of flying capacitors 130, 132, 134, 136, 138, and 140 of the switched capacitor converter. Through these inputs, the logic circuitry 116 may receive second end voltages CP1A-2, CP1B-2, CP2A-2, CP2B-2, CP3A-2, and CP3B-2. The logic circuitry 116 may include additional inputs through which threshold voltages VTH1 and VTH2 are provided to the logic circuitry 116.

[0047] In one or more embodiments, in response to an assertion of the enable signal EN_PIN_SHORT by the FSM 112, the logic circuitry 116 is configured to compare each of the second end voltages CP1A-2, CP1B-2, CP2A-2, CP2B-2, CP3A-2, and CP3B-2 with a threshold voltage VTH1 (e.g., by way of non-limiting example, approximately 0.2V). For example, the logic circuitry 116 may include comparators, each having an input receiving the threshold voltage VTH1 and an input receiving a corresponding second end voltage, where the outputs of these comparators indicate whether the corresponding second end voltage is less than or greater than the threshold voltage VTH1. In response to determining that any of the second end voltages is less than the threshold voltage VTH1 when EN_PIN_SHORT is asserted (e.g., in the bias state of the startup sequence), the logic circuitry 116 may assert a fault signal PIN_SHORT to indicate that a pin short has been detected, and the logic circuitry 116 provides the fault signal PIN_SHORT to the FSM 112. The detection of pin shorts by the logic circuitry 116 based on the threshold voltage VTH1 is described in more detail below.

[0048] In one or more embodiments, in response to an assertion of the enable signal EN_CAP_SHORT by the FSM 112, the logic circuitry 116 is configured to compare each of the second terminal voltages CP1A-2, CP1B-2, CP2A-2, CP2B-2, CP3A-2, and CP3B-2 with a threshold voltage VTH2 (e.g., as a non-limiting example, from about 0V to about 0.1V). For example, the logic circuitry 116 may include comparators, each comparator having an input receiving the threshold voltage VTH2 and an input receiving a corresponding second terminal voltage, where the outputs of these comparators indicate whether the corresponding second terminal voltage is less than or greater than the threshold voltage VTH2. In response to determining that any of the second terminal voltages is greater than the threshold voltage VTH2, the logic circuitry 116 may assert a fault signal CAP_SHORT to indicate that a capacitor plate short has been detected, and the logic circuitry 116 provides the fault signal CAP_SHORT to the FSM 112. The detection of the capacitor plate short by the logic circuitry 116 based on the threshold voltage VTH2 is described in more detail below.

[0049] In response to detecting a fault, the FSM 112 may cause the control circuitry 110 to deactivate or turn off the switched-capacitor converter 102. In one or more embodiments, the detection of a fault by the FSM 112 may occur in response to determining that any of the second terminal voltages is less than VTH1 when EN_PIN_SHORT is asserted in the bias state, any of the second terminal voltages is greater than VTH2 when EN_CAP_SHORT is asserted in the pre-charge state, OVPOUT is less than OVPOUT_TH2 between the bias state and the pre-charge state, and OVPOUT is less than OVPOUT_TH3 at the end of the semi-synchronous switching state.

[0050] Figure 2 An example of a switched-capacitor converter 200 arranged according to the Dickson topology is shown. In one or more embodiments, the switched-capacitor converter 200 is a DC-to-DC converter. The switched-capacitor converter 200 may correspond to Figure 1 an embodiment of one of the power stages 106 and 108 (and corresponding flying capacitors) of the switched-capacitor converter 102, where the same reference numerals are sometimes used herein to denote the same elements. When describing the switched-capacitor converter 200 in this example, reference is made to Figure 1System 100 and its components. It should be understood that, according to one or more embodiments, the switched-capacitor converter 200 may include additional power stages (not shown), which may be coupled in parallel between the overvoltage protection node 128 and the output node 142. In this example, the switched-capacitor converter 200 may provide DC-to-DC conversion (e.g., 1:4, 1:2, 2:1, 4:1, etc.) between VOUT (at node 142) and OVPOUT (at node 128) during normal operation.

[0051] The switched-capacitor converter 200 includes an input node 124, an output node 142, an overvoltage protection node 128, switches 126, 202, 204, 206, 208, 209, 210, 212, 214, and 216 (denoted as S0, S1, S2, S3, S4, S 4A , S5, S6, S7, and S8 respectively) and capacitors 218, 220, and 222 (denoted as C1, C2, and C3 respectively). Switch 126 (S0) is coupled between the input node 124 and the overvoltage protection node 128 and is configured to selectively connect the input node 124 and the overvoltage protection node 128. Switch 202 (S1) is coupled between the overvoltage protection node 128 and node 224 and is configured to selectively connect the overvoltage protection node 128 and node 224. Switch 204 (S2) is coupled between node 224 and node 226 and is configured to selectively connect node 224 and node 226. Switch 206 (S3) is coupled between node 226 and node 228 and is configured to selectively connect node 226 and node 228. Switch 208 (S4) is coupled between node 228 and the output node 142 and is configured to selectively connect node 228 and the output node 142. Switch 209 (S 4A ) is coupled in parallel with switch 208 between node 228 and the output node 142. Switch 210 (S5) is coupled between node 231 and the output node 142 and is configured to selectively connect node 231 and the output node 142. Switch 212 (S6) is coupled between node 230 and the reference node 144 and is configured to selectively connect node 230 and the reference node 144. Switch 214 (S7) is coupled between node 232 and the output node 142 and is configured to selectively connect node 232 and the output node 142. Switch 216 (S8) is coupled between node 232 and the reference node 144 and is configured to selectively connect node 232 to the reference node 144. In one or more embodiments, switches 202, 204, 206, 208, 209, 210, 212, 214, and 216 may collectively correspond to Figure 1 either of the power stages 106 and 108.

[0052] Capacitor 218 (C1) is coupled (e.g., directly connected) between node 224 and node 230. Capacitor 218 has a second terminal voltage CP1-2 measurable at node 230 and a first terminal voltage CP1-1 measurable at node 224. In one or more embodiments, capacitor 218 may correspond to Figure 1 capacitor 130 or capacitor 132 of switched capacitor converter 102.

[0053] Capacitor 220 (C2) is coupled (e.g., directly connected) between node 226 and node 232. Capacitor 220 has a second terminal voltage CP2-2 measurable at node 232 and a first terminal voltage CP2-1 measurable at node 226. In one or more embodiments, capacitor 220 may correspond to Figure 1 capacitor 134 or capacitor 136 of switched capacitor converter 102.

[0054] Capacitor 222 (C3) is coupled (e.g., directly connected) between node 228 and node 231. Capacitor 222 has a second terminal voltage CP3-2 measurable at node 231 and a first terminal voltage CP3-1 measurable at node 228. As shown, node 231 may be connected to node 230 such that the second terminal voltage CP3-2 at node 231 is the same as the second terminal voltage at node 230 (i.e., CP3-2 = CP1-2). In one or more other embodiments, node 231 may alternatively be separated from node 230 and selectively connected to reference node 144 via a separate switch (not shown). In one or more embodiments, capacitor 222 may correspond to Figure 1 capacitor 136 or capacitor 138 of switched capacitor converter 102.

[0055] During the startup sequence of switched capacitor converter 200, switches 126, 202, 204, 206, 208, 209, 210, 212, 214, and 216 may be selectively controlled according to a sequence of switch configurations. These switch configurations may be state-based, at least they may depend on the state of switched capacitor converter 200. Switched capacitor converter 200 may be configured to step through a sequence of states as part of a startup sequence, where the process may be controlled by a state machine (e.g., Figure 1 FSM 112). A non-limiting example of an illustrative startup sequence of switched capacitor converter 200 will now be described.

[0056] In an initial state of a startup sequence, an external discharge circuit system (not shown) can be used to discharge flying capacitors 218, 220, and 222 and node 128 such that the OVPOUT of flying capacitors 218, 220, and 222 and the top and second terminal voltages are equal to (or at least expected to be equal to) or approximately equal to a reference potential (e.g., 0V). When it is determined that the OVPOUT is less than a threshold OVPOUT_TH1 (which can be 200 mV), the switched capacitor converter 200 can transition from the initial state to the next state (e.g., a "first" or "biased" state).

[0057] In one or more embodiments, when transitioning from the initial state to the first or biased state, an ADC (e.g., Figure 1 the ADC 122) can sample the value of VOUT to obtain a value VOUT_0 (sometimes referred to herein as the "sampled output voltage value") and store (e.g., latch) the value VOUT_0. The VOUT_0 can be used when subsequently calculating thresholds such as OVPOUT_TH2 and OVPOUT_TH3.

[0058] In a first state (sometimes referred to as the "biased state") of the startup sequence, switches 126, 208, 210, 212, 214, and 216 are open, and switches 202, 204, 206, and 209 are closed (e.g., closed by the control circuit system 110 of Figure 1 the FSM 112). This switch configuration in the first state couples the first terminal of each of the flying capacitors 218, 220, and 222 and node 128 to the output node 142, thereby biasing the first terminals of the flying capacitors 218, 220, and 222 to VOUT when the second terminals of the flying capacitors 218, 220, and 222 are open or "floating". The voltage VOUT applied at the first terminals of the flying capacitors gradually causes the second terminal voltage to "rise" to VOUT. In one or more embodiments, in the biased state, a fault detection circuit system (e.g., Figure 1The fault detection circuit system 101) can monitor the second terminal voltages CP1-2, CP2-2, and CP-3- as described above to detect a pin short. Switch 209 can be smaller than switch 208 (i.e., have a larger "on" resistance) and can be used to connect node 228 to node 142 in the bias state instead of switch 208 to reduce current in the event of a pin short at any of the flying capacitors 218, 220, and 222. In a subsequent state of the startup sequence, after determining that no pin fault has occurred at any of the flying capacitors 218, 220, and 222, the larger switch 208 can be used to connect the output node 142 to node 228, which can allow the flying capacitors 218, 220, and 222 to charge faster.

[0059] In one or more embodiments, when transitioning from the bias state to the "second" or "precharge state", the voltage OVPOUT at node 128 can be sampled (e.g., by Figure 1 the ADC 122) and OVPOUT can be compared to a threshold OVPOUT_TH2 (e.g., by Figure 1 the FSM 112). In one or more embodiments, OVPOUT_TH2 can be equal to VOUT_0 minus a voltage offset (e.g., as a non-limiting example, approximately 1V). In response to determining that OVPOUT is less than OVPOUT_TH2 - indicating that OVPOUT is not fully charged (e.g., due to a defect in the switched capacitor converter 200), the fault detection circuit system (e.g., Figure 1 the FSM 112 of the fault detection circuit system 101) indicates a fault and can deactivate the switched capacitor converter 200.

[0060] In the second state of the startup sequence (sometimes referred to as the "precharge state"), switches 126, 210, and 214 are open, and switches 202, 204, 206, 208, 212, and 216 are closed (e.g., closed by the FSM 112 via Figure 1 the control circuit system 110). This switch configuration in the second state couples the first end of each of the flying capacitors 218, 220, and 222 and node 128 to the output node 142, and couples the second end of each of the flying capacitors 218, 220, and 222 to the reference node 144. By coupling the second end of the flying capacitors 218, 220, and 222 to the reference potential when the first end is at VOUT, the second terminal voltage gradually decreases to the reference potential (e.g., such that with a reference potential of 0V, the voltage across each of the flying capacitors is approximately VOUT). In one or more embodiments, in the precharge state, the fault detection circuit system (e.g.,Figure 1 The fault detection circuit system 101) can monitor the second terminal voltages CP1-2, CP2-2, and CP3-2 as described above to detect a short circuit of the capacitor plates. In one or more embodiments, when entering the pre-charge state, switches 212 and 216 are not necessarily closed (turned on) simultaneously. For example, when entering the pre-charge state, switch 212 can be closed before closing switch 216, which can advantageously reduce the input inrush current in the switched capacitor converter 200. In the third state of the startup sequence (sometimes referred to as the "semi-synchronous switching state"), switches 126 and 209 can be opened, and the switching configurations of the switches 202, 204, 206, 208, 209, 210, 212, 214, and 216 used can vary according to the conversion ratio of the switched capacitor converter 200, as shown in Table 1:

[0061] Conversion ratio S1 S2 S3 S4 S5 S6 S7 S8 4:1 or 1:4 Turn off Turn off Turn off Turn off Φ1 Φ2 Φ2 Φ1 2:1 or 1:2 Turn off Turn off Turn off Turn off Φ1 Φ2 Φ1 Φ2 1:1 Turn on Turn on Turn on Turn on Turn off Turn on Turn off Turn on

[0062] Table 1

[0063] As shown in the example of Table 1, for a 4:1 or 1:4 conversion ratio, switches 202, 204, 206, and 208 can be opened, switches 210 and 216 can be timed using a first signal with phase Φ1 (i.e., periodically switched between the open state and the closed state), and switches 212 and 214 can be timed using a second signal with phase Φ2, where Φ1 and Φ2 are 180 degrees or approximately 180 degrees out of phase with respect to each other. For a 2:1 or 1:2 conversion ratio, switches 202, 204, 206, and 208 can be opened, switches 210 and 214 can be timed using a first signal with phase Φ1, and switches 212 and 216 can be timed using a second signal with phase Φ2. For a 1:1 conversion ratio, switches 202, 204, 206, 208, 212, and 216 can be closed, and switches 210 and 214 can be opened.

[0064] In one or more embodiments, at the end of the semi-synchronous switching state, a fault detection circuit system coupled to node 128 of the switched capacitor converter 200 (e.g., Figure 1The FSM 112) can monitor the voltage OVPOUT as described above to detect a fault (e.g., by comparing OVPOUT with OVPOUT_TH3). For example, a fault detected in the semi-synchronous switch state may be caused by an unexpectedly high transistor resistance value, transistor gate leakage, gate driver error, etc., which may prevent OVPOUT from reaching the expected voltage level of OVPOUT_TH3, and the expected voltage level may be equal to ((VOUT_0 * X) - Y), where X is an integer determined based on the conversion ratio of the switched-capacitor converter 200 (e.g., as a non-limiting example, 4 for a 4:1 ratio, 2 for a 2:1 ratio, 1 for a 1:1 ratio), and where Y is a configurable value between, for example, 2V and 4V (e.g., as non-limiting examples, 2V, 2.5V, 3V, or 3.5V). In response to such a fault, a fault detection circuitry (e.g., Figure 1 the fault detection circuitry 101) coupled to the switched-capacitor converter 200 can indicate the fault, and in response to the fault, the switched-capacitor converter 200 can be deactivated. In one or more embodiments, OVPOUT_TH3 can be greater than VOUT.

[0065] In the fourth state of the startup sequence (sometimes referred to as the "current-limiting full-synchronous switch state"), switches 126 and 209 can be opened, and the switch configurations of the switches 202, 204, 206, 208, 209, 210, 212, 214, and 216 used can vary according to the conversion ratio of the switched-capacitor converter 200, as shown in Table 2:

[0066] Conversion ratio S1 S2 S3 S4 S5 S6 S7 S8 4:1 or 1:4 Φ1 Φ2 Φ1 Φ2 Φ1 Φ2 Φ2 Φ1 2:1 or 1:2 Φ1 Turn on Turn on Φ2 Φ1 Φ2 Φ1 Φ2 1:1 Turn on Turn on Turn on Turn on Turn off Turn on Turn off Turn on

[0067] Table 2

[0068] As shown in the example of Table 2, for a 4:1 or 1:4 conversion ratio, switches 202, 206, 210, and 216 can be timed using a first signal with phase Φ1, and switches 204, 208, 212, and 214 can be timed using a second signal with phase Φ2. For a 2:1 or 1:2 conversion ratio, switches 204 and 206 can be closed, switches 202, 210, and 214 can be timed using a first signal with phase Φ1, and switches 208, 212, and 216 can be timed using a second signal with phase Φ2. For a 1:1 conversion ratio, switches 202, 204, 206, 208, 212, and 216 can be closed, and switches 210 and 214 can be opened.

[0069] In the fifth state of the startup sequence (sometimes referred to as the "fully synchronous switch state"), the switch configuration of the switched capacitor converter 200 can be the same as in the current-limiting fully synchronous switch state, but the current limiting is deactivated and switch 126 is closed to connect node 128 to node 124 (such that VIN≈OVPOUT). For example, the startup sequence can transition from the current-limiting fully synchronous switch state to the fully synchronous switch state when a timer expires.

[0070] After entering the fully synchronous switch state, the normal operation of the switched capacitor converter 200 is enabled (e.g., by a fault detection circuitry and / or control circuitry coupled to the switched capacitor converter 200). During normal operation, switch 126 is closed, and switches 202, 204, 206, 208, 210, 212, 214, and 216 are selectively controlled (e.g., by control circuitry 110) to charge the flying capacitors 218, 220, and 222, thereby providing DC-to-DC conversion (e.g., 1:4, 1:2, 2:1, 4:1, etc.) between VIN and VOUT.

[0071] It should be understood that for one or more embodiments in which the switched capacitor converter 200 includes one or more other power stages in addition to the power stage shown in this example, the switch configuration associated with each state of the startup sequence described in this example can be similarly applied to the other power stages.

[0072] Figure 3 Illustrated is a diagram 300 showing the startup sequence of a switched capacitor converter. For example, as a non-limiting example, the startup sequence shown can be applied to Figure 1 the switched capacitor converter 102 or Figure 2 one or more embodiments of the switched capacitor converter 200. Although the diagram 300 is described below with reference to Figure 1 the system 100 and its elements, it should be understood that the startup sequence represented in the diagram 300 can be applied to other suitable systems having a switched capacitor converter.

[0073] Diagram 300 includes a curve 308 representing the expected voltage OVPOUT at the overvoltage protection node 128 and a curve 310 representing the expected second terminal voltage of the flying capacitor of the switched capacitor converter 102.

[0074] In the initial state, from time T0 to time T1, when the flying capacitor of the switched capacitor converter 102 discharges to the reference potential (about 0V in this example), the FSM 112 monitors OVPOUT measured by the ADC 122. In response to determining that OVPOUT is less than OVPOUT_TH1 (e.g., about 200 mV), the FSM 112 can transition from the initial state to the bias state.

[0075] At time T1, the FSM 112 controls the power stage of the switched-capacitor converter 102 such that the first end of the flying capacitor of the switched-capacitor converter 102 is connected to VOUT, while the voltage of the second end remains floating. In the bias state, from time T1 to time T3 (sometimes referred to as the "first time period"), the voltage of the second end of the flying capacitor floats up to VOUT, and OVPOUT similarly gradually increases to VOUT. Between time T2 and time T3, the FSM 112 asserts the signal EN_PIN_SHORT, in response to which the logic circuitry 116 of the fault detection module 114 compares the voltage of the second end with the threshold VTH1 to determine whether any pin short circuit has occurred, which would prevent the voltage of any second end affected by such a pin short circuit from rising to VOUT. At time T3, the FSM 112 determines whether the signal PIN_SHORT has been asserted by the logic circuitry 116 (i.e., in response to detecting a pin short circuit), and proceeds to the pre-charge state in response to determining that PIN_SHORT is not asserted. Alternatively, in response to determining that PIN_SHORT is asserted, the FSM 112 indicates a fault and deactivates or shuts down the switched-capacitor converter 102.

[0076] At or near time T3, the FSM 112 compares OVPOUT with OVPOUT_TH2 to determine whether the over-voltage protection node is sufficiently charged. In response to determining that OVPOUT is less than OVPOUT_TH2, the FSM 112 indicates a fault and deactivates or shuts down the switched-capacitor converter 102.

[0077] At time T3, the FSM 112 controls the power stage of the switched-capacitor converter 102 such that the second end of the flying capacitor is connected to the reference potential (0V in this example). In the pre-charge state, between time T3 and time T5 (sometimes referred to as the "second time period"), the voltage of the second end gradually transitions from VOUT to 0V. At time T4, the FSM 112 asserts the signal EN_CAP_SHORT, in response to which the logic circuitry 116 of the fault detection module 114 compares the voltage of the second end with the threshold VTH2 to determine whether any capacitor plate short circuit has occurred, which would prevent the voltage of any second end affected by such a capacitor plate short circuit from decreasing to 0V. At time T5, the FSM 112 determines whether the signal CAP_SHORT has been asserted by the logic circuitry 116 (i.e., in response to detecting a capacitor plate short circuit), and proceeds to the semi-synchronous switching state in response to determining that CAP_SHORT is not asserted. Alternatively, in response to determining that CAP_SHORT is asserted, the FSM 112 indicates a fault and deactivates or shuts down the switched-capacitor converter 102.

[0078] At time T5, the FSM 112 controls the power stage of the switched capacitor converter 102 according to the semi-synchronous switch state (e.g., as described above in the example of Figure 2 ). In the semi-synchronous switch state, from time T5 to time T7 (sometimes referred to as the "third time period"), the power stage of the switched capacitor converter 102 is controlled by the control circuitry 110 to charge OVPOUT to voltage V1. In one or more embodiments, V1 may correspond to the threshold OVPOUT_TH3 defined above. In one or more embodiments, the FSM 112 monitors OVPOUT from time T6 to time T7 to determine whether OVPOUT is greater than or equal to voltage V1 (e.g., based on a comparison of OVPOUT with the threshold OVPOUT_TH3). In response to determining that OVPOUT is greater than or equal to V1 at time T7, the FSM 112 proceeds to the current-limiting full-synchronous switch state. Alternatively, in response to determining that OVPOUT is not greater than or equal to voltage V1, the FSM 112 indicates a fault and deactivates or shuts down the switched capacitor converter 102.

[0079] At time T7, the FSM 112 controls the power stage of the switched capacitor converter 102 according to the current-limiting full-synchronous switch state (e.g., as described above in the example of Figure 2 ). In the current-limiting full-synchronous switch state, from time T7 to time T9 (sometimes referred to as the "fourth time period"), the power stage of the switched capacitor converter 102 is controlled by the control circuitry 110 to charge OVPOUT to voltage V2. The voltage V2 may be the target output voltage of the switched capacitor converter 102 (e.g., as a non-limiting example, for a 4:1 conversion ratio, the target output voltage V2 may be 4*VOUT). When the timer associated with the fourth time period expires, the FSM 112 proceeds to the full-synchronous switch state.

[0080] At time T9, the FSM 112 controls the power stage of the switched capacitor converter 102 according to the full-synchronous switch state (e.g., as described above in the example of Figure 2 ). In the full-synchronous switch state, from time T9 to time T11 (sometimes referred to as the "fifth time period"), the power stage of the switched capacitor converter 102 is controlled by the control circuitry 110 to charge OVPOUT to voltage V2 without current limiting. For example, a current-limiting circuit system (not shown) coupled to the switched capacitor converter may be disconnected, shut down, or otherwise deactivated at time T9 to remove current limiting from the switched capacitor converter 102. When the timer associated with the fifth time period expires, the startup sequence is complete and the FSM 112 initiates normal operation of the switched capacitor converter 102.

[0081] Figure 4Illustrative processing flow of method 400 is shown, by which faults including pin short - circuits and capacitor - plate short - circuits can be detected during the startup sequence of a switched - capacitor converter (e.g., Figure 1 the switched - capacitor converter 102 of Figure 1 . Component description of system 100 of

[0082] is referred to for method 400. The system 100 includes a fault - detection circuitry 101 and a switched - capacitor converter 102. However, it should be understood that this is illustrative and not restrictive, and in at least one or more other embodiments, other suitable switched - capacitor converters and fault - detection systems can be used to implement method 400.

[0083] At block 402, an external discharge circuitry (not shown) discharges the over - voltage protection node 128 of the switched - capacitor converter 102, thereby discharging the voltage OVPOUT to a reference voltage (e.g., 0V) or near the reference voltage.

[0084] At block 404, the digital FSM 112 performs a comparison of the voltage OVPOUT at the over - voltage protection node 128 with a threshold OVPOUT_TH1, which may be equal to 200 mV. If the digital FSM 112 determines that OVPOUT is less than OVPUT_TH1 as a result of this comparison, indicating that the capacitor of the switched - capacitor converter 102 is sufficiently discharged, then method 400 proceeds to block 406. If the digital FSM 112 determines that OVPOUT is not less than OVPOUT_TH1, indicating that the capacitor of the switched - capacitor converter 102 is not sufficiently discharged, then method 400 returns to block 402 to continue discharging node 128 and OVPOUT. In this way, the digital FSM 112 can delay the transition to the bias state of the switched - capacitor converter 102 until it is determined that node 128 (and the flying capacitor that may be coupled to node 128) is sufficiently discharged.

[0085] At block 408, the switched-capacitor converter 102 enters a bias state, in which the control circuitry 110 controls the power stage (e.g., its switches) of the switched-capacitor converter 102 to bias the first end of each of the flying capacitors (e.g., flying capacitors 130, 132, 134, 136, and 140) of the switched-capacitor converter 102 to the voltage VOUT. In one or more embodiments, the first end of the flying capacitor may be coupled to the voltage VOUT, and the second end of the flying capacitor may be disconnected such that the second end voltage gradually floats up to VOUT.

[0086] At block 410, the fault detection module 114 determines whether any of the second end voltages of the flying capacitors (e.g., second end voltages C1A-2, C1B-2, C2A-2, C2B-2, C3A-2, C3B-2) indicate a short circuit in the switched-capacitor converter 102. For example, since it is expected that the second end of the flying capacitor is biased to VOUT at block 408, the second end voltages of the flying capacitors can each be compared with a first threshold voltage VTHR1 using logic circuitry 116 (e.g., one or more of its comparators) to determine whether a pin short has occurred in the switched-capacitor converter 102. In one or more embodiments, the first threshold voltage VTHR1 can be a positive voltage between a reference potential (e.g., ground voltage VGND; 0V) and VOUT. In one or more embodiments, the first threshold voltage VTHR1 can be equal to or approximately equal to 0.2V. In response to determining that any of the second end voltages of the flying capacitors is less than VTHR1, the logic circuitry 116 may assert a signal PIN_SHORT to indicate that a pin short has been detected in the switched-capacitor converter 102. In one or more embodiments, at block 410, the signal EN_PIN_SHORT is asserted by the digital FSM 112 to enable the portion of the logic circuitry 116 that is allocated for pin short detection.

[0087] It should be understood that the example of performing a direct comparison of each flying capacitor second-end voltage with a threshold to detect a pin short in the switched capacitor converter 102 is illustrative and not restrictive, and other suitable methods for detecting a pin short based on the flying capacitor second-end voltage may alternatively be performed at block 410. For example, in one or more other embodiments, the second end of each of the flying capacitors in the switched capacitor converter 102 is coupled to the respective transistor gates of a set of parallel-coupled transistors (e.g., PMOS transistors) in a first logic circuit of the logic circuitry 116, where the set of parallel-coupled transistors has source terminals each coupled to a positive voltage. In one or more such other embodiments, when, at block 410, any second-end voltage of a flying capacitor drops below a corresponding gate threshold voltage relative to the voltage at the source terminals of the parallel transistors (e.g., when EN_PIN_SHORT is asserted by the digital FSM 112), the associated transistor closes, thereby connecting the positive voltage to the output of the first logic circuit. The output of the first logic circuit may be provided to a first comparator that may compare the output of the first logic circuit with a threshold, and when the output of the first logic circuit is connected to the positive voltage, the output of the first comparator may indicate a short (e.g., cause the PIN_SHORT signal to be asserted to indicate a pin short).

[0088] If, at block 410, the fault detection module 114 determines that any second-end voltage of a flying capacitor indicates a short (e.g., PIN_SHORT is asserted), then method 400 proceeds to block 428, where the digital FSM 112 deactivates or otherwise shuts down the switched capacitor converter 102 due to the detected fault. Otherwise, if the fault detection module 114 determines that none of the second-end voltages of the flying capacitors indicate a short (e.g., PIN_SHORT is not asserted), then method 400 proceeds to block 412.

[0089] At block 412, after the bias state, the digital FSM 112 compares the value of OVPOUT measured by the ADC 122 with a threshold OVPOUT_TH2. In one or more embodiments, OVPOUT_TH2 may be equal to VOUT_0 minus a voltage offset (e.g., as a non-limiting example, about 1V). In response to determining that OVPOUT is less than OVPOUT_TH2 - indicating that OVPOUT is not sufficiently charged (e.g., due to a defect in the switched capacitor converter 200), method 400 proceeds to block 428, where the digital FSM 112 disables or otherwise shuts down the switched capacitor converter 102 in the control circuitry 110 due to the detected fault. Otherwise, in response to determining that OVPOUT is not less than OVPOUT_TH2 - indicating that OVPOUT is sufficiently charged, method 400 proceeds to block 414.

[0090] At block 414, the switched capacitor converter 102 enters a pre-charge state, in which the control circuitry 110 controls the power stage (e.g., its switches) of the switched capacitor converter 102 to pre-charge the flying capacitor of the switched capacitor converter 102 to VOUT. For example, the control circuitry 110 may control the switches of the power stages 106 and 108 to connect the first end of the flying capacitor of the switched capacitor converter 102 to VOUT and the second end of the flying capacitor of the switched capacitor converter 102 to a reference potential (e.g., ground voltage VGND; 0V).

[0091] At block 416, the fault detection module 114 determines whether either of the second end voltages of the flying capacitor indicates a short circuit. For example, since it is expected that the second end of the flying capacitor is biased to a reference potential (e.g., 0V) at block 414, a logic circuitry 116 (e.g., one or more of its comparators) may be used to compare the second end voltage of the flying capacitor with a second threshold voltage VTHR2 in order to determine whether a capacitor plate short circuit has occurred in the switched capacitor converter 102. In one or more embodiments, as a non-limiting example, the second threshold voltage VTHR2 may be equal to or approximately equal to the reference potential (e.g., ground voltage; 0V). In one or more embodiments, as a non-limiting example, the second threshold voltage VTHR2 may be between about 0V and about 0.1V. In response to determining that either of the second end voltages of the flying capacitor is greater than VTHR2, the logic circuitry 116 may assert a signal CAP_SHORT to indicate a capacitor plate short circuit in one or more of the flying capacitors of the switched capacitor converter 102. In one or more embodiments, at block 416, the digital FSM 112 asserts a signal EN_CAP_SHORT to enable the portion of the logic circuitry 116 that is allocated for capacitor plate short circuit detection.

[0092] It should be understood that the example of performing a direct comparison of the voltage at the second end of each flying capacitor with a threshold to detect a short circuit of the capacitor plates in the switched capacitor converter 102 is illustrative and not restrictive, and other suitable methods for detecting a short circuit of the capacitor plates based on the voltage at the second end of the flying capacitor may alternatively be performed at block 416. For example, in one or more other embodiments, the second end of each of the flying capacitors in the switched capacitor converter 102 is coupled to the respective transistor gates of a set of parallel-coupled transistors (e.g., NMOS transistors) in the second logic circuit of the logic circuitry 116, where the set of parallel-coupled transistors has source terminals each coupled to a ground voltage. In one or more such other embodiments, when at block 416, the voltage at any second end of a flying capacitor exceeds a corresponding gate threshold voltage with respect to the voltage at the source terminals of the parallel transistors (e.g., when EN_CAP_SHORT is asserted), the associated transistor closes, thereby connecting the ground voltage to the output of the second logic circuit. The output of the second logic circuit may be provided to a second comparator, which may compare the output of the second logic circuit with a threshold, and when the output of the second logic circuit is connected to the ground voltage, the output of the second comparator may indicate a short circuit (e.g., cause the CAP_SHORT signal to be asserted to indicate a short circuit between the plates of one or more of the flying capacitors).

[0093] If at block 416 the fault detection module 114 determines that the voltage at any second end of a flying capacitor indicates a short circuit (e.g., CAP_SHORT is asserted), then method 400 proceeds to block 428, where the digital FSM 112 deactivates or otherwise shuts down the switched capacitor converter 102 in the control circuitry 110 due to the detected fault. Otherwise, if the fault detection module 114 determines that the voltages at the second ends of the flying capacitors do not indicate a short circuit (e.g., CAP_SHORT is not asserted), then method 400 proceeds to block 418.

[0094] At block 418, the switched capacitor converter 102 enters a semi-synchronous switching state for the duration of a first timer, causing the control circuitry 110 to control the power stage (e.g., its switches) of the switched capacitor converter 102 to operate in a semi-synchronous mode, in which, for conversion ratios other than 1:1, half of the switches (e.g., Figure 2 switches S1, S2, S3, and S4) each remain in an on state or an off state, while the other half of the switches (e.g., Figure 2The switches S5, S6, S7, and S8) periodically switch between an off state and an on state (i.e., an open state and a closed state, respectively). Examples of semi - synchronous switch - state operations for various conversion ratios are provided in Table 1 above. In the semi - synchronous switch state, it is expected that OVPOUT is equal to or approximately equal to a first target voltage level corresponding to a threshold OVPOUT_TH3. As described above, OVPOUT_TH3 can be equal to ((VOUT_0 * X)-Y), where X is an integer determined based on the conversion ratio of the switched - capacitor converter 200 (e.g., as a non - limiting example, 4 for a 4:1 ratio, 2 for a 2:1 ratio, 1 for a 1:1 ratio), and where Y is a configurable value between, for example, 2V and 4V (e.g., as non - limiting examples, 2V, 2.5V, 3V, or 3.5V). When the first timer expires, method 400 proceeds to block 416.

[0095] At block 420, when the first timer expires, the digital FSM 112 compares OVPOUT (e.g., sampled by the ADC 122) with the threshold OVPOUT_TH3. If the digital FSM 112 determines that OVPOUT is less than the threshold OVPOUT_TH3, indicating a fault, then method 400 proceeds to block 428, where the digital FSM 112 deactivates or otherwise shuts down the switched - capacitor converter 102 of the control circuitry 110 due to the detected fault. Otherwise, if the digital FSM 112 determines that OVPOUT is greater than or equal to the threshold OVPOUT_TH3, then method 400 proceeds to block 422.

[0096] At block 422, the switched - capacitor converter 102 enters a current - limited full - synchronous switch state for the duration of a second timer, causing the control circuitry 110 to control the power stage (e.g., its switches) of the switched - capacitor converter 102 to operate in a full - synchronous mode (with current - limiting), in which for conversion ratios other than 1:1, some or all of the switches of each power stage of the switched - capacitor converter 102 periodically switch between an off state and an on state (i.e., an open state and a closed state, respectively). Examples of full - synchronous switch - state operations for various conversion ratios are provided in Table 2 above. In the current - limited full - synchronous switch state, it is expected that OVPOUT is equal to or approximately equal to a second target voltage level (e.g., Figure 3 V2; in the case where the switched - capacitor converter 102 is configured as an N:1 or 1:N DC - to - DC converter, approximately N times VOUT, where as a non - limiting example, N can be 2 or 4). When the second timer expires, method 400 proceeds to block 420.

[0097] At block 424, the switched-capacitor converter 102 enters a fully synchronous switching state for the duration of a third timer, such that the control circuitry 110 controls the power stage (e.g., its switches) of the switched-capacitor converter 102 to operate in the fully synchronous mode as described above, without current limiting. In the fully synchronous switching state, it is expected that OVPOUT is equal to or approximately equal to a second target voltage level (e.g., Figure 3 V2 of

[0098] ). When the third timer expires, method 400 proceeds to block 426.

[0099] At block 426, the digital FSM 112 enables normal operation of the switched-capacitor converter 102, such that the control circuitry 110 controls the power stage (e.g., its switches) of the switched-capacitor converter 102 accordingly (e.g., as a non-limiting example, to provide DC-to-DC conversion between VIN and VOUT with a conversion ratio of 1:4, 1:2, 2:1, or 4:1).

[0100] Note that in one or more embodiments, state transitions of the switched-capacitor converter (e.g., at blocks 406, 410, 414, 418, 422, and 426) may be controlled by the digital FSM 112.

[0101] The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless stated otherwise explicitly, “connected” means that one element is directly joined to another element (or directly communicates with another element), and not necessarily joined mechanically. Similarly, unless stated otherwise explicitly, “coupled” means that one element is directly or indirectly joined to another element (or directly or indirectly communicates with another element), and not necessarily joined mechanically. Thus, although the schematic illustrations shown in the figures depict an exemplary arrangement of elements, one or more additional intervening elements, devices, features, or components may be present in one or more embodiments of the subject matter being depicted.

[0102] It should also be noted that at least some operations of the methods described herein can be implemented using software instructions stored on a computer-usable storage medium for execution by a computer. By way of example, an embodiment of a computer program product includes a computer-usable storage medium for storing a computer-readable program. A computer-usable or computer-readable storage medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device). Examples of non-transitory computer-usable and computer-readable storage media include semiconductor or solid state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and optical disk. Current examples of optical disks include high density disks with read-only memory (CD-ROM), high density disks with read / write capabilities (CD-R / W), and digital video disks (DVD).

[0103] Alternatively, the embodiments described herein can be implemented entirely in hardware or in an implementation that includes both hardware and software elements. In embodiments using software, the software can include, but is not limited to, firmware, resident software, microcode, etc.

[0104] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that there are a large number of variations. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit in any way the scope, applicability, or configuration of the claimed subject matter. Indeed, the foregoing detailed description will provide those skilled in the art with a convenient guide for implementing the one or more embodiments described. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which scope includes known equivalents and foreseeable equivalents at the time of filing this patent application.

Claims

1. A system, characterized in that: include: A switched capacitor converter, the switched capacitor converter being configured to perform direct current (DC) to DC conversion at a predefined conversion ratio, the switched capacitor converter comprising: a first power stage comprising a first plurality of switches; and a first plurality of capacitors coupled to the first power stage and having a first end and a second end; and fault detection circuitry coupled to the second ends of the first plurality of capacitors of the switched capacitor converter, wherein the fault detection circuitry is configured to: monitoring a voltage at a second terminal of the first plurality of capacitors; and In response to determining that any of the second terminal voltages during a startup sequence of the switched capacitor converter indicates a fault, at least one fault signal is asserted.

2. The system according to claim 1, characterized in that The fault detection circuitry is additionally configured to disable the switched capacitor converter in response to assertion of the at least one fault signal.

3. The system according to claim 1, characterized in that The fault detection circuit system is further configured to assert the at least one fault signal in response to determining that at least one of the second terminal voltages of the first plurality of capacitors is less than a first threshold voltage during a first time period, wherein the first ends of the first plurality of capacitors are coupled to an output voltage of a battery of the system and the second ends are floating.

4. The system according to claim 3, characterized in that The fault detection circuitry is further configured to assert the at least one fault signal in response to determining that at least one of the second terminal voltages is greater than a second threshold voltage during a second time period, wherein the second terminal is coupled to a reference potential and the first ends of the first plurality of capacitors are coupled to the output voltage of the battery of the system.

5. The system according to claim 4, characterized in that The fault detection circuitry further comprises an analog-to-digital converter ADC, and wherein the fault detection circuitry is further configured to: obtaining a sampled output voltage value by sampling the output voltage of the battery before the first time period using the ADC; as well as Stores the sampled output voltage value.

6. The system according to claim 5, characterized in that The fault detection circuitry is additionally configured to: after the first time period of the startup sequence, comparing a voltage at an overvoltage protection node coupled to the switched capacitor converter to a third threshold voltage, wherein the third threshold voltage is based on the sampled output voltage value; as well as In response to determining that the voltage at the overvoltage protection node is less than the third threshold voltage, the switched capacitor converter is disabled.

7. The system according to claim 6, characterized in that The fault detection circuitry is additionally configured to: during a third time period of the startup sequence, comparing the voltage at the overvoltage protection node coupled to the switched capacitor converter to a fourth threshold voltage, wherein the fourth threshold voltage is based on the sampled output voltage value; as well as In response to determining that the voltage at the overvoltage protection node is less than the third threshold voltage during the third time period, the switched capacitor converter is disabled, wherein the third time period corresponds to a semi-synchronous switching state of the switched capacitor converter and the third threshold voltage is greater than the output voltage of the battery.

8. The system according to claim 1, characterized in that The first plurality of capacitors includes a flying capacitor configured to provide energy storage for the switched capacitor converter.

9. A method, characterized in that include: During the startup sequence of a switched capacitor converter: detecting, by fault detection circuitry coupled to the switched capacitor converter, a fault in the switched capacitor converter based on a second terminal voltage of a plurality of flying capacitors of the switched capacitor converter, the plurality of flying capacitors having a first terminal and a second terminal; and In response to detecting the fault, the switched capacitor converter is disabled by the fault detection circuitry.

10. A system, characterized in that: include: A fault detection circuit system configured to receive a voltage from a plurality of capacitors of a switched capacitor converter, the plurality of capacitors having a first terminal and a second terminal, and comprising logic circuitry configured to: monitoring said voltage during a first state of a startup sequence and a second state of said startup sequence; responsive to determining that any of the voltages is greater than a first threshold voltage when in the first state, asserting a first fault signal; as well as In response to determining that any of the voltages is less than a second threshold voltage while in the second state, a second fault signal is asserted.

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