Circuit for power supply micro-interruption resistance, chip and electronic equipment

Abstract

The invention relates to the technical field of vehicle-mounted electronic power supply design, and discloses a circuit for power supply micro-interruption resistance, a chip and electronic equipment, the circuit comprises a power supply, a first transistor circuit connected with the power supply, a second transistor circuit connected with the first transistor circuit, and a second capacitor connected with the first transistor circuit, a load in circuit connection with the first transistor; under the condition that the power supply supplies power, the first transistor circuit is switched on, the second transistor circuit is switched off, and the power supply current of the power supply stores electric energy for the second capacitor through the first transistor circuit and supplies power for the load through the first transistor circuit; and under the condition of micro-interruption of the power supply, the second capacitor supplies power to the load through the stored electric energy, the second transistor circuit is switched on, and the first transistor circuit is switched off. Under the condition that the power supply is slightly interrupted, the complementary connection and disconnection of the first transistor circuit and the second transistor circuit are utilized, the electric energy stored by the second capacitor is used for supplying power to the load, and the load operates uninterruptedly.

Description

Technical Field

[0001] The present invention relates to the technical field of in-vehicle electronic power supply design, and particularly to a circuit, a chip, and an electronic device for withstanding power micro-interruptions. Background Art

[0002] Power micro-interruption refers to a transient voltage interruption or fluctuation in the power supply, which is usually used to test the tolerance of electronic devices under instantaneous power-off or voltage changes. The instantaneous disconnection / connection of the power line or signal line can be simulated by the device to test the stability of the device under test under extreme voltage changes.

[0003] In the PMOS (Positive channel Metal Oxide Semiconductor) anti-reverse circuit in the related art, in the case of coping with the power micro-interruption test, due to design limitations such as structural design or cost control, the capacitance in the PMOS anti-reverse circuit in the related art cannot support the load without power-off, there is a situation where the load restarts, and it cannot meet the requirements of in-vehicle electronic tests. Summary of the Invention

[0004] In view of this, the present invention provides a circuit, a chip, and an electronic device for withstanding power micro-interruptions, so as to solve the problem that the capacitance in the PMOS anti-reverse circuit in the related art cannot support the load without power-off, there is a situation where the load restarts, and it cannot meet the requirements of in-vehicle electronic tests.

[0005] In a first aspect, the present invention provides a circuit for withstanding power micro-interruptions, the circuit comprising: a power supply, a first transistor circuit connected to the power supply, a second transistor circuit connected to the first transistor circuit, a second capacitor connected to the first transistor circuit, and a load connected to the first transistor circuit; when the power supply supplies power, the first transistor circuit is turned on, the second transistor circuit is turned off, the supply current of the power supply stores electrical energy for the second capacitor via the first transistor circuit, and the supply current also supplies power to the load via the first transistor circuit; when there is a power micro-interruption, the second capacitor supplies power to the load through the stored electrical energy, the second transistor circuit is turned on, and the first transistor circuit is turned off.

[0006] In an alternative embodiment, the second transistor circuit includes: a second transistor, a third resistor, and a fourth resistor. A first end of the second transistor is connected to the first transistor circuit. One end of the third resistor is connected to the positive pole of the power supply, the other end of the third resistor is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the negative pole of the power supply, a second end of the second transistor is connected to the other end of the third resistor, and a third end of the second transistor is connected to the first transistor circuit.

[0007] In an alternative embodiment, the second transistor is a P-type metal-oxide-semiconductor field-effect transistor.

[0008] In an alternative embodiment, the first transistor circuit includes: a first transistor, a first resistor, a second resistor, and a first capacitor. A first end of the first transistor is connected to the positive pole of the power supply, a second end of the first transistor is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, a third end of the first transistor is connected to one end of the first resistor, the other end of the first resistor is connected to the negative pole of the power supply, one end of the first capacitor is connected to one end of the second resistor, and the other end of the first capacitor is connected to the other end of the second resistor.

[0009] In an alternative embodiment, the first transistor is a P-type metal-oxide-semiconductor field-effect transistor.

[0010] In an alternative embodiment, one end of the second capacitor is connected to the first transistor, the other end of the second capacitor is connected to the negative pole of the power supply, one end of the load is connected to the first transistor, and the other end of the load is connected to the negative pole of the power supply.

[0011] In an alternative embodiment, in the case of a power micro-interruption, the second capacitor supplies power to the load through the stored electrical energy, the second transistor circuit is turned on, and the first transistor circuit is turned off, including: the current generated by the electrical energy stored in the second capacitor flows through the load to supply power to the load and flows to the negative pole of the second capacitor; the current generated by the electrical energy stored in the second capacitor flows through the second transistor and the first resistor and flows to the negative pole of the second capacitor.

[0012] In an alternative embodiment, when the power supply is in operation, the first transistor circuit is turned on and the second transistor circuit is turned off. The supply current of the power supply stores electrical energy for the second capacitor via the first transistor circuit. The supply current supplies power to the load via the first transistor circuit, including: the supply current flows through the first transistor, the second resistor, and the first resistor and then flows to the negative terminal of the power supply; the supply current flows through the first transistor and the second capacitor and then flows to the negative terminal of the power supply; the supply current flows through the first transistor and the load and then flows to the negative terminal of the power supply.

[0013] In a second aspect, the present invention provides a chip for resisting power micro-interruptions, which includes the circuit for resisting power micro-interruptions according to the first aspect or any corresponding embodiment thereof.

[0014] In a third aspect, the present invention provides an electronic device, which includes the circuit for resisting power micro-interruptions according to the first aspect or any corresponding embodiment thereof.

[0015] The circuit for resisting power micro-interruptions provided in this embodiment can supply power to the load with the electrical energy stored in the second capacitor in the case of a power micro-interruption, ensuring uninterrupted operation of the load; by using the complementary on and off mechanism of the first transistor circuit and the second transistor circuit, it realizes instantaneous switching when the power supply state changes, reducing the risk of voltage drop; through the capacitor energy storage and transistor isolation design, it suppresses the current impact or voltage fluctuation generated during the power supply switching process, which can improve the stability of the system; when the power supply is in operation, the supply current of the power supply supplies power to the load and charges the capacitor simultaneously, optimizing the energy utilization efficiency; the capacitor only needs to supply power briefly during the micro-interruption, reducing the capacity requirement of the energy storage element; in addition, the logical control of the first transistor circuit and the second transistor circuit can reduce the loss of the power supply and the capacitor caused by frequent charging and discharging, improving the reliability of the overall circuit. Description of the Drawings

[0016] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related art, the following will briefly introduce the drawings required to be used in the description of the specific embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 Shows a schematic diagram of some requirements for the EMC electrical performance;

[0018] Figure 2 Shows a schematic diagram of the PMOS anti-reverse circuit structure in the related art;

[0019] Figure 3 The structural schematic diagram of the PMOS reverse protection circuit test in the related art is shown;

[0020] Figure 4 The schematic diagram of electronic characteristic parameters is shown;

[0021] Figure 5 The schematic diagram of the power supply situation during the test of the PMOS reverse protection circuit in the related art is shown;

[0022] Figure 6 The schematic diagram of the current flow direction during the test of the PMOS reverse protection circuit in the related art is shown;

[0023] Figure 7 The schematic diagram of the parameter of the interference pulse during the test of the PMOS reverse protection circuit in the related art is shown;

[0024] Figure 8 The schematic diagram of the equivalent circuit during the interference test of the PMOS reverse protection circuit in the related art is shown;

[0025] Figure 9 The schematic diagram of the current flow direction during the interference test of the PMOS reverse protection circuit in the related art is shown;

[0026] Figure 10 The schematic diagram of the current flow direction when Q1 in the PMOS reverse protection circuit in the related art is not conducting is shown;

[0027] Figure 11 The schematic diagram of the time interval parameter between interference pulses during the test of the PMOS reverse protection circuit in the related art is shown;

[0028] Figure 12 The schematic diagram of the voltage across the load during the test of the PMOS reverse protection circuit in the related art is shown;

[0029] Figure 13 The structural schematic diagram of the circuit for resisting power micro-interruptions according to the embodiment of the present invention is shown;

[0030] Figure 14 The schematic diagram of the current flow direction of the circuit for resisting power micro-interruptions according to the embodiment of the present invention is shown;

[0031] Figure 15 Another schematic diagram of the current flow direction of the circuit for resisting power micro-interruptions according to the embodiment of the present invention is shown;

[0032] Figure 16 The schematic diagram of the voltage across the load changing with time is shown;

[0033] Figure 17 It shows that the capacitance of the second capacitor satisfies that t0 is greater than td Schematic diagram of the voltage across the load varying with time in the case of

[0034] Figure 18 It shows that the second capacitance satisfies t0 < t d Schematic diagram of the voltage across the load varying with time in the case of

[0035] Figure 19 Schematic diagram showing the voltage across the load varying with time in the case of a power micro-interruption for the circuit for resisting power micro-interruptions according to an embodiment of the present invention;

[0036] Figure 20 Another schematic diagram showing the circuit structure of the circuit for resisting power micro-interruptions according to an embodiment of the present invention;

[0037] Figure 21 Schematic diagram of the loop of the circuit for resisting power micro-interruptions according to an embodiment of the present invention in the case of a power micro-interruption. Detailed implementation manners

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0039] In the embodiments of the present application, sometimes subscripts such as W1 may be miswritten as non-subscript forms such as W1. When the difference is not emphasized, the meanings they express are the same.

[0040] Under the requirements of the electro-magnetic compatibility (EMC) electrical performance part in the automotive electronics industry, vehicle manufacturers generally require automotive electronics to meet the following test requirements: a first power micro-interruption duration, which can be 5 ms, and it is required that there be no restart during the test process. Figure 1 It shows a schematic diagram of the requirements of the EMC electrical performance part. As Figure 1 shown, the EMC electrical performance parameters include: operating voltage U a , fall time t f , rise time t r , delay time t d , pulse duration t1, pulse interval time t2, and recovery time t3. Among them, U a is used to characterize the normal operating voltage of the device. The operating voltage range of vehicle electronic components can be configured as 9 - 16 V, and 14 can be selected as the typical operating voltage; tf It is used to characterize the time required for the pulse signal to drop from 90% amplitude to 10%, which can reflect the attenuation characteristics of the interference signal; t r It is used to characterize the time required for the pulse signal to rise from 10% amplitude to 90%, which can be used to evaluate the steepness of the transient interference; t d It is used to characterize the power supply interruption generation time; t1 is used to characterize the micro-interruption period, including the time of power supply interruption generation and the time of power supply maintenance. As described above, t d It is used to characterize the power supply interruption generation time, t1 - t d It is used to characterize the normal operating voltage maintenance time within a single micro-interruption test cycle; t2 is used to characterize the total micro-interruption test cycle. For example, if the single micro-interruption cycle t1 is 10 ms and the total micro-interruption test cycle t2 lasts for 100 ms, it means 10 cycles are to be performed; t3 is used to characterize the time required for the device to recover normal function after being interfered.

[0041] Figure 2 It shows the schematic diagram of the PMOS reverse protection circuit structure in the related art. Figure 3 It shows the schematic diagram of the PMOS reverse protection circuit test in the related art. As Figure 3 shown, during the test of the PMOS reverse protection circuit, the Figure 2 battery voltage (Voltage Battery, abbreviated as VBAT) power supply in is replaced by an experimental instrument, and the experimental instrument (Vin) generates a test waveform.

[0042] As Figure 2 shown, VBAT first passes through the body diode of the first triode Q1 to the S pole, and the voltage drop of the body diode is about 0.6V. At this time, the voltage of the S pole of Q1 is VBAT - 0.6V, the voltage of the G pole of Q1 is (VBAT - 0.6V)*R1 / (R1 + R2), VGS = -(VBAT - 0.6V)*R2 / (R1 + R2). Since the conduction condition of Q1 in the PMOS control circuit is that the value of VGS is greater than VGS(TH), that is, the voltage of the S pole is higher than the voltage of the G pole by a certain value, the S pole and the D pole can be conducted.

[0043] Figure 4 It shows the schematic diagram of the electronic characteristic parameters. Figure 4 Taking the specification of model ZMA040P04N as an example, the electronic characteristic parameters are exemplarily described. As Figure 4As shown, when taking VGS(TH) as the conduction voltage of the first triode being -1.3V, that is, VSG(TH)min being 1.3V, when (VBAT - 0.6V)*R2 / (R1 + R2) > 1.3V, the S pole and D pole of Q1 conduct, the first triode conducts, and after conduction, VSG = VBAT*R2 / (R1 + R2). According to actual debugging, generally take R1 = 47KΩ, R2 = 100KΩ, C1 = 10nF. The range of VBAT is 9 - 16V, take VBAT min = 9V, the initial VSG min = 8.4V * 100KΩ / 147KΩ ≈ 5.7V, the S pole and D pole of Q1 conduct, at this time VSG = 8.4V * 100KΩ / 147KΩ ≈ 6.1V, and the S pole and D pole of Q1 maintain conduction to keep a stable state.

[0044] Figure 5 The figure shows a schematic diagram of the power supply situation during the test of the PMOS reverse protection circuit in the related technology. As Figure 5 shown, during the test of the PMOS reverse protection circuit, Vin is equivalent to the VBAT power supply, and the circuit diagram powered by Vin can be equivalent to Figure 2 the circuit diagram shown.

[0045] Figure 6 The figure shows a schematic diagram of the current flow direction during the test of the PMOS reverse protection circuit in the related technology. As Figure 6 shown, during the test of the PMOS reverse protection circuit in the related technology, it includes multiple circuit loops. The first loop is that the current flows from the positive pole of the experimental instrument, through Q1, R2, and R1, and flows to the negative pole of the experimental instrument; the second loop is that the current flows from the positive pole of the experimental instrument, through Q1 and C2, and flows to the negative pole of the experimental instrument; the third loop is that the current flows from the positive pole of the experimental instrument, through Q1 and the load, and flows to the negative pole of the experimental instrument.

[0046] Figure 7 The figure shows a schematic diagram of the parameters of the interference pulse during the test of the PMOS reverse protection circuit in the related technology. As Figure 7 shown, during the test of the PMOS method circuit in the related technology, during the period when the power supply is interfered, it is the test time period corresponding to U a being 0.

[0047] Figure 8 The figure shows a schematic diagram of the equivalent circuit during the interference test of the PMOS reverse protection circuit in the related technology. As Figure 8 shown, when performing the interference test on the PMOS reverse protection circuit in the related technology, the experimental instrument is equivalent to the resistor Ri.

[0048] Figure 9Shows a schematic diagram of the current flow during the interference test of the PMOS reverse protection circuit in the related art. As Figure 9 shown, when performing an interference test on the PMOS reverse protection circuit in the related art, at this time, it is powered by the capacitor C2 in the circuit. The condition for Q1 to conduct is VSG > 1.3V, VSG = Vc2 * R2 / (R1 + R2), R1 = 47KΩ, R2 = 100KΩ. After conversion, when Vc2 is greater than the first voltage threshold, that is, when the voltage Vc2 across C2 > 1.911V, Q1 conducts. When Q1 conducts, the current flow includes multiple loops. The first loop is that the current flows from the positive pole of C2, through the load, and to the negative pole of C2; the second loop is that the current flows from the positive pole of C2, through R2 and R1, and to the negative pole of C2; the third loop is that the current flows from the positive pole of C2, through Ri, and to the negative pole of C2. The electrical energy stored in C2 is continuously consumed until Vc2 is less than the first voltage threshold again, that is, in the case of Vc2 < 1.911V, Q1 does not conduct.

[0049] Figure 10 Shows a schematic diagram of the current flow when Q1 in the PMOS reverse protection circuit in the related art does not conduct. As Figure 10 shown, in the case where Q1 does not conduct, the current flow includes multiple loops. The first loop is that the current flows from the positive pole of C2, through the load, and to the negative pole of C2; the second loop is that the current flows from the positive pole of C2, through R2 and R1, and to the negative pole of C2.

[0050] Figure 11 Shows a schematic diagram of the time interval parameter between interference pulses during the test of the PMOS reverse protection circuit in the related art. As Figure 11 shown, assuming that the time interval between adjacent interference pulses is long enough, that is, t d = ∞.

[0051] Figure 12 Shows a schematic diagram of the voltage across the load during the test of the PMOS reverse protection circuit in the related art. As Figure 12 shown, during the test of the PMOS reverse protection circuit in the related art, the voltage curve of the voltage Vc2 across the load changes with time and includes multiple stages. Among them, t1 is used to represent the case where interference has not occurred, and the voltage Vc2 across the load is constant at 14V. t2 and t3 are used to represent the duration of interference (t d ). Among them, t2 is used to represent the case where Vc2 > 1.911V and Q1 conducts; t3 is used to represent the case where Vc2 < 1.911V and Q1 does not conduct. The main factor affecting the duration of t2 is the capacitance of C2. t2 corresponds to Figure 9 the circuit schematic diagram shown, and t3 corresponds to Figure 10 the circuit schematic diagram shown.

[0052] According to an embodiment of the present invention, a circuit embodiment for tolerating power micro-interruptions is provided. Figure 13 The schematic structural diagram of the circuit for tolerating power micro-interruptions according to an embodiment of the present invention is shown, as Figure 13 shown, the circuit includes: a power supply 1301, a first transistor circuit 1302 connected to the power supply 1301, a second transistor circuit 1303 connected to the first transistor circuit 1302, a second capacitor 1304 connected to the first transistor circuit 1302, and a load 1305 connected to the first transistor circuit 1302.

[0053] Figure 14 The schematic diagram of the current flow direction of the circuit for tolerating power micro-interruptions according to an embodiment of the present invention is shown, as Figure 14 shown, when the power supply 1301 supplies power, the first transistor circuit 1302 is turned on, the second transistor circuit 1303 is turned off, the supply current of the power supply 1301 stores electrical energy for the second capacitor 1304 via the first transistor circuit 1302, and the supply current also supplies power to the load 1305 via the first transistor circuit 1302.

[0054] Figure 15 Another schematic diagram of the current flow direction of the circuit for tolerating power micro-interruptions according to an embodiment of the present invention is shown, as Figure 15 shown, when the power supply 1301 has a micro-interruption, the second capacitor 1304 supplies power to the load 1305 through the stored electrical energy, the second transistor circuit 1303 is turned on, and the first transistor circuit 1302 is turned off. After the interference pulse is emitted, the first transistor circuit can be quickly turned off.

[0055] In the actual circuit design process, the supply voltage of the load needs to be higher than a preset voltage value, and the preset voltage value can be 5V. Figure 16 The schematic diagram of the voltage across the load changing with time is shown. As Figure 16 shown, the voltage Vc2 across the load is reduced from a constant voltage value to the lowest value at which the load can operate normally, that is, Vc2 is reduced from 14V to 5V, and the corresponding time period is marked as t0.

[0056] Assume t d takes a value of 5 ms, and the capacitance of the second capacitor can satisfy that t0 is greater than t d , that is, it can meet the requirement that the device under test (DUT) does not restart. Figure 17 The schematic diagram of the voltage across the load changing with time when the capacitance of the second capacitor satisfies that t0 is greater than t d is shown. As Figure 17 shown, if the capacitance of the second capacitor is large enough, within a single interference time period, the waveform of the voltage Vc2 across the load is as Figure 17 shown by the blue line in.

[0057] Figure 18 shows that when the second capacitance satisfies t0 less than t d , a schematic diagram of the voltage across the load changing with time is shown. As Figure 18 shown, if the second capacitance is small and the capacitance of the second capacitor satisfies t0 < t d , within a single interference time period, the waveform of the voltage Vc2 across the load is as shown by the yellow line in Figure 18 . The voltage across the load is lower than 5V, and the load has a restart situation.

[0058] In the actual design process of the circuit, due to limitations such as structural design or cost control, the capacitance of the second capacitor cannot be infinitely large. Generally, the value ranges from 220 μf to 2200 μf, and it is difficult to support t0 greater than t d . However, the circuit for resisting power micro-interruptions provided by the embodiments of the present invention can quickly turn off the first transistor circuit in the case of a power micro-interruption, so that the circuit for resisting power micro-interruptions provided by the embodiments of the present invention can quickly enter the situation shown in Figure 15 , that is, the second capacitor supplies power to the load, and when the voltage across the load is greater than the first voltage threshold (1.911V), the first transistor circuit is turned off. Figure 19 shows a schematic diagram of the voltage across the load changing with time in the circuit for resisting power micro-interruptions according to the embodiments of the present invention in the case of a power micro-interruption. As Figure 19 shown, the condition for the first transistor circuit to work is that the voltage of the first transistor circuit satisfies the conduction voltage of the first triode. In the case of a power micro-interruption, the voltage of the first transistor circuit drops to 0, the first transistor circuit is disconnected, and the second transistor circuit is turned on, so that in the case of a power micro-interruption, the second capacitor can supply power to the load and the load does not restart.

[0059] The circuit for resisting power micro-interruptions provided by this embodiment can supply power to the load through the electric energy stored in the second capacitor in the case of a power micro-interruption, ensuring the uninterrupted operation of the load; using the complementary conduction and disconnection mechanism of the first transistor circuit and the second transistor circuit to achieve instantaneous switching when the power state changes and reducing the risk of voltage drop; through the capacitor energy storage and transistor isolation design, suppressing the current impact or voltage fluctuation generated during the power switch process, which can improve the stability of the system; when the power supply is supplying power, the supply current of the power supply supplies power to the load and charges the capacitor at the same time, optimizing the energy utilization efficiency; the capacitor only needs to supply power briefly during the micro-interruption, reducing the capacity requirement of the energy storage element; in addition, the logic control of the first transistor circuit and the second transistor circuit can reduce the loss of the power supply and the capacitor caused by frequent charging and discharging, improving the reliability of the overall circuit.

[0060] Figure 20Another schematic diagram of the circuit structure for tolerating power micro-interruptions according to an embodiment of the present invention is shown. As Figure 20 shown, in some alternative embodiments, the second transistor circuit 1303 includes: a second transistor Q2, a third resistor R3, and a fourth resistor R4. The first terminal (S pole) of the second transistor Q2 is connected to the first transistor circuit 1302. One end of the third resistor R3 is connected to the positive electrode of the power supply, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the negative electrode of the power supply, the second terminal (G pole) of the second transistor Q2 is connected to the other end of the third resistor R3, and the third terminal (D pole) of the second transistor Q2 is connected to the first transistor circuit 1302.

[0061] In this embodiment, the third resistor R3 and the fourth resistor R4 are voltage-dividing resistors, forming a voltage-dividing network that is connected across the positive and negative electrodes of the power supply. The voltage at the voltage-dividing point (the connection point of R3 and R4) is in a fixed ratio to the power supply voltage and reflects the power supply state in real time. The driving logic of the second transistor Q2 is as follows:

[0062] When the power supply is normal, the voltage difference between the source voltage and the gate voltage of Q2 is small, which is not sufficient to turn on the drain and source of Q2, that is, Q2 is in the off state. At this time, the first transistor circuit is turned on.

[0063] In the case of a power micro-interruption, the power supply voltage drops, and the voltage at the voltage-dividing point drops to the conduction threshold of Q2. Q2 conducts, and at the same time, it triggers the first transistor circuit to turn off, switching the load power supply to the second capacitor C2.

[0064] The conduction state of Q2 is connected to the control terminal of the first transistor circuit through its first terminal, forming a reverse driving logic. When Q2 conducts, it pulls down the control signal of the first transistor circuit, forcing q1 to turn off.

[0065] In this way, without additional chip detection, only through the complementary conduction design of the first transistor circuit and the second transistor circuit, and the voltage-dividing network, the power supply state judgment and switching can be realized, which can reduce costs; at the same time, fast and low-power supply switching can be realized, ensuring the continuous operation of the load during power micro-interruptions, with high reliability.

[0066] In some alternative embodiments, the second transistor is a P-type metal-oxide-semiconductor field-effect transistor.

[0067] The PMOS has a low output impedance characteristic in the on state, which can quickly provide a stable current for the load, reduce the voltage drop caused by the path resistance during switching, and ensure the power supply continuity of the capacitor to the load. At the same time, the second transistor is configured as a PMOS. Through its high input impedance, low output impedance, and complementary logic characteristics, it realizes a fast and low-loss power supply path switching, while taking into account temperature stability and anti-interference ability, and is suitable for power supply micro-interruption scenarios with high requirements for power consumption, response speed, and reliability.

[0068] In some alternative embodiments, such as Figure 20 shown, the first transistor circuit 1302 includes: a first transistor q1, a first resistor r1, a second resistor r2, and a first capacitor c1. The first end of the first transistor q1 is connected to the positive pole of the power supply, the second end of the first transistor q1 is connected to one end of the second resistor r2, the other end of the second resistor r2 is connected to one end of the first resistor r1, the third end of the first transistor q1 is connected to one end of the first resistor r1, the other end of the first resistor r1 is connected to the negative pole of the power supply, one end of the first capacitor c1 is connected to one end of the second resistor r2, and the other end of the first capacitor c1 is connected to the other end of the second resistor r2.

[0069] In this embodiment, the first resistor r1 and the second resistor r2 form a voltage dividing network. r1 is connected to the negative pole of the power supply, r2 is connected to the positive pole of the power supply, and the voltage dividing point is the connection point of r1 and r2. c1 is connected in parallel across r2 to form an RC filtering network, which can suppress the instantaneous fluctuation of the power supply voltage and prevent q1 from being accidentally turned off. In the case of a power supply micro-interruption, c1 discharges through r2, which can delay the voltage drop speed of the voltage dividing point and provide a buffer time for the switching of the second transistor circuit to avoid voltage spikes caused by transient switching.

[0070] When the power supply is normal, q1 is turned on, and the current flows from the positive pole of the power supply → q1 → the load → the negative pole of the power supply, and at the same time charges the second capacitor C2. When there is a power supply micro-interruption, q1 is turned off, cutting off the direct connection between the power supply and the load, preventing reverse current or voltage backflow, and ensuring the independence of the power supply path of the second capacitor.

[0071] In this way, the voltage dividing network composed of r1 and r2 can provide a stable bias voltage. Combining with the filtering function of c1, it can suppress the interference of power supply noise on the control signal of q1, and improve the reliability of turning on or off. The delay characteristic of c1 maintains the short-term conduction of q1 during short-term fluctuations of the power supply to avoid frequent switching; while it quickly turns off q1 during continuous interruptions to reduce energy loss. In addition, when q1 is turned off, it completely cuts off the physical connection between the power supply and the load, preventing the surge current from impacting the load when the power supply resumes, and at the same time avoiding the backflow of capacitor electrical energy to the power supply.

[0072] In some alternative embodiments, the first transistor can be configured as a P-type metal oxide semiconductor field effect transistor.

[0073] With its high input impedance, low static power consumption, and complementary logic characteristics, the PMOS can achieve efficient power supply path switching and low-loss control in the first transistor circuit, while taking into account temperature stability and anti-interference ability. It is suitable for power management scenarios with high requirements for power consumption, integration, and reliability.

[0074] In some alternative embodiments, such as Figure 20 shown, one end of the second capacitor C2 is connected to the first transistor q1, the other end of the second capacitor C2 is connected to the negative pole of the power supply, one end of the load is connected to the first transistor q1, and the other end of the load is connected to the negative pole of the power supply.

[0075] In this embodiment, C2 is charged when the power supply is normal and serves as a temporary power supply when the power supply is interrupted, providing short-term energy buffering for the load. It is suitable for coping with power micro-interruption scenarios. C2 is connected in parallel across the load, which can absorb the high-frequency noise of the load current, reduce the voltage fluctuation on the power line, and improve the system stability.

[0076] The load and C2 are directly connected in parallel to the source of the first transistor, eliminating the need for an additional switching circuit, reducing the number of components and failure points. At the same time, the natural isolation characteristic of the PMOS avoids the short-circuit risk.

[0077] In some alternative embodiments, in the case of a power micro-interruption, the second capacitor supplies power to the load through the stored electrical energy, the second transistor circuit is turned on, and the first transistor circuit is turned off, including: the current generated by the electrical energy stored in the second capacitor flows through the load to supply power to the load and flows to the negative pole of the second capacitor; the current generated by the electrical energy stored in the second capacitor flows through the second transistor and the first resistor and flows to the negative pole of the second capacitor.

[0078] In this embodiment, when a power micro-interruption occurs, the power supply voltage VBAT = 0V. Due to the presence of the C2 energy storage capacitor in the system, when VBAT is powered off, the electrical energy stored in C2 supplies power to the load system. The S-pole voltage VS of Q2 is 14V, the G-pole voltage of Q2 is 0V, VSG(Q2) = 14V > 1.3V, the DS pole of Q2 is turned on, VSG(q1) = VSD(Q2) = 0V, and the DS of q1 is turned off. At this time, the body diode inside q1 prevents the electrical energy of C2 from flowing to the outside, that is, the loop from the positive pole of the second capacitor, through the first transistor and the power supply, to the negative pole of the second capacitor is disconnected.

[0079] Figure 21 Shows a loop schematic diagram of the circuit for resisting power micro-interruption according to an embodiment of the present invention in the case of a power micro-interruption. As Figure 21 shown, in the case of a power micro-interruption, the disconnected loop is crossed out with a red cross as Figure 21 shown, and the power supply loop of the second capacitor, such asFigure 21 As shown by the red arrow in the figure, Path 1: The power supply current of the second capacitor flows from the positive electrode of the second capacitor C2, through Q2 and r1, to the negative electrode of C2, and Path 2: C2 supplies power to the load.

[0080] When C2 discharges, most of the current preferentially passes through the load path to ensure continuous operation of the load; for Path 1, through the on-resistance of the second transistor and the current-limiting effect of R1, the discharge speed and energy utilization rate are balanced to avoid overheating or voltage drop caused by instantaneous large current discharge of C2.

[0081] r1 acts as a current-limiting resistor for Path 1 when the power supply is interrupted, preventing the second transistor from being damaged due to excessive initial discharge current of C2; r2 participates in PMOS voltage division when the power supply is normal and becomes a floating high-impedance state when interrupted, avoiding interfering with the discharge of C2.

[0082] In this way, C2 continuously discharges through the load path during a micro power interruption of the power supply, realizing seamless switching of power supply, and avoiding restart or damage of the load due to voltage drop. The parallel structure of C2 can suppress voltage fluctuations at the load end, and maintain a stable voltage through a low-impedance discharge path (Path 1 + Path 2) when the power supply is interrupted, reducing the risk of abnormal operation of the load.

[0083] During a micro power interruption of the power supply, this circuit works in cooperation with the energy storage discharge of C2 and the low-impedance conduction path of the second transistor to realize seamless switching of load power supply and efficient energy release. Its design combines technologies such as dynamic path priority control, thermal safety current limiting, and reverse current isolation, significantly improving the reliability and continuity of the system in short-term power interruption scenarios, and is applicable to equipment such as precision instruments and communication modules that require high anti-interference ability and uninterrupted power supply.

[0084] In some alternative embodiments, when the power supply is powered, the first transistor circuit is turned on and the second transistor circuit is turned off. The power supply current of the power supply stores electrical energy for the second capacitor via the first transistor circuit, and the power supply current supplies power to the load via the first transistor circuit, including: the power supply current flows through the first transistor, the second resistor, and the first resistor, and flows to the negative electrode of the power supply; the power supply current flows through the first transistor and the second capacitor, and flows to the negative electrode of the power supply; the power supply current flows through the first transistor and the load, and flows to the negative electrode of the power supply.

[0085] In this embodiment, when the DS pole of Q2 is turned on, VSG(Q1) = 0V of q1, and the DS pole of q1 is not turned on. The condition for the DS pole of Q2 to be turned on is VSG(Q2) > 1.3V.

[0086] When the power supply is powered on, the power supply provides a constant voltage, for example, VBAT = 14V. Q1 conducts, and the voltage at the S pole of Q2 is the same as the constant voltage provided by the power supply, VS = VBAT = 14V. The voltage at the G pole is VG = VBAT*R4 / (R3 + R4). Taking R4 = 100KΩ and R3 = 100Ω, VSG(Q2) = VBAT*R3 / (R3 + R4) = 0.014V < 1.3V, and the DS of Q2 does not conduct, while Q1 remains conducting.

[0087] When the power supply is supplying power, the first transistor conducts, forming the following current paths:

[0088] The first path: positive pole of the power supply → the first transistor → the second resistor r2 and the first resistor r1 → negative pole of the power supply. In this way, r1 and r2 may be used for voltage division or current limiting to ensure that the first transistor operates in the saturation region and at the same time protect the circuit from overcurrent damage.

[0089] The second path: positive pole of the power supply → the first transistor → the second capacitor C2 → negative pole of the power supply. In this way, C2 is charged and stores energy when the power supply is supplying power, serving as a backup energy source.

[0090] The third path: positive pole of the power supply → the first transistor → the load → negative pole of the power supply. In this way, the main power supply is directly provided to the load.

[0091] The second transistor is in the off state to avoid current shunting or reverse interference.

[0092] When the power supply is normal, C2 is charged to a voltage close to the power supply voltage, and the load is directly powered by the power supply. When the power supply is interrupted, since the source and drain of the second transistor are conducting, the gate and source of the first transistor are short-circuited, and the gate and source of the first transistor are cut off because the voltage difference is not sufficient to conduct. This is because the external input voltage is pulled to ground, and there is a voltage difference between the gate and source of the second transistor, which is sufficient to conduct the source and drain of the second transistor. At the same time, when the power supply is interrupted, C2 discharges through the load to maintain short-term power supply and prevent the system from suddenly losing power.

[0093] In this way, the second capacitor (C2) serves as an energy storage element. When there are power fluctuations or short interruptions, it discharges to provide continuous power supply to the load, improving the system stability and avoiding data loss or device restart.

[0094] The embodiment of the present invention also provides a chip for resisting power micro-interruptions, including the aforementioned circuit for resisting power micro-interruptions.

[0095] The embodiment of the present invention also provides an electronic device, and the electronic device includes the aforementioned chip for resisting power micro-interruptions.

[0096] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized.

[0097] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0098] In several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0099] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0100] In addition, the functional units in various embodiments of the present invention can be integrated in one processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0101] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A circuit for withstanding micro interruptions of power supply, characterized in that The circuit comprises: A power supply, a first transistor circuit connected to the power supply, a second transistor circuit connected to the first transistor circuit, a second capacitor connected to the first transistor circuit, and a load connected to the first transistor circuit; When the power supply is powered, the first transistor circuit is turned on, the second transistor circuit is turned off, the power supply current of the power supply is used to store electric energy for the second capacitor via the first transistor circuit, and the power supply current is used to power the load via the first transistor circuit; In the case of a slight interruption of the power supply, the second capacitor supplies power to the load through the stored electric energy, the second transistor circuit is turned on, and the first transistor circuit is turned off.

2. The circuit according to claim 1, characterized in that The second transistor circuit includes: a second transistor, a third resistor and a fourth resistor, the first end of the second transistor is connected to the first transistor circuit, one end of the third resistor is connected to the positive electrode of the power supply, the other end of the third resistor is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the negative electrode of the power supply, the second end of the second transistor is connected to the other end of the third resistor, and the third end of the second transistor is connected to the first transistor circuit.

3. The circuit according to claim 2, characterized in that The second transistor is a P-type metal oxide semiconductor field effect transistor.

4. The circuit according to claim 2, characterized in that The first transistor circuit includes: a first transistor, a first resistor, a second resistor and a first capacitor, the first end of the first transistor is connected to the positive electrode of the power supply, the second end of the first transistor is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, the third end of the first transistor is connected to one end of the first resistor, the other end of the first resistor is connected to the negative electrode of the power supply, one end of the first capacitor is connected to one end of the second resistor, and the other end of the first capacitor is connected to the other end of the second resistor.

5. The circuit according to claim 4, characterized in that The first transistor is a P-type metal oxide semiconductor field effect transistor.

6. The circuit according to claim 4, characterized in that One end of the second capacitor is connected to the first transistor, and the other end of the second capacitor is connected to the negative electrode of the power supply. One end of the load is connected to the first transistor, and the other end of the load is connected to the negative electrode of the power supply.

7. The circuit according to claim 6, characterized in that In the case of a slight interruption of the power supply, the second capacitor supplies power to the load through the stored electric energy, the second transistor circuit is turned on, and the first transistor circuit is turned off, including: The current generated by the electric energy stored in the second capacitor flows through the load to supply power to the load and flows to the negative electrode of the second capacitor; The current generated by the electric energy stored in the second capacitor flows through the second transistor and the first resistor, and flows to the negative electrode of the second capacitor.

8. The circuit according to claim 6, characterized in that When the power supply is powered, the first transistor circuit is turned on, the second transistor circuit is turned off, the power supply current of the power supply, via the first transistor circuit, stores electric energy for the second capacitor, and the power supply current, via the first transistor circuit, supplies power to the load, including: The supply current flows through the first transistor, the second resistor and the first resistor, and flows to the negative electrode of the power supply; The supply current flows through the first transistor and the second capacitor and flows to the negative electrode of the power supply; The supply current flows through the first transistor and the load and flows to the negative electrode of the power supply.

9. A chip for withstanding power micro-interruptions, characterized in that: The chip comprises the circuit for withstanding power micro interruptions according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the chip according to claim 9.

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