Switching circuit for battery balancing in battery management system

Abstract

The present disclosure describes a switching circuit for battery balancing in a battery management system (BMS). The switching circuit comprises a first battery pack connecting end used for being connected to a first battery pack end; the second battery pack connecting end is used for being connected to a second battery pack end; and a battery balanced field effect transistor (FET). The battery balancing FET includes: a gate terminal; a drain terminal connected to the first battery pack connection terminal; a source terminal for connecting to the second battery pack connection terminal; and a body end. The switching circuit additionally includes a gate control circuit configured to connect the gate terminal of the cell balancing FET to a battery pack connection terminal having a lowest voltage; and a bias resistor connected in series between the body end of the battery balancing FET and one of the first battery pack connection end and the second battery pack connection end.

Description

Technical Field

[0001] The present disclosure relates to a switching circuit for battery balancing in a battery management system (BMS). Background Art

[0002] In a battery management system (BMS), it is possible to perform passive battery balancing using an IC (integrated circuit) integrated switch. This switch can have an extremely low on-resistance (when an FET is used as the switch, this on-resistance can be referred to as R dson ; that is, when the FET is turned on, the resistance between the drain and the source), for example, 0.25 ohms. Advantageously, such a low on-resistance can result in minimal heat dissipation in the IC when the switch is closed and battery balancing is activated. The leakage through this switch has a significant impact on the accuracy of battery measurements, which is a key aspect of the BMS. In addition, even when the battery pack cells are replaced by busbars, this switch should have minimal leakage. When the battery pack cells are replaced by busbars, the busbars may generate a negative voltage across the switch when drawing current from the battery pack including the battery pack cells. If a single MOS is used as the switch, then if a busbar is used, unwanted leakage current will flow through its body diode, such that there is a negative voltage across the switch. Such a busbar can simply be a metal wire used in place of the battery pack cells. When drawing current from the battery pack, the busbar can generate up to -3V across the switch due to its resistance. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a switching circuit for battery balancing in a battery management system BMS, the switching circuit comprising:

[0004] A first battery pack connection terminal for connecting to a first battery pack end;

[0005] A second battery pack connection terminal for connecting to a second battery pack end;

[0006] A battery balancing field effect transistor FET, comprising:

[0007] A gate terminal;

[0008] A drain terminal connected to the first battery pack connection terminal;

[0009] A source terminal for connecting to the second battery pack connection terminal; and

[0010] A body terminal;

[0011] A gate control circuit configured to connect the gate terminal of the battery balancing FET to the battery pack connection terminal having the lowest voltage; and

[0012] A bias resistor, the bias resistor being connected in series between the body terminal of the battery balancing FET and one of the first battery pack connection terminal and the second battery pack connection terminal.

[0013] Advantageously, such a switching circuit can benefit from occupying a relatively small area on the integrated circuit while still achieving a leakage current equivalent to that of a back-to-back switching implementation.

[0014] In one or more embodiments, the bias resistor is connected in series between the body terminal of the battery balancing FET and the second battery pack connection terminal.

[0015] In one or more embodiments, the bias resistor has a resistance value of approximately several megaohms.

[0016] In one or more embodiments, the battery balancing FET is the only FET connected between the first battery pack connection terminal and the second battery pack connection terminal.

[0017] In one or more embodiments, the FET control circuit includes:

[0018] A lowest power supply node; and

[0019] A gate pull-down switch, the gate pull-down switch being connected between the lowest power supply node and the gate terminal of the battery balancing FET.

[0020] In one or more embodiments, the FET control circuit includes:

[0021] A first battery pack connection switch, the first battery pack connection switch being connected between the first battery pack connection terminal and the lowest power supply node;

[0022] A second battery pack connection switch, the second battery pack connection switch being connected between the second battery pack connection terminal and the lowest power supply node; and

[0023] A LOS node control circuit, the LOS node control circuit being configured to:

[0024] When the voltage level at the first battery pack connection terminal is lower than the voltage level at the second battery pack connection terminal, close the first battery pack connection switch and open the second battery pack connection switch; and

[0025] When the voltage level at the first battery pack connection terminal is higher than the voltage level at the second battery pack connection terminal, open the first battery pack connection switch and close the second battery pack connection switch.

[0026] In one or more embodiments, the LOS node control circuit includes:

[0027] an amplifier configured to:

[0028] compare the voltage level at the first battery pack connection terminal with the voltage level at the second battery pack connection terminal;

[0029] provide a first amplifier output signal to the control terminal of the first battery pack connection switch so that: i) when the voltage level at the first battery pack connection terminal is lower than the voltage level at the second battery pack connection terminal, close the first battery pack connection switch; and ii) when the voltage level at the first battery pack connection terminal is higher than the voltage level at the second battery pack connection terminal, open the first battery pack connection switch; and

[0030] provide a second amplifier output signal to the control terminal of the second battery pack connection switch so that: i) when the voltage level at the first battery pack connection terminal is lower than the voltage level at the second battery pack connection terminal, open the second battery pack connection switch; and ii) when the voltage level at the first battery pack connection terminal is higher than the voltage level at the second battery pack connection terminal, close the second battery pack connection switch.

[0031] In one or more embodiments, the amplifier is a hysteresis amplifier.

[0032] In one or more embodiments, the FET control circuit further includes:

[0033] a first capacitor serially connected between the control terminal of the first battery pack connection switch and the second battery pack connection terminal; and

[0034] a second capacitor serially connected between the control terminal of the second battery pack connection switch and the first battery pack connection terminal.

[0035] In one or more embodiments, the capacitance values of the first capacitor and the second capacitor are about a few picofarads.

[0036] In one or more embodiments, the FET control circuit further includes a gate pull-up switch connected between the power supply voltage terminal and the gate terminal of the battery balancing FET.

[0037] There is also disclosed a battery management system BMS, including:

[0038] any switch circuit disclosed herein;

[0039] A battery pack cell having a first battery pack terminal and a second battery pack terminal;

[0040] A first balancing resistor serially connected between the first battery pack connection terminal and the first battery pack terminal; and

[0041] A second balancing resistor serially connected between the second battery pack connection terminal and the second battery pack terminal.

[0042] Although the present disclosure admits of various modifications and alternative forms, the details thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that there may be other embodiments beyond the specific embodiments described. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered therein.

[0043] The foregoing discussion is not intended to present every example embodiment or every implementation within the scope of the current or future claim sets. The drawings and the detailed description also illustrate various example embodiments. The various example embodiments can be more fully understood in view of the following detailed description in conjunction with the drawings. Description of the Drawings

[0044] One or more embodiments will now be described by way of example only with reference to the drawings, in which:

[0045] Figure 1 Examples of battery balancing switches are shown;

[0046] Figure 2 Back-to-back battery balancing switches are shown;

[0047] Figure 3 Example embodiments of a switching circuit for battery balancing in a BMS according to the present disclosure are shown;

[0048] Figure 4 A direct power injection "DPI" simulation platform is shown; and

[0049] Figure 5 Simulation results are shown. Detailed Description

[0050] Figure 1 An example of a battery balancing switch 102 is shown, the battery balancing switch 102 being a MOSFET (metal oxide semiconductor field effect transistor) in Figure 1 . In an EMI (electromagnetic interference) polluted environment, a transient voltage can be applied to the DC level of the battery pack cell and injected onto the switch 102. And when the battery balancing switch 102 is connected to the bus bar, a leakage current (I leak ) can occur. Negative leakage current (Ipeak ) Through the body diode of MOSFET 102. If the EMI level becomes negative and / or the switch 102 is connected to the bus bar, then using a single MOS switch with a single body diode ( Figure 1 ) will result in a DC shift. As shown on the right side of Figure 1 , this results in a DC voltage shift / offset 103, which in turn results in clipping of the negative portion of the AC voltage waveform shown in Figure 1 . This will highly affect the achievable accuracy of battery voltage measurement accuracy, which will endanger the BMS performance and may cause safety problems.

[0051] Figure 2 shows a back-to-back battery balance switch 204, which limits the negative leakage current and prevents Figure 1 the DC voltage shift shown in

[0052] However, the area required to implement the back-to-back battery balance switch 204 on an integrated circuit is Figure 2 four times that of the battery balance switch of Figure 1 . In addition, in some applications, there may be 18 battery equalization switches on a single integrated circuit. In this case, the total area of those switches is greatly increased.

[0053] Figure 3 shows an example embodiment of a switch circuit 305 for battery balance in a BMS according to the present disclosure. The switch circuit 305 includes a first battery bank connection terminal (CBH - Cell Balance High) 306 and a second battery bank connection terminal (CBL - Cell Balance Low) 307. The first battery bank connection terminal 306 is used to connect to the first battery bank terminal, which in this example is the positive terminal of the battery bank cell 308. The second battery bank connection terminal 307 is used to connect to the second battery bank terminal, which in this example is the negative terminal of the battery bank cell 308.

[0054] The switch circuit 305 includes a battery balance field effect transistor FET 309 connected between the first battery bank connection terminal 306 and the second battery bank connection terminal 307. More specifically, the conductive channel of the battery balance FET 309 is connected in series between the first battery bank connection terminal 306 and the second battery bank connection terminal 307. In this example, as shown in Figure 3 , the battery balance FET 309 is the only FET connected between the first battery bank connection terminal 306 and the second battery bank connection terminal 307. That is, a back-to-back arrangement, such as the back-to-back arrangement shown in Figure 2 , is not required.

[0055] The battery balancing FET 309 has a gate terminal, a drain terminal, a source terminal, and a body terminal. The drain terminal is connected to the first battery pack connection terminal 306. The source terminal is connected to the second battery pack connection terminal. In Figure 3 FIG. Figure 3 , an NMOS battery balancing FET 309 is shown. However, it should be understood that in other examples, a PMOS battery balancing FET may be used instead, and the necessary changes to the circuit may be made to accommodate the different type of FET.

[0056] The switching circuit 305 also includes an FET control circuit 310. As will be discussed in detail below, the FET control circuit 310 connects the gate terminal of the battery balancing FET 309 to the battery pack connection terminal 306, 307 having the lowest voltage. This lowest voltage will be referred to as the lowest supply (LOS).

[0057] The switching circuit 305 also includes a bias resistor (Rb) 324, which is connected in series between the body terminal of the battery balancing FET 309 and one of the battery pack connection terminals, i.e., the first battery pack connection terminal (CBH) 306 and the second battery pack connection terminal (CBL) 307. In Figure 3 the example of FIG. Figure 3 , the bias resistor (Rb) 324 is connected in series between the body terminal of the battery balancing FET 309 and the second battery pack connection terminal (CBL) 307. The bias resistor (Rb) 324 may have a relatively high resistance value, such as about several megohms, such that the circuit benefits from the back-to-back body-to-source and body-to-drain diodes across the battery pack cells. As a result, there is little or no rectification (DC shift) that may impair the accuracy of the battery measurement. Thus, advantageously, a highly accurate BMS can be achieved.

[0058] The FET control circuit 310 includes a lowest supply node (LOS) 311, which, as will be discussed below, is set at a voltage level corresponding to one of the lower voltages at the first battery pack connection terminal 306 and the second battery pack connection terminal 307. The FET control circuit 310 also includes a gate pull-down switch (M PD_swi ) 312 connected between the lowest supply node (LOS) 311 and the gate terminal of the battery balancing FET 309. More specifically, the conductive channel of the gate pull-down switch (M PD_swi ) 312 is connected in series between the gate terminal of the battery balancing FET 309 and the lowest supply node (LOS) 311. In this way, the gate pull-down switch (M PD_swi ) 312 can selectively connect the gate terminal of the battery balancing FET 309 to the lowest supply node (LOS) 311.

[0059] The FET control circuit 310 further includes a gate pull-up switch (M PU_swi ) 314 connected between the power supply voltage terminal 313 and the gate terminal of the battery balancing FET 309. More specifically, the conductive channel of the gate pull-up switch (M PU_swi ) 314 is connected in series between the power supply voltage terminal 313 and the gate terminal of the battery balancing FET 309. In this way, the gate pull-up switch (M PU_swi ) 314 can selectively connect the gate terminal of the battery balancing FET 309 to the power supply voltage. As is known in the art, the gate pull-down switch (M PD_swi ) 312 and the gate pull-up switch (M PU_swi ) 314 are controlled by complementary control signals such that they are not both closed or open simultaneously. In this example, the voltage level at the power supply voltage terminal 313 is set at 5V higher than the voltage at the second battery pack connection terminal 307 (CBL + 5V).

[0060] The FET control circuit 310 further includes a first battery pack connection switch (M1) 315, a second battery pack connection switch (M2) 316, and a LOS node control circuit 317 for controlling these switches. The first battery pack connection switch (M1) 315 is connected between the first battery pack connection terminal (CBH) 306 and the lowest power supply node (LOS) 311. The second battery pack connection switch (M2) 316 is connected between the second battery pack connection terminal (CBL) 307 and the lowest power supply node (LOS) 311. The LOS node control circuit 317 is operable to:

[0061] ● When the voltage level at the first battery pack connection terminal (CBH) 306 is lower than the voltage level at the second battery pack connection terminal (CBL) 307, close the first battery pack connection switch (M1) 315 and open the second battery pack connection switch (M2) 316; and

[0062] ● When the voltage level at the first battery pack connection terminal (CBH) 306 is higher than the voltage level at the second battery pack connection terminal (CBL) 307, open the first battery pack connection switch (M1) 315 and close the second battery pack connection switch (M2) 316.

[0063] In the Figure 3 example, the LOS node control circuit 317 is provided as an amplifier. The amplifier compares the voltage level at the first battery pack connection terminal (CBH) 306 with the voltage level at the second battery pack connection terminal (CBL) 307. The amplifier can then provide a first amplifier output signal (Vom) and a second amplifier output signal (Vop) to the respective control terminals of the first battery pack connection switch (M1) 315 and the second battery pack connection switch (M2) 316.

[0064] The first amplifier output signal (Vom) is provided to the control terminal of the first battery pack connection switch (M1) 315 so that: i) when the voltage level at the first battery pack connection terminal (CBH) 306 is lower than the voltage level at the second battery pack connection terminal (CBL) 307, the first battery pack connection switch (M1) 315 is closed; and ii) when the voltage level at the first battery pack connection terminal (CBH) 306 is higher than the voltage level at the second battery pack connection terminal (CBH) 307, the first battery pack connection switch (M1) 315 is opened.

[0065] The second amplifier output signal (Vop) is provided to the control terminal of the second battery pack connection switch (M2) 316 so that: i) when the voltage level at the first battery pack connection terminal (CBH) 306 is lower than the voltage level at the second battery pack connection terminal (CBL) 307, the second battery pack connection switch (M2) 316 is opened; and ii) when the voltage level at the first battery pack connection terminal (CBH) 306 is higher than the voltage level at the second battery pack connection terminal (CBH) 307, the second battery pack connection switch (M2) 316 is closed.

[0066] Advantageously, in this example, the amplifier is a hysteresis amplifier such that it exhibits hysteresis when changing the polarities of the first amplifier output signal (Vom) and the second amplifier output signal (Vop).

[0067] Figure 3 An important aspect of the circuit is that a single MOSFET 309 can be used as the battery balancing switch (M swi ). The gate pull-up switch (M PU_swi ) 314 and the gate pull-down switch (M PD_swi ) 312 are used to turn on and off the MOSFET 309. When the voltage at the first battery pack connection terminal 306 is greater than the voltage at the second battery pack connection terminal 307 (i.e., CBH > CBL), which reflects the condition of the battery pack cells or the positive bus bar (current injected into the battery pack package), the hysteresis amplifier 317 (which can also be referred to as a hysteresis comparator) turns on the second battery pack connection switch (M2) 316 and turns off the first battery pack connection switch (M1) 315. This allows the gate of the battery balancing FET 309 to be pulled down to the lowest supply (LOS) through the gate pull-down switch (M PD_swi ) 312. Conversely, if the voltage at the first battery pack connection terminal 306 is less than the voltage at the second battery pack connection terminal 307 (i.e., CBH < CBL), which may occur in the case of the negative bus bar (current drawn from the battery pack package), then the second battery pack connection switch (M2) 316 is turned off and the first battery pack connection switch (M1) 315 is turned on. This allows the gate of the battery balancing FET 309 to be pulled down through the gate pull-down switch (M PD_swi)312 pulls the gate of the battery balancing FET 309 down to LOS, which in this case is the first battery pack connection terminal 306. In any case, the body of the battery balancing switch (M swi )309 is connected to the second battery pack connection terminal (CBL) 307 through a high-value biasing resistor (Rb) 324 to limit any kind of leakage that may occur from the second battery pack connection terminal (CBL) 307. Therefore, any direct power injection (which is modeled as DPI at the first battery pack connection terminal (CBH) 306 in Figure 3 ) will experience a high impedance. Thus, the back-to-back body-to-source and body-to-drain diodes are maintained.

[0068] Figure 3 The FET control circuit 310 also includes a first capacitor (C1) 320 and a second capacitor (C2) 321. The first capacitor (C1) 320 is connected in series between the control terminal of the first battery pack connection switch (M1) 315 and the second battery pack connection terminal (CBL) 307. The second capacitor (C2) 321 is connected in series between the control terminal of the second battery pack connection switch (M2) 316 and the first battery pack connection terminal (CBH) 306.

[0069] When the voltage at the first battery pack connection terminal (CBH) 306 is higher than the voltage at the second battery pack connection terminal (CBL) 307, the second battery pack connection switch (M2) 316 closes, causing the lowest power supply node (LOS) 311 to be connected to the second battery pack connection terminal (CBL) 307. In this scenario, and at high frequencies, the second capacitor (C2) 321 shorts the gate voltage to the first battery pack connection terminal (CBH) 306, thereby ensuring that the second battery pack connection switch (M2) 316 is turned on. Similarly, when the voltage at the first battery pack connection terminal (CBH) 306 is lower than the voltage at the second battery pack connection terminal (CBL) 307, the first battery pack connection switch (M1) 315 closes, causing the lowest power supply node (LOS) 311 to be connected to the first battery pack connection terminal (CBH) 306. In this scenario, and at high frequencies, the first capacitor (C1) 320 shorts the gate voltage to the second battery pack connection terminal (CBL) 307, thereby ensuring that the first battery pack connection switch (M1) 315 is turned on. In this way, the first capacitor (C1) 320 and the second capacitor (C2) 321 connected to the control terminals of the corresponding battery pack connection switches (M1, M2) 315, 316 can improve the operation of the battery pack connection switches (M1, M2) 315, 316.

[0070] The use of a first capacitor (C1) 320 and a second capacitor (C2) (321) can increase the response time of the switching circuit such that it can more quickly react to a change in which of the voltages at the first battery pack connection terminal (CBH) 306 and the second battery pack connection terminal (CBL) 307 is the lowest. For example, if the frequency of any DPI is higher than the bandwidth of the amplifier 317, then during direct power injection, the charge stored on the first capacitor (C1) 320 and the second capacitor (C2) 321 can place the lowest supply node (LOS) 311 at the lowest potential among the first battery pack connection terminal (CBH) 306 and the second battery pack connection terminal (CBL) 307. In some examples, the DPI can have a frequency range between 150 kHz and 1 GHz. Additionally, in this example, the values of the first capacitor (C1) 320 and the second capacitor (C2) (321) are on the order of a few picofarads. The specific capacitance values used can be selected depending on how quickly they should "take over" the amplifier 317.

[0071] During DPI, when the voltage at the second battery pack connection terminal (CBL) 307 is momentarily higher than the voltage at the first battery pack connection terminal (CBH) 306, if the gate of the battery balancing FET (M swi ) 309 remains connected to the second battery pack connection terminal (CBL) 307, then the battery balancing FET (M swi ) 309 is momentarily turned on and draws current only when the voltage at the second battery pack connection terminal (CBL) 307 is higher than the voltage at the first battery pack connection terminal (CBL) 306. That is, there is a DC shift. In the presence of the hysteresis amplifier 317, M1 315, M2 316, C1 320, C2 321, when the voltage at the second battery pack connection terminal (CBL) 307 is momentarily greater than the voltage at the first battery pack connection terminal (CBH) 306 during DPI, the gate of the battery balancing FET (M swi ) 309 is briefly connected to the first battery pack connection terminal (CBH) 306. If the DPI injection frequency is within the bandwidth of the amplifier 317, then so are the first amplifier output signal (Vom) and the second amplifier output signal (Vop), and during DPI, the battery balancing FET (M swi) The gate of 309 is connected to the lowest potential among the first cell bank connection terminal (CBH) 306 and the second cell bank connection terminal (CBL) 307. If the DPI injection frequency is higher than the bandwidth of the amplifier 317, then C1 320 and C2 321 and the way they are connected ensure that during DPI, the lowest power supply node (LOS) 311 is set to the lowest potential among the first cell bank connection terminal (CBH) 306 and the second cell bank connection terminal (CBL) 307. In addition, in this example, the values of the first capacitor (C1) 320 and the second capacitor (C2) (321) are about a few picofarads. The specific capacitance values used can be selected depending on how quickly they should "take over" the amplifier 317.

[0072] Finally, the body of the battery balancing FET (M swi ) 309 can be kept floating to have a back-to-back body diode configuration. However, the breakdown voltage (BVDSS) of the MOS will be greatly reduced. In fact, the resistance of the biasing resistor (Rb) 324 helps to keep the BVDSS of the MOS high enough, which is particularly beneficial for high-voltage applications.

[0073] Circuit for DC shift test induced in a harsh DPI environment Figure 3 and Figure 2 of the circuit. Figure 4 Shows a setup for simulating DPI, where the switching circuit 405 is Figure 3 of the circuit or Figure 2 of the circuit.

[0074] It is found that Figure 3 of the circuit generates a DC shift quite equivalent to that of the Figure 2 back-to-back switch. However, Figure 3 of the circuit requires a significantly smaller area on the IC.

[0075] To perform the comparison, the following setup is implemented:

[0076] ● DPI is applied to two designs both having a level of 30 dBm coupled to the IC through PCB (printed circuit board) traces, and the PCB (printed circuit board) traces are properly modeled.

[0077] ● 30 dBm is injected differentially to generate a high amplitude level across the switch. High enough to have a negative oscillation in order to test Figure 3 of the circuit and compare it.

[0078] ● 40 points are considered per decade in the range of [150 kHz; 1 GHz] to cover as many frequencies and resonances as possible.

[0079] ● 2000 cycles are simulated for each frequency to ensure that a steady state has been reached.

[0080] ● Give the battery the lowest value that the battery can take for the voltage of the battery pack battery (represented by a voltage source in Figure 4 ), and this lowest value is about 2V, so that the oscillation across the switch can become negative (below 0V).

[0081] ● Calculate the DC value of the oscillation across the switch and average it over the last 50 cycles of the simulation. Then, calculate and compare the difference between this quantity and the battery voltage (2V).

[0082] Figure 5 Show the results of the test. The first curve (shown as a dotted line) 560 is the DC value of the oscillation generated by the switch of the circuit across Figure 3 minus the battery voltage (2V). The second curve (shown as a dashed line) 561 is the DC shift value generated by the oscillation of the switch of the circuit across Figure 2 minus the battery voltage (2V). As can be seen, the DC shifts of the two circuits are quite comparable, which means that the same result can be achieved by using only one MOSFET in Figure 3 , rather than multiplying the area by 4 by using a back-to-back circuit such as the circuit in Figure 2 . In addition, at 1.125 MHz, both circuits fail due to the extremely high injection level. In most of the rest of the frequency range, the DC shifts match. In fact, starting from 100 MHz, Figure 3 the circuit does not fail, while Figure 2 the DC shift of the circuit reaches an extremely high value.

[0083] Return to Figure 3 , the first balancing resistor 322 is connected in series between the first battery pack connection terminal (CBH) 306 and the first battery pack terminal of the battery pack battery 308. And, the second balancing resistor 323 is connected in series between the second battery pack connection terminal (CBL) 307 and the second battery pack terminal of the battery pack battery 308. Therefore, the example disclosed herein relates to a BMS, which includes:

[0084] ● Any of the switch circuits disclosed herein;

[0085] ● The battery pack battery 308, which has a first battery pack terminal and a second battery pack terminal;

[0086] ● The first balancing resistor 322, which is connected in series between the first battery pack connection terminal (CBH) 306 and the first battery pack terminal; and

[0087] ● A second balancing resistor 323, the second balancing resistor 323 being serially connected between a second battery pack connection terminal (CBL) 307 and a second battery pack terminal.

[0088] Advantages associated with the switch circuits disclosed herein may include one or more of the following:

[0089] ● Reduction in area on an integrated circuit, the area reduction being up to 1 mm 2 .

[0090] ● The leakage of the switch circuits disclosed herein may be equivalent to a back-to-back switch implementation.

[0091] ● A drive configuration capable of setting the gate of a single cell balancing MOS switch to the lowest transient voltage (drain or source) in order to keep the switch off and prevent the switch from causing any DC shift across the entire DPI frequency range [e.g., 150 kHz; 1 GHz], even if the drive configuration includes a bandwidth-limited hysteresis amplifier.

[0092] ● Improved electromagnetic compatibility (EMC) with very little IC area cost.

[0093] ● Lower DC shift at high frequencies (>100 MHz) when compared to a back-to-back solution.

[0094] ● Improved accuracy measurement in a highly EMI-polluted environment with very little IC area cost.

[0095] Advantageously, one or more of the embodiments disclosed herein include connecting the body of a single MOS switch to a first portion of its source through a high-value biasing resistor (e.g., a few megaohms) in order to benefit from the back-to-back body-to-source and body-to-drain diodes across the battery pack cells. As a result, rectification (DC shift) that would compromise battery measurement accuracy may be reduced or eliminated. However, if EMI is present and a negative transient voltage crosses the MOS switch, it may briefly turn on and conduct current, thus generating rectification (DC shift) if its gate is not tied to the lowest potential (source or drain) in order to keep it off during this event. To this end, a second portion of the embodiments disclosed herein relates to a drive configuration that can tightly tie the gate of a single MOS switch to the lowest transient voltage of the source and drain across the entire direct power injection (DPI) frequency range (150 kHz; 1 GHz). In this way, the examples described herein may be able to prevent DC shift in a highly EMI-polluted environment for more accurate measurements. This can achieve the level of a back-to-back solution without resulting in a significant increase in area and cost.

[0096] Any of the switching circuits disclosed herein can be used in a battery pack battery controller (BCC) and a battery pack management system (BMS), especially in an EMI-polluted environment, such as may be the case in an electric vehicle.

[0097] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above schema can be executed in any order. Moreover, those skilled in the art will recognize that although an example instruction set / method has been discussed, the materials in this specification can be combined in many ways to yield other examples as well, and should be understood within the context provided in this detailed description.

[0098] In some example embodiments, the instruction set / method steps described above are implemented as functions and software instructions embodied in an executable instruction set, which is implemented on a computer or a machine programmed and controlled by the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor can refer to a single component or multiple components.

[0099] In other examples, the instruction set / method shown herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture can refer to any single component or multiple components that are manufactured. As defined herein, non-transitory machine or computer-usable media do not include signals, but such media may be capable of receiving and processing information from signals and / or other transient media.

[0100] Example embodiments of the materials discussed in this specification can be implemented, in whole or in part, via a network, a computer, or data-based devices and / or services. These can include the cloud, the Internet, an intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As used herein and in the claims, the following non-exclusive definitions are provided.

[0101] In one example, one or more of the instructions or steps discussed herein are automated. The term automated or automatically (and its similar variants) means using a computer and / or a mechanical / electrical device to control the operation of a device, system, and / or process without human intervention, observation, effort, and / or decision-making.

[0102] It should be understood that any components that are alleged to be coupled can be coupled or connected directly or indirectly. In the case of indirect coupling, additional components can be placed between the two components that are said to be coupled.

[0103] In this specification, example embodiments have been presented with a selected set of details. However, those of ordinary skill in the art will understand that many other example embodiments can be practiced with different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A switching circuit for battery balancing in a battery management system BMS, characterized in that: The switch circuit comprises: A first battery pack connection terminal, used to connect to a first battery pack terminal; A second battery pack connection terminal, used to connect to a second battery pack terminal; Cell balancing field effect transistor FET, including: Gate terminal; A drain terminal connected to the first battery pack connection terminal; a source terminal, configured to be connected to the second battery pack connection terminal; and Subject end; a gate control circuit configured to connect the gate terminal of the cell balancing FET to a battery pack connection terminal having a lowest voltage; and A bias resistor is connected in series between the body terminal of the cell balancing FET and one of the first battery pack connection terminal and the second battery pack connection terminal.

2. The switch circuit according to claim 1, characterized in that: The bias resistor is connected in series between the body terminal of the cell balancing FET and the second battery pack connection terminal.

3. The switch circuit according to claim 1 or claim 2, characterized in that: The bias resistor has a resistance value of approximately several megohms.

4. A switching circuit according to any one of the preceding claims, characterised in that The cell balancing FET is the only FET connected between the first battery pack connection terminal and the second battery pack connection terminal.

5. A switching circuit according to any one of the preceding claims, characterised in that: The FET control circuit comprises: The lowest powered node; and A gate pull-down switch is connected between the lowest supply node and the gate terminal of the cell balancing FET.

6. The switch circuit according to claim 5, characterized in that: The FET control circuit comprises: a first battery pack connection switch connected between the first battery pack connection terminal and the lowest power supply node; a second battery pack connection switch connected between the second battery pack connection terminal and the lowest power supply node; and LOS node control circuit, the LOS node control circuit is configured to: When the voltage level at the first battery pack connection terminal is lower than the voltage level at the second battery pack connection terminal, closing the first battery pack connection switch and opening the second battery pack connection switch; and When the voltage level at the first battery pack connection terminal is higher than the voltage level at the second battery pack connection terminal, the first battery pack connection switch is opened and the second battery pack connection switch is closed.

7. The switch circuit according to claim 6, characterized in that: The LOS node control circuit comprises: An amplifier, the amplifier being configured to: comparing the voltage level at the first battery pack connection terminal with the voltage level at the second battery pack connection terminal; providing a first amplifier output signal to a control terminal of the first battery pack connection switch so as to: i) close the first battery pack connection switch when the voltage level at the first battery pack connection terminal is lower than the voltage level at the second battery pack connection terminal; and ii) open the first battery pack connection switch when the voltage level at the first battery pack connection terminal is higher than the voltage level at the second battery pack connection terminal; and The second amplifier output signal is provided to the control terminal of the second battery pack connection switch so as to: i) open the second battery pack connection switch when the voltage level at the first battery pack connection terminal is lower than the voltage level at the second battery pack connection terminal; and ii) close the second battery pack connection switch when the voltage level at the first battery pack connection terminal is higher than the voltage level at the second battery pack connection terminal.

8. The switch circuit according to claim 7, characterized in that: The amplifier is a hysteresis amplifier.

9. The switch circuit according to claim 7 or claim 8, characterized in that: The FET control circuit further comprises: a first capacitor connected in series between the control terminal of the first battery pack connection switch and the second battery pack connection terminal; and A second capacitor is connected in series between the control terminal of the second battery group connecting switch and the first battery group connecting terminal.

10. A battery management system BMS, characterized in that: include: A switching circuit according to any preceding claim; a battery cell having a first battery end and a second battery end; a first balancing resistor connected in series between the first battery group connection terminal and the first battery group terminal; as well as A second balancing resistor is connected in series between the second battery group connection terminal and the second battery group terminal.

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