A control circuit applied to reducing standby power consumption and improving the power supply load regulation rate

Abstract

The present invention relates to a control circuit applied to reducing standby power consumption and improving the power load regulation rate. The present invention includes a clock signal circuit for generating a clock signal with a fixed frequency; a CLK clock counting circuit connected to the clock signal circuit for counting the clock signal to obtain the off-time of the main power transistor inside the system; a PWM period counting circuit connected to the CLK clock counting circuit for outputting a control signal based on the change trend of the off-time and when a pre-designed counting condition is met; a discharge resistor control circuit whose input end is connected to the output end of the PWM period counting circuit, including a connected discharge MOS transistor and a resistor control loop, and the resistor control loop includes a discharge resistor; an FB sampling circuit connected to the discharge resistor control circuit for detecting the sampled voltage at the output end and controlling the PWM period of the main power transistor drive according to the sampled voltage. The present invention improves the stability and reliability of the power supply.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a control circuit applied to reduce standby power consumption and improve the power load regulation rate. Background Art

[0002] Due to its advantages such as high efficiency and small volume, switching power supplies are widely used in various electronic devices. The load regulation rate is one of the important indicators to measure the performance of a switching power supply, which reflects the stability of the output voltage when the load changes. During the switching process from no-load to full-load, due to the sudden change of the load, the output voltage is prone to large fluctuations, affecting the normal operation of the device. Especially in the application environment of a 5V output non-isolated buck step-down type, the 5V output voltage directly supplies power to the MCU. Non-isolated power supplies are mainly used in the small household appliance field, where the cost requirement for the solution is extremely high. The input voltage limit range of the mainstream domestic MCUs is relatively small, usually with an input voltage upper limit of 5.5V. If the output voltage fluctuation exceeds 5.5V, there will be extremely high input voltage stress on the MCU, with the risk and potential hazard of breaking down the power supply pin of the MCU.

[0003] Traditional methods for improving the load regulation rate mainly focus on optimizing control loop parameters, increasing output capacitors, etc., but these methods have the following deficiencies:

[0004] Limited optimization of control loop parameters: Optimizing control loop parameters requires a trade-off between stability and dynamic response, and it is difficult to meet the performance requirements under both no-load and full-load conditions simultaneously.

[0005] High cost of increasing output capacitors: Increasing output capacitors can slow down the output voltage fluctuation, but it will increase the cost and volume, and the effect of suppressing high-frequency ripple is limited. Summary of the Invention

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the prior art, which can effectively reduce the load regulation rate of the switching power supply during the switching process from no-load to full-load, reduce the output voltage fluctuation, and improve the stability and reliability of the power supply.

[0007] To solve the above technical problem, the present invention provides a control circuit applied to reduce standby power consumption and improve the power load regulation rate, including a power management chip, and the power management chip includes:

[0008] A clock signal circuit for generating a clock signal with a fixed frequency;

[0009] A CLK clock counting circuit connected to the clock signal circuit for counting the clock signal to obtain the turn-off time of the main power transistor inside the system;

[0010] A PWM period counting circuit, connected to the CLK clock counting circuit, is configured to output a control signal based on the changing trend of the turn-off time and when a preset counting condition is met;

[0011] A discharge resistor control circuit, whose input terminal is connected to the output terminal of the PWM period counting circuit, includes a connected discharge MOS transistor Q3 and a resistor control loop, and the resistor control loop includes a discharge resistor R1;

[0012] An FB sampling circuit, connected to the discharge resistor control circuit, is configured to detect the sampling voltage at the output terminal and control the PWM period of the main power transistor drive according to the sampling voltage;

[0013] Wherein, the discharge resistor control circuit can dynamically control the conduction or turn-off of the discharge MOS transistor Q3 according to the control signal to realize the connection or disconnection of the discharge resistor in the resistor control loop, thereby adjusting the RC time constant in the FB sampling circuit.

[0014] In an embodiment of the present invention, the resistor control loop further includes a first voltage-dividing resistor R2 and a second voltage-dividing resistor R3;

[0015] The gate of the discharge MOS transistor Q3 is connected to the output terminal of the PWM period counting circuit;

[0016] The drain of the discharge MOS transistor Q3 is connected to one end of the first voltage-dividing resistor R2, the other end of the first voltage-dividing resistor R2 is respectively connected to the FB sampling circuit and one end of the second voltage-dividing resistor R3, and the other end of the second voltage-dividing resistor R3 is grounded;

[0017] The source of the discharge MOS transistor Q3 is connected to one end of the discharge resistor R1, and the other end of the discharge resistor R1 is grounded.

[0018] In an embodiment of the present invention, it further includes a first diode D1 and a second capacitor C2;

[0019] The positive electrode of the first diode D1 is connected to the drain of the discharge MOS transistor Q3, and the negative electrode of the first diode D1 is connected to the voltage output terminal VOUT;

[0020] Both ends of the second capacitor C2 are respectively connected to the negative electrode of the first diode D1 and the ground.

[0021] In an embodiment of the present invention, it further includes a third capacitor C3, a second diode D2, a freewheeling inductor L1 and a fourth capacitor C4;

[0022] Both ends of the third capacitor C3 are connected between the live wire and the neutral wire;

[0023] The negative electrode of the second diode D2 is connected to the ground terminal, and the positive electrode of the second diode D2 is connected to the neutral wire;

[0024] One end of the freewheeling inductor L1 is connected to the ground terminal, and the other end of the freewheeling inductor L1 is respectively connected to the voltage output terminal VOUT and one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to the neutral line.

[0025] In an embodiment of the present invention, the clock signal circuit includes a first inverter U2, a first MOS transistor Q1, a second MOS transistor Q2, a comparator U8, and a first capacitor C1;

[0026] The drain of the first MOS transistor Q1 is connected to the current source;

[0027] The input terminal of the first inverter U2 is connected to the minimum turn-off time signal of the main power transistor, and the output terminal of the first inverter U2 is connected to the gate of the first MOS transistor Q1;

[0028] The source of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2 and the positive input terminal of the comparator U8, and the negative input terminal of the comparator U8 is connected to the reference voltage;

[0029] The source of the second MOS transistor Q2 is grounded;

[0030] One end of the first capacitor C1 is connected to the positive input terminal of the comparator U8, and the other end is grounded.

[0031] In an embodiment of the present invention, the CLK clock counting circuit includes an AND gate U9, a second inverter U10, a first frequency division counter, a first NAND gate U1A, a third inverter U7, and a fifth flip-flop U11;

[0032] The output terminal of the AND gate U9 is connected to the input terminal of the second inverter U10, and the output terminal of the second inverter U10 is connected to the input terminal of the first frequency division counter;

[0033] The first frequency division counter is a sixteen-frequency division counter, which includes a first D flip-flop U3, a second D flip-flop U4, a third D flip-flop U5, and a fourth D flip-flop U6 cascaded in sequence; the positive output terminals of the first D flip-flop U3, the third D flip-flop U5, and the fourth D flip-flop U6 are respectively connected to the input terminals of the first NAND gate U1A; the reverse output terminals of the first D flip-flop U3, the second D flip-flop U4, the third D flip-flop U5, and the fourth D flip-flop U6 are connected to their own data input terminals;

[0034] The output terminal of the comparator U8 and the gate of the second MOS transistor Q2 are both connected to the first input terminal of the AND gate U9;

[0035] The output terminal of the first NAND gate U1A is respectively connected to the second input terminal of the AND gate U9 and the input terminal of the third inverter U7;

[0036] The output terminal of the third inverter U7 is connected to the data input terminal of the fifth flip-flop U11, and the clock input terminal of the fifth flip-flop U11 is connected to the drive signal of the main power transistor.

[0037] In an embodiment of the present invention, the PWM period counting circuit includes a first PWM period counter and a second PWM period counter;

[0038] The first PWM period counter includes a second NAND gate U14B, a fourth inverter U15, a second frequency division counter, a sixth D flip-flop U12; a fifth inverter U13;

[0039] Among them, the output terminal of the second NAND gate U14B is connected to the input terminal of the fourth inverter U15, and the output terminal of the fourth inverter U15 is connected to the input terminal of the second frequency division counter;

[0040] The second frequency division counter is a sixteen-frequency division counter, including four cascaded sixth D flip-flops U12;

[0041] The positive output terminal of the fifth D flip-flop U11 is connected to the set terminals of each of the sixth D flip-flops U12; the output terminal of the second frequency division counter is connected to the input terminal of the fifth inverter U13;

[0042] The output terminal of the fifth inverter U13 is connected to the first input terminal of the second NAND gate U14B, and the second input terminal of the second NAND gate U14B is connected to the drive signal of the main power transistor;

[0043] The second PWM period counter includes a third frequency division counter, a sixth inverter U17, a seventh inverter U19, a third NAND gate U14A, a seventh D flip-flop U16;

[0044] Among them, the third frequency division counter is a sixteen-frequency division counter, including four cascaded seventh D flip-flops U16; the output terminal of the fifth inverter U13 is connected to the set terminals of each of the seventh D flip-flops U12;

[0045] The output terminal of the third frequency division counter is connected to the input terminal of the sixth inverter U17;

[0046] The output terminal of the third NAND gate U14A is connected to the input terminal of the seventh inverter U19, and the output terminal of the seventh inverter U19 is connected to the input terminal of the second frequency division counter;

[0047] The output terminal of the sixth inverter U17 is connected to the first input terminal of the third NAND gate U14A, and the second input terminal of the third NAND gate U14A is connected to the drive signal of the main power transistor.

[0048] In an embodiment of the present invention, it further includes a seventh inverter U18;

[0049] The output terminal of the sixth inverter U17 is connected to the input terminal of the seventh inverter U18, and the output terminal of the seventh inverter U18 is connected to the gate of the discharge MOS transistor Q3.

[0050] The above technical solution of the present invention has the following advantages compared with the prior art:

[0051] A control circuit applied to reducing standby power consumption and improving the power load regulation rate of the present invention can improve the load regulation rate of the switching power supply during the no-load to full-load switching. By detecting the turn-off time Toff of the switching power supply and judging the system load state (decrease or increase) according to the change trend (become larger or smaller) of the turn-off time Toff, the access and disconnection of the discharge resistor control circuit (discharge resistor) are dynamically adjusted according to the load state; the PMW drive signal is controlled according to the voltage parameter adjusted by the FB (feedback) sampling circuit, and the main power transistor of the switching power supply is controlled. By real-time monitoring the load state and dynamically adjusting the discharge resistor R1 inside the power management chip by using the discharge resistor control circuit, the RC time constant across the FB capacitor in the FB sampling circuit can be adjusted, which can effectively reduce the load regulation rate of the switching power supply during the no-load to full-load switching process, reduce the output voltage fluctuation, not only improve the stability and reliability of the power supply, but also reduce the standby power consumption of the system, meeting the required energy efficiency level requirements. Description of the Drawings

[0052] In order to make the content of the present invention easier to be clearly understood, the present invention will be further described in detail below according to the specific embodiments of the present invention in conjunction with the drawings.

[0053] Figure 1 It is the overall structure diagram of the control circuit of the present invention applied to reducing standby power consumption and improving the power load regulation rate.

[0054] Figure 2 It is the internal structure diagram of the power management chip of the control circuit of the present invention applied to reducing standby power consumption and improving the power load regulation rate.

[0055] Figure 3 It is the working flow chart of the control circuit of the present invention applied to reducing standby power consumption and improving the power load regulation rate.

[0056] Figure 4 It is the simulation diagram when the system load changes from large to small when the discharge resistor control circuit is connected to the system.

[0057] Figure 5 It is the simulation diagram when the system load changes from small to large when the discharge resistor control circuit is connected to the system.

[0058] Figure 6 It is the simulation waveform diagram of the output voltage when the system switches from no-load to loaded when the discharge resistor control circuit is connected to the system.

[0059] Figure 7 It is the output voltage waveform when the system switches from no-load to load with the discharge resistor control circuit not connected to the system. Specific embodiments

[0060] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the embodiments cited are not intended to limit the present invention.

[0061] In the present invention, if there is a description of directions (up, down, left, right, front and back), it is only for the convenience of describing the technical solution of the present invention, rather than indicating or implying that the technical features referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0062] In the present invention, the meaning of "several" is one or more, the meaning of "multiple" is two or more, and "greater than", "less than", "exceeding", etc. are understood not to include the present number; "above", "below", "within", etc. are understood to include the present number. In the description of the present invention, if there is a description of "first" and "second", it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0063] In the present invention, unless otherwise clearly defined, terms such as "set", "installed", "connected", etc. should be understood in a broad sense. For example, they can be directly connected, or indirectly connected through an intermediate medium; they can be fixedly connected, or detachably connected, and can also be integrally formed; they can be mechanically connected, or electrically connected or capable of communicating with each other; they can be the communication inside two components or the interaction relationship between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in the present invention in combination with the specific content of the technical solution.

[0064] Refer to Figures 1 to 3 As shown, a control circuit for reducing standby power consumption and improving the power load regulation rate of the present invention includes a power management chip, and the power management chip includes:

[0065] An (OSC) clock signal circuit for generating a (CLK) clock signal with a fixed frequency;

[0066] A CLK clock counting circuit connected to the clock signal circuit for counting the clock signal to obtain the turn-off time (Toff) of the main power transistor inside the system;

[0067] The PWM period counting circuit, as a delay circuit, is connected to the CLK clock counting circuit and is used to output a control signal based on the change trend of the turn-off time and when a preset counting condition is met;

[0068] The discharge resistor control circuit, whose input end is connected to the output end of the PWM period counting circuit, includes a connected discharge MOS transistor Q3 and a resistor control loop, and the resistor control loop includes a discharge resistor R1;

[0069] The FB sampling circuit is connected to the discharge resistor control circuit and is used to detect the sampling voltage at the output end and control the PWM period of the main power transistor drive according to the sampling voltage;

[0070] Wherein, the discharge resistor control circuit can dynamically control the conduction or turn-off of the discharge MOS transistor Q3 according to the control signal to realize the access or disconnection of the discharge resistor in the resistor control loop, thereby adjusting the RC time constant in the FB sampling circuit.

[0071] Through the above settings, the load regulation rate of the switching power supply during no-load to full-load switching can be improved. By detecting the turn-off time Toff of the switching power supply and judging the system load state (decrease or increase) according to the change trend (become larger or smaller) of the turn-off time Toff, the access and disconnection of the discharge resistor control circuit (discharge resistor) are dynamically adjusted according to the load state; the PMW drive signal is controlled according to the voltage parameter adjusted by the FB (feedback) sampling circuit to control the main power transistor of the switching power supply.

[0072] By real-time monitoring the load state and using the discharge resistor control circuit to dynamically adjust the discharge resistor R1 inside the power management chip to adjust the RC time constant across the FB capacitor in the FB sampling circuit, the load regulation rate during the no-load to full-load switching process of the switching power supply can be effectively reduced, and the output voltage fluctuation can be reduced. It can not only improve the stability and reliability of the power supply, but also reduce the standby power consumption of the system and meet the required energy efficiency level requirements.

[0073] In one embodiment,

[0074] The resistor control loop further includes a first voltage-dividing resistor R2 and a second voltage-dividing resistor R3;

[0075] The gate of the discharge MOS transistor Q3 is connected to the output end of the PWM period counting circuit;

[0076] The drain of the discharge MOS transistor Q3 is connected to one end of the first voltage-dividing resistor R2, the other end of the first voltage-dividing resistor R2 is respectively connected to the FB sampling circuit and one end of the second voltage-dividing resistor R3, and the other end of the second voltage-dividing resistor R3 is grounded;

[0077] The source of the discharge MOS transistor Q3 is connected to one end of the discharge resistor R1, and the other end of the discharge resistor R1 is grounded.

[0078] Refer to Figure 2 As shown, the drain of the discharge MOS transistor Q3, one end of the first voltage-dividing resistor R2, and the negative electrode of the first diode D1 are all connected to the FB (feedback) pin of the power management chip.

[0079] In one embodiment, it further includes a first diode D1 and a second capacitor C2;

[0080] The positive electrode of the first diode D1 is connected to the drain of the discharge MOS transistor Q3, and the negative electrode of the first diode D1 is connected to the voltage output terminal VOUT;

[0081] Both ends of the second capacitor C2 are respectively connected to the negative electrode of the first diode D1 and the ground.

[0082] It should be noted that the second capacitor C2, as a filter capacitor outside the chip, plays a role in stabilizing the FB voltage.

[0083] It can be understood that the main power transistor inside the system is encapsulated between the second capacitor C2 and the DRAIN pin of the power management chip (not shown in the figure), corresponding to the drain and source of the main power transistor MOS.

[0084] In one embodiment, it further includes a third capacitor C3, a second diode D2, a freewheeling inductor L1, and a fourth capacitor C4;

[0085] Both ends of the third capacitor C3 are connected between the live wire (L) and the neutral wire (N);

[0086] The negative electrode of the second diode D2 is connected to the ground terminal, and the positive electrode of the second diode D2 is connected to the neutral wire;

[0087] One end of the freewheeling inductor L1 is connected to the ground terminal, the other end of the freewheeling inductor L1 is respectively connected to the voltage output terminal VOUT and one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to the neutral wire.

[0088] In one embodiment, the clock signal circuit includes a first inverter U2, a first MOS transistor Q1, a second MOS transistor Q2, a comparator U8, and a first capacitor C1;

[0089] The drain of the first MOS transistor Q1 is connected to the current source (live wire L);

[0090] The input terminal of the first inverter U2 is connected to the main power transistor minimum turn-off time signal (toffmin), and the output terminal of the first inverter U2 is connected to the gate of the first MOS transistor Q1;

[0091] The source of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2 and the positive input terminal of the comparator U8, and the negative input terminal of the comparator U8 is connected to a reference voltage;

[0092] The source of the second MOS transistor Q2 is grounded;

[0093] One end of the first capacitor C1 is connected to the positive input terminal of the comparator U8, and the other end is grounded.

[0094] In one embodiment, the CLK clock counting circuit includes an AND gate U9, a second inverter U10, a first frequency division counter, a first NAND gate U1A, a third inverter U7, and a fifth flip-flop U11;

[0095] The output terminal of the AND gate U9 is connected to the input terminal of the second inverter U10, and the output terminal of the second inverter U10 is connected to the input terminal of the first frequency division counter;

[0096] The first frequency division counter is a sixteen-frequency division counter, which includes a first D flip-flop U3, a second D flip-flop U4, a third D flip-flop U5, and a fourth D flip-flop U6 connected in cascade in sequence; the positive output terminals of the first D flip-flop U3, the third D flip-flop U5, and the fourth D flip-flop U6 are respectively connected to the input terminals of the first NAND gate U1A; the inverted output terminals of the first D flip-flop U3, the second D flip-flop U4, the third D flip-flop U5, and the fourth D flip-flop U6 are connected to their own data input terminals;

[0097] The output terminal of the comparator U8 and the gate of the second MOS transistor Q2 are both connected to the first input terminal of the AND gate U9;

[0098] The output terminal of the first NAND gate U1A is respectively connected to the second input terminal of the AND gate U9 and the input terminal of the third inverter U7;

[0099] The output terminal of the third inverter U7 is connected to the data input terminal of the fifth flip-flop U11, and the clock input terminal of the fifth flip-flop U11 is connected to the drive signal (PWM) of the main power transistor.

[0100] In one embodiment, the PWM cycle counting circuit includes a first PWM cycle counter and a second PWM cycle counter;

[0101] The first PWM cycle counter includes a second NAND gate U14B, a fourth inverter U15, a second frequency division counter, a sixth D flip-flop U12, and a fifth inverter U13;

[0102] Among them, the output terminal of the second NAND gate U14B is connected to the input terminal of the fourth inverter U15, and the output terminal of the fourth inverter U15 is connected to the input terminal of the second frequency division counter;

[0103] The second frequency divider counter is a sixteen-frequency divider counter, including four sixth D flip-flops U12 cascaded in sequence;

[0104] The positive output terminal of the fifth D flip-flop U11 is connected to the set terminals of each sixth D flip-flop U12; the output terminal of the second frequency divider counter is connected to the input terminal of the fifth inverter U13;

[0105] The output terminal of the fifth inverter U13 is connected to the first input terminal of the second NAND gate U14B, and the second input terminal of the second NAND gate U14B is connected to the drive signal (PWM) of the main power transistor;

[0106] The second PWM period counter includes a third frequency divider counter, a sixth inverter U17, a seventh inverter U19, a third NAND gate U14A, and a seventh D flip-flop U16;

[0107] Among them, the third frequency divider counter is a sixteen-frequency divider counter, including four seventh D flip-flops U16 cascaded in sequence; the output terminal of the fifth inverter U13 is connected to the set terminals of each seventh D flip-flop U12;

[0108] The output terminal of the third frequency divider counter is connected to the input terminal of the sixth inverter U17;

[0109] The output terminal of the third NAND gate U14A is connected to the input terminal of the seventh inverter U19, and the output terminal of the seventh inverter U19 is connected to the input terminal of the second frequency divider counter;

[0110] The output terminal of the sixth inverter U17 is connected to the first input terminal of the third NAND gate U14A, and the second input terminal of the third NAND gate U14A is connected to the drive signal (PWM) of the main power transistor.

[0111] In one embodiment, it further includes a seventh inverter U18;

[0112] The output terminal of the sixth inverter U17 is connected to the input terminal of the seventh inverter U18, and the output terminal of the seventh inverter U18 is connected to the gate of the discharge MOS transistor Q3.

[0113] Referring to Figure 4 、 Figure 5 as shown, the working principle of the present invention is as follows:

[0114] When the load of the switching power supply changes, the output load current starts to decrease (i.e., the current of the freewheeling inductor L1 starts to decrease), and the turn-off time (Toff) of the main power transistor inside the system increases accordingly. At this time, the number of CLK clock signals generated by the clock signal circuit starts to increase, and the 16-frequency divider counter composed of the first D flip-flop U3, the second D flip-flop U4, the third D flip-flop U5, and the fourth D flip-flop U6 starts to count, and starts to count the CLK clock signals.

[0115] When the cumulative count value of the CLK clock signal is greater than 13, the drive signal (PWM) of the main power transistor will make the enable signal Reset level of the first PWM period counter high, and the first PWM period counter starts to count. When the PWM count period is greater than 8, the Ctrl control signal flips from high level to low level, disconnecting the discharge MOS transistor Q3 and the discharge resistor R1. The resistance at the FB terminal changes from R1 / (R2 + R3) to R2 + R3, and the voltage across the second C2 capacitor is approximately equal to the output voltage. According to the capacitor discharge formula at both ends:

[0116] ,

[0117] In the formula:

[0118] V(t) represents the voltage across the capacitor at any moment; represents the initial voltage across the input capacitor after power-off; is the natural constant; R represents the equivalent resistance of the discharge circuit; C represents the capacitance value of the capacitor; t represents the capacitor discharge time.

[0119] According to the above discharge formula, it can be obtained that when the equivalent resistance R of the discharge circuit increases, the voltage drop rate of V(t) slows down. Similarly, the voltage across the second voltage-dividing resistor R3 is derived from V(t), and the voltage across the second voltage-dividing resistor R3 also decreases slowly. The internal FB sampling circuit of the chip detects that the voltage across the second voltage-dividing resistor R3 decreases slowly, thereby lengthening the PWM period and reducing the output voltage of the system. At the same time, since the equivalent resistance R of the discharge circuit becomes larger, the current loss in the standby state of the system can be effectively reduced, achieving the effect of reducing standby power consumption.

[0120] Conversely, when the system load increases, the output load current starts to increase (i.e., the current of the flyback inductor L1 starts to increase), and the turn-off time (Toff) of the main power transistor inside the system starts to decrease. At this time, the number of CLK clock signals generated by the clock signal circuit starts to decrease, and the 16-frequency divider counter composed of the first D flip-flop U3, the second D flip-flop U4, the third D flip-flop U5, and the fourth D flip-flop U6 starts to count and work, starting to count the CLK clock signal.

[0121] When the cumulative count value of the CLK clock signal is less than 12, the drive signal (PWM) of the main power transistor makes the enable signal Reset level of the first PWM period counter low for reset. The second PWM period counter starts to count. When the PWM count period is greater than 8, the Ctrl control signal flips from low level to high level, and the MOS transistor Q3 conducts, connecting the discharge resistor R1 to the circuit. The equivalent discharge resistance at both ends of the FB capacitor (the second capacitor C2) becomes smaller, and the internal FB sampling circuit of the chip detects that the voltage drop rate at both ends of the second voltage dividing resistor R3 accelerates, thereby shortening the PWM period and increasing the output voltage.

[0122] When the above discharge resistor control circuit is connected to the system, when the system switches from no-load to loaded, the output voltage drops from 5.188V to 5.08V, and the voltage change amount , referring to Figure 6 the output voltage simulation waveform, the load regulation rate is: 2.08%.

[0123] When the discharge resistor control circuit of the present invention is not connected to the system, when the system switches from no-load to loaded, the output voltage drops from 5.55V to 5.18V, and the voltage change amount , referring to Figure 7 the output voltage simulation waveform, the load regulation rate is 6.73%.

[0124] From the comparison of the above data, it can be seen that the control circuit of the present invention can not only significantly reduce the load regulation rate of the 5V buck power supply (that is, the output voltage volatility from no-load to full-load drops from 6.73% to 2.08%), but also effectively reduce the standby power consumption of the system, further improving the overall performance and market competitiveness of the non-isolated chip solution.

[0125] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and are not restrictive. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A control circuit applied to reduce standby power consumption and improve the power load regulation rate, characterized in that including a power management chip, the power management chip comprising: a clock signal circuit for generating a clock signal with a fixed frequency; a CLK clock counting circuit connected to the clock signal circuit for counting the clock signal to obtain the off-time of the main power transistor inside the system; a PWM period counting circuit connected to the CLK clock counting circuit for outputting a control signal based on the changing trend of the off-time and when a preset counting condition is met; a discharge resistor control circuit, whose input end is connected to the output end of the PWM period counting circuit, including a connected discharge MOS transistor Q3 and a resistor control loop, and the resistor control loop includes a discharge resistor R1; an FB sampling circuit connected to the discharge resistor control circuit for detecting the sampling voltage at the output end and controlling the PWM period of the main power transistor drive according to the sampling voltage; wherein, the discharge resistor control circuit can dynamically control the on or off of the discharge MOS transistor Q3 according to the control signal to realize the connection or disconnection of the discharge resistor in the resistor control loop, thereby adjusting the RC time constant in the FB sampling circuit.

2. The control circuit according to claim 1, which is applied to reducing standby power consumption and improving power supply load regulation rate, is characterized in that The resistor control loop further includes a first voltage-dividing resistor R2 and a second voltage-dividing resistor R3; The gate of the discharge MOS transistor Q3 is connected to the output end of the PWM period counting circuit; The drain of the discharge MOS transistor Q3 is connected to one end of the first voltage-dividing resistor R2, the other end of the first voltage-dividing resistor R2 is respectively connected to the FB sampling circuit and one end of the second voltage-dividing resistor R3, and the other end of the second voltage-dividing resistor R3 is grounded; The source of the discharge MOS transistor Q3 is connected to one end of the discharge resistor R1, and the other end of the discharge resistor R1 is grounded.

3. The control circuit for reducing standby power consumption and improving power supply load regulation rate according to claim 2, wherein, It further includes a first diode D1 and a second capacitor C2; The positive electrode of the first diode D1 is connected to the drain of the discharge MOS transistor Q3, and the negative electrode of the first diode D1 is connected to the voltage output terminal VOUT; Both ends of the second capacitor C2 are respectively connected to the negative electrode of the first diode D1 and grounded.

4. A control circuit applied to reducing standby power consumption and improving power supply load regulation rate according to claim 3, characterized in that, It further includes a third capacitor C3, a second diode D2, a freewheeling inductor L1 and a fourth capacitor C4; Both ends of the third capacitor C3 are connected between the live wire and the neutral wire; The negative electrode of the second diode D2 is connected to the ground terminal, and the positive electrode of the second diode D2 is connected to the neutral wire; One end of the freewheeling inductor L1 is connected to the ground terminal, the other end of the freewheeling inductor L1 is respectively connected to the voltage output terminal VOUT and one end of the fourth capacitor C4, and the other end of the fourth capacitor C4 is connected to the neutral wire.

5. A control circuit for reducing standby power consumption and improving power supply load regulation rate according to claim 1, characterized in that, The clock signal circuit includes a first inverter U2, a first MOS transistor Q1, a second MOS transistor Q2, a comparator U8, and a first capacitor C1; The drain of the first MOS transistor Q1 is connected to a current source; The input end of the first inverter U2 is connected to the minimum off-time signal of the main power transistor, and the output end of the first inverter U2 is connected to the gate of the first MOS transistor Q1; The source of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2 and the positive input terminal of the comparator U8, and the negative input terminal of the comparator U8 is connected to a reference voltage; The source of the second MOS transistor Q2 is grounded; One end of the first capacitor C1 is connected to the positive input terminal of the comparator U8, and the other end is grounded.

6. The control circuit for reducing standby power consumption and improving power supply load regulation rate according to claim 5, wherein The CLK clock counting circuit includes an AND gate U9, a second inverter U10, a first frequency division counter, a first NAND gate U1A, a third inverter U7, and a fifth flip-flop U11; The output terminal of the AND gate U9 is connected to the input terminal of the second inverter U10, and the output terminal of the second inverter U10 is connected to the input terminal of the first frequency division counter; The first frequency division counter is a sixteen-frequency division counter, which includes a first D flip-flop U3, a second D flip-flop U4, a third D flip-flop U5, and a fourth D flip-flop U6 connected in cascade in sequence; The positive output terminals of the first D flip-flop U3, the third D flip-flop U5, and the fourth D flip-flop U6 are respectively connected to the input terminals of the first NAND gate U1A; the reverse output terminals of the first D flip-flop U3, the second D flip-flop U4, the third D flip-flop U5, and the fourth D flip-flop U6 are connected to their own data input terminals; The output terminal of the comparator U8 and the gate electrode of the second MOS transistor Q2 are both connected to the first input terminal of the AND gate U9; The output terminal of the first NAND gate U1A is respectively connected to the second input terminal of the AND gate U9 and the input terminal of the third inverter U7; The output terminal of the third inverter U7 is connected to the data input terminal of the fifth flip-flop U11, and the clock input terminal of the fifth flip-flop U11 is connected to the drive signal of the main power transistor.

7. The control circuit for reducing standby power consumption and improving power supply load regulation rate according to claim 6, wherein The PWM cycle counting circuit includes a first PWM cycle counter and a second PWM cycle counter; The first PWM cycle counter includes a second NAND gate U14B, a fourth inverter U15, a second frequency division counter, and a sixth D flip-flop U12; a fifth inverter U13; Among them, the output terminal of the second NAND gate U14B is connected to the input terminal of the fourth inverter U15, and the output terminal of the fourth inverter U15 is connected to the input terminal of the second frequency division counter; The second frequency division counter is a sixteen-frequency division counter, which includes four sixth D flip-flops U12 connected in cascade in sequence; The positive output terminal of the fifth D flip-flop U11 is connected to the set terminals of the respective sixth D flip-flops U12; the output terminal of the second frequency division counter is connected to the input terminal of the fifth inverter U13; The output terminal of the fifth inverter U13 is connected to the first input terminal of the second NAND gate U14B, and the second input terminal of the second NAND gate U14B is connected to the drive signal of the main power transistor; The second PWM cycle counter includes a third frequency division counter, a sixth inverter U17, a seventh inverter U19, a third NAND gate U14A, and a seventh D flip-flop U16; Among them, the third frequency division counter is a sixteen-frequency division counter, which includes four seventh D flip-flops U16 connected in cascade in sequence; the output terminal of the fifth inverter U13 is connected to the set terminals of the respective seventh D flip-flops U12; The output terminal of the third frequency division counter is connected to the input terminal of the sixth inverter U17; The output terminal of the third NAND gate U14A is connected to the input terminal of the seventh inverter U19, and the output terminal of the seventh inverter U19 is connected to the input terminal of the second frequency division counter; The output terminal of the sixth inverter U17 is connected to the first input terminal of the third NAND gate U14A, and the second input terminal of the third NAND gate U14A is connected to the drive signal of the main power transistor.

8. A control circuit applied to reducing standby power consumption and improving power supply load regulation rate according to claim 7, characterized in that, It further includes a seventh inverter U18; The output terminal of the sixth inverter U17 is connected to the input terminal of the seventh inverter U18, and the output terminal of the seventh inverter U18 is connected to the gate of the discharge MOS transistor Q3.

Images