SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter

Abstract

The invention relates to the technical field of power electronics, and particularly discloses a SiC MOSFETs crosstalk suppression active gate drive circuit based on a voltage inverter, aiming at a half-bridge converter formed by SiC MOSFETs, two suppression sub-circuits are designed for crosstalk suppression, each suppression sub-circuit comprises a voltage inverter formed by a P-channel MOSFET and an N-channel MOSFET, and the voltage inverter is connected with the voltage inverter. The circuit further comprises a working power supply, a capacitor Cvs, a capacitor Cvd, a resistor RP and a resistor RN. According to the invention, fewer active and passive auxiliary elements are used, and the active auxiliary elements do not need additional control signals, so that the circuit design and the element type selection are relatively simple. The active gate drive circuit designed by the invention has the characteristic of low static power loss, can be applied under the condition that an original drive circuit is not modified, and has the advantage of low invasiveness. According to the invention, the switching speed of SiC MOSFETs can be improved and the switching loss can be reduced while the crosstalk peak is effectively suppressed, so that the reliability and efficiency of the converter can be synchronously improved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and particularly to an active gate drive circuit for suppressing crosstalk of SiC MOSFETs based on a voltage inverter. Background Art

[0002] Compared with silicon-based devices, SiC MOSFETs have fast switching speeds and strong heat resistance, which are more conducive to the converter to achieve higher power density and efficiency. Therefore, they have greater application potential in many scenarios such as solar energy and motor drive.

[0003] In the field of power electronics, a half-bridge structure composed of two power devices is the basic unit of most converters. In the half-bridge structure, the turn-on / turn-off behavior of one device will affect its complementary device, resulting in overshoot and undershoot of the gate voltage of the complementary device. This phenomenon is called crosstalk. Due to the low threshold voltage of SiC MOSFETs and the weak tolerance of the maximum negative gate voltage, the upward overshoot may cause the device to be wrongly turned on, resulting in shoot-through short circuit of the bridge arm. This may significantly increase the switching loss of SiC MOSFETs, and may even cause the device to be overcurrent and overheat breakdown in severe cases. At the same time, the downward undershoot may shorten the service life of SiC MOSFETs, and a large enough undershoot may even cause overvoltage breakdown of the gate oxide layer. The crosstalk problem significantly reduces the reliability of SiC MOSFETs and poses a serious threat to the safe and reliable operation of the converter. Summary of the Invention

[0004] The present invention provides an active gate drive circuit for suppressing crosstalk of SiC MOSFETs based on a voltage inverter, and the technical problem to be solved is: how to improve the switching speed of the device while suppressing the crosstalk voltage of SiC MOSFETs.

[0005] To solve the above technical problems, the present invention provides an active gate drive circuit for suppressing crosstalk of SiC MOSFETs based on a voltage inverter, which is applicable to a half-bridge converter. The half-bridge converter is formed by connecting two SiC MOSFETs. The key lies in: the active gate drive circuit includes more than 2 suppression sub-circuits, and one of the suppression sub-circuits is connected between the drain, source and gate of each SiC MOSFET; the suppression sub-circuit includes a voltage inverter composed of a P-channel MOSFET and an N-channel MOSFET, and also includes a working power supply, capacitor C vs 、capacitor C vd 、resistor R P and resistor R N ,capacitor C vsOne end is connected to the drain of the SiC MOSFET, and the other end is connected to the gates of the P-channel MOSFET and the N-channel MOSFET. The drain of the P-channel MOSFET is connected to the working power supply, and the source of the P-channel MOSFET is connected to the resistor R P and then connected to the capacitor C vd at one end. The source of the N-channel MOSFET is connected to the source of the SiC MOSFET, and the drain of the N-channel MOSFET is connected to the resistor R N and then connected to the capacitor C vd at one end. The other end of the capacitor C vd is connected to the gate of the SiC MOSFET.

[0006] Preferably, in a half-bridge converter, the connection relationship between its two SiC MOSFETs S1 and S2 is as follows: the drain of S1 is connected to the bus voltage source, the source of S1 is connected to the drain of S2, and the source of S2 is grounded.

[0007] Preferably, the capacitor C vs has a value of (C ISSP +C ISSN )×V CC ×(V bus -V CC ), where V -1 is the bus power supply voltage, V bus is the working power supply voltage, C CC is the input capacitance of the P-channel auxiliary MOSFET, and C ISSP is the input capacitance of the N-channel auxiliary MOSFET. ISSN is the input capacitance of the N-channel auxiliary MOSFET.

[0008] Preferably, the capacitor C vd has a value of Q gd ×(λV CC ), where Q -1 is the Miller charge of S1 and S2, and λ is the exponential decay ratio. gd is the Miller charge of S1 and S2, and λ is the exponential decay ratio.

[0009] Preferably, the resistance values of the resistors R P2 and R N2 satisfy Q gd =Q on1 +Q on2 , where Q on1 , Q on2 are the total charges extracted by the capacitor C vd2 during the time periods t1–t2 and t2–t3 respectively. The capacitor C vd2 refers to the capacitor C vd connected to S2, and R P2 and R N2 refer to the resistors R P and RN ; P1 and N1 respectively represent the P-channel MOSFET and the N-channel MOSFET connected to S1, P2 and N2 respectively represent the P-channel MOSFET connected to S2 and the N-channel MOSFET connected to S2; t0, t1, t2, t3 are four consecutive moments during the turn-on process of S1. Before the moment of t0, the half-bridge converter operates in a steady state, P1 and N2 are in a fully-off state. t0 refers to the moment when S1 enters the Miller stage, t1 refers to the moment when the gate voltage v GSN2 of N2 reaches its threshold voltage V THN and the gate voltage v GSP1 of P1 reaches its threshold voltage –V THP and starts to conduct. t2 refers to the moment when the gate voltage of N2 rises to its Miller voltage V milN . t3 refers to the moment when the voltage v vd2 of the capacitor C Cvd2 drops to (1–λ)V CC . The resistors R P and R N connected to S1 are respectively represented as R P1 and R N1 , and there is R P1 =R P2 and R N1 =R N2 .

[0010] Preferably, Q on1 is equal to I vd2_on1 ·T1, I vd2_on1 represents the discharge current of the capacitor C vd2 during the time period from t1 to t2, and T1 represents the duration of the time period from t1 to t2; Q on2 is equal to I vd2_on2 ·T2, I vd2_on2 represents the discharge current of the capacitor C vd2 during the time period from t2 to t3, and T2 represents the duration of the time period from t2 to t3.

[0011] Preferably, I vd2_on1 is equal to [(R P2 +R N2 )·V C1 –R N2 ·V CC / (2R P2 ·R N2 ), V C1 represents the voltage of the capacitor C vd2 at the moment of t2, V C1 is equal to V CC –[g mN (V milN –V THN)T1] / (2C vd2 ), g mN represents the transconductance of N-channel MOSFET;

[0012] T1 is equal to [C ISSN (V milN -V THN )+C GDN ·V CC ] / I GSN2_on , I GSN2_on represents the gate current of N2 during the period t1–t2, C ISSN represents the input capacitance of N-channel MOSFET, C GDN Represents the gate-drain capacitance of an N-channel MOSFET;

[0013] I vd2_on2 Equal to I vd2_on1 +[R P2 -λ(R P2 +R N2 )]V CC / (2R P2 ·R N2 );

[0014] T2 is equal to [(V CC -V THP -V THN )·T on ] / V CC -T1, T on It represents the rising time of the drain voltage of S2 during the turning-on process of S1, which is the time length from time t0 to t4. t4 represents the time when N1 and P2 are completely turned off after time t3.

[0015] Preferably, the resistor R P2 and R N2 The resistance value satisfies Q gd =Q off1 +Q off2 , Q off1 , Q off2 The capacitance C in the time period t6-t7 and the time period t7-t8 are respectively vd2 The total charge pumped into the gate of S2, t5, t6, t7, t8 are the four moments in the process of S1 turning off, t5 refers to the time when v gs1 The moment when N1 and P2 start to conduct, t6 refers to the moment when the gate voltage of P2 drops from –V THP Down to –V milP The moment, V milP represents the Miller voltage of the P-channel MOSFET, and t8 refers to the time when the gate voltage of N2 drops to its threshold voltage V THN moment.

[0016] Preferably, Q off1 equals I vd2_off1 ·T3, where I vd2_off1 represents the current pumped into the gate node during the time period t6–t7, and T3 represents the duration of the time period t6–t7; Q vd2 equals I off2 ·T4, where I vd2_off2 represents the charging current during the time period t7–t8, and T4 represents the duration of the time period t7–t8. vd2_off2 vd2 vd2_off1 N2

[0017] Preferably, I vd2_off1 equals [R N2 ·V CC −V C2 (R P2 +R N2 )] / (2R P2 ·R N2 ), where V C2 represents the voltage of the capacitor C vd2 at the moment t7, and V C2 equals [g mP (V milP −V THP )T3] / (2C vd2 ), where g mP represents the transconductance of the P-channel MOSFET;

[0018] T3 equals [C ISSP (V milP −V THP ) + C GDP ·V CC / I GSP2_off , where I GSP2_off represents the gate current of P2 during the time period t6–t7, C ISSP represents the input capacitance of the P-channel MOSFET, and C GDP represents the gate-drain capacitance of the P-channel MOSFET;

[0019] I vd2_off2 equals I vd2_off1 +[R N2 −λ(R P2 +R N2 )]V CC / (2R P2 ·R N2 );

[0020] T4 equals [(V CC −V THP −V THN )·T off / VCC - T3, T off Indicates the fall time of the drain voltage of S2 during the turn-on process of S1, which is the time length from time t5 to t9. t9 represents the time when N2 and P1 are completely turned off after time t8.

[0021] The active gate drive circuit for crosstalk suppression of SiC MOSFETs based on a voltage inverter provided by the present invention is designed for a half-bridge converter composed of SiC MOSFETs. Two suppression sub-circuits are designed for crosstalk suppression. The suppression sub-circuit includes a voltage inverter composed of a P-channel MOSFET and an N-channel MOSFET, and also includes a working power supply, capacitor C vs 、capacitor C vd 、resistor R P and resistor R N . The present invention uses fewer active and passive auxiliary components, and the active auxiliary components do not require additional control signals. Therefore, the circuit design and component selection are relatively simple. The active gate drive circuit designed by the present invention has the characteristic of low static power loss, and can be applied without modifying the original drive circuit, with the advantage of low invasiveness. While effectively suppressing crosstalk spikes, the present invention can also improve the switching speed of SiC MOSFETs, reduce switching losses, and thus synchronously improve the reliability and efficiency of the converter. Description of the Drawings

[0022] Figure 1 is the circuit diagram of the active gate drive circuit provided by the embodiment of the present invention;

[0023] Figure 2 is the key waveform diagram of the active gate drive circuit provided by the embodiment of the present invention during the turn-on process;

[0024] Figure 3 is the key waveform diagram of the active gate drive circuit provided by the embodiment of the present invention during the turn-off process;

[0025] Figure 4 is the equivalent circuit diagram of the active gate drive circuit provided by the embodiment of the present invention in stage 1;

[0026] Figure 5 is the equivalent circuit diagram of the active gate drive circuit provided by the embodiment of the present invention in stage 2;

[0027] Figure 6 is the equivalent circuit diagram of the active gate drive circuit provided by the embodiment of the present invention in stage 3;

[0028] Figure 7 is the equivalent circuit diagram of the active gate drive circuit provided by the embodiment of the present invention in stage 4;

[0029] Figure 8It is the equivalent circuit diagram of the active gate drive circuit provided by the embodiment of the present invention in stage 5;

[0030] Figure 9 It is the equivalent circuit diagram of the active gate drive circuit provided by the embodiment of the present invention in stage 6;

[0031] Figure 10 It is the crosstalk voltage waveform diagram (500V / 20A) of the active gate drive circuit and the traditional gate drive provided by the embodiment of the present invention;

[0032] Figure 11 It is the drain-source voltage waveform diagram (500V / 20A) of the active gate drive circuit and the traditional gate drive provided by the embodiment of the present invention;

[0033] Figure 12 It is the crosstalk voltage waveform diagram (700V / 20A) of the active gate drive circuit and the traditional gate drive at a higher voltage level. Specific embodiments

[0034] The embodiments of the present invention will be specifically described below in conjunction with the accompanying drawings. The given embodiments are only for illustrative purposes and should not be construed as limiting the present invention. The accompanying drawings are for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from its spirit and scope.

[0035] The SiC MOSFETs crosstalk suppression active gate drive circuit based on a voltage inverter provided by the embodiment of the present invention is aimed at a half-bridge converter composed of SiC MOSFETs, that is, the half-bridge converter is the basic unit. For the two SiC MOSFETs in each half-bridge converter, two suppression sub-circuits are designed, and one of the suppression sub-circuits is connected between the drain, source, and gate of each SiC MOSFET. The suppression sub-circuit includes a voltage inverter composed of a P-channel MOSFET and an N-channel MOSFET, and also includes a working power supply, capacitor C vs 、capacitor C vd 、resistor R P and resistor R N . One end of capacitor C vs is connected to the drain of the SiC MOSFET, and the other end is connected to the gates of the P-channel MOSFET and the N-channel MOSFET. The drain of the P-channel MOSFET is connected to the working power supply, the source of the P-channel MOSFET is connected to resistor R P and then connected to one end of capacitor C vd . The source of the N-channel MOSFET is connected to the source of the SiC MOSFET, and the drain of the N-channel MOSFET is connected to resistor R N and then connected to capacitor C vdOne end of capacitor C vd is connected to the gate of the SiC MOSFET.

[0036] Figure 1 FIG. is a circuit diagram of a crosstalk suppression active gate drive circuit for a half-bridge converter, which includes two suppression sub-circuits AGD1 and AGD2. First, it should be noted that the half-bridge converter is provided with two SiC MOSFETs S1 and S2, and their connection relationship is as follows: the drain of S1 is connected to the bus voltage source V bus , the source of S1 is connected to the drain of S2, the source of S2 is grounded, and the common connection end of S1 and S2 is also connected to the inductor L p for connecting to the subsequent circuit. A resistor R g1 and a drive signal V g1 are also connected between the gate and source of S1. A resistor R g2 and a drive signal V g2 are also connected between the gate and source of S2. The suppression sub-circuit AGD1 connected to S1 includes a voltage inverter composed of a P-channel MOSFET P1 and an N-channel MOSFET N1, and also includes a working power supply V CC1 , capacitor C vs1 , capacitor C vd1 , resistor R P1 and resistor R N1 . The suppression sub-circuit AGD2 connected to S2 includes a voltage inverter composed of a P-channel MOSFET P2 and an N-channel MOSFET N2, and also includes a working power supply V CC2 , capacitor C vs2 , capacitor C vd2 , resistor R P2 and resistor R N2 . Among them, V CC1 = V CC2 = V CC , R P1 = R P2 , R N1 = R N2 , C vs1 = C vs2 = C vs , C vd1 = C vd2 = C vd , R g1 = R g2 .

[0037] During the turn-on / turn-off process of the active devices S1 and S2 in the invented active gate drive circuit, current is extracted or pumped into from the gate nodes of the SiC MOSFETs, thereby achieving the effects of crosstalk voltage suppression and switching speed improvement. Taking the turn-on process of the active switching device as an example, the crosstalk device drain-source voltage vds During the Miller stage of the turn-on process, it approximately rises from 0V to V bus , and the change in its drain-source voltage from 0V to V bus is collected, scaled, and inverted by the voltage-sensing capacitor C vs , resulting in the voltage on the left side of the capacitor C vd dropping from V CC to 0V and discharging through the resistor. Thus, the Miller current generated by the gate-drain capacitance C gd of SiC MOSFETs is extracted by the discharge current of the capacitor C vd , and the crosstalk voltage is suppressed. For the device of the active switch, its drain-source voltage approximately drops from V bus to 0V during the turn-on process, and this behavior is also collected and scaled by the voltage-sensing capacitor C vs . Subsequently, under the action of the P-channel and N-channel auxiliary MOSFETs, the change in the drain-source voltage V bus ~0V of the SiC MOSFETs is reduced and inverted into the change in the capacitor C vd voltage from 0V to V CC . The capacitor C vd is charged, and this charging current is pumped into the gate node, which can improve the switching speed and reduce the loss of the SiC MOSFETs.

[0038] The voltage inverter composed of the P-channel and N-channel auxiliary MOSFETs can be driven by the voltage-sensing capacitor C vs , and no additional driving signal needs to be designed. According to the capacitor voltage division theorem, the gate voltages of the P-channel and N-channel auxiliary MOSFETs can be expressed as:

[0039]

[0040] v GSP is the gate voltage of the P-channel auxiliary MOSFET, and v GSN is the gate voltage of the N-channel auxiliary MOSFET. V CC is the supply voltage of the voltage inverter. C ISSP is the input capacitance of the P-channel auxiliary MOSFET, and C ISSN is the input capacitance of the N-channel auxiliary MOSFET.

[0041] According to formula (1), the voltage-sensing capacitor under a given bus voltage level can be expressed as:

[0042]

[0043] Generally, it takes a time constant τ for a capacitor to discharge from its maximum voltage to 36.8%, and then its discharge current will rapidly decay. To ensure that all Miller current can be extracted / injected during the Miller stage, capacitor C vd is designed as:

[0044]

[0045] where λ is the exponential decay ratio at time τ, which is taken as 0.632 here. Q gd is the Miller charge, which is solved by the following formula:

[0046]

[0047] C gd is the capacitance connected between the gate and drain of the SiC MOSFET, and v ds is the drain voltage of the SiC MOSFET.

[0048] The invented active gate drive circuit can be divided into six stages according to its working principle. Refer to Figure 2 the key waveform diagram of the active gate drive circuit during the turn-on process shown, Figure 3 the key waveform diagram of the active gate drive circuit during the turn-off process shown, and Figures 4 to 9 the equivalent circuit diagram of the six stages of the active gate drive circuit shown, where C gs 、C gd and C ds are the gate-source capacitance, gate-drain capacitance and drain-source capacitance of the SiC MOSFETs respectively, and there is a relationship of C gs =C gs1 =C gs2 、C gd =C gd1 =C gd2 and C ds =C ds1 =C ds2 The specific process of the six stages of the invented active gate drive circuit is as follows.

[0049] 1) Turn-on process of the active device S1

[0050] a) Stage 1 (t0–t1)

[0051] Before t0, the drain voltages v ds1 and v ds2 of the SiC MOSFETs S1 and S2 remain constant, approximately V bus and 0V respectively. Capacitors C vs1 and C vs2 charge v ds1 and v ds2Sampling and scaling are performed. According to the capacitive voltage division rule, the gate voltages v GSN1 and v GSN2 of the N-channel auxiliary MOSFETs N1 and N2 are respectively equal to V CC and 0V. The equivalent circuit of the active gate drive circuit at this time is as shown in Figure 4 . The active gate drive circuit operates in the steady state stage, and the auxiliary MOSFETs P1 and N2 operate in the fully off state without static losses. At time t0, the power device S1 enters the Miller stage, and v ds1 rapidly decreases and v ds2 rises synchronously. v ds2 charges the capacitor C vs2 , thereby driving the subsequent-stage auxiliary MOSFETs. The current of the capacitor C vs2 at this stage can be expressed as:

[0052]

[0053] T on represents the time length for v GSN1 to decrease from V CC to 0V, that is, the turn-on duration of the active device S1.

[0054] In Figure 2 , when v GSN1 reaches (V CC –V THP ), the gate voltage v GSP1 of the auxiliary MOSFET P1 reaches its threshold voltage –V THP , and this stage ends.

[0055] b) Stage 2 (t1–t3)

[0056] At time t1, the gate voltages of the auxiliary MOSFETs P1 and N2 reach their threshold voltages and start to turn on. The equivalent circuit diagram of the circuit at this time is as shown in Figure 5 . For the crosstalk device S2, as the drain-source voltage v DSN2 decreases, the capacitor C vd2 discharges through N2, and most of the Miller current i Cgd2 flowing into the gate node of S2 cancels out the discharge current i vd2 of the capacitor C vd2 . At this time, only a small part of the Miller current flows into the gate node of the crosstalk device S2, so the crosstalk voltage is suppressed. For the active device S1, V CC1 charges the capacitor C vd1 through the auxiliary MOSFET P1. At this moment, more current (i vd1 +i g1) Flows into the S1 gate node, thus improving the switching speed of S1. In stage 2, the extraction of Miller charge is divided into two sub-stages, namely t1–t2 and t2–t3. In the t1–t2 sub-stage, assume the capacitance voltage v Cvd2 is V CC at time t1 and discharges to V C1 at time t2. Then the discharge current of capacitance C vd2 can be expressed as:

[0057]

[0058] where the voltage V C1 is:

[0059]

[0060] where g mN is the transconductance of the N-channel MOSFET. At time t2, the gate voltage of v GSN2 rises from V THN to its Miller voltage V milN . Therefore, the duration of this sub-stage (t1–t2) is:

[0061]

[0062] where I GSN2_on is the gate current of the auxiliary MOSFET N2 in this stage and can be expressed as:

[0063]

[0064] In the t1–t2 sub-stage, the total charge extracted by capacitance C vd2 is:

[0065] Q on1 = I vd2_on1 T1 (10)

[0066] At time t3, the capacitance voltage v Cvd2 drops to (1–λ)V CC . Then the current of capacitance C vd2 in the t2–t3 sub-stage is

[0067]

[0068] Correspondingly, the duration of the t2–t3 sub-stage is:

[0069]

[0070] In the t2–t3 sub-stage, the total charge extracted by C vd2 is:

[0071] Q on2 = I vd2_on2 T2 (13)

[0072] By selecting an appropriate R P2 and R N2 , ensure that Q gd = Q on1 + Q on2 is established, then the crosstalk voltage of SiC MOSFETs can be suppressed.

[0073] c) Stage 3 (t3–t4)

[0074] At this stage, v ds1 and v ds2 are approximately 0V and V bus respectively. Correspondingly, the auxiliary MOSFETs N1 and P2 are fully turned off. The equivalent circuit at this time is as Figure 6 shown. Although the voltages of capacitors C vd1 and C vd2 have not reached their steady-state values, their charging / discharging currents have decayed significantly and hardly affect the switching behavior of SiC MOSFETs. At t = 5τ, the voltages of capacitors C vd1 and C vd2 reach their steady-state values, and the active gate drive circuit enters the steady-state stage, and this stage ends.

[0075] 2) Turn-off process of the active device S1

[0076] d) Stage 4 (t5–t6)

[0077] As Figure 3 shown, before t5, although the gate voltage v gs1 of the active device S1 has started to decrease, the drain-source voltages v ds1 and v ds2 have not changed, and the active gate drive circuit is still in a stable state. The corresponding equivalent circuit is as Figure 7 shown. At t5, v gs1 drops to the Miller voltage, and v ds1 and v ds2 start to rise and fall respectively. For the auxiliary MOSFETs, v GSN1 and v GSN2 change synchronously with it. At t6, v GSN1 and v GSN2 reach V THN and (V CC – V THP ), and the auxiliary MOSFETs N1 and P2 start to conduct, and this stage ends.

[0078] e) Stage 5 (t6–t8)

[0079] At time t6, the auxiliary MOSFETs N1 and P2 start to conduct, and their drain-source voltages v DSN1 and v DSP2 rapidly decrease. The corresponding equivalent circuit is as shown in Figure 8 . Similar to the turn-on process, C vd1 and C vd2 are discharged and charged respectively. The current i vd1 is drawn from the gate node of S1. At the same time, i vd2 is pumped into the gate node of S2. Correspondingly, the crosstalk voltage of the power device S2 is suppressed, while the switching speed of the power device S1 is synchronously increased.

[0080] In this stage, the pumping process of Miller charge is also divided into two sub-stages: t6–t7 and t7–t8. In the t6–t7 sub-stage, assuming that the capacitor voltage v Cvd2 rises from 0V to V C2 , the current pumped into the gate node can be expressed as:

[0081]

[0082] where the voltage V C2 can be approximately estimated as:

[0083]

[0084] g mP and V milP are the transconductance and Miller voltage of the P-channel MOSFET respectively.

[0085] The gate current of the auxiliary MOSFET P2 can be expressed as:

[0086]

[0087] C ISSP is the input capacitance of the P-channel auxiliary MOSFET, and C ISSN is the input capacitance of the N-channel auxiliary MOSFET.

[0088] Among them, the average current of the capacitor C vs2 in the off stage can be estimated as:

[0089]

[0090] In this sub-stage, the gate voltage of the auxiliary MOSFET P2 drops from –V THP to –V milP , and the duration of this stage (t7–t6) can be expressed as:

[0091]

[0092] Capacitance C vd2 The total charge pumped into the gate at this stage is:

[0093] Q off1 = I vd2_off1 T3 (19)

[0094] At time t7, although P2 is fully turned on, the capacitor voltage v Cvd2 only rises to V C2 , far from its steady-state value V CC . Therefore, the power supply V CC2 continues to charge the capacitance C vd2 , and its charging current is:

[0095]

[0096] The duration of the sub-phase (t8–t7) can be expressed as:

[0097]

[0098] The total charge pumped by the capacitance C vd2 into the gate during this sub-phase is:

[0099] Q off2 = I vd2_off2 T4 (22)

[0100] Effective suppression of the crosstalk voltage requires reasonable selection of R P2 and R N2 , to ensure that Q gd = Q off1 + Q off2 holds.

[0101] f) Phase 6 (t8–t9)

[0102] After time t8, the drain-source voltage v ds2 has approximately dropped to 0 V, the crosstalk process ends, and the auxiliary MOSFETs P1 and N2 are fully turned off. The equivalent circuit at this time is as shown in Figure 9 . Although the voltages of the capacitances C vd1 and C vd2 have not reached the steady state, their charge / discharge currents have significantly decayed and hardly affect the switching behavior of the SiC MOSFETs. When t = 5τ, the active gate drive circuit reaches the steady state and this stage ends.

[0103] Summarizing the above six stages, in the invented active gate drive circuit, the capacitances C vd2 and the resistances R P2 、RN2 Two RC circuits are formed to extract and pump the Miller current i of SiC MOSFETs Cgd2 .

[0104] To achieve good crosstalk suppression effect, the resistors R P2 and R N2 need to be solved by the following formula:

[0105]

[0106] Figures 10 to 12 The comparison results between the invented active gate drive and the traditional gate drive are given. As Figure 10 shown, at the power level of 500V / 20A, when S1 is turned off, the traditional gate drive generates a negative crosstalk voltage of 4.3V; when S1 is turned on, the traditional gate drive generates a positive crosstalk voltage of 4.2V. When the invented active gate drive is applied, the crosstalk voltages in the turn-off and turn-on stages are reduced by 3V and 2.5V respectively, which indicates that the invented active gate circuit can effectively suppress the crosstalk voltage. Figure 11 The drain voltage waveform of S1 is given. Obviously, the invented active gate drive circuit has a larger slew rate, and in this case, the switching speed of SiC MOSFETs is faster and the switching loss is lower. Figure 12 Furthermore, the crosstalk waveform comparison between the active gate drive circuit and the crosstalk gate drive at a higher bus voltage level (V bus =700V) is given. The experimental results show that the invented active gate drive circuit can reduce the crosstalk voltage to an acceptable range even at a higher bus voltage, which proves the effectiveness of the drive circuit.

[0107] In summary, the active gate drive circuit for crosstalk suppression of SiC MOSFETs based on a voltage inverter provided by the embodiments of the present invention designs two suppression sub-circuits for crosstalk suppression for the half-bridge converter composed of SiC MOSFETs. The suppression sub-circuit includes a voltage inverter composed of a P-channel MOSFET and an N-channel MOSFET, and also includes a working power supply, capacitor C vs , capacitor C vd , resistor R P and resistor R N . The present invention uses fewer active and passive auxiliary components, and the active auxiliary components do not require additional control signals. Therefore, the circuit design and component selection are relatively simple. The designed active gate drive circuit of the present invention has the characteristic of low static power loss, and can be applied without modifying the original drive circuit, with the advantage of low invasiveness. While effectively suppressing crosstalk spikes, the present invention can also improve the switching speed of SiC MOSFETs, reduce the switching loss, and thus synchronously improve the reliability and efficiency of the converter.

[0108] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the above embodiments. Any other changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included within the protection scope of the present invention.

Claims

1. A voltage inverter based SiC MOSFETs crosstalk suppression active gate drive circuit, suitable for a half-bridge converter, wherein the half-bridge converter is formed by connecting two SiC MOSFETs, characterized in that: The active gate drive circuit includes more than two suppression sub-circuits, and one of the suppression sub-circuits is connected between the drain, source and gate of each SiC MOSFET; the suppression sub-circuit includes a voltage inverter composed of a P-channel MOSFET and an N-channel MOSFET, and also includes a working power supply, a capacitor C vs , capacitor C vd , resistor R P and resistor R N , capacitor C vs One end is connected to the drain of SiC MOSFET, and the other end is connected to the gate of P-channel MOSFET and the gate of N-channel MOSFET. The drain of P-channel MOSFET is connected to the working power supply, and the source of P-channel MOSFET is connected to the resistor R P After connecting capacitor C vd The source of the N-channel MOSFET is connected to the source of the SiC MOSFET, and the drain of the N-channel MOSFET is connected to the resistor R N After connecting capacitor C vd One end of the capacitor C vd The other end is connected to the gate of the SiC MOSFET.

2. The SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter according to claim 1, characterized in that: In a half-bridge converter, the connection relationship between its two SiC MOSFETs S1 and S2 is: the drain of S1 is connected to the bus voltage source, the source of S1 is connected to the drain of S2, and the source of S2 is grounded.

3. The SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter according to claim 2, characterized in that: Capacitor C vs The value is (C ISSP +C ISSN )×V CC ×(V bus -V CC ) -1 , V bus is the bus supply voltage, V CC is the working power supply voltage, C ISSP is the input capacitance of the P-channel auxiliary MOSFET, C ISSN is the input capacitance of the N-channel auxiliary MOSFET.

4. The SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter according to claim 3, characterized in that: Capacitor C vd The value is Q gd ×(λV CC ) -1 , Q gd is the Miller charge of S1 and S2, and λ is the exponential decay ratio.

5. The SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter according to claim 4, characterized in that: Resistor R P2 and R N2 The resistance value satisfies Q gd =Q on1 +Q on2 , Q on1 , Q on2 They are respectively the capacitor C vd2 The total charge drawn during the time periods t1–t2 and t2–t3, the capacitance C vd2 Refers to the capacitor C connected to S2 vd , R P2 and R N2 Respectively refers to the resistor R connected to S2 P and R N ; P1 and N1 represent the P-channel MOSFET and N-channel MOSFET connected to S1, respectively; P2 and N2 represent the P-channel MOSFET and N-channel MOSFET connected to S2, respectively; t0, t1, t2, and t3 are the four moments in the process of S1 turning on. Before t0, the half-bridge converter works in the steady-state stage, P1 and N2 work in the completely off state, t0 refers to the moment when S1 enters the Miller stage, and t1 refers to the gate voltage v of N2. GSN2 reaches its threshold voltage V THN and the gate voltage v of P1 GSP1 reaches its threshold voltage –V THP and starts to conduct, t2 refers to the moment when the gate voltage of N2 rises to its Miller voltage V milN The moment t3 refers to the capacitance C vd2 The voltage v Cvd2 Down to (1–λ)V CC moment; connect the resistor R of S1 P and R N Respectively represented by R P1 and R N1 , and R P1 =R P2 and R N1 =R N2 .

6. The SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter according to claim 5, characterized in that: Q on1 Equal to I vd2_on1 T1, I vd2_on1 Represents capacitance C vd2 The discharge current in the time period t1-t2, T1 represents the duration of the time period t1-t2; Q on2 Equal to I vd2_on2 T2, I vd2_on2 Represents capacitance C vd2 The discharge current in the time period t2–t3, T2 represents the duration of the time period t2–t3.

7. The SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter according to claim 6, characterized in that: I vd2_on1 Equal to [(R P2 +R N2 )·V C1 -R N2 ·V CC ] / (2R P2 ·R N2 ), V C1 Represents capacitance C vd2 The voltage at time t2, V C1 Equal to V CC -[g mN (V milN -V THN )T1] / (2C vd2 ), g mN represents the transconductance of N-channel MOSFET; T1 is equal to [C ISSN (V milN -V THN )+C GDN ·V CC ] / I GSN2_on , I GSN2_on represents the gate current of N2 during the period t1–t2, C ISSN represents the input capacitance of N-channel MOSFET, C GDN Represents the gate-drain capacitance of an N-channel MOSFET; I vd2_on2 Etc. I vd2_on1 +[R P2 −λ(R P2 +R N2 )]V CC / (2R P2 ·R N2 ) ; T2 is equal to [(V CC -V THP -V THN )·T on ] / V CC -T1, T on It represents the rising time of the drain voltage of S2 during the turning-on process of S1, which is the time length from time t0 to t4. t4 represents the time when N1 and P2 are completely turned off after time t3.

8. The SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter according to claim 7, characterized in that: Resistor R P2 and R N2 The resistance value satisfies Q gd =Q off1 +Q off2 , Q off1 , Q off2 The capacitance C in the time period t6-t7 and the time period t7-t8 are respectively vd2 The total charge pumped into the gate of S2, t5, t6, t7, t8 are the four moments in the process of S1 turning off, t5 refers to the time when v gs1 The moment when N1 and P2 start to conduct, t6 refers to the moment when the gate voltage of P2 drops from –V THP Down to –V milP The moment, V milP represents the Miller voltage of the P-channel MOSFET, and t8 refers to the time when the gate voltage of N2 drops to its threshold voltage V THN moment.

9. The SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter according to claim 8, characterized in that: Q off1 Equal to I vd2_off1 T3, I vd2_off1 Represents capacitance C vd2 The current pumped into the gate node during the t6–t7 period, T3 represents the duration of the t6–t7 period; Q off2 Equal to I vd2_off2 T4, I vd2_off2 Represents capacitance C vd2 The charging current in the time period t7-t8, T4 represents the duration of the time period t7-t8.

10. The SiC MOSFETs crosstalk suppression active gate drive circuit based on voltage inverter according to claim 9, characterized in that: I vd2_off1 Equal to [R N2 ·V CC -V C2 (R P2 +R N2 )] / (2R P2 ·R N2 ), V C2 Represents capacitance C vd2 The voltage at time t7, V C2 Equal to [g mP (V milP -V THP )T3] / (2C vd2 ), g mP represents the transconductance of the P-channel MOSFET; T3 is equal to [C ISSP (V milP -V THP )+C GDP ·V CC ] / I GSP2_off , I GSP2_off represents the gate current of P2 during the period t6–t7, C ISSP represents the input capacitance of the P-channel MOSFET, C GDP Represents the gate-drain capacitance of a P-channel MOSFET; I vd2_off2 Etc. I vd2_off1 +[R N2 −λ(R P2 +R N2 )]V CC / (2R P2 ·R N2 ) ; T4 is equal to [(V CC -V THP -V THN )·T off ] / V CC -T3, T off It represents the falling time of the drain voltage of S2 during the turning-on process of S1, which is the time length from time t5 to t9. t9 represents the time when N2 and P1 are completely turned off after time t8.

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