On-time generator applied to Buck converter
By designing the on-time generator circuit in the Buck converter, including a ramp generator and a transmission delay cancellation module, the problems of large operating frequency changes and large quiescent current in traditional adaptive on-time control are solved, and the effects of constant frequency and low quiescent current are achieved.
Patent Information
- Application Number
- CN202510339834.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-06-20
AI Technical Summary
When the load and input voltage are changed, the traditional Buck converter with adaptive on-time control changes, the operating frequency changes greatly and the quiescent current is large, so it cannot effectively adapt to the load changes.
An on-time generator circuit is designed, including a ramp generator module, a transmission delay cancellation module, a logic module, an enable module and a comparator. The transmission delay cancellation module cancels the comparator's transmission delay, and the on-time is inversely proportional to the switching node voltage through the ramp generator module, avoiding the use of an error amplifier to reduce the quiescent current.
Adaptive adjustment of on-time and load and input voltage changes is achieved, which reduces the change of operating frequency and reduces quiescent current and improves the efficiency of the buck converter.
Smart Images
Figure CN120185368A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and more particularly, to a turn-on time generator applied to a Buck converter. Background Art
[0002] Adaptive turn-on time control is a new type of switching power supply control scheme that can automatically adjust the switching frequency of a converter according to the load. As Figure 1 shown, a traditional turn-on time control module generates a signal for controlling the turn-on time of a power transistor based on the values of the output voltage and the input voltage to ensure that the switching frequency is not affected by changes in the input and output voltages in the continuous conduction mode (CCM). Among them, the positive input terminal of the comparator is connected to the voltage of capacitor C on , the negative input terminal is connected to the output voltage, the mirror ratio of the current mirror is 1:1, and the charging current I on = R o2 / [R o3 (R o1 + R o2 )] × V IN . According to the flip point of the comparator and the current-voltage relationship of the capacitor, it can be obtained that: R o2 / [R o3 (R o1 + R o2 )] × V IN × T ON = C on × V OUT . In theory, the turn-on time of the upper power transistor can be obtained where A = (R o1 + R o2 )R o3 C on / R o2 . From the expression of T ON , it can be seen that the turn-on time is proportional to V OUT and inversely proportional to V IN . However, in practice, the expression of T ON also needs to add the propagation delay Td of the comparator, and the propagation delay of the comparator will change with the change of V IN , resulting in a large change in the operating frequency of the buck converter under different input voltages, which is not conducive to peripheral applications.
[0003] In addition, according to the volt-second balance principle of the buck converter, the following equation is obtained under actual application conditions:
[0004] (V IN - I L R gh - V OUT ) × T ON = VOUT ×T off (1)
[0005] Among them, I L is the inductor current, R gh is the on-resistance of the upper power transistor, and T off is the turn-off time of the upper power transistor. Also, because in CCM, the average value of the inductor current within one switching period is equal to the output load current I Load of the buck converter, so by converting Equation (1), we get:
[0006] (V IN -I Load R gh )×T ON =V OUT ×T off +V OUT ×T ON =V OUT ×T S (2)
[0007] T ON =V OUT ×T S ÷(V IN -I Load R gh ) (3)
[0008] Among them, T S is the time of the buck converter's switching period. It can be seen that when I Load varies greatly, the change in the on-conduction loss I Load R gh of the upper power transistor cannot be ignored. That is, at this time, T ON and the input voltage V IN are not inversely proportional, but inversely proportional to (V IN -I Load R gh ). However, the T Figure 1 obtained from the on-conduction time generation circuit in ON is still inversely proportional to V IN , without considering the influence of I Load on T ON . Therefore, the actual T ON will also vary greatly when I Load varies greatly, resulting in a large change in the operating frequency.
[0009] In addition, in the traditional adaptive on-conduction time control circuit, an error amplifier is used to convert the input voltage V IN into a current related to the input voltage, resulting in a relatively large static current, thus reducing the efficiency of the buck converter.
[0010] In summary, the problems of large working frequency variation and large static current in the traditional adaptive on-time controlled buck converter need to be solved urgently. SUMMARY OF THE INVENTION
[0011] To solve the technical problem that the frequency of the Buck converter with adaptive on-time control in the prior art deviates with the change of load and input voltage, the present invention proposes a on-time generator circuit applied to the Buck converter. The on-time generator circuit includes a ramp generator module, a transmission delay cancellation module, a comparator, an enable module, and a logic module.
[0012] The transmission delay cancellation circuit includes: a variable resistance unit, a comparator unit, a second resistor, first to seventh transistors, a first transmission gate, a second transmission gate, and a current module. One end of the current module is connected to the switch node, the other end of the current module is connected to one end of the second transmission gate, and the control signal of the current module is connected to the EN and ENB signals. The gates of the first transistor, the second transistor, the drain of the fifth transistor, and one end of the second resistor are all connected to the other end of the second transmission gate. The gates of the third transistor, the fourth transistor, the drain of the sixth transistor, and the drain of the second transistor are all connected to the other end of the second resistor. The source of the second transistor is connected to the drain of the third transistor, the source of the first transistor is connected to the drain of the fourth transistor, the sources of the third transistor and the fourth transistor are both connected to the ground terminal. The drain of the first transistor, the drain of the seventh transistor are connected to one end of the variable resistance unit, one end of the first transmission gate is connected to the other end of the variable resistance unit, the other end of the first transmission gate is connected to the output voltage, and the two control signals of the first and second transmission gates are respectively connected to the EN and ENB signals; the comparator unit is configured to generate a switch control signal according to the input voltage; the variable resistance unit is configured to adjust the resistance value of the variable resistance unit according to the switch control signal.
[0013] The ramp generator module includes: an eighth transistor, a ninth transistor, a first resistor, and a first capacitor. The source of the ninth transistor is connected to the switch node, the gate of the ninth transistor is connected to the gate of the eighth transistor, the drain of the ninth transistor is connected to one end of the first resistor, the drain of the eighth transistor and the other end of the first resistor are both connected to one end of the first capacitor, the source of the eighth transistor is connected to the ground terminal, and the other end of the first capacitor is connected to the ground terminal.
[0014] The logic circuit includes: a second NOR gate, a third NOR gate, and a first OR gate. The two input terminals of the second NOR gate are respectively connected to the output signal T of the comparatorON is connected to the output terminal VAOT of the third NOR gate. The two input terminals of the third NOR gate are respectively connected to the on-signal PWM_H of the upper power transistor output by the buck converter loop and the output terminal of the second NOR gate. The two input terminals of the first OR gate are respectively connected to the output terminal VAOT of the third NOR gate and the on-signal VGH of the upper power transistor. The logic circuit is configured to input the comparator output signal T ON and the PWM_H signal into an RS flip-flop composed of NOR gates to generate the turn-off signal VAOT, and use the transmission delay between PWM_H and VGH to shield the output of the comparator to prevent the comparator from making misjudgments when it is just turned on.
[0015] The enabling module includes: a first NOR gate and a first inverter. Among them, the two input terminals of the first NOR gate are respectively connected to the turn-off signal VAOT and the on-signal PWM_H of the upper power transistor output by the buck converter loop. The output of the first NOR gate is connected to the input of the first inverter, and the output terminal of the first inverter is connected to ENB. The enabling module is configured to output a high level after the upper power transistor is turned on to enable the comparator, the current module, and the current mirror to work normally.
[0016] The variable resistor unit includes N resistors and N switches. Among them, the N resistors are connected in series in sequence, and a switch is connected in parallel on both sides of each resistor.
[0017] The comparator control unit includes N comparators and N reference signals. The switch control signal includes N switch signals. Among them, the positive input terminals of the N comparators receive the input voltage, the output terminals of the N comparators output the N switch signals, and the N switch signals control the opening and closing of the N switches, and each switch corresponds to a switch signal.
[0018] The on-time generator proposed by the present invention cancels the transmission delay of the comparator through the delay generated by the transmission delay cancellation module, thereby eliminating the influence of the transmission delay of the comparator on the on-time T ON . Also, since when the upper power transistor is turned on, the voltage of the switch node is the input voltage minus the on-loss of the upper power transistor (V IN -I Load R gh ), therefore, by generating a voltage proportional to the voltage of the switch node through the ramp generator module, the on-time can be made inversely proportional to the voltage of the switch node, that is, the on-time is inversely proportional to (V IN -I Load R gh)is inversely proportional. In addition, an error amplifier is avoided to implement the conversion of the input voltage into a current related to the input voltage, and a lower static current can be achieved. Compared with the existing adaptive on-time control circuit, the influence of the load current and the propagation delay of the comparator on T ON is considered, and a lower static current is also achieved. In summary, the on-time generator circuit of the embodiments of the present disclosure can adjust the on-time of the upper power transistor of the switching converter based on the changes in the load and the input voltage, so as to achieve a constant frequency of the buck converter. At the same time, the on-time generator circuit also adaptively adjusts the on-time according to the change of the output voltage to achieve a constant frequency of the buck converter. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] To illustrate the technical solutions of the embodiments of the present disclosure more clearly, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:
[0020] Figure 1 shows a schematic block diagram of a conventional adaptive on-time control circuit;
[0021] Figure 2 shows a schematic block diagram of an on-time generator circuit according to an embodiment of the present disclosure;
[0022] Figure 3 shows a schematic circuit diagram of another on-time generator circuit according to an embodiment of the present disclosure;
[0023] Figure 4 shows an exemplary circuit diagram of a propagation delay cancellation module in an on-time generator circuit according to an embodiment of the present disclosure;
[0024] Figure 5 shows an exemplary circuit diagram of a comparator unit and a variable resistor unit in a propagation delay cancellation module of an on-time generator circuit according to an embodiment of the present disclosure;
[0025] Figure 6 shows an exemplary circuit diagram of a current module in a propagation delay cancellation module of an on-time generator circuit according to an embodiment of the present disclosure;
[0026] Figure 7 shows an exemplary circuit diagram of a ramp generator module in an on-time generator circuit according to an embodiment of the present disclosure;
[0027] Figure 8 shows an exemplary circuit diagram of a logic module in an on-time generator circuit according to an embodiment of the present disclosure;
[0028] Figure 9Shows an exemplary circuit diagram of an enable module in a conduction time generator circuit according to an embodiment of the present disclosure;
[0029] The elements in the drawings are schematic and not drawn to scale. Detailed implementation manners
[0030] Based on the problems that the switching frequency of the buck converter with conduction time control in the prior art shifts with the load and input voltage changes and the static current of the traditional conduction time generator circuit is large, the present invention proposes a conduction time generator circuit to solve the above problems. Specifically, as Figure 2 shown, the conduction time generator circuit includes a ramp generator module, a transmission delay cancellation module, a logic module, an enable module, and a comparator. The conduction time generator circuit of the present disclosure will be described in detail below.
[0031] The input end of the ramp generator module is connected to the switching node of the buck converter and the output VC of the logic circuit. The output end of the ramp generator module is connected to the positive input end of the comparator. The switching node is the node between the upper power transistor and the inductor in the buck converter. The ramp generator module is configured to generate a voltage proportional to the voltage of the switching node after the upper power transistor is turned on, which can make the conduction time T ON inversely proportional to the voltage of the switching node VSW. That is, the conduction time T ON is inversely proportional to (V IN - I Load R gh ). Compared with the traditional conduction time generation circuit, the embodiment of the present disclosure takes into account the influence of the load current on the conduction time.
[0032] The four input ends of the transmission delay cancellation module are respectively connected to the output voltage of the buck converter, the switching node of the buck converter, and the EN and ENB signals output by the enable module. The output end of the transmission delay cancellation module is connected to the negative input end of the comparator. The transmission delay cancellation module is configured to cancel the transmission delay of the comparator according to the variable resistance unit. The resistance value of the variable resistance unit is controlled by the input voltage of the buck converter; the output voltage VN of the transmission delay cancellation module is set to (V OUT - IR S ). Compared with the traditional conduction time generator circuit, the conduction time generator circuit of the embodiment of the present disclosure eliminates the influence of the comparator flip delay and the change of the load current on the conduction time, so that the conduction time generator circuit can ensure a small change in the system operating frequency under different input voltages V IN , output voltages V OUT and different loads, and better meets the requirements of peripheral applications.
[0033] The two input terminals of the enabling module are respectively connected to the upper power transistor conduction signal PWM_H output from the buck converter loop and the turn-off signal VAOT, and the output signals of the enabling module are EN and ENB respectively; the three input terminals of the logic circuit are respectively connected to the output terminal T of the comparator ON , the upper power transistor conduction signal PWM_H output from the buck converter loop and the upper power transistor conduction signal VGH. The output terminal VC of the logic circuit is connected to the input terminal of the ramp generator module, the output terminal VAOT of the logic circuit is connected to the input terminal of the enabling module, and the output terminal AVOT of the logic circuit is the turn-off signal. When the upper power transistor is conducting, the enabling module outputs a high level to make the current mirror and the comparator work normally. When the upper power transistor is turned off, the enabling module outputs a low level to turn off the current mirror and the comparator, thereby achieving low static current consumption.
[0034] The negative input terminal of the comparator is connected to the output node VN of the transmission delay cancellation module, the positive input terminal of the comparator is connected to the output node VP of the ramp generator module, and the enable terminal of the comparator is connected to the output EN of the enabling module. The comparator is configured to compare the voltages of the VN node and the VP node and generate a signal V OUT . Specifically, when the ramp voltage VP is greater than the VN voltage, the output voltage T of the comparator ON becomes high level, and the output signal T of the comparator ON and the upper power transistor conduction signal PWM_H output from the buck converter loop pass through an RS flip-flop composed of NOR gates to output the turn-off signal VAOT, so that the logic control unit in the buck converter controls the turn-off of the upper power transistor according to the turn-off signal VAOT. Among them, the VN voltage is set to (V out -IR S ).
[0035] Such as Figure 4As shown in the figure, the transmission delay cancellation circuit includes: a variable resistance unit, a comparator unit, a second resistor, first to seventh transistors, a first transmission gate, a second transmission gate, and a current module. One end of the current module is connected to the switch node, and the other end of the current module is connected to one end of the second transmission gate. The gates of the first transistor, the second transistor, the drain of the fifth transistor, and one end of the second resistor are all connected to the other end of the second transmission gate. The gates of the third transistor, the fourth transistor, the drain of the sixth transistor, and the drain of the second transistor are all connected to the other end of the second resistor. The source of the second transistor is connected to the drain of the third transistor, the source of the first transistor is connected to the drain of the fourth transistor, the sources of the third transistor and the fourth transistor are connected to the ground terminal. The drain of the first transistor, the drain of the seventh transistor are connected to one end of the variable resistance unit. One end of the first transmission gate is connected to the other end of the variable resistance unit, and the other end of the first transmission gate is connected to the output voltage. The two control signals of the first and second transmission gates are respectively connected to the EN and ENB signals; the comparator unit is configured to generate a switch control signal according to the input voltage; the variable resistance unit is configured to adjust the resistance value of the variable resistance unit according to the switch control signal.
[0036] As Figure 5 shown, the variable resistance unit includes N resistors (R S1 , R S2 , …, R Sn ), N switches (S1, S2, …, S n ), where the N resistors are connected in series in sequence, and a switch is connected in parallel on both sides of each resistor. The comparator control unit includes N comparators, N reference signals (V REF1 , V REF2 , …, V REFn ). The switch control signal includes N switch signals. Among them, the positive input terminals of the N comparators receive the input voltage, the output terminals of the N comparators output the N switch signals, and the N switch signals control the opening and closing of the N switches. Each switch corresponds to a switch signal. Among them, the resistance value R S of the variable resistance unit is inversely proportional to the input voltage V IN . That is, the larger V IN is, the smaller R S is, and the smaller V IN is, the larger R S is.
[0037] As Figure 6As shown, the current module includes a third resistor, a fourth resistor, and transistors T10 to T17. One end of the fourth resistor is connected to VSW, and the other end of the fourth resistor is connected to the drain of the tenth transistor and the gate of the thirteenth transistor. The gate of the tenth transistor is connected to the gate of the eleventh transistor, the drain of the eleventh transistor, and the drain of the fourteenth transistor. The source of the tenth transistor is connected to the source of the eleventh transistor and one end of the current source. The other end of the current source is connected to the gate of the fourteenth transistor, the gate of the fifteenth transistor, and the drain of the fifteenth transistor. The source of the fourteenth transistor is connected to the source of the twelfth transistor. The source of the fifteenth transistor is connected to the source of the thirteenth transistor. The gate of the twelfth transistor is connected to the drain of the twelfth transistor and one end of the third resistor. The other end of the third resistor and the drain of the thirteenth transistor are both connected to the ground terminal.
[0038] As Figure 7 shown, the ramp generator module includes: an eighth transistor, a ninth transistor, a first resistor, and a first capacitor. The source of the ninth transistor is connected to the switch node. The gate of the ninth transistor is connected to the gate of the eighth transistor. The drain of the ninth transistor is connected to one end of the first resistor. The drain of the eighth transistor is connected to the other end of the first resistor and one end of the first capacitor. The source of the eighth transistor is connected to the ground terminal. The other end of the first capacitor is connected to the ground terminal.
[0039] As Figure 8 shown, the logic circuit includes: a second NOR gate, a third NOR gate, and a first OR gate. The two input terminals of the second NOR gate are respectively connected to the output signal T of the comparator ON and the output terminal VAOT of the third NOR gate. The two input terminals of the third NOR gate are respectively connected to the upper power transistor conduction signal PWM_H output by the loop and the output terminal of the second NOR gate. The two input terminals of the first OR gate are respectively connected to the output terminal VAOT of the third NOR gate and the upper power transistor conduction signal VGH. The logic circuit is configured to input the PWM_H signal and the output signal T of the comparator ON into an RS flip-flop composed of NOR gates to generate the shutdown signal, and use the propagation delay between PWM_H and VGH to shield the output of the comparator to prevent misjudgment of the comparator when it is just turned on.
[0040] As Figure 9As shown, the enabling module includes: a first NOR gate and a first inverter. Among them, the two input terminals of the first NOR gate are respectively connected to the turn-off signal VAOT and the upper power transistor conduction signal PWM_H output by the buck converter loop. The output of the first NOR gate is connected to the input of the first inverter, and the output terminal of the first inverter is connected to ENB. The enabling module is configured to output a high level to make the comparator, current module, and current mirror work properly after the upper power transistor is turned on, and output a low level to make the comparator, current module, and current mirror not work.
[0041] Combined with Figures 2 - 9 , the principle of the conduction time generator circuit in the embodiments of the present disclosure is analyzed: when the upper power transistor is turned on, the ramp generator module starts to work. According to the relevant formula of the first-order RC network, the output voltage VP of the ramp generator module is:
[0042]
[0043] Among them, V SW is the voltage of the switching node. When R1C1 >> T ON and VN < V IN , Equation (4) is approximately first-order by the Taylor formula as:
[0044]
[0045] According to Figure 4 in the circuit structure, it can be obtained that:
[0046] VN = V OUT -IRs (6)
[0047] Among them, Rs is Figure 4 the equivalent resistance in the variable resistance unit.
[0048] According to Figure 6 of the circuit, it can be obtained that
[0049] I1 = (V SW -VB1) / R4 (7)
[0050] VB1 + V gs13 +V gs15 = V R3 +V gs12 +V gs14 (8)
[0051] Among them, V gs12 、V gs13 、V gs14 、V gs15 are the gate-source voltages of the twelfth transistor, thirteenth transistor, fourteenth transistor, and fifteenth transistor respectively,
[0052] Moreover, since the current mirror ratios in the current module are all 1:1, and the twelfth transistor and the thirteenth transistor are the same transistors, the following can be obtained:
[0053] V gs15 = V gs14 ,V gs12 = V gs13 (9)
[0054] Substituting the two equalities in Equation (9) into Equation (8), the following can be obtained:
[0055] V R3 = VB1 (10)
[0056] Among them, the resistance value of R4 is equal to that of R3. Therefore, the second current I2 can be obtained as:
[0057]
[0058] According to Equations (7) and (11), the current I is:
[0059] I = I1 + I2 = V SW / R4 (12)
[0060] According to Figures 2 - 9 the circuit diagram, it can be obtained that at the end of the conduction timing, the following equation is satisfied:
[0061]
[0062] Transforming Equation (13) gives:
[0063]
[0064] Substituting Equation (12) into Equation (14) gives:
[0065]
[0066] The actual conduction time needs to add the transmission delay Td of the comparator. Therefore, Equation (15) becomes:
[0067]
[0068] In Equation (16), Td changes with V IN and also changes with Vin. If the two are equal, that is, Td = it can offset the influence of the transmission delay Td of the comparator on T ON . When and Td are offset, the following can be obtained:
[0069]
[0070] According to the volt-second balance principle, it can be obtained that:
[0071]
[0072] By comparing Equation (17) with Equation (18), the switching frequency Tsw in the embodiments of the present disclosure can be obtained as:
[0073] Tsw = R1C1 (19)
[0074] It can be seen from Equation (19) that Tsw in the embodiments of the present disclosure does not change with I Load variation. When the values of R1 and C1 are fixed, Tsw is a constant. Therefore, the operating frequency can be made invariant. It should be noted that the invariance of the operating frequency here is not an absolute invariance. It can be considered invariant relative to the variation in the background technology. However, in practice, it may still be affected by the non-ideality of some devices such as inductance, parasitic capacitance, and parasitic resistance, as well as the delay of some logic circuits. The embodiments of the present disclosure mainly aim to eliminate the influence of the propagation delay of the comparator and the load current on T ON of.
[0075] In addition, the determination and setting of the equivalent resistance value R S of the variable resistance unit are described as follows: According to it can be determined that R S = Td×R4 / (R1C1), where R4, R1, and C1 are constants, and Td will vary with V IN variation, and the larger V IN is, the smaller Td is, and R S is also smaller. According to the variation of R S , R1, R2,..., Rn can be set. An example is given for illustration. Suppose there are 10 values for V IN , and correspondingly 10 values of Td can be obtained. Then, 10 values of R S can also be calculated. Then, according to the 10 values of R S , the number of resistors in the variable resistance unit and the value of each resistor can be set. For example, it can be set to 10 resistors, and the value of each resistor is set to one of the values of R S . When the circuit is working, the switch corresponding to the resistor whose R S value is required is turned on, and the switches of other resistors are closed. Or it can also be set in such a way that the value of each R S is equal to the sum of two or more resistors. The embodiments of the present disclosure do not limit the setting method of the number and resistance value of the resistors in the variable resistance unit.
[0076] In summary, the on-time generator circuit in the embodiments of the present disclosure can obtain a VIN , V OUT , I Load The effect of a working frequency with very small variations, and in addition, a lower static current can also be achieved.
[0077] Several embodiments of the present disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.
Claims
1. A conduction time generator for a Buck converter, characterized in that: The on-time generator circuit includes a ramp generator module, a transmission delay compensation module, a comparator, an enable module, and a logic module. The input end of the ramp generator module is connected to the switch node of the buck converter and the output signal VC of the logic circuit, the output end of the ramp generator module is connected to the positive input end of the comparator, the switch node is the node VSW between the upper power tube and the inductor in the buck converter, and the ramp generator module is configured to generate a voltage proportional to the voltage of the switch node after the upper power tube is turned on; The four input ends of the transmission delay compensation module are respectively connected to the output voltage of the buck converter, the switch node VSW of the buck converter and the EN and ENB signals output by the enable module, the output end of the transmission delay compensation module is connected to the negative input end of the comparator, and the transmission delay compensation module is configured to compensate the transmission delay of the comparator according to the variable resistance unit, and the resistance value of the variable resistance unit is controlled by the input voltage of the buck converter; The negative input terminal of the comparator is connected to the output node VN of the transmission delay compensation module, the positive input terminal of the comparator is connected to the output node VP of the ramp generator module, the enable terminal of the comparator is connected to the output EN of the enable module, and the comparator is configured to compare the size of the VN node with the VP node and generate a signal T ON ; The two input ends of the enabling module are respectively connected to the upper power tube conduction signal PWM_H output by the buck converter loop and the output signal VAOT of the conduction time generator, and the output signals of the enabling module are EN and ENB respectively; The three input terminals of the logic circuit are respectively connected to the output terminals T ON , the upper power tube turn-on signal PWM_H and the upper power tube turn-on signal VGH output by the buck converter loop, the output end VC of the logic circuit is connected to the input end of the ramp generator module, the output end VAOT of the logic circuit is connected to the input end of the enable module, and the output end AVOT of the logic circuit is the shutdown signal.
2. The on-time generator circuit according to claim 1, characterized in that: The transmission delay compensation circuit includes: a variable resistance unit, a comparator unit, a second resistor, first to seventh transistors, first to second transmission gates, and a current module. Wherein, one end of the current module is connected to the switch node, the other end of the current module is connected to one end of the second transmission gate, the gate of the first transistor, the gate of the second transistor, the drain of the fifth transistor and one end of the second resistor are all connected to the other end of the second transmission gate, the gate of the third transistor, the gate of the fourth transistor, the drain of the sixth transistor and the drain of the second transistor are all connected to the other end of the second resistor, the source of the second transistor is connected to the drain of the third transistor, the source of the first transistor is connected to the drain of the fourth transistor, the source of the third transistor and the source of the fourth transistor are connected to the ground terminal, the drain of the first transistor and the drain of the seventh transistor are connected to one end of the variable resistance unit, one end of the first transmission gate is connected to the other end of the variable resistance unit, the other end of the first transmission gate is connected to the output voltage, and the two control signals of the first and second transmission gates are respectively connected to the EN and ENB signals; The comparator unit is configured to generate a switch control signal according to an input voltage; The variable resistance unit is configured to adjust the resistance value of the variable resistance unit according to the switch control signal.
3. The on-time generator circuit according to claim 2, characterized in that: The variable resistance unit includes N resistors and N switches. Among them, N resistors are connected in series in sequence, and a switch is connected in parallel on both sides of each resistor.
4. The on-time generator circuit according to claim 3, characterized in that: The comparator control unit includes N comparators and N reference signals, and the switch control signal includes N switch signals. Among them, the positive input terminals of the N comparators receive the input voltage, and the output terminals of the N comparators output the N switch signals, and the N switch signals control the opening and closing of the N switches, and each switch corresponds to a switch signal.
5. The on-time generator circuit according to claim 1, wherein: The ramp generator module includes: an eighth transistor, a ninth transistor, a first resistor, and a first capacitor. Among them, the source of the ninth transistor is connected to the switch node, the gate of the ninth transistor is connected to the gate of the eighth transistor, the drain of the ninth transistor is connected to one end of the first resistor, the drain of the eighth transistor is connected to the other end of the first resistor and one end of the first capacitor, the source of the eighth transistor is connected to the ground, and the other end of the first capacitor is connected to the ground.
6. The on-time generator circuit according to claim 2, wherein: The current module includes a third resistor, a fourth resistor, and tenth to seventeenth transistors. Among them, one end of the fourth resistor is connected to VSW, the other end of the fourth resistor is connected to the drain end of the tenth transistor and the gate end of the thirteenth transistor, the gate end of the tenth transistor is connected to the gate end of the eleventh transistor, the drain end of the eleventh transistor, and the drain end of the fourteenth transistor, the source end of the tenth transistor is connected to the source end of the eleventh transistor and one end of the current source, the other end of the current source is connected to the gate end of the fourteenth transistor, the gate end of the fifteenth transistor, and the drain end of the fifteenth transistor, the source end of the fourteenth transistor is connected to the source end of the twelfth transistor, the source end of the fifteenth transistor is connected to the source end of the thirteenth transistor, the gate end of the twelfth transistor is connected to the drain end of the twelfth transistor and one end of the third resistor, and the other end of the third resistor and the drain end of the thirteenth transistor are both connected to the ground.
7. The on-time generator circuit according to claim 1, wherein: The enabling module includes: a first NOR gate, a first inverter, The two input ends of the first NOR gate are respectively connected to the shutdown signal VAOT and the upper power tube conduction signal PWM_H output by the buck converter loop, the output of the first NOR gate is connected to the input of the first inverter, and the output end of the first inverter is connected to ENB; The enabling module is configured to output a high level to enable the comparator, the current module and the current mirror to work normally after the upper power tube is turned on.
8. The on-time generator circuit according to claim 1, wherein: The logic circuit comprises: a second NOR gate, a third NOR gate, and a first OR gate. The two input terminals of the second NOR gate are respectively connected to the output signal T ON The first or gate is connected to the output terminal VAOT of the third or-not gate, the two input terminals of the third or-not gate are respectively connected to the upper power tube conduction signal PWM_H output by the loop and the output terminal of the second or-not gate, and the two input terminals of the first or gate are respectively connected to the output terminal VAOT of the third or-not gate and the control signal VGH of the upper power tube; The logic circuit is configured to convert the PWM_H signal and the comparator output signal T ON The shutdown signal is generated after the RS trigger composed of a NOR gate is input, and the transmission delay between PWM_H and VGH is used to shield the output of the comparator to prevent the comparator from making a wrong judgment when it is just turned on.