Power-on initial stage conduction time circuit in COT architecture

Abstract

The invention provides a power-on initial stage conduction time circuit in a COT architecture. The power-on initial stage conduction time circuit comprises a power inductor, an output capacitor, a first feedback resistor, a second feedback resistor, a loop comparator, a Ton1 timing module, a Ton2 timing module, a Vout detection module, a selection switch, a PWM control logic module and a power module. Under a high-voltage technology with a large parasitic ratio, the influence of large delay of the level converter is effectively resisted, simultaneous conduction of the upper power tube and the lower power tube is avoided, the chip safety is ensured, meanwhile, the structure is simple, and normal work of a system is not additionally influenced.

Description

Technical Field

[0001] The present invention belongs to the technical field of switching power supply chips, and particularly relates to a turn-on time circuit in the initial power-on stage of a COT architecture. Background Art

[0002] In a synchronous rectification BUCK structure, when the upper and lower power transistors conduct simultaneously, a very large current will be generated, which may cause the chip to burn out. Therefore, before the upper and lower transistors are turned on, a dead time must be set separately to prevent simultaneous conduction. For most application scenarios, this design can effectively ensure safety; however, in a Constant On-Time (COT) structure, during the initial power-on stage, there may be other situations.

[0003] In a common constant on-time COT structure, for frequency stability, the on-time Ton is determined by K*(Vout / Vin), where K is a coefficient, Vout is the output voltage, and Vin is the input voltage. During the initial power-on stage, since Vout = 0 and Ton = 0, the system cannot start. A fixed on-time Ton_min must be set so that Ton = K*(Vout / Vin)+Ton_min. When Vout = 0, Ton = Ton_min and the system can start; as Vout gradually rises, Ton gradually increases; when Vout power-on is completed, Ton becomes stable. After Vout power-on is completed, Ton_min is generally retained for a period of time for other purposes, such as the shielding signal for upper transistor current detection. The time is generally not set too long, usually 30ns - 50ns.

[0004] Figure 1 It is a schematic diagram of a BUCK drive stage, where LF1 / LF3 are low-to-high level shifters that transfer the logic level of a signal from (0 - VCC) to (SW - BST), LF2 is a high-to-low level shifter that transfers the logic level of a signal from (SW - BST) to (0 - VCC); DT1 / DT2 are delay circuits that delay the falling edges of DR_LS / DR_HS (the drive signals of LS / HS) respectively to set the dead time before HS / LS is turned on.

[0005] In some high-voltage processes, the transmission delay of the level shifter is relatively large. Under extreme conditions, at the initial stage of Vout power-on, the high level of the driving signal (DR_HS) of the high-side switch (HS) is "eaten up" by the delay of the high-to-low level shifter. During the turn-on and turn-off of HS, the output of the high-to-low level shifter is always low, causing the "logic circuit to prevent simultaneous conduction of the upper and lower transistors" to fail. When the PWM signal becomes low, the low-side switch (LS) is immediately turned on, while HS has not been fully turned off at this time, resulting in a large current in the VIN--HS--LS--GND path, causing chip damage or burnout.

[0006] Figure 2 Give the schematic diagram of the normal / abnormal LS driving logic. The left side is the normal waveform, where T1 is the rising-edge delay of LF2 and T2 is the falling-edge delay of LF2. Ton > T1, and the signal transmission is normal. The right side is the abnormal waveform, Ton_min < T1, the high level of DR_HS is "eaten up", DR_HS1 is always low, and during the T3 time period, HS / LS conducts simultaneously. Summary of the Invention

[0007] The purpose of the present invention is to provide a turn-on time circuit at the initial power-on stage in a COT architecture to solve the technical problem of chip damage or burnout caused by simultaneous conduction of the upper and lower power transistors as mentioned in the above background technology.

[0008] To achieve the above purpose, the present invention provides the following technical solutions:

[0009] A turn-on time circuit at the initial power-on stage in a COT architecture, comprising a power inductor, an output capacitor, a first feedback resistor, a second feedback resistor, a loop comparator, a Ton1 timing module, a Ton2 timing module, a Vout detection module, a selection switch, a PWM control logic module, and a power module;

[0010] One end of the power inductor is connected to the output end of the power module, and the other end of the power inductor is connected to the output end of the BUCK converter; the output capacitor is connected between the ground and the output end of the BUCK converter; the first feedback resistor and the second feedback resistor are connected in series and connected between the ground and the output end of the BUCK converter, and the series node is respectively connected to the negative input end of the loop comparator and the positive input end of the Vout detection module; the positive input end of the loop comparator is connected to the reference voltage Vref1, and the output end of the loop comparator is connected to the input end of the Ton1 timing module; the output end of the Ton1 timing module is respectively connected to a selection contact of the selection switch and the input end of the Ton2 timing module; the output end of the Ton2 timing module is connected to another selection contact of the selection switch; the output end of the selection switch is connected to the PWM control logic module; the negative input end of the Vout detection module is connected to the reference voltage Vref2, and the signal PG output by its output end controls the selection switch; the PWM control logic module is connected to the power module.

[0011] Further, the Ton1 timing module generates a conduction time Ton1 = K*(Vout / Vin) + Ton_min = Ton0 + Ton_min; the Ton2 timing module generates a fixed conduction time Ton2, and satisfies Ton_min + Ton2 > T1, where T1 is the rising edge delay of the high-to-low level converter.

[0012] Further, the signal PG output by the output end of the Vout detection module controls the selection switch. When PG = L, Ton = Ton1 + Ton2 = Ton0 + Ton2 + Ton_min; when PG = H, Ton = Ton1 = Ton0 + Ton_min; the PWM control logic module generates a low-voltage PWM signal.

[0013] The present invention has the following beneficial effects:

[0014] 1. Under the high-voltage process with large parasitics, it effectively resists the greater influence of the level shifter delay, avoids the simultaneous conduction of the upper and lower power transistors, and ensures the safety of the chip;

[0015] 2. The structure is simple and has no additional impact on the normal operation of the system. Description of the Drawings

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other accompanying drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 It is a schematic diagram of the BUCK drive stage;

[0018] Figure 2 It is a schematic diagram of the drive logic of the low-end switch tube (LS);

[0019] Figure 3 It is a schematic diagram of the COT architecture of the present invention. Specific embodiments

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0021] Refer to Figure 3 As shown, a turn-on initial conduction time circuit in a COT architecture includes a power inductor L, an output capacitor Cout, a first feedback resistor RFB1, a second feedback resistor RFB2, a loop comparator CMP, a Ton1 timing module Ton1 timer, a Ton2 timing module Ton2 timer, a Vout detection module Vout_det, a selection switch, a pulse width modulation PWM control logic module pwm logic, and a power module power stage.

[0022] One end of the power inductor L is connected to the output end of the power module power stage, and the other end of the power inductor L is connected to the output end Vout of the BUCK converter; the output capacitor Cout is connected between the ground GND and the output end Vout of the BUCK converter; the first feedback resistor RFB1 and the second feedback resistor RFB2 are connected in series and connected between the ground GND and the output end Vout of the BUCK converter, and their series node is respectively connected to the negative input end of the loop comparator CMP and the positive input end of the Vout detection module Vout_det, and a voltage information Vfb proportional to the output voltage Vout is obtained at their series node; the positive input end of the loop comparator is connected to the reference voltage Vref1, the output end of the loop comparator is connected to the input end of the Ton1 timing module Ton1 timer, and the loop comparator CMP obtains a conduction time control signal by comparing the voltages at its positive and negative input ends, and further controls the Ton1 timing module to generate a conduction time Ton1; the output end of the Ton1 timing module Ton1 timer is respectively connected to a selection contact of the selection switch and the input end of the Ton2 timing module Ton2timer; the output end of the Ton2 timing module Ton2 timer is connected to another selection contact of the selection switch; the output end of the selection switch is connected to the PWM control logic module pwm logic; the negative input end of the Vout detection module Vout_det is connected to the reference voltage Vref2, and the signal PG output by its output end controls the selection switch. After Vout is powered on, PG = H; the PWM control logic module pwm logic is connected to the power module powerstage, and the PWM control logic module generates a low-voltage PWM signal.

[0023] The Ton1 timing module generates a conduction time Ton1 = K*(Vout / Vin)+Ton_min = Ton0+Ton_min; the Ton2 timing module generates a fixed conduction time Ton2, and satisfies Ton_min+Ton2>T1, where T1 is the rising edge delay of the high-to-low level converter (LF2). Using the selection switch, when PG = L, Ton = Ton1+Ton2 = Ton0+Ton2+Ton_min; when PG = H, Ton = Ton1 = Ton0+Ton_min.

[0024] In the initial stage of power-on, since Vout = 0 and PG = L, Ton = Ton0 + Ton2 + Ton_min is followed. And since Ton0 = 0, then Ton = Ton_min + Ton2 > T1. The high-level of the upper transistor drive signal (DR_HS) in the high-voltage domain can be correctly transmitted, ensuring that the upper and lower transistors do not conduct simultaneously and avoiding the risk of chip burning caused by large current. After Vout power-on is completed, PG = H, and Ton = Ton_min + Ton0 is followed, which has no impact on normal functional parameters (such as switching frequency).

[0025] The present invention detects the power-on of Vout. Before Vout power-on is completed, Ton = Ton_min + Ton0 + Ton2, where Ton_min + Ton2 is greater than T1. After Vout power-on is completed, Ton = Ton_min + Ton0, ensuring that the upper and lower transistors do not conduct simultaneously and avoiding the risk of chip burning caused by large current.

[0026] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art in the relevant technical field can well understand and utilize the present invention.

Claims

1. A power-on initial conduction time circuit in a COT architecture, characterized in that: It includes a power inductor, an output capacitor, a first feedback resistor, a second feedback resistor, a loop comparator, a Ton1 timing module, a Ton2 timing module, a Vout detection module, a selection switch, a PWM control logic module and a power module; One end of the power inductor is connected to the output end of the power module, and the other end of the power inductor is connected to the output end of the BUCK converter; the output capacitor is connected between the ground and the output end of the BUCK converter; the first feedback resistor and the second feedback resistor are connected in series and connected between the ground and the output end of the BUCK converter, and their series nodes are respectively connected to the negative input end of the loop comparator and the positive input end of the Vout detection module; the positive input end of the loop comparator is connected to the reference voltage Vref1, and the output end of the loop comparator is connected to the input end of the Ton1 timing module; the output end of the Ton1 timing module is respectively connected to a selection contact of the selection switch and the input end of the Ton2 timing module; the output end of the Ton2 timing module is connected to another selection contact of the selection switch; the output end of the selection switch is connected to the PWM control logic module; the negative input end of the Vout detection module is connected to the reference voltage Vref2, and the signal PG outputted from its output end controls the selection switch; the PWM control logic module is connected to the power module.

2. The power-on initial conduction time circuit in a COT architecture according to claim 1, characterized in that: The Ton1 timing module generates a conduction time Ton1=K*(Vout / Vin)+Ton_min=Ton0+Ton_min; the Ton2 timing module generates a fixed conduction time Ton2, and satisfies Ton_min+Ton2>T1, where T1 is the rising edge delay of the high-to-low level converter.

3. The power-on initial conduction time circuit in a COT architecture according to claim 2, characterized in that: The signal PG outputted from the output end of the Vout detection module controls the selection switch. When PG=L, Ton=Ton1+Ton2=Ton0+Ton2+Ton_min; when PG=H, Ton=Ton1=Ton0+Ton_min.

Images