Self-powered chip system

Abstract

The invention provides a self-powered chip system which is characterized in that one end of a primary winding of a power circuit where the system is located receives input voltage, the other end of the primary winding is grounded through a J-FET upper tube, a first node and an NMOS lower tube in sequence, the control end of the J-FET upper tube is grounded, one end of a chip power supply capacitor of the self-powered chip system is grounded, and the other end of the chip power supply capacitor is grounded. One end of the controller is coupled to a first node through a J-FET upper tube, the other end of the controller is coupled to a first node through a default on-state constant current source and a first switch, the chip power supply capacitor supplies power to the power supply end of the controller, and due to the fact that the power supply voltage needed by the controller is smaller than the pinch-off voltage of the J-FET upper tube, self power supply is conducted on the controller through the constant current source in the power-on process; when the voltage of the power supply end is smaller than or equal to the first voltage threshold value, the first switch is controlled to be switched on to carry out lossless self-power supply on the controller, and when the voltage of the power supply end is smaller than or equal to the third voltage threshold value, the constant current source and the first switch are simultaneously controlled to be switched on to carry out self-power supply on the controller. The power supply circuit of the controller is simplified, and the power supply efficiency of the circuit is improved.

Description

Technical Field

[0001] The present invention relates to the field of circuit electronic technology, and in particular to a self-powered chip system. Background Art

[0002] In the prior art, power supply equipment usually needs to support a wide input voltage range and a wide output voltage range at the same time. For example, a power supply equipment with a PD 3.0 protocol has an AC input voltage range of 90Vac~264Vac and an output voltage range of 3.3V~20V. For another example, a power supply equipment with a PD3.1 protocol has an AC input voltage range of 90Vac~264Vac and an output voltage range of 5V~28V. Such a wide input voltage range and a wide output voltage range pose a great challenge to the efficiency of the power supply equipment.

[0003] The primary side control chip of the current power supply equipment generally adopts the forward power supply method or the flyback power supply method. However, both methods make the voltage variation range of the power supply end of the primary side control chip very large. In order to ensure the stable operation of the primary side control chip, it is usually necessary to use a high-voltage withstand process to manufacture the power supply end of the primary side control chip, or add an external voltage stabilization circuit at the power supply end, which not only significantly increases the system cost, but also reduces the efficiency of the system when fully loaded.

[0004] Therefore, how to improve the power supply efficiency of power supply equipment while reducing circuit costs has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0005] The present invention provides a self-powered chip system, which solves the technical problem of how to improve the power supply efficiency of a power supply device while reducing the circuit cost.

[0006] According to a first aspect of the present invention, an embodiment of the present invention provides a self-powered chip system, which is applied to a power circuit, wherein the power circuit includes a primary circuit, wherein the primary circuit includes a primary winding, a J-FET upper tube and an NMOS lower tube, wherein a first end of the primary winding receives an input voltage, and a second end thereof is connected to ground via the J-FET upper tube and the NMOS lower tube in sequence, wherein a control end of the J-FET upper tube is coupled to ground, and the J-FET upper tube and the NMOS lower tube are coupled via a first node; The self-powered chip system comprises: a chip power supply capacitor, a constant current source, a first switch and a controller, wherein the constant current source is in an on state by default; The first end of the chip power supply capacitor is grounded, and the second end thereof is coupled to the first node through the constant current source and the first switch respectively; the power supply end of the controller is coupled to the second end of the chip power supply capacitor, the first end thereof is coupled to the control end of the constant current source, and the second end thereof is coupled to the control end of the first switch; The controller is configured to: enter a normal operating state when the voltage at the power supply terminal reaches a startup voltage, and control the constant current source to enter an off state, where the startup voltage is less than the pinch-off voltage of the J-FET upper transistor; After entering the normal operating state, based on the voltage at the power supply terminal, control the operating state of the constant current source and the on / off state of the first switch, where: When the voltage at the power supply terminal is less than or equal to a first voltage threshold, control the first switch to conduct until the voltage at the power supply terminal is greater than or equal to a second voltage threshold, where the startup voltage is greater than the second voltage threshold, and the second voltage threshold is greater than the first voltage threshold; When the voltage at the power supply terminal is less than or equal to a third voltage threshold, control the operating state of the constant current source to be on until the voltage at the power supply terminal is greater than or equal to the first voltage threshold, where the third voltage threshold is less than the first voltage threshold.

[0007] Optionally, the third terminal of the controller is coupled to the control terminal of the NMOS lower transistor; The controller is further configured to: generate an internal clock signal when the controller is in the normal operating state; and control the on / off state of the NMOS lower transistor based on the internal clock signal.

[0008] Optionally, the method of controlling the first switch to conduct when the voltage at the power supply terminal is less than or equal to the first voltage threshold until the voltage at the power supply terminal is greater than or equal to the second voltage threshold includes: In the current switching cycle of the internal clock signal, if the voltage at the power supply terminal is less than or equal to the first voltage threshold, control the first switch to remain in the off state; When the internal clock signal enters the switching cycle after the current switching cycle, if the voltage at the power supply terminal is less than the second voltage threshold, perform the following steps in each switching cycle of the internal clock signal until the voltage at the power supply terminal is greater than or equal to the second voltage threshold: Sequentially control the first switch to conduct and the NMOS lower transistor to conduct; After the NMOS lower transistor conducts, control the first switch to disconnect.

[0009] Optionally, control the first switch to conduct at the start of the switching cycle.

[0010] Optionally, after the NMOS lower transistor conducts, controlling the first switch to disconnect includes: Controlling the first switch and the NMOS lower transistor to disconnect simultaneously.

[0011] Optionally, after the first switch is turned off, control the NMOS lower transistor to turn off.

[0012] Optionally, when the voltage at the power supply terminal is less than or equal to a first voltage threshold, a method for controlling the first switch to conduct until the voltage at the power supply terminal is greater than or equal to the second voltage threshold includes: In the current switching cycle of the internal clock signal, if the voltage at the power supply terminal is less than or equal to the first voltage threshold, control the first switch to remain in the off state; In the switching cycle after the internal clock signal enters the current switching cycle, if the voltage at the power supply terminal is less than the second voltage threshold, perform the following steps in each switching cycle of the internal clock signal until the voltage at the power supply terminal is greater than or equal to the second voltage threshold: Control the first switch to conduct or the NMOS lower transistor to conduct.

[0013] Optionally, in the first switching cycle after the internal clock signal enters the current switching cycle, control the first switch to conduct.

[0014] Optionally, when the voltage at the power supply terminal is less than or equal to a third voltage threshold, controlling the working state of the constant current source to be on and controlling the first switch to conduct includes: In the current switching cycle of the internal clock signal, if the voltage at the power supply terminal is less than or equal to the third voltage threshold, control the working state of the constant current source to be on; In the switching cycle after the internal clock signal enters the current switching cycle, control the first switch to conduct, and the first switch conducts before the NMOS lower transistor.

[0015] Optionally, the self-powered chip system further includes a first diode; the negative electrode of the first diode is coupled to the second end of the chip power supply capacitor, the positive electrode of the first diode is coupled to the first node through the first switch.

[0016] Optionally, the power circuit further includes a secondary circuit and a first circuit that are magnetically coupled to the primary winding respectively; The secondary circuit is used to sense the change in magnetic flux of the primary winding and output an output voltage; The first circuit is used to sense the change in magnetic flux of the primary winding and output a first feedback signal; The fourth terminal of the controller receives the first feedback signal, and the controller is further configured to: based on the first feedback signal and the on / off state of the NMOS lower transistor, control the working state of the power circuit, where: When controlling the NMOS lower transistor to conduct, obtain the voltage value of the first feedback signal, and based on the voltage value of the first feedback signal, control whether the primary circuit enters a protection state; When controlling the NMOS lower transistor to turn off, obtain the voltage value and current value of the first feedback signal, and when the voltage value of the first feedback signal is less than or equal to the fourth voltage threshold, based on the current value of the first feedback signal, control whether the secondary circuit enters a protection state.

[0017] Optionally, the first circuit includes a first winding, a first voltage-dividing resistor, and a second voltage-dividing resistor; The first output terminal of the first winding is coupled to the first end of the first voltage-dividing resistor, the second end of the first voltage-dividing resistor is coupled to the first end of the second voltage-dividing resistor through a second node, the second end of the second voltage-dividing resistor is coupled to the second output terminal of the first winding, and the second node is coupled to the fourth terminal of the controller for outputting the first feedback signal.

[0018] Optionally, the secondary circuit includes a secondary winding, a second diode, a first capacitor, and a first resistor; The first output terminal of the secondary winding is coupled to the first end of the first capacitor through the second diode, the second end of the first capacitor is coupled to the second output terminal of the secondary winding, and the first capacitor is in parallel with the first resistor.

[0019] Optionally, the first winding is an EMI shielding layer winding, and the polarity of the first winding is opposite to the polarity of the secondary winding.

[0020] Optionally, the first winding is an auxiliary winding.

[0021] Optionally, the eighth terminal of the controller receives the output voltage, and the controller is further configured to: based on the voltage value of the output voltage, control the frequency of the internal clock signal.

[0022] Optionally, the secondary circuit further includes a first feedback module, and the primary circuit further includes a second feedback module; The first feedback module is in parallel with the first capacitor, and the first feedback module is used to obtain the output voltage and output a second feedback signal, and the second feedback signal includes the voltage value information of the output voltage; The first end of the second feedback module is coupled to the eighth terminal of the controller, the second end of the second feedback module is grounded, the receiving end of the second feedback module receives the second feedback signal, and the second feedback module is used to transmit the voltage value information of the output voltage to the controller.

[0023] Optionally, the primary circuit further includes a current sampling module configured to obtain the magnitude of the current flowing through the first node and output a third feedback signal to the fifth terminal of the controller, where the third feedback signal includes the current value information of the current flowing through the first node. The controller is further configured to: based on the third feedback signal, determine the turn-on time and turn-off time of the NMOS lower transistor in each switching cycle of the internal clock signal.

[0024] Optionally, the current sampling module includes a first NMOS transistor and a sampling resistor. The gate of the first NMOS transistor is coupled to the control terminal of the NMOS lower transistor, the drain of the first NMOS transistor is coupled to the sixth terminal of the controller, its source is grounded, the first end of the sampling resistor is coupled to the fifth terminal of the controller, and its second end is grounded. The controller is further configured to: output a first current to the fifth terminal of the controller and obtain the voltage value at the first end of the sampling resistor, where the current value of the first current is equal to the current value of the current flowing through the sixth terminal of the controller.

[0025] Optionally, the current sampling module includes a sampling resistor connected in series between the first node and the drain of the NMOS lower transistor, and the fifth terminal of the controller is configured to obtain the voltage across the sampling resistor to obtain the current value information of the current flowing through the first node.

[0026] Optionally, the primary circuit further includes an RCD snubber module, and the RCD snubber module includes a second resistor, a second capacitor, and a third diode. The first end of the primary winding is respectively coupled to the first end of the second capacitor and the first end of the second resistor, the second end of the second capacitor is respectively coupled to the second end of the second resistor and the cathode of the third diode, and the anode of the third diode is coupled to the second end of the primary winding.

[0027] Optionally, the primary circuit further includes a power supply side capacitor, and the first end of the primary winding is grounded through the power supply side capacitor.

[0028] Optionally, the primary circuit further includes a rectification module and a power extraction module, the power supply side capacitor is connected in parallel with the rectification module, the input terminals of the rectification module and the power extraction module are both coupled to an AC power supply, and the output terminal of the power extraction module is coupled to the high-voltage power extraction terminal of the controller. The controller is configured to: when the voltage value of the AC power supply is less than the fifth voltage threshold and the voltage value of the AC power supply is greater than or equal to 0, control the first switch to conduct, or control the working state of the constant current source to be in the on state and control the first switch to conduct.

[0029] Optionally, the AC power supply includes an AC live wire and an AC neutral wire, and the power extraction module includes a fourth diode, a fifth diode, and a third resistor; The negative electrode of the fourth diode and the positive electrode of the fifth diode are respectively coupled to the AC live wire and the AC neutral wire, the negative electrodes of the fourth diode and the fifth diode are both coupled to the first end of the third resistor, and the second end of the third resistor is coupled to the high-voltage power extraction terminal of the controller.

[0030] Optionally, the self-powered chip system further includes a turn-on / off speed control module, and the turn-on / off speed control module includes a sixth diode and a fourth resistor; The first end of the fourth resistor is coupled to the control terminal of the J-FET upper transistor, and its second end is coupled to the positive electrode of the sixth diode; the negative electrode of the sixth diode is coupled to the second end of the fourth resistor.

[0031] Optionally, the seventh terminal of the controller is further coupled to the first node; The controller is further configured to control whether the primary circuit enters a protection state based on the voltage value and / or current value of the first node.

[0032] Optionally, the constant current source further has a current limiting function.

[0033] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects: In the self-powered chip system of the technical solution of the present invention, one end of the primary winding of the power circuit where the system is located receives an input voltage, and the other end is grounded through the J-FET upper transistor, the first node, and the NMOS lower transistor in sequence. The control terminal of the J-FET upper transistor is grounded. One end of the chip power supply capacitor of the self-powered chip system is grounded, and the other end is coupled to the first node through the default-on constant current source and the first switch respectively. The chip power supply capacitor supplies power to the power supply terminal of the controller. Since the required supply voltage of the controller is less than the pinch-off voltage of the J-FET upper transistor, the present invention supplies power to the controller through the constant current source during power-on, conducts the first switch to supply power to the controller without loss when the voltage at the power supply terminal is less than or equal to the first voltage threshold, and supplies power to the controller by simultaneously controlling the constant current source and the first switch to conduct when the voltage at the power supply terminal is less than or equal to the third voltage threshold. This not only simplifies the power supply circuit of the controller but also improves the power supply efficiency of the circuit.

[0034] Further, the power circuit where the self-powered chip system is located further includes a first circuit. The first output end of the first winding therein is coupled to the first end of the first voltage-dividing resistor. The second end of the first voltage-dividing resistor and the first end of the second voltage-dividing resistor are coupled through a second node. The second end of the second voltage-dividing resistor is coupled to the second output end of the first winding. The second node is coupled to the fourth end of the controller for outputting a first feedback signal. Among them, the first winding is an EMI shielding layer winding, and the polarity of the first winding is opposite to that of the secondary winding. The present invention realizes the sampling of the input voltage and output voltage information by multiplexing the EMI shielding layer winding, further simplifying the architecture of the power circuit. Brief Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 is a schematic structural diagram of a controller power supply circuit in an embodiment of the prior art; Figure 2 corresponds to Figure 1 the working waveform diagram of the circuit shown; Figure 3 is a schematic structural diagram of a self-powered chip system provided by an embodiment of the present invention; Figure 4 corresponds to Figure 3 the working waveform Figure 1 ; Figure 5 corresponds to Figure 3 the working waveform Figure 2 ; Figure 6 corresponds to Figure 3 the working waveform Figure 3 ; Figure 7 is a schematic structural diagram of a self-powered chip system provided by another embodiment of the present invention; Figure 8 is a schematic structural diagram of a self-powered chip system provided by still another embodiment of the present invention. Detailed Description of the Embodiments

[0037] As described in the background art, it is difficult for the prior art to improve the power supply efficiency of power equipment while reducing the circuit cost. The following will be described in detail with reference to the drawings.

[0038] Figure 1It is a schematic structural diagram of a controller power supply circuit in a flyback power supply. The flyback power supply includes: A primary circuit, including a primary winding Np, a controller U1, and a first switching transistor M1; the output terminal of the controller U1 is coupled to the control terminal of the first switching transistor M1, the first terminal of the first switching transistor M1 is coupled to the first terminal of the primary winding Np, and the second terminal of the first switching transistor M1 is grounded.

[0039] A secondary circuit, including a secondary winding Ns, a second diode D2, a first capacitor C1, and a first resistor R1.

[0040] The first output terminal of the secondary winding Ns is coupled to the first terminal of the first capacitor C1 through the second diode D2, the second terminal of the first capacitor C1 is coupled to the second output terminal of the secondary winding Ns, and the first capacitor C1 is in parallel with the first resistor R1.

[0041] An auxiliary circuit, including an auxiliary winding Naux, a first diode D1, a second capacitor C2, a second resistor R2, a first voltage-dividing resistor Rup, and a second voltage-dividing resistor Rdw; where: The positive electrode of the first diode D1 and the first terminal of the first voltage-dividing resistor Rup are coupled to the first output terminal of the auxiliary winding Naux, the negative electrode of the first diode D1 is respectively coupled to the first terminal of the second capacitor C2 and the power supply terminal of the controller U1, the second capacitor C2 is in parallel with the second resistor R2, and the second terminal of the second capacitor C2 is grounded. The second terminal of the first voltage-dividing resistor Rup is respectively coupled to the first terminal of the second voltage-dividing resistor Rdw and the first input terminal of the controller U1, and the second terminal of the second voltage-dividing resistor Rdw is coupled to the second output terminal of the auxiliary winding Naux, and the second terminal of the second voltage-dividing resistor Rdw is grounded.

[0042] An electromagnetic shielding circuit, including an EMI shielding layer winding N-E_shield, the polarity of the EMI shielding layer winding N-E_shield is opposite to that of the auxiliary winding Naux, the first output terminal of the EMI shielding layer winding N-E_shield is floating NC, and its second output terminal is grounded.

[0043] It can be seen that in actual operation, the transformer needs to be provided with at least two auxiliary windings Naux: one of the auxiliary windings Naux (i.e., the above-mentioned electromagnetic shielding circuit) is specifically used for electromagnetic interference (EMI) shielding; the other auxiliary winding Naux is used to provide a power supply voltage for the controller U1. This structure increases the manufacturing complexity and cost of the transformer.

[0044] Moreover, in this embodiment, the controller U1 is powered by the auxiliary winding Naux. Due to the leakage inductance of the transformer itself, the voltage at the power supply terminal is not only affected by the changes in the input voltage and the output voltage, but also fluctuates significantly with the load of the output, which results in a large voltage fluctuation range at the power supply terminal. Therefore, in actual design, a high breakdown voltage process is used to manufacture the power supply terminal of the controller U1, or an external voltage stabilizing circuit is added to the power supply terminal, further increasing the manufacturing complexity and cost of the transformer.

[0045] Not only that, when the power circuit is in the full-load state, the supply voltage provided by the auxiliary winding Naux also reaches the highest point, which leads to an increase in power supply loss. Moreover, when the power circuit is under a heavy load, the current demand at the power supply terminal is also relatively high, further increasing the power supply loss and reducing the working efficiency of the overall system.

[0046] Please refer to Figure 2 , Figure 2 which shows the working waveform diagram corresponding to Figure 1 . Among them: DRV can be understood as the control signal of the first switching transistor M1; Vds can be understood as the voltage at the drain of the first switching transistor M1; Vcc can be understood as the voltage at the power supply terminal; Vo can be understood as the output voltage of the secondary circuit; Naux / Ns can be understood as the turn ratio of the auxiliary winding Naux to the secondary winding Ns; N can be understood as the turn ratio of the secondary winding Ns to the primary winding Np.

[0047] It can be seen that in the example shown in Figure 1 , the voltage at the power supply terminal is not only affected by the changes in the input voltage and the output voltage, but also fluctuates significantly with the load of the output, which results in a large voltage fluctuation range at the power supply terminal. Not only that, as the load increases, the controller U1 also increases the power supply loss of the power circuit, affecting the working efficiency of the overall system.

[0048] To solve the above problems, an embodiment of the present invention provides a self-powered chip system. One end of the primary winding of the power circuit where the system is located receives an input voltage, and the other end is grounded through a J-FET upper transistor, a first node, and an NMOS lower transistor in sequence. The control end of the J-FET upper transistor is grounded. One end of the chip power supply capacitor of the self-powered chip system is grounded, and the other end is coupled to the first node through a default-conduction constant current source and a first switch respectively. The chip power supply capacitor supplies power to the power supply terminal of the controller. Since the required power supply voltages of the controller are all less than the pinch-off voltage of the J-FET upper transistor, the present invention self-supplies power to the controller through the constant current source during power-on, performs lossless self-power supply to the controller by controlling the first switch to conduct when the voltage at the power supply terminal is less than or equal to the first voltage threshold, and self-supplies power to the controller by simultaneously controlling the constant current source and the first switch to conduct when the voltage at the power supply terminal is less than or equal to the third voltage threshold. This not only simplifies the power supply circuit of the controller but also improves the power supply efficiency of the circuit.

[0049] Next, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0050] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0051] Next, the technical solutions of the present invention will be described in detail with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0052] Figure 3It is a self-powered chip system according to an embodiment of the present invention. This system is applied to a power circuit. The power circuit includes a primary circuit. The primary circuit includes a primary winding Np, a J-FET upper transistor Q1, and an NMOS lower transistor Q2. The first end of the primary winding Np receives an input voltage Vin, and its second end is grounded through the J-FET upper transistor Q1 and the NMOS lower transistor Q2 in sequence. The control end of the J-FET upper transistor Q1 is coupled to the ground, and the J-FET upper transistor Q1 and the NMOS lower transistor Q2 are coupled through a first node m. The self-powered chip system includes: a chip power supply capacitor Cvcc, a constant current source Ist, a first switch Q3, and a controller U1. The default working state of the constant current source Ist is the on state. The first end of the chip power supply capacitor Cvcc is grounded, and its second end is coupled to the first node m through the constant current source Ist and the first switch Q3 respectively. The power supply terminal VCC of the controller U1 is coupled to the second end of the chip power supply capacitor Cvcc. Its first end EN is coupled to the control end of the constant current source Ist, and its second end CH is coupled to the control end of the first switch Q3. The controller U1 is configured to: enter the normal working state when the voltage at the power supply terminal VCC reaches the startup voltage, and control the working state of the constant current source Ist to be the off state. The startup voltage is less than the pinch-off voltage of the J-FET upper transistor Q1; and Based on the voltage at the power supply terminal VCC, control the working state of the constant current source Ist and the on / off of the first switch Q3, where: When the voltage at the power supply terminal VCC is less than or equal to a first voltage threshold VCC_L, control the first switch Q3 to conduct until the voltage at the power supply terminal VCC is greater than or equal to a second voltage threshold VCC_H. The startup voltage is greater than the second voltage threshold VCC_H, and the second voltage threshold VCC_H is greater than the first voltage threshold VCC_L; When the voltage at the power supply terminal VCC is less than or equal to a third voltage threshold VCC_Min, control the working state of the constant current source Ist to be the on state until the voltage at the power supply terminal VCC is greater than or equal to the first voltage threshold VCC_L. The third voltage threshold VCC_Min is less than the first voltage threshold VCC_L.

[0053] In a preferred embodiment, the constant current source Ist also has a current limiting function. Of course, the present invention does not limit the specific implementation manner of this function. For example, a constant current source based on LM317, a constant current source including an operational amplifier, etc. can all implement this function, and the present invention will not elaborate on this.

[0054] It is easy to understand that when the constant current source Ist is in the on-state or the first switch Q3 is turned on, the chip power supply capacitor Cvcc will be charged, causing the voltage of the power supply terminal VCC to rise. As an example, the J-FET upper transistor Q1 can be a D-mode gallium nitride power device (Cascode GaN), a SiC power device, etc. The present invention does not limit this, and those skilled in the art can select a suitable normally-on device according to needs.

[0055] It can be seen that the J-FET upper transistor Q1 and the NMOS lower transistor Q2 in the embodiment of the present invention form a Cascode switch tube structure. The controller U1 takes power from the midpoint m of the Cascode switch tube, performs lossy self-power supply during the initial power-on and light load periods of the power circuit, and performs lossless self-power supply when the power circuit enters medium and heavy loads, so that the power supply terminal VCC has a very stable power supply voltage, and at the same time improves the power supply efficiency of the power circuit.

[0056] Specifically, since the J-FET upper transistor Q1 is a normally-on device, when the controller U1 performs lossy self-power supply, the J-FET upper transistor Q1 needs to be close to the off state, so that the voltage of the first node m is greater than the voltage of the power supply terminal VCC. In this case, both ends of the J-FET upper transistor Q1 will bear the input voltage Vin, resulting in circuit losses; When the controller U1 performs lossless self-power supply, Vin, the inductor (i.e., the inductor Lp of the primary winding), the J-FET upper transistor Q1, the first switch Q3, and the chip power supply capacitor Cvcc form a power supply loop. Since the VCC voltage (power supply terminal voltage) is much lower than the J-FET pinch-off voltage, the J-FET is in a fully-on state, and the Vin voltage is almost entirely applied across Lp. The voltage drops of Q1 and Q3 are extremely low, the device losses are almost zero, the circuit hardly generates heat, and thus the circuit efficiency is relatively high.

[0057] As an example, the controller U1 in the embodiment of the present invention can be a flyback controller, a forward controller, an AHB controller, an LLC controller, etc. The control mode of the controller U1 can also have a COT fixed conduction time mode, a fixed turn-off time mode, a voltage mode control mode, a current mode control mode, etc. The present invention does not limit this, and those skilled in the art can select the type of the controller U1 and the control mode of the controller U1 for the NMOS lower transistor Q2 according to needs.

[0058] To ensure that the charging current flows unidirectionally, in a preferred embodiment, please continue to refer to Figure 3 , the self-powered chip system further includes a first diode D1; the negative electrode of the first diode D1 is coupled to the second end of the chip power supply capacitor Cvcc, The positive electrode of the first diode D1 is coupled to the first node m through the first switch Q3.

[0059] In actual operation, the self-powered chip system further includes a turn-on / off speed control module. Please continue to refer to Figure 3 , and the turn-on / off speed control module includes a sixth diode Ddd and a fourth resistor Rdd; The first end of the fourth resistor Rdd is coupled to the control end of the J-FET upper transistor Q1, and its second end is coupled to the positive electrode of the sixth diode Ddd; the negative electrode of the sixth diode Ddd is coupled to the second end of the fourth resistor Rdd.

[0060] Among them, the fourth resistor Rdd is used to suppress the turn-on speed of the J-FET upper transistor Q1, and the sixth diode Ddd is used to accelerate the turn-off speed of the J-FET upper transistor Q1. It should be understood that the present invention does not limit the resistance value of the fourth resistor Rdd, and those skilled in the art can select a suitable resistance value according to needs.

[0061] During actual operation, the controller U1 periodically turns on and off the NMOS lower transistor Q2 to meet the load requirements of the power circuit. Furthermore, please continue to refer to Figure 3 , in one embodiment, the third terminal Gate of the controller U1 is coupled to the control end of the NMOS lower transistor Q2; The controller U1 is further configured to: generate an internal clock signal when the controller U1 is in a normal operating state; and control the turn-on and off of the NMOS lower transistor Q2 based on the internal clock signal.

[0062] In this case, to ensure that the power supply to the controller U1 is not lower than the minimum operating voltage threshold required by it, in a preferred embodiment, when the voltage of the power supply terminal VCC is less than or equal to the third voltage threshold VCC_Min, control the operating state of the constant current source Ist to be on, and control the first switch Q3 to conduct, including: In the current switching cycle of the internal clock signal, if the voltage of the power supply terminal VCC is less than or equal to the third voltage threshold VCC_Min, control the operating state of the constant current source Ist to be on; In the switching cycle after the internal clock signal enters the current switching cycle, control the first switch Q3 to conduct, and the first switch Q3 conducts before the NMOS lower transistor.

[0063] It should be understood that when the voltage at the power supply terminal is less than or equal to the third voltage threshold, the constant current source Ist and the first switch Q3 will work simultaneously. The constant current source Ist will turn off when the voltage of the power supply terminal VCC is greater than or equal to the first voltage threshold VCC_L, but the first switch Q3 will still conduct in the subsequent switching cycle, enabling the controller U1 to perform lossless self-power supply until the voltage of the power supply terminal is greater than or equal to the second voltage threshold.

[0064] Now, in combination with Figure 4 to Figure 3 illustrate the working effect of the power circuit shown, Figure 4 is Figure 3 the working waveform diagram of the power circuit shown, where: VCC can be understood as the voltage of the power supply terminal VCC; VCC_ON can be understood as the startup voltage; VCC_H can be understood as the second voltage threshold VCC_H; VCC_L can be understood as the first voltage threshold VCC_L; VCC_Min can be understood as the third voltage threshold VCC_Min; EN can be understood as the first control signal for controlling the working state of the constant current source Ist; Clock can be understood as the internal clock signal; CH can be understood as the second control signal for controlling the on / off of the first switch Q3; Gate can be understood as the gate control signal for controlling the on / off of the NMOS lower transistor Q2; Id can be understood as the current flowing through the primary winding Np; Ivcc can be understood as the current flowing through the first switch Q3; Is can be understood as the current flowing through the D pole of the NMOS lower transistor; Vm can be understood as the voltage of the first node m.

[0065] It can be seen that from time t0 to t1, the power circuit is in the initial power-on stage. Since the constant current source Ist is default in the on state and the first switch Q3 is in the off state, the input voltage Vin charges the chip power supply capacitor Cvcc through the J-FET upper transistor Q1 and the constant current source Ist; At time t1, the voltage of the power supply terminal VCC reaches the startup voltage VCC_ON, and the controller U1 starts to work normally and controls the working state of the constant current source Ist to the off state to reduce the static loss; At time t2, the internal clock signal is at a high level, and the gate drive signal is set high, causing the NMOS lower transistor Q2 to conduct. The voltage of the first node m rapidly decreases, and the current flowing through the primary winding Np and the current flowing through the D pole of the NMOS lower transistor both linearly increase at a slope of Vin / Lp, where Vin is the input voltage Vin and Lp is the inductance of the primary winding Np; At time t3, the gate drive signal is turned off, causing the NMOS lower transistor Q2 to cut off. When the voltage of the first node m rises above the pinch-off voltage threshold Vth of the J-FET transistor, the J-FET transistor is turned off, and the current flowing through the primary winding Np and the current flowing through the D pole of the NMOS lower transistor decrease to zero; At time t4, when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, the controller U1 enables the power supply self-power supply function, that is, the second control signal is set high, causing the first switch Q3 to conduct. The voltage of the first node m is clamped to a voltage close to the power supply terminal VCC. At the same time, since the voltage of the power supply terminal VCC is lower than the pinch-off threshold Vth of the J-FET transistor, the J-FET transistor is also turned on again. In this case, the current in the inductor Lp of the primary winding Np linearly increases at a slope of (Vin - VCC) / Lp and charges the VCC capacitor through the first switch Q3. The voltage drop of this conduction path is extremely low, and the controller U1 realizes lossless self-power supply.

[0066] At time t5, the gate drive signal is set high again, and the NMOS lower transistor Q2 conducts again. The inductor Lp current continues to increase at a slope of Vin / Lp. Although the second control signal remains set high, the current flowing through the first switch Q3 drops to zero, and the voltage of the first node m is pulled to close to zero volts; At time t6, the second control signal is turned off, and the gate drive signal remains set high; At time t7, the gate drive signal is turned off, causing the NMOS lower transistor Q2 to cut off. The voltage of the first node m rises above the pinch-off threshold Vth of the J-FET transistor again, thereby causing the J-FET transistor to turn off, and the inductor current Id rapidly drops to zero; During the time from t7 to t8, the circuit enters the CCM operating state. During this period, the controller U1 can still perform lossless self-power supply; At time t8, the voltage of the power supply terminal VCC rises to the second voltage threshold VCC_H, completing the self-power supply charging. After that, when the clock signal Clock triggers, the CH signal is no longer turned on; During the time from t8 to t9, the power circuit enters the light load state, and the controller U1 can still perform lossless self-power supply when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L; At time t9, the lossless self-power supply cannot meet the charging demand, and the voltage of the power supply terminal VCC drops to the third voltage threshold VCC_Min (which can be understood as the minimum operating voltage threshold of the controller U1). The controller U1 starts to set the first control signal high to turn on the constant current source Ist, and immediately makes the controller U1 enter the lossy self-power supply mode, and when the internal clock signal enters the next switching cycle, the second control signal is set high to control the first switch Q3 to turn on.

[0067] At time t10, the chip power supply capacitor Cvcc is charged to the first voltage threshold VCC_L, and the first control signal is controlled to be turned off, so that the controller U1 enters the lossless self-power supply mode.

[0068] At time t11, the chip power supply capacitor Cvcc is charged to the second voltage threshold VCC_H, and the second control signal is controlled to be turned off to stop charging the chip power supply capacitor Cvcc.

[0069] At time t12, the internal clock signal is at a high level, the gate drive signal is set high, and the circuit enters the next period of working cycle.

[0070] In summary, the present invention performs lossy self-powering only when the power circuit is just powered on and the lossless self-powering such as light load cannot meet the power supply requirements, and performs lossless self-powering when the power circuit enters medium or heavy load, so that the power supply end VCC has a very stable supply voltage, while improving the power supply efficiency of the power circuit.

[0071] In order to coordinate the conduction timing of the first switch Q3 and the NMOS lower tube Q2, in one implementation, when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, the method of controlling the first switch Q3 to be turned on until the voltage of the power supply terminal VCC is greater than or equal to the second voltage threshold VCC_H includes: In the current switching cycle of the internal clock signal, if the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, the first switch Q3 is controlled to remain in the off state.

[0072] This is because the state of the first switch can be refreshed only when the internal clock signal enters a new cycle.

[0073] When the internal clock signal enters a switching cycle after the current switching cycle, if the voltage of the power supply terminal VCC is less than the second voltage threshold VCC_H, the following steps are performed in each switching cycle of the internal clock signal until the voltage of the power supply terminal VCC is greater than or equal to the second voltage threshold VCC_H: The first switch Q3 and the NMOS lower tube Q2 are controlled to be turned on in sequence.

[0074] It should be understood that in each cycle, the first switch Q3 turns on before the NMOS lower transistor Q2.

[0075] After the NMOS lower transistor Q2 conducts, control the first switch Q3 to turn off.

[0076] It should be understood that the present invention does not limit the on-time and off-time of the first switch Q3. The first switch Q3 can be in the on state simultaneously with the NMOS transistor, as long as the first switch Q3 is in the on state before the NMOS transistor and the first switch Q3 is turned off when the NMOS transistor is in the on state, then it is within the protection scope of the present invention.

[0077] In a preferred embodiment, when the internal clock signal enters the switch cycle after the current switch cycle, if the voltage of the power supply terminal VCC is less than the second voltage threshold VCC_H, then control the first switch Q3 to turn on at the start of each switch cycle of the internal clock signal.

[0078] In a specific embodiment, after the NMOS lower transistor conducts, controlling the first switch to turn off includes: Control the first switch and the NMOS lower transistor to turn off simultaneously.

[0079] Of course, the present invention does not limit this. In another specific embodiment, the NMOS lower transistor can also be controlled to turn off after the first switch is turned off.

[0080] In this case, now in combination with Figure 5 For Figure 3 The working effect of the shown power circuit is described. Figure 5 Is Figure 3 The working waveform diagram of the shown power circuit, where: VCC can be understood as the voltage of the power supply terminal VCC; VCC_H can be understood as the second voltage threshold VCC_H; VCC_L can be understood as the first voltage threshold VCC_L; VCC_Min can be understood as the third voltage threshold VCC_Min; EN can be understood as the first control signal for controlling the working state of the constant current source Ist; Clock can be understood as the internal clock signal; CH can be understood as the second control signal for controlling the on / off of the first switch Q3; Gate can be understood as the gate control signal for controlling the on / off state of the NMOS lower transistor Q2; Vm can be understood as the voltage of the first node m; Id can be understood as the current flowing through the primary winding Np; Is can be understood as the drain current of the NMOS lower transistor Q2.

[0081] It can be seen that at time t1, when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, the first switch Q3 is kept off; At time t2, when the internal clock signal enters the next switching cycle, the controller U1 controls the first switch Q3 to conduct; At time t3, control the NMOS lower transistor Q2 to conduct; At time t4, control the first switch Q3 to turn off.

[0082] In summary, in this control method, the present invention avoids unnecessary on / off switching of the J-FET Q1 switch and reduces switching losses and interference by controlling the NMOS lower transistor Q2 to turn off after the first switch Q3 turns off.

[0083] It should be understood that the first switch Q3 can be turned off at any time when the NMOS lower transistor Q2 is conducting.

[0084] In another embodiment, when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, the method of controlling the first switch Q3 to conduct until the voltage of the power supply terminal VCC is greater than or equal to the second voltage threshold VCC_H includes: In the current switching cycle of the internal clock signal, if the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L, then control the first switch Q3 to remain in the off state; When the internal clock signal enters the switching cycle after the current switching cycle, if the voltage of the power supply terminal VCC is less than the second voltage threshold VCC_H, then perform the following steps in each switching cycle of the internal clock signal until the voltage of the power supply terminal VCC is greater than or equal to the second voltage threshold VCC_H: Control the first switch Q3 to conduct or the NMOS lower transistor Q2 to conduct.

[0085] It can be seen that in this method, the first switch Q3 and the NMOS lower transistor Q2 adopt an either-or control strategy, and only the first switch Q3 or the NMOS lower transistor Q2 can conduct within one switching cycle.

[0086] To ensure timely charging of the power supply capacitor Cvcc for the chip, in a specific embodiment, when the internal clock signal enters the first switching cycle after the current switching cycle, the first switch Q3 is controlled to conduct.

[0087] In this case, now in combination with Figure 6 for Figure 3 the working effect of the power circuit shown is described. Figure 6 is Figure 3 the working waveform diagram of the power circuit shown, where: VCC can be understood as the voltage of the power supply terminal VCC; VCC_H can be understood as the second voltage threshold VCC_H; VCC_L can be understood as the first voltage threshold VCC_L; VCC_Min can be understood as the third voltage threshold VCC_Min; EN can be understood as the first control signal for controlling the working state of the constant current source Ist; Clock can be understood as the internal clock signal; CH can be understood as the second control signal for controlling the on / off of the first switch Q3; Gate can be understood as the gate control signal for controlling the on / off of the NMOS lower transistor Q2; Vm can be understood as the voltage of the first node m; Id can be understood as the current flowing through the primary winding Np; Is can be understood as the drain current of the NMOS lower transistor Q2.

[0088] It can be seen that when it is necessary to charge the power supply capacitor Cvcc for the chip, the present invention adopts the method of turning on the first switch Q3 or the NMOS lower transistor Q2 within the switching cycle. This switching strategy of the single-cycle one-of-two selection mode simplifies the control difficulty.

[0089] In summary, the present invention simplifies the peripheral circuit required for the power supply terminal VCC, and solves the problems such as the wide power supply voltage range of the traditional power supply terminal VCC and the low power supply efficiency of the power circuit when full-load high-voltage output.

[0090] In actual work, please refer to Figure 6 In one embodiment, the primary circuit may further include an RCD absorption module, and the RCD absorption module includes a second resistor R2, a second capacitor C2, and a third diode; The first end of the primary winding Np is respectively coupled to the first end of the second capacitor C2 and the first end of the second resistor R2. The second end of the second capacitor C2 is respectively coupled to the second end of the second resistor R2 and the cathode of the third diode. The anode of the third diode is coupled to the second end of the primary winding Np.

[0091] In practical applications, please refer to Figure 7 , the primary circuit further includes a power supply side capacitor Cin, and the first end of the primary winding Np is grounded through the power supply side capacitor Cin.

[0092] Based on this, the controller U1 provided by the present invention will be further elaborated.

[0093] During actual operation, the controller U1 also has a protection function. In a specific implementation manner, please continue to refer to Figure 7 , the power circuit further includes a secondary circuit and a first circuit that are magnetically coupled to the primary winding Np respectively; The secondary circuit is used to sense the magnetic flux change of the primary winding Np and output an output voltage Vo; The first circuit is used to sense the magnetic flux change of the primary winding Np and output a first feedback signal VMS; The fourth terminal VMS of the controller U1 receives the first feedback signal VMS, and the controller U1 is further configured to: based on the first feedback signal VMS and the on / off state of the NMOS lower transistor Q2, control the working state of the power circuit, where: When controlling the NMOS lower transistor Q2 to conduct, obtain the voltage value of the first feedback signal VMS, and based on the voltage value of the first feedback signal VMS, control whether the primary circuit enters a protection state; When controlling the NMOS lower transistor Q2 to disconnect, obtain the voltage value and current value of the first feedback signal VMS, and when the voltage value of the first feedback signal VMS is less than or equal to the fourth voltage threshold, based on the current value of the first feedback signal, control whether the secondary circuit enters a protection state.

[0094] It can be seen that in this embodiment, when the NMOS lower transistor Q2 conducts, the controller U1 can monitor and protect the circuit on the input voltage Vin side. Generally, the protection state may include an overvoltage monitoring protection (Brown-in) state, an undervoltage monitoring protection (Brown-out) state, and an input overvoltage protection (OVP) state.

[0095] When the NMOS lower transistor Q2 is turned off, the controller U1 can monitor and protect the circuit on the output voltage Vo side. Generally, the protection status may include an output overvoltage protection (OVP) status and an output undervoltage protection (UVP) status.

[0096] It should be understood that the above-mentioned controller U1 can only determine whether the primary circuit enters the protection state when the NMOS lower transistor Q2 is turned on. In a preferred embodiment, please refer to Figure 7 The seventh terminal of the controller U1 is also coupled to the first node m; The controller U1 is further configured to control whether the primary circuit enters the protection state based on the voltage value and / or current value of the first node m.

[0097] Specifically, the controller U1 can detect the voltage and / or current conditions of the first node m in real time through a built-in comparator or a sampling circuit, and turn off the NMOS lower transistor Q2 when the voltage value and / or current value exceeds the corresponding set voltage and / or set current to achieve protection and prevent system damage. This technology is prior art and will not be elaborated herein.

[0098] In a specific embodiment, please refer to Figure 7 The secondary circuit includes a secondary winding Ns, a second diode D2, a first capacitor C1, and a first resistor R1; The first output terminal of the secondary winding Ns is coupled to the first end of the first capacitor C1 through the second diode D2. The second end of the first capacitor C1 is coupled to the second output terminal of the secondary winding Ns, and the first capacitor C1 is in parallel with the first resistor R1.

[0099] Please continue to refer to Figure 7 In one embodiment, the first circuit includes a first winding, a first voltage-dividing resistor Rup, and a second voltage-dividing resistor Rdw; The first output terminal of the first winding is coupled to the first end of the first voltage-dividing resistor Rup. The second end of the first voltage-dividing resistor Rup and the first end of the second voltage-dividing resistor Rdw are coupled through a second node. The second end of the second voltage-dividing resistor Rdw is coupled to the second output terminal of the first winding, and the second node is coupled to the fourth terminal of the controller U1 for outputting the first feedback signal VMS.

[0100] In this case, when controlling the NMOS lower transistor Q2 to be turned on, the voltage value of the first feedback signal VMS , where N1 is the number of turns of the first winding, N p is the number of turns of the primary winding Np, is the resistance value of the first voltage-dividing resistor Rup, is the resistance value of the second voltage dividing resistor Rdw.

[0101] After the NMOS lower transistor Q2 is turned off, when the circuit enters the excitation inductor reset period, the controller U1 internally clamps the voltage of the VMS pin to a relatively low voltage, such as zero volts or 0.1V, etc. In this case, by sampling the current signal of the first feedback signal VMSVMS, the output voltage signal can be obtained, and there is a relational expression for this current value , where Vo is the voltage value of the output voltage, and Ns is the number of turns of the secondary winding Ns.

[0102] In Figure 7 example, the first winding is the auxiliary winding Naux, and the polarity of the auxiliary winding Naux is opposite to that of the secondary winding Ns.

[0103] In a preferred embodiment, the power circuit may further include an electromagnetic shielding circuit ( Figure 7 not shown in the figure), the electromagnetic shielding circuit includes an EMI shielding layer winding, the first output terminal of the EMI shielding layer winding N-E_shield is left floating NC, and its second output terminal is a fixed potential point.

[0104] As an example, this fixed potential point can be ground or an EMI static point voltage, such as a relatively fixed potential point like VCC, Vin, etc.

[0105] In another embodiment, please refer to Figure 8 , the first winding can also be the EMI shielding layer winding N-E_shield, and the polarity of the first winding is opposite to that of the secondary winding Ns.

[0106] It can be seen that the present invention ingeniously utilizes the original shielding layer winding of the transformer to undertake the functions of input voltage Vin sampling and output voltage Vo sampling, further simplifying the design of the power circuit without adding any additional windings or optocoupler devices.

[0107] In actual operation, the frequency of the internal clock signal changes with the change of the load size. Generally, the heavier the load, the higher the frequency of the internal clock signal, and the lighter the load, the lower the frequency of the internal clock signal. On this basis, please refer to Figure 7 , the eighth terminal FB of the controller U1 also receives the output voltage Vo, and the controller U1 is further configured to: control the frequency of the internal clock signal based on the voltage value of the output voltage Vo.

[0108] On this basis, in a specific embodiment, please continue to refer to Figure 7 , the secondary circuit further includes a first feedback module 10, and the primary circuit further includes a second feedback module 20; The first feedback module 10 is connected in parallel with the first capacitor C1. The first feedback module 10 is used to obtain the output voltage Vo and output a second feedback signal, and the second feedback signal includes voltage value information of the output voltage Vo. The first end of the second feedback module 20 is coupled to the eighth end FB of the controller U1, the second end of the second feedback module 20 is grounded, the receiving end of the second feedback module 20 receives the second feedback signal, and the second feedback module 20 is used to transfer the voltage value information of the output voltage Vo to the controller U1.

[0109] As an example, the first feedback module 10 may be the output end of an optocoupler, and the second feedback module 20 may be the receiving end of an optocoupler. Of course, the present invention does not limit this, and those skilled in the art can select appropriate components according to needs.

[0110] In actual operation, the controller U1 also controls the conduction time of the NMOS lower transistor Q2. In a specific implementation, please refer to Figure 7 , the primary circuit further includes a current sampling module. The current sampling module is used to obtain the magnitude of the current flowing through the first node m and output a third feedback signal to the fifth end Vcs of the controller U1, and the third feedback signal includes current value information of the current flowing through the first node m. The controller U1 is further configured to: based on the third feedback signal, determine the conduction moment and the disconnection moment of the NMOS lower transistor Q2 in each switching cycle of the internal clock signal.

[0111] In Figure 7 's example, the current sampling module includes a first NMOS transistor NM1 and a sampling resistor Rsns; The gate of the first NMOS transistor NM1 is coupled to the control end of the NMOS lower transistor Q2, the drain of the first NMOS transistor NM1 is coupled to the sixth end of the controller U1, its source is grounded, the first end of the sampling resistor Rsns is coupled to the fifth end Vcs of the controller U1, and its second end is grounded; The controller U1 is further configured to: output a first current to the fifth end Vcs of the controller U1 and obtain the voltage value of the first end of the sampling resistor Rsns, and the current value of the first current is equal to the current value of the current flowing through the sixth end of the controller U1.

[0112] Of course, the present invention does not limit the method of obtaining the current flowing through the first node m. In other implementations, please refer to Figure 8, the current sampling module includes a sampling resistor Rsns, the sampling resistor Rsns is connected in series between the first node m and the drain of the NMOS lower transistor Q2, and the fifth terminal Vcs of the controller U1 is used to obtain the voltage across the sampling resistor Rsns to obtain the current value information of the current flowing through the first node m.

[0113] In actual work, please refer to Figure 8 , the primary circuit further includes a rectification module 30 and a power extraction module 40, the power supply side capacitor Cin is connected in parallel with the rectification module 30, the input terminals of the rectification module 30 and the power extraction module 40 are both coupled to the AC power supply, and the output terminal of the power extraction module 40 is coupled to the high-voltage power extraction terminal of the controller U1.

[0114] In this case, the controller U1 is configured to: when the voltage value of the AC power supply is less than the fifth voltage threshold and the voltage value of the AC power supply is greater than or equal to 0, control the first switch Q3 to conduct, or control the working state of the constant current source Ist to be in the on state and control the first switch Q3 to conduct.

[0115] This embodiment can be understood as that when the chip power supply capacitor Cvcc needs to be charged, the controller U1 is configured to control the working state of the constant current source Ist and the first switch Q3 to conduct only near the zero crossing of the alternating current to complete power extraction.

[0116] Specifically, when the voltage of the power supply terminal VCC is less than or equal to the first voltage threshold VCC_L and near the zero crossing of the alternating current of the AC power supply, control the first switch Q3 to conduct; When the voltage of the power supply terminal VCC is less than or equal to the third voltage threshold VCC_Min and near the zero crossing of the alternating current of the AC power supply, control the first switch Q3 to conduct and control the working state of the constant current source Ist to be in the on state.

[0117] In this way, the present invention can further optimize the power supply efficiency of the power circuit.

[0118] In a specific embodiment, please continue to refer to Figure 8 , the AC power supply includes an AC live wire ACL and an AC neutral wire ACN, and the power extraction module 40 includes a fourth diode D4, a fifth diode D5 and a third resistor Rhv; The negative electrode of the fourth diode D4 and the positive electrode of the fifth diode D5 are respectively coupled to the AC live wire ACL and the AC neutral wire ACN. The negative electrodes of the fourth diode D4 and the fifth diode D5 are both coupled to the first end of the third resistor Rhv, and the second end of the third resistor Rhv is coupled to the high-voltage power-taking terminal HV of the controller U1.

[0119] In summary, in the embodiment of the present invention, the primary winding of the power circuit where the self-powered chip system is located receives the input voltage at one end, and the other end is grounded through the J-FET upper tube, the first node, and the NMOS lower tube in sequence. The control terminal of the J-FET upper tube is grounded. One end of the chip power supply capacitor of the self-powered chip system is grounded, and the other end is coupled to the first node through the default-conduction constant current source and the first switch respectively. The chip power supply capacitor supplies power to the power supply terminal of the controller. Since the required power supply voltage of the controller is less than the pinch-off voltage of the J-FET upper tube, the present invention self-supplies power to the controller through the constant current source during power-on, performs lossless self-power supply to the controller by controlling the first switch to conduct when the voltage at the power supply terminal is less than or equal to the first voltage threshold, and self-supplies power to the controller by simultaneously controlling the constant current source and the first switch to conduct when the voltage at the power supply terminal is less than or equal to the third voltage threshold. This not only simplifies the power supply circuit of the controller but also improves the power supply efficiency of the circuit.

[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A self-powered chip system, characterized in that, The system is applied to a power circuit, and the power circuit includes a primary circuit. The primary circuit includes a primary winding, a J-FET upper transistor, and an NMOS lower transistor. The first end of the primary winding receives an input voltage, and its second end is grounded through the J-FET upper transistor and the NMOS lower transistor in sequence. The control end of the J-FET upper transistor is coupled to the ground, and the J-FET upper transistor and the NMOS lower transistor are coupled through a first node. The self-powered chip system includes: a chip power supply capacitor, a constant current source, a first switch, and a controller. The constant current source is default in the on state. The first end of the chip power supply capacitor is grounded, and its second end is coupled to the first node through the constant current source and the first switch respectively. The power supply end of the controller is coupled to the second end of the chip power supply capacitor, its first end is coupled to the control end of the constant current source, and its second end is coupled to the control end of the first switch. The controller is configured to: enter the normal working state when the voltage at the power supply end reaches the startup voltage, and control the constant current source to enter the off state. The startup voltage is less than the pinch-off voltage of the J-FET upper transistor. After entering the normal working state, based on the voltage at the power supply end, control the working state of the constant current source and the on / off of the first switch, where: When the voltage at the power supply end is less than or equal to a first voltage threshold, control the first switch to conduct until the voltage at the power supply end is greater than or equal to a second voltage threshold. The startup voltage is greater than the second voltage threshold, and the second voltage threshold is greater than the first voltage threshold. When the voltage at the power supply end is less than or equal to a third voltage threshold, control the constant current source to be in the on state until the voltage at the power supply end is greater than or equal to the first voltage threshold. The third voltage threshold is less than the first voltage threshold.

2. The self-powered chip system according to claim 1, characterized in that, The third end of the controller is coupled to the control end of the NMOS lower transistor. The controller is further configured to: generate an internal clock signal when the controller is in the normal working state; and Control the on / off of the NMOS lower transistor based on the internal clock signal.

3. The self-powered chip system according to claim 2, characterized in that, The method of controlling the first switch to conduct when the voltage at the power supply end is less than or equal to the first voltage threshold until the voltage at the power supply end is greater than or equal to the second voltage threshold includes: In the current switching cycle of the internal clock signal, if the voltage at the power supply end is less than or equal to the first voltage threshold, control the first switch to remain in the off state; When the internal clock signal enters the switching cycle after the current switching cycle, if the voltage at the power supply end is less than the second voltage threshold, perform the following steps in each switching cycle of the internal clock signal until the voltage at the power supply end is greater than or equal to the second voltage threshold: Control the first switch to conduct and the NMOS lower transistor to conduct in sequence; After the NMOS lower transistor conducts, control the first switch to disconnect.

4. The self-powered chip system according to claim 3, characterized in that, Control the first switch to conduct at the beginning of the switching cycle.

5. The self-powered chip system according to claim 3, characterized in that, After the NMOS lower transistor conducts, controlling the first switch to disconnect includes: Control the first switch and the lower NMOS transistor to be turned off simultaneously.

6. The self-powered chip system according to claim 3, characterized in that, After the first switch is turned off, control the lower NMOS transistor to be turned off.

7. The self-powered chip system according to claim 2, characterized in that, A method for controlling the first switch to be turned on until the voltage of the power supply terminal is greater than or equal to the second voltage threshold when the voltage of the power supply terminal is less than or equal to the first voltage threshold, includes: In the current switching cycle of the internal clock signal, if the voltage of the power supply terminal is less than or equal to the first voltage threshold, control the first switch to remain in the off state; In the switching cycle after the internal clock signal enters the current switching cycle, if the voltage of the power supply terminal is less than the second voltage threshold, perform the following steps in each switching cycle of the internal clock signal until the voltage of the power supply terminal is greater than or equal to the second voltage threshold: Control the first switch to be turned on or the lower NMOS transistor to be turned on.

8. The self-powered chip system according to claim 7, characterized in that, In the first switching cycle after the internal clock signal enters the current switching cycle, control the first switch to be turned on.

9. The self-powered chip system according to claim 2, characterized in that, A method for controlling the working state of the constant current source to be on when the voltage of the power supply terminal is less than or equal to the third voltage threshold, includes: In the current switching cycle of the internal clock signal, if the voltage of the power supply terminal is less than or equal to the third voltage threshold, control the working state of the constant current source to be on; In the switching cycle after the internal clock signal enters the current switching cycle, control the first switch to be turned on, and the first switch is turned on prior to the lower NMOS transistor.

10. The self-powered chip system according to claim 1, characterized in that, The self-powered chip system further includes a first diode; the negative electrode of the first diode is coupled to the second end of the chip power supply capacitor, The positive electrode of the first diode is coupled to the first node through the first switch.

11. The self-powered chip system according to any one of claims 2 to 10, characterized in that, The power circuit further includes a secondary circuit and a first circuit that are magnetically coupled to the primary winding respectively; The secondary circuit is configured to sense the change in magnetic flux of the primary winding and output an output voltage; The first circuit is configured to sense the change in magnetic flux of the primary winding and output a first feedback signal; The fourth terminal of the controller receives the first feedback signal, and the controller is further configured to: based on the first feedback signal and the on / off state of the lower NMOS transistor, control the working state of the power circuit, where: When controlling the lower NMOS transistor to be turned on, obtain the voltage value of the first feedback signal, and based on the voltage value of the first feedback signal, control whether the primary circuit enters the protection state; When controlling the lower NMOS transistor to be turned off, obtain the voltage value and the current value of the first feedback signal, and when the voltage value of the first feedback signal is less than or equal to the fourth voltage threshold, based on the current value of the first feedback signal, control whether the secondary circuit enters the protection state.

12. The self-powered chip system according to claim 11, characterized in that, The first circuit includes a first winding, a first voltage dividing resistor, and a second voltage dividing resistor; The first output terminal of the first winding is coupled to the first end of the first voltage dividing resistor. The second end of the first voltage dividing resistor and the first end of the second voltage dividing resistor are coupled through a second node. The second end of the second voltage dividing resistor is coupled to the second output terminal of the first winding. The second node is coupled to the fourth terminal of the controller for outputting the first feedback signal.

13. The self-powered chip system according to claim 12, characterized in that, The secondary circuit includes a secondary winding, a second diode, a first capacitor, and a first resistor. The first output terminal of the secondary winding is coupled to the first end of the first capacitor through the second diode. The second end of the first capacitor is coupled to the second output terminal of the secondary winding. The first capacitor is in parallel with the first resistor.

14. The self-powered chip system according to claim 13, characterized in that, The first winding is an EMI shielding layer winding, and the polarity of the first winding is opposite to that of the secondary winding.

15. The self-powered chip system according to claim 13, characterized in that, The first winding is an auxiliary winding.

16. The self-powered chip system according to claim 13, characterized in that, The eighth terminal of the controller receives the output voltage. The controller is further configured to: based on the voltage value of the output voltage, control the frequency of the internal clock signal.

17. The self-powered chip system according to claim 16, characterized in that, The secondary circuit further includes a first feedback module, and the primary circuit further includes a second feedback module. The first feedback module is in parallel with the first capacitor. The first feedback module is used to obtain the output voltage and output a second feedback signal, and the second feedback signal includes the voltage value information of the output voltage. The first end of the second feedback module is coupled to the eighth terminal of the controller, the second end of the second feedback module is grounded, and the receiving end of the second feedback module receives the second feedback signal. The second feedback module is used to transfer the voltage value information of the output voltage to the controller.

18. The self-powered chip system according to any one of claims 2 to 10, characterized in that, The primary circuit further includes a current sampling module. The current sampling module is used to obtain the magnitude of the current flowing through the first node and output a third feedback signal to the fifth terminal of the controller. The third feedback signal includes the current value information of the current flowing through the first node. The controller is further configured to: based on the third feedback signal, determine the on-time and off-time of the NMOS lower transistor in each switching cycle of the internal clock signal.

19. The self-powered chip system according to claim 18, characterized in that, The current sampling module includes a first NMOS transistor and a sampling resistor. The gate of the first NMOS transistor is coupled to the control terminal of the NMOS lower transistor. The drain of the first NMOS transistor is coupled to the sixth terminal of the controller, and its source is grounded. The first end of the sampling resistor is coupled to the fifth terminal of the controller, and its second end is grounded. The controller is further configured to: output a first current to the fifth terminal of the controller and obtain the voltage value at the first end of the sampling resistor. The current value of the first current is equal to the current value of the current flowing through the sixth terminal of the controller.

20. The self-powered chip system according to claim 18, characterized in that, The current sampling module includes a sampling resistor. The sampling resistor is connected in series between the first node and the drain of the NMOS lower transistor. The fifth terminal of the controller is used to obtain the voltage across the sampling resistor to obtain the current value information of the current flowing through the first node.

21. The self-powered chip system according to claim 1, characterized in that, The primary side circuit further includes an RCD absorption module, and the RCD absorption module includes a second resistor, a second capacitor, and a third diode; The first end of the primary winding is respectively coupled to the first end of the second capacitor and the first end of the second resistor. The second end of the second capacitor is respectively coupled to the second end of the second resistor and the cathode of the third diode. The anode of the third diode is coupled to the second end of the primary winding.

22. The self-powered chip system according to claim 1, characterized in that, The primary side circuit further includes a power supply side capacitor, and the first end of the primary winding is grounded through the power supply side capacitor.

23. The self-powered chip system according to claim 22, wherein, The primary side circuit further includes a rectification module and a power extraction module. The power supply side capacitor is connected in parallel with the rectification module. The input ends of the rectification module and the power extraction module are both coupled to an AC power supply. The output end of the power extraction module is coupled to the high-voltage power extraction end of the controller; The controller is configured to: when the voltage value of the AC power supply is less than a fifth voltage threshold and the voltage value of the AC power supply is greater than or equal to 0, control the first switch to conduct, or control the working state of the constant current source to be on and control the first switch to conduct.

24. The self-powered chip system according to claim 23, wherein, The AC power supply includes an AC live wire and an AC neutral wire, and the power extraction module includes a fourth diode, a fifth diode, and a third resistor; The cathode of the fourth diode and the anode of the fifth diode are respectively coupled to the AC live wire and the AC neutral wire. The cathode of the fourth diode and the cathode of the fifth diode are both coupled to the first end of the third resistor. The second end of the third resistor is coupled to the high-voltage power extraction end of the controller.

25. The self-powered chip system according to claim 1, wherein, The self-powered chip system further includes a turn-on / off speed control module, and the turn-on / off speed control module includes a sixth diode and a fourth resistor; The first end of the fourth resistor is coupled to the control end of the J-FET upper tube, and its second end is coupled to the anode of the sixth diode; the cathode of the sixth diode is coupled to the second end of the fourth resistor.

26. The self-powered chip system according to claim 1, wherein, The seventh end of the controller is further coupled to the first node; The controller is further configured to control whether the primary side circuit enters a protection state based on the voltage value and / or current value of the first node.

27. The self-powered chip system according to claim 1, wherein, The constant current source also has a current limiting function.

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