A gain-boosted floating inverting dynamic amplifier circuit

Abstract

The present invention discloses a gain-boosted floating inverting dynamic amplifier circuit, which relates to the field of integrated circuit technology. The circuit includes a power supply, a main amplifier, a first auxiliary amplifier, and a second auxiliary amplifier. The main amplifier and the auxiliary amplifier both adopt a common-source and common-gate floating inverting dynamic amplifier structure. The main amplifier includes a first power supply capacitor, a second power supply capacitor, a plurality of first common-source transistors, and a plurality of first common-gate transistors. The plurality of drains of the plurality of first common-source transistors are respectively connected to the input terminals of the first auxiliary amplifier and the second auxiliary amplifier, and the plurality of gates of the first common-gate transistors are respectively connected to the output terminals of the first auxiliary amplifier and the second auxiliary amplifier. The first auxiliary amplifier and the second auxiliary amplifier both include a plurality of second common-gate transistors, and the plurality of gates of the second common-gate transistors are directly connected to the common-mode voltage. The amplifier circuit of the present invention improves the gain of the amplifier while ensuring speed and stability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a gain-boosted floating inverting dynamic amplifier circuit. Background Art

[0002] Analog-to-digital converters (ADCs) convert real-world analog signals into digital signals and play a crucial role in modern electronic information systems. Most ADCs, such as pipeline ADCs and Delta-Sigma ADCs, rely on amplifiers to perform internal functions such as signal amplification and integration. Amplifier performance, such as noise, gain, and power consumption, largely determines key ADC specifications such as overall accuracy and power consumption. Therefore, improving amplifier performance and reducing power consumption are crucial for ADC design in systems such as sensor networks and biomedical devices.

[0003] As integrated circuit feature sizes continue to shrink, device characteristic frequencies continue to increase, and power supply voltages continue to decrease, significantly improving ADC power efficiency. However, due to thermal noise limitations, the amplifier has become the primary source of ADC power consumption. To reduce power consumption, clock-controlled dynamic amplifier structures have been adopted in ADC design in recent years. Dynamic amplifiers consume no static current and only generate dynamic power during specific clock phases, significantly reducing overall power consumption. However, traditional dynamic amplifier structures have low gain and can only operate in open-loop mode. These structures are significantly affected by PVT fluctuations (PVT)—including process, power supply voltage, and temperature—making them difficult to maintain stable performance. Furthermore, the noise, offset, and speed performance of traditional dynamic amplifiers are heavily dependent on the input common-mode voltage, which severely limits ADC accuracy when used in ADCs.

[0004] In recent years, a floating inverter amplifier (FIA) has emerged. This structure uses a floating energy storage capacitor to power an amplifier, reducing power consumption while providing a certain amount of gain to facilitate the construction of a closed-loop amplification structure and improve the amplifier's ability to suppress PVT fluctuations. Furthermore, the FIA's inherent ability to suppress input common-mode fluctuations makes it ideal for use in low-power ADCs.

[0005] However, existing single-stage FIAs have low gain (typically below 60dB), making it difficult to achieve precise closed-loop amplification or integration, and thus unable to meet the design requirements of high-precision Delta-Sigma ADCs and pipeline ADCs. While cascading two or more FIAs can increase gain, multi-stage circuits create multiple low-frequency poles, significantly affecting circuit speed and potentially causing system instability. Therefore, cascaded FIAs are difficult to implement in practical ADCs. Therefore, increasing the gain of dynamic amplifiers like FIAs while maintaining speed and stability has become a key issue in designing efficient and high-precision ADCs. Summary of the Invention

[0006] Based on the defects of the above-mentioned existing technologies, the present invention provides a gain-boosted floating inverting dynamic amplifier circuit, which solves the problem that the existing cascade FIA ​​ADC design scheme can improve the gain, but the multi-stage circuit will produce multiple low-frequency poles, which significantly affects the circuit speed and may cause system instability.

[0007] The present invention adopts the following technical solutions:

[0008] The present invention provides a gain-boosted floating inverting dynamic amplifier circuit, comprising a main amplifier, a first auxiliary amplifier and a second auxiliary amplifier;

[0009] The main amplifier includes a first power supply capacitor C RES31 , the second power supply capacitor C RES32 , multiple first common-source transistors, multiple first common-gate transistors, a first control switch, a second control switch, a third control switch, a fourth control switch and a fifth control switch; multiple drains of the multiple first common-source transistors are respectively connected to the input terminals of the first auxiliary amplifier and the second auxiliary amplifier, and multiple gates are used to receive input signals; multiple gates of the first common-gate transistors are respectively connected to the output terminals of the first auxiliary amplifier and the second auxiliary amplifier; the first power supply capacitor C RES31 The two ends of the first power supply capacitor and the two ends of the second power supply capacitor are connected through a first control switch, the two ends of the first power supply capacitor and the multiple sources of the first common-source transistor are connected through a third control switch, and the two ends of the second power supply capacitor and the multiple sources of the first common-source transistor are connected through a fourth control switch;

[0010] The first auxiliary amplifier and the second auxiliary amplifier each include a plurality of second common-gate transistors, wherein a plurality of gates of the second common-gate transistors are directly connected to a common-mode level.

[0011] Preferably, the plurality of first common-source transistors include a first transistor Mn31 , the second transistor M n32 , the third transistor M p31 and the fourth transistor M p32 , the first common-gate transistor includes a fifth transistor M cn31 , the sixth transistor M cn32 , the seventh transistor M cp31 and the eighth transistor M cp32 The first control switch includes a first switch s 301 and the second switch s 302 , the second control switch includes a third switch s 303 and the fourth switch s 304 , the third control switch includes a fifth switch s 305 and the sixth switch s 306 , the fourth control switch includes a seventh switch s 307 and the eighth switch s 308 , the fifth control switch includes a ninth switch s 309 and the tenth switch s 310 ;

[0012] The first switch s 301 One end of the switch is connected to the power supply, and the second switch s 302 One end of the first switch s is grounded. 301 and the second switch s 302 The other end of the first power supply capacitor C RES31 The two ends of the third switch s 303 and the fourth switch s 304 One end of each of the first power supply capacitor C RES31 The other end is connected to the second power supply capacitor C RES32 The two ends of the first transistor M are connected; n31 and the second transistor M n32 The source of the sixth switch s 306 and the eighth switch s 308 One end of the third transistor M is connected p31 and the fourth transistor M p32 The source of the fifth switch s 305 and the seventh switch s 307 One end of the fifth switch s 305 and the sixth switch s 306 The other end of the first power supply capacitor C RES31 The two ends of the seventh switch s 307 and the eighth switch s 308 The other end of the second power supply capacitorC RES32 The two ends of the first transistor M are connected; n31 and the third transistor M p31 The gates are connected to each other and are used to input the input signal V in The second transistor M n32 and the fourth transistor M p32 The gates are connected to each other and are used to input the input signal V ip The first transistor M n31 and the second transistor M n32 The drains of the third transistors M are connected to the input terminals of the first auxiliary amplifier, p31 and the fourth transistor M p32 The drains are respectively connected to the input terminals of the second auxiliary amplifier.

[0013] Preferably, the fifth transistor M cn31 and the sixth transistor M cn32 The gates are connected to the output terminals of the first auxiliary amplifier, and the sources are connected to the first transistors M n31 and the second transistor M n32 The drain of the seventh transistor M cp31 and the eighth transistor M cp32 The drains are connected to the output terminals of the second auxiliary amplifier, and the sources are connected to the third transistor M p31 and the fourth transistor M p32 The drain of the fifth transistor M cn31 and the seventh transistor M cp31 The drain of the ninth switch s 309 One end is connected and used to output the output signal V op The sixth transistor M cn32 and the eighth transistor M cp32 The drain of the tenth switch s 310 One end is connected and used to output the output signal V on , the ninth switch s 309 and the tenth switch s 310 The other end is connected to the common-mode level.

[0014] Preferably, the first auxiliary amplifier and the second auxiliary amplifier further include a third power supply capacitor C RES4 , multiple second common-source transistors, a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch and a tenth control switch; the structures of the first auxiliary amplifier and the second auxiliary amplifier both adopt a common-source and common-gate floating inverting dynamic amplifier structure.

[0015] Preferably, the first control signalφ 11 The first control switch is controlled by the second control signal φ 12 The second control switch is controlled by the third control signal φ 21 The third control switch is controlled by the fourth control signal φ 22 The fourth control switch is controlled.

[0016] Preferably, when the first control signal φ 11 When the first control switch is closed, the power supply to the first power supply capacitor C RES31 Charging, while the output node is reset to the common mode level;

[0017] When the second control signal φ 12 When the second control switch is closed, the first power supply capacitor C RES31 and the second power supply capacitor C RES32 Connect in parallel for charge sharing;

[0018] When the third control signal φ 21 When the third control switch is closed, the input signal is input to the gain-boosted floating inverting dynamic amplifier, and the first power supply capacitor C RES31 Power the amplifier to obtain a first-order amplified output signal;

[0019] When the fourth control signal φ 22 When the fourth control switch is closed, the input signal is input to the gain-boosted floating inverting dynamic amplifier, and the first power supply capacitor C RES31 and the second power supply capacitor C RES32 Power the amplifier and obtain the second-order amplified output signal.

[0020] Compared with the prior art, the at least one technical solution adopted by the present invention can achieve the following beneficial effects:

[0021] The present invention proposes a gain-boosted floating inverting dynamic amplifier circuit, comprising a main amplifier, a first auxiliary amplifier, and a second auxiliary amplifier. Both the main amplifier and the auxiliary amplifier adopt a common-source common-gate floating inverting dynamic amplifier structure, so their pole frequencies will change synchronously with the working state of the circuit, ensuring the stability of the circuit. At the same time, the introduction of a common-mode feedback circuit is avoided, reducing the complexity of the circuit. Furthermore, the main amplifier of the present invention comprises a first power supply capacitor and a second power supply capacitor, and two energy storage capacitors are used to achieve reverse-correlated level conversion. By sharing the charge between the power supply capacitors, the power supply voltage during signal amplification is reduced, and the current waste caused by excessive current at the moment of circuit conduction is avoided, thereby effectively improving the current utilization efficiency. The gate of the common-gate device of the main amplifier is connected to the output end of the auxiliary amplifier, which improves the output swing of the overall amplifier. When used in an ADC, the signal range and signal-to-noise ratio of the ADC can be improved. By introducing two auxiliary amplifiers to form a gain-boosting structure, the overall gain of the amplifier is significantly improved with a smaller circuit and power consumption overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 This is the circuit structure diagram of the traditional FIA;

[0024] Figure 2 This is the timing diagram of traditional FIA;

[0025] Figure 3 This is the circuit structure diagram of the traditional cascode FIA;

[0026] Figure 4 This is the timing diagram of the traditional cascode FIA;

[0027] Figure 5 This is a circuit diagram of a gain-boosted floating inverting dynamic amplifier according to the present invention;

[0028] Figure 6 It is a timing diagram of the gain-boosted floating inverting dynamic amplifier of the present invention;

[0029] Figure 7 It is a structural schematic diagram of the auxiliary amplifier of the present invention;

[0030] Figure 8 is a schematic diagram of the abstract structure of the auxiliary amplifier of the present invention;

[0031] Figure 9 is a timing diagram of the auxiliary amplifier of the present invention;

[0032] Figure 10 The circuit structure diagram of the switched capacitor integrator based on the fully differential GBFIA of the present invention;

[0033] Figure 11 This is a timing diagram of the switched capacitor integrator implemented based on the fully differential GBFIA of the present invention;

[0034] Figure 12 Schematic diagram of the fully differential GBFIA circuit of the present invention in the reset phase;

[0035] Figure 13 This is a timing diagram of the fully differential GBFIA circuit of the present invention during the reset phase;

[0036] Figure 14 Schematic diagram of the fully differential GBFIA circuit of the present invention in the conversion phase;

[0037] Figure 15 It is a timing diagram of the fully differential GBFIA circuit of the present invention in the conversion phase;

[0038] Figure 16 It is a schematic diagram of the first-order amplification stage of the fully differential GBFIA circuit of the present invention;

[0039] Figure 17 It is a timing diagram of the fully differential GBFIA circuit of the present invention in the first-order amplification stage;

[0040] Figure 18 Schematic diagram of the fully differential GBFIA circuit of the present invention at the second-order amplification stage;

[0041] Figure 19 It is a timing diagram of the fully differential GBFIA circuit of the present invention in the second-order amplification stage;

[0042] Figure 20 1 is a comparison chart of the passband gain simulation results of the traditional cascode FIA ​​and the fully differential GBFIA of the present invention. DETAILED DESCRIPTION

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0044] In order to illustrate the principle and effect of the present invention, the structure and principle of the traditional FIA are first described. Figure 1 and Figure 2 They are the circuit structure and timing diagram of the traditional single-stage FIA, M n11 、M n112 、M p11 and M p12 is the transistor in the unipolar FIA, s 101 -s 110 is the control switch in the single-pole FIA, C RES1 It is a single floating energy storage capacitor that provides power for the amplifier. in and V ip is the input signal, V on and V op is the output signal, V CM is the common mode level, V DD is the power supply, GND is the ground. 101 -s 110 By control signal φ 1 and φ 2Control on and off. When the control signal φ When 1 is high, C RES1 Stored V DD voltage; φ 2 is high, FIA enters the amplification phase. As the current passes through the amplifier, C RES1 The charge stored in the capacitor is gradually depleted, eventually causing the amplifier to shut down, thus forming a self-attenuation mechanism. C RES1 The power consumption during charging is reduced significantly, thus significantly reducing the power consumption of the amplifier. C RES1 Works like a floating power supply, flowing out C RES1 The current in the top plate must be equal to the current flowing into the bottom plate, i.e. I top = I bottom Therefore, only differential current can flow in the amplifier circuit, ensuring that the FIA ​​has a stable output common-mode voltage, avoiding the common-mode feedback circuit introduced in traditional amplifiers, and reducing circuit complexity.

[0045] The gain of a single-stage FIA ​​circuit is usually less than 30dB, which is difficult to meet the amplifier gain requirements of the switched capacitor integrator circuit. In order to improve the amplifier gain, a cascode FIA ​​can be used, such as Figure 3 and Figure 4 As shown in the figure, M n21 、M n22 、M p21 and M p22 is the common source transistor of the cascode FIA, M cn21 、M cn22 、M cp21 and M cp22 is the common-gate transistor of the cascode FIA, s 201 -s 210 is the control switch of the cascode FIA, C RES2 The floating energy storage capacitor provides power for the common source and common gate FIA, V in and V ip is the input signal, V on and V op is the output signal, V CM is the common mode level (its value is V DD / 2, which is half the power supply voltage), V DD It is the power supply of the whole circuit, and GND is the ground. 201 -s 210 By control signal φ 1 and φ 2 controls the on and off. Its DC gain expression is:

[0046] (1);

[0047] in, A v,FIA is the DC gain, g mn21,22 and g mp21,22 Common source tube M n21 、M n22 、M p21 and M p22 The transconductance, g mcn21,22 and g mcp21,22 They are respectively common gate tube M cn21 、M cn22 、M cp21 and M cp22 The transconductance, r on21,22 、 r op21,22 、 r onc21,22 and r opc21,22 Mn21 、M n22 、M p21 、M p22 、M cn21 、M cn22 、M cp21 and M cp22 To avoid generating additional bias voltage, the gate of the common-gate device is connected to V CM = V DD / 2. M cn21 、M cn22 、M cp21 and M cp22 The size of the common source device M is designed to be large enough to ensure that it works in the subthreshold region, thereby ensuring that the common source device M n21 、M n22 、M p21 and M p22 The drain voltage is high enough to prevent it from entering the linear region. The cascode FIA ​​can achieve a gain of 50dB~60dB, which is better than the unipolar FIA gain, but still cannot meet the requirements of the switched capacitor integrator circuit. And because the gate of the cascode device is V CM , which significantly reduces the output swing of the amplifier.

[0048] To overcome the shortcomings of the prior art, the present invention provides a gain-boosted floating inverter amplifier (GBFIA) circuit, specifically a fully differential gain-boosted floating inverter amplifier circuit. This circuit offers the advantages of high gain, low power consumption, and high stability. When used in high-precision pipelines and delta-sigma ADCs, it can significantly reduce ADC power consumption while maintaining ADC accuracy. This circuit incorporates two auxiliary amplifiers into the main FIA to form a gain-boosting structure, significantly increasing the amplifier's overall gain by increasing the FIA's output impedance. Unlike conventional FIAs, the present invention's main FIA utilizes two energy storage capacitors to achieve reverse-correlated level conversion, improving current efficiency. Furthermore, the main FIA's input does not need to be reset to a common-mode level, effectively avoiding errors introduced by the reset switch.

[0049] The auxiliary amplifier in the fully differential GBFIA of the present invention also adopts a common-source common-gate FIA ​​structure, which not only further reduces power consumption but also avoids the introduction of a common-mode feedback circuit, reducing circuit complexity. A notable feature of the fully differential GBFIA is that the pole frequencies of the auxiliary FIA and the main FIA change synchronously with the circuit state, ensuring circuit stability. The control timing of the main FIA and the auxiliary FIA are both based on the same clock, generated through frequency division and logic circuits, simplifying circuit design. In addition, the gate bias level of the common-gate transistor of the main FIA is determined by the output of the auxiliary FIA, further improving the output swing of the fully differential GBFIA.

[0050] In order to achieve the required high gain (greater than 100dB) and avoid the introduction of traditional common-mode feedback circuits while ensuring the stability of the circuit, the main amplifier and the auxiliary amplifier in the present invention are both cascode FIAs. To avoid the introduction of additional bias voltage, the gate of the cascode device of the auxiliary FIA is directly connected to the common-mode level. V CM , where the common-mode level V CM Approximately power supply voltage V DD Half of V CM ≈ V DD / 2). The gate of the common-gate device of the main FIA is connected to the output of the auxiliary FIA, thereby further improving the output swing of the GBFIA.

[0051] In the present invention, the fully differential GBFIA is composed of a main amplifier and two auxiliary FIAs, the two auxiliary FIAs include a first auxiliary amplifier and a second auxiliary amplifier, and both the main amplifier and the auxiliary amplifier adopt FIA structure. The structure and typical control timing of GBFIA are as follows: Figure 5 and Figure 6 shown.

[0052] The main amplifier includes a first power supply capacitor C RES31 , the second power supply capacitor C RES32 , a plurality of first common-source transistors, a plurality of first common-gate transistors, a first control switch, a second control switch, a third control switch, a fourth control switch and a fifth control switch.

[0053] In this embodiment, the plurality of first common-source transistors include a first transistor M n31 , the second transistor M n32 , the third transistor M p31 and the fourth transistor M p32 , the first common-gate transistor includes a fifth transistor M cn31, the sixth transistor M cn32 , the seventh transistor M cp31 and the eighth transistor M cp32 , the first control switch includes a first switch s 301 and the second switch s 302 , the second control switch includes a third switch s 303 and the fourth switch s 304 , the third control switch includes a fifth switch s 305 and the sixth switch s 306 , the fourth control switch includes a seventh switch s 307 and the eighth switch s 308 , the fifth control switch includes a ninth switch s 309 and the tenth switch s 310 .

[0054] The drains of the first common-source transistors are connected to the input terminals of the first auxiliary amplifier and the second auxiliary amplifier respectively, and the gates of the first common-gate transistors are connected to the output terminals of the first auxiliary amplifier and the second auxiliary amplifier respectively. C RES31 The two ends are connected to the power supply through a first control switch, the two ends of the first power supply capacitor and the two ends of the second power supply capacitor are connected through a second control switch, the two ends of the first power supply capacitor and the multiple sources of the first common-source transistor are connected through a third control switch, and the two ends of the second power supply capacitor and the multiple sources of the first common-source transistor are connected through a fourth control switch.

[0055] First switch 301 One end of the switch is connected to the power supply, and the second switch s 302 One end of the first switch s is grounded. 301 and the second switch s 302 The other end of the first power supply capacitor C RES31 The third switch s 303 and the fourth switch s 304 One end of each of the first power supply capacitor C RES31 The other end is connected to the second power supply capacitor C RES32 The two ends of the first transistor M are connected. n31 and the second transistor M n32 The source of the sixth switch s 306 and the eighth switch s 308 One end of the third transistor M p31 and the fourth transistor M p32 The source of the fifth switch s 305 and the seventh switch s 307 One end of the fifth switch s305 and the sixth switch s 306 The other end of the first power supply capacitor C RES31 The two ends of the seventh switch s 307 and the eighth switch s 308 The other end of the second power supply capacitor C RES32 The two ends of the first transistor M are connected. n31 and the third transistor M p31 The gates are connected to each other and are used to input the input signal V in The second transistor M n32 and the fourth transistor M p32 The gates are connected to each other and are used to input the input signal V ip The first transistor M n31 and the second transistor M n32 The drains of the third transistor M are connected to the input terminals of the first auxiliary amplifier, p31 and the fourth transistor M p32 The drains are respectively connected to the input terminals of the second auxiliary amplifier.

[0056] The fifth transistor M cn31 and the sixth transistor M cn32 The gates are connected to the output terminals of the first auxiliary amplifier, and the sources are connected to the first transistors M n31 and the second transistor M n32 The drain of the seventh transistor M is connected. cp31 and the eighth transistor M cp32 The drains are connected to the output terminals of the second auxiliary amplifier, and the sources are connected to the third transistor M p31 and the fourth transistor M p32 The drain of the fifth transistor M is connected. cn31 and the seventh transistor M cp31 The drain of the ninth switch s 309 One end is connected and used to output the output signal V op The sixth transistor M cn32 and the eighth transistor M cp32 The drain of the tenth switch s 310 One end is connected and used to output the output signal V on , ninth switch s 309 and the tenth switch s 310 The other end is connected to the common-mode level.

[0057] Through the first control signal φ 11 The first control switch is controlled by the second control signal φ 12The second control switch is controlled by the third control signal φ 21 The fourth control switch is controlled by the fourth control signal φ 22 The fourth control switch is controlled.

[0058] M n31 、M n32 and M p31 、M p32 is the common source transistor of the main FIA in the fully differential GBFIA, M cn31 、M cn32 and M cp31 、M cp32 is the common-gate transistor of the main FIA in the fully differential GBFIA, s 301 -s 310 is the control switch of the main FIA in the fully differential GBFIA, C RES31 and C RES32 Provides power to the floating energy storage capacitor for the main FIA, V in and V ip is the input signal, V on and V op is the output signal, V DD The power supply of the whole circuit, GND is the ground. n31 、M n32 、M p31 and M p32 The drain of the auxiliary FIA is connected to the input of the auxiliary FIA, and the output of the auxiliary FIA is connected to the common gate transistor M in the main FIA. cn31 、M cn32 、M cp31 and M cp32 The gate. s 301 -s 310 Depend on φ 11 、 φ 12 、 φ 21 、 φ 22 Controls on and off. The main FIA's operating sequence includes the reset phase ( φ 11 is high level), conversion phase ( φ 12 is high level), first-order amplification stage ( φ 21 is high) and the second-stage amplifier stage ( φ 22is high). Use the fully differential GBFIA to build a switched capacitor integrator circuit. In the reset phase ( φ 11 is high level), the main power supply capacitor C RES31 Charging begins and the output node is reset to the common-mode level V CM During the conversion phase ( φ 12 is high level), the main power supply capacitor C RES31 With auxiliary power supply capacitor C RES32 Connect in parallel to share charge. In the first-order amplification stage, the main power supply capacitor C RES31 The amplifier is powered until the end of this stage, when the output node gets the result of the FIA ​​integration output powered only by the main power supply capacitor. C RES31 and auxiliary power supply capacitors C RES32 Together, they power the fully differential GBFIA, further increasing the overall gain and thus improving the accuracy of the integrator implemented using the GBFIA. The circuit timing ensures that the high gain of the amplifier is maintained while fully utilizing the operating current provided by the capacitors.

[0059] The structure and timing of the auxiliary FIA are as follows Figure 7-Figure 9 As shown. Including the third power supply capacitor C RES4 , a plurality of second common-source transistors, a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch and a tenth control switch.

[0060] The plurality of second common-source transistors include a ninth transistor M n41 , the tenth transistor M n42 , the eleventh transistor M p41 and the twelfth transistor M p42 , the second common-gate transistor includes a thirteenth transistor M cn41 , the fourteenth transistor M cn42 , the fifteenth transistor M cp41 and the sixteenth transistor M cp42 The sixth control switch includes an eleventh switch s 401 and the twelfth switch s 402 , the seventh control switch includes a thirteenth switch s 403 and the fourteenth switch s 404 , the eighth control switch includes a fifteenth switch s 405 and the sixteenth switch s 406 , the ninth control switch includes a seventeenth switch s407 and the eighteenth switch s 408 , the tenth control switch includes a nineteenth switch s 409 and the 20th switch s 410 .

[0061] M n41 、M n42 、M p41 and M p42 is the common source transistor of the auxiliary FIA in the fully differential GBFIA, M cn41 、M cn42 、M cp41 and M cp42 is the common-gate transistor of the auxiliary FIA in the fully differential GBFIA, s 401 -s 410 is the control switch of the auxiliary FIA in the fully differential GBFIA, C RES4 The floating energy storage capacitor provides power for the auxiliary FIA, V in_au and V ip_au is the input signal, V on_au and V op_au is the output signal, V DD It is the power supply of the whole circuit, and GND is the ground. 401 -s 410 By control signal φ 1 and φ 2 Control on and off. In order to simplify the circuit design, the work of auxiliary FIA is divided into charging stage ( φ 1 is high) and the amplification stage ( φ 2 is high level). During the charging phase, the energy storage capacitor C RES4 Charge to V DD , and the input and output nodes of the auxiliary FIA are reset to the common mode level V CM During the amplification phase, the capacitor C RES4 To power the auxiliary FIA, the output node of the auxiliary FIA is connected to the gate of the common-gate device of the main FIA, which not only improves the output resistance of the overall fully differential GBFIA, increases the gain, but also further expands the output swing.

[0062] To better illustrate the benefits of the fully differential GBFIA of the present invention, Figure 10 and Figure 11The structure and timing diagram of the switched capacitor integrator based on the fully differential GBFIA are given respectively. The black part is the GBFIA and the gray part is the switched capacitor circuit required to form the integrator. The working timing of the gain-boosted floating inverting dynamic amplifier (GBFIA) circuit includes the reset phase ( φ 11 phase), conversion phase ( φ 12 phase), first-order amplification stage ( φ 21 phase) and the second-order amplification stage ( φ 22 When the switched capacitor integrator is sampling, the fully differential GBFIA works in the reset phase and the conversion phase. In the reset phase, the power supply C RES31 Charging, conversion phase main power supply capacitor C RES1 With auxiliary power supply capacitor C RES32 When the switched capacitor integrator is integrating, the fully differential GBFIA works in the first-order amplification stage and the second-order amplification stage. The main power supply capacitor in the first-order amplification stage C RES31 Powering the amplifier, the main power supply capacitor for the second-stage amplification stage C RES31 and auxiliary power supply capacitors C RES32 Together they power the fully differential GBFIA. During the entire operation of the switched capacitor integrator, only the energy storage capacitor is C RES1 The power consumption during charging (i.e., the reset phase) is reduced significantly, thereby significantly reducing the power consumption of the switched capacitor integrator. At the same time, the high gain of the fully differential GBFIA amplification phase ensures the accuracy of the switched capacitor integrator's integration results.

[0063] The fully differential GBFIA is the same as the FIA. During its operation, the current is not constant, but decreases exponentially. When the amplifier circuit just enters the amplification stage ( φ 21 When the current is high (first-order amplification stage), the current is large, but the current generated at this time cannot be fully utilized in the switched capacitor integrator composed of the amplifier. In order to solve this problem, the main FIA of the present invention is connected to the main power supply capacitor by the main power supply capacitor. C RES31 and auxiliary power supply capacitors C RES32 Common power supply, the overall working sequence of the circuit is as follows Figures 12-19 shown. φ 11 、 φ 12 、 φ 21 、 φ 22 is the control signal, controlling the switch s 31 -s 310 Specifically, the reset phase ( φ 11 is high level) power supply C RES31 After charging is completed, in the conversion phase ( φ 12 is high), the main power supply capacitor C RES1 With auxiliary power supply capacitor C RES32 Charge sharing is achieved, thus achieving inversely related level shifts and reducing the voltages of the two capacitors. This process helps reduce the first-order amplification stage ( φ 21 is high), thereby reducing the current in this stage and effectively improving the current utilization efficiency. When entering the second-order amplification stage ( φ 22 is high level), then C RES32 and C RES31 They are connected in parallel to realize common power supply to ensure the performance of the overall circuit in the middle and late stages of the amplification stage.

[0064] The main effect of the GBFIA of the present invention is that the gain-boosting structure formed by the two auxiliary FIAs increases the output impedance of the amplifier, thereby increasing the gain of the amplifier, thereby improving the accuracy of the entire integrator when used in the integrator. It can be deduced that Figure 5 The gain expression of GBFIA is:

[0065] (2);

[0066] in, A v,GBFIA is the DC gain of GBFIA, g mn31,32 、 g mp31,32 Common source tube M n31 、M n32 、M p31 and M p32 The transconductance, g mcn31,32 、 g mcp31,32 They are respectively common gate tube M cn31 、M cn32 、M cp31 and M cp32The transconductance, r on31,32 、 r op31,32 、 r onc31,32 、 r opc31,32 M n31 、M n32 、M p31 、M p32 、M cn31 、M cn32 、M cp31 and M cp32 The output resistance, A v,FIA,au for Figure 7 The gain of auxiliary FIA ( A v,FIA,au The expression is the same as equation (1). It can be seen that the total gain of the GBFIA of the present invention is the product of the gain of the main FIA and the gain of the auxiliary FIA, which is greatly improved compared to the gain of the traditional FIA. In order to ensure the stability of the gain-boosted amplifier, it is necessary to ensure that the unit gain bandwidth (Gain-BandWidth Product, GBW) of the auxiliary FIA is greater than the -3dB bandwidth of the main amplifier. During the operation of the FIA ​​circuit, the voltage and current are constantly changing, so their poles will also change accordingly. In order to ensure that the circuit remains stable throughout the entire working cycle, the poles of the auxiliary amplifier need to change synchronously. In the fully differential GBFIA of the present invention, since the auxiliary amplifier also adopts the common source and common gate FIA ​​structure, and the energy storage capacitor of the auxiliary amplifier is smaller than the energy storage capacitor of the main amplifier, it can be ensured that the circuit can meet the pole size relationship required by the main FIA and the auxiliary FIA at any time, thereby ensuring the stability of the entire GBFIA. In addition, the use of the FIA ​​structure by the auxiliary amplifier can also avoid the introduction of a common-mode feedback circuit, thereby reducing system complexity and further improving the overall performance of the circuit. Since the output node voltage of the auxiliary FIA deviates from the common-mode voltage V CM (i.e. NMOS terminal is lower than V CM , the PMOS end is higher than V CM ), which further improves the output swing of the overall circuit, optimizes the circuit's signal transmission capability, and improves its performance and stability.

[0067] To verify the effectiveness of the present invention, a cascode FIA ​​and a fully differential GBFIA of the present invention were built using a 180nm CMOS (Complementary Metal-Oxide-Semiconductor) process. Their gains were simulated and compared. Both schemes were powered by a 1.8V power supply and a unity-gain integrator was built for integration. Small-signal simulations were performed on the output to obtain the amplifier gain. The results are shown in Figure 2. Figure 20 As shown. From the simulation results, it can be seen that the passband gain of the fully differential GBFIA of the present invention exceeds 100dB, while the DC gain of the traditional cascode FIA ​​is only about 50dB. Through the analysis of the average operating current of the circuit, it is concluded that the average power consumption of the fully differential GBFIA is 7.56μW, while the power consumption of the cascode FIA ​​is 2.43μW. The results show that compared with FIA, the fully differential GBFIA of the present invention improves the gain by 50dB with very low power consumption. When traditional continuous-time differential amplifiers want to achieve the same gain and bandwidth as the fully differential GBFIA of the present invention, the power consumption is usually tens to hundreds of μW. Therefore, the fully differential GBFIA of the present invention has obvious low power consumption advantages.

[0068] In summary, the fully differential GBFIA proposed in this paper significantly improves FIA gain while maintaining low power consumption and increasing output swing. Compared to traditional differential amplifier circuits, this invention eliminates the need for common-mode feedback circuitry, effectively reducing system complexity and improving circuit stability.

[0069] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0070] Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the claims and their equivalents, the present invention is intended to include such modifications and variations.

Claims

1. A gain-boosted floating inverting dynamic amplifier circuit, characterized in that: comprising a main amplifier, a first auxiliary amplifier and a second auxiliary amplifier; The main amplifier includes a first power supply capacitor ( C RES31 )、Second power supply capacitor( C RES32 ), a plurality of first common-source transistors, a plurality of first common-gate transistors, a first control switch, a second control switch, a third control switch, a fourth control switch, and a fifth control switch; a plurality of drains of the plurality of first common-source transistors are respectively connected to the input terminals of the first auxiliary amplifier and the second auxiliary amplifier, and a plurality of gates are used to receive input signals; The gates of the first common-gate transistor are respectively connected to the output terminals of the first auxiliary amplifier and the second auxiliary amplifier; the first power supply capacitor ( C RES31 ) are connected to a power supply via a first control switch, the first power supply capacitor and the second power supply capacitor are connected via a second control switch, the first power supply capacitor and the multiple sources of the first common-source transistor are connected via a third control switch, and the second power supply capacitor and the multiple sources of the first common-source transistor are connected via a fourth control switch; The first auxiliary amplifier and the second auxiliary amplifier each include a plurality of second common-gate transistors, wherein a plurality of gates of the second common-gate transistors are directly connected to a common-mode voltage level; By the first control signal ( φ 11 ) controls the first control switch and controls the second control signal ( φ 12 ) controls the second control switch, and controls the second control switch through the third control signal ( φ 21 ) controls the third control switch, and controls the fourth control signal ( φ 22 ) controlling the fourth control switch; When the first control signal ( φ 11 ) is high, the first control switch is closed, and the power supply to the first power supply capacitor ( C RES31 ) is charged, and the output node is reset to the common-mode level; When the second control signal ( φ 12 ) is high, the second control switch is closed, and the first power supply capacitor ( C RES31 ) and the second power supply capacitor ( C RES32 ) are connected in parallel for charge sharing; When the third control signal ( φ 21 ) is high, the third control switch is closed, the input signal is input to the gain-boosted floating inverting dynamic amplifier, and the first power supply capacitor ( C RES31 ) supplies power to the amplifier to obtain a first-order amplified output signal; When the fourth control signal ( φ 22 ) is high, the fourth control switch is closed, the input signal is input to the gain-boosted floating inverting dynamic amplifier, and the first power supply capacitor ( C RES31 ) and the second power supply capacitor ( C RES32 ) powers the amplifier to obtain a second-order amplified output signal.

2. A gain-boosted floating inverting dynamic amplifier circuit as claimed in claim 1, characterized in that: The plurality of first common-source transistors include a first transistor (M n31 ), the second transistor (M n32 ), the third transistor (M p31 ) and the fourth transistor (M p32 ), the first common-gate transistor includes a fifth transistor (M cn31 ), the sixth transistor (M cn32 ), the seventh transistor (M cp31 ) and the eighth transistor (M cp32 The first control switch includes a first switch (s 301 ) and the second switch (s 302 ), the second control switch includes a third switch (s 303 ) and the fourth switch (s 304 ), the third control switch includes a fifth switch (s 305 ) and the sixth switch (s 306 ), the fourth control switch includes a seventh switch (s 307 ) and the eighth switch (s 308 ), the fifth control switch includes a ninth switch (s 309 ) and the tenth switch (s 310 ); The first switch (s 301 ) is connected to the power supply, and the second switch (s 302 ) is grounded, the first switch (s 301 ) and the second switch (s 302 ) are connected to the other end of the first power supply capacitor ( C RES31 ) are connected at both ends; the third switch (s 303 ) and the fourth switch (s 304 ) are connected to the first power supply capacitor ( C RES31 ) are connected to both ends of the capacitor and the other end are connected to the second power supply capacitor ( C RES32 ) are connected at both ends; the first transistor (M n31 ) and the second transistor (M n32 ) and the source of the sixth switch (s 306 ) and the eighth switch (s 308 ) is connected to one end of the third transistor (M p31 ) and the fourth transistor (M p32 ) source and the fifth switch (s 305 ) and the seventh switch (s 307 ) is connected to one end of the fifth switch (s 305 ) and the sixth switch (s 306 ) are connected to the other end of the first power supply capacitor ( C RES31 ) are connected to both ends, the seventh switch (s 307 ) and the eighth switch (s 308 ) and the other end of the second power supply capacitor ( C RES32 ) are connected at both ends; the first transistor (M n31 ) and the third transistor (M p31 ) are connected to each other and are used to input the input signal V in The second transistor (M n32 ) and the fourth transistor (M p32 ) are connected to each other and are used to input the input signal V ip The first transistor (M n31 ) and the second transistor (M n32 ) are connected to the input terminal of the first auxiliary amplifier respectively, and the drain of the third transistor (M p31 ) and the fourth transistor (M p32 ) are respectively connected to the input end of the second auxiliary amplifier.

3. A gain-boosted floating inverting dynamic amplifier circuit as claimed in claim 2, characterized in that: The fifth transistor (M cn31 ) and the sixth transistor (M cn32 ) are connected to the output terminal of the first auxiliary amplifier, and their sources are connected to the first transistor (M n31 ) and the second transistor (M n32 ) is connected to the drain of the seventh transistor (M cp31 ) and the eighth transistor (M cp32 ) are connected to the output terminal of the second auxiliary amplifier, and their sources are connected to the third transistor (M p31 ) and the fourth transistor (M p32 ) is connected to the drain of the fifth transistor (M cn31 ) and the seventh transistor (M cp31 ) are connected to the drain of the ninth switch (s 309 ) and is used to output the output signal V op The sixth transistor (M cn32 ) and the eighth transistor (M cp32 ) are connected to the drain of the tenth switch (s 310 ) and is used to output the output signal V on , the ninth switch (s 309 ) and the tenth switch (s 310 ) is connected to the common-mode level.

4. The gain-boosted floating inverting dynamic amplifier circuit according to claim 1, wherein: The first auxiliary amplifier and the second auxiliary amplifier further include a third power supply capacitor ( C RES4 ), multiple second common-source transistors, a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch and a tenth control switch; the structures of the first auxiliary amplifier and the second auxiliary amplifier both adopt a common-source and common-gate floating inverting dynamic amplifier structure.

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