Cascade switching device, power switching device and gate driver thereof

Abstract

The invention provides a cascade switching device. The cascade switching device comprises a normally-on switching device, a normally-off switching device and a gate driver. The normally-on switching device has a first end, a second end and a control end. The normally-off switching device has a first end, a second end, and a control end. Wherein the first end of the normally-off switching device is coupled to the second end of the normally-on switching device, and the control end of the normally-off switching device is coupled to the control end of the normally-on switching device. The gate driver is used for providing a gate driving signal to the control end of the normally-on switching device so as to control the switching conversion rate of the voltage of the first end of the normally-on switching device. Wherein the normally-on switching device is turned on or turned off in response to a gate driving signal. According to the cascade switch device, the switch conversion rate of the drain voltage of the cascade switch device can be controlled.

Description

Technical Field

[0001] Embodiments of the present invention relate to a power supply circuit, and more particularly, to a cascaded switching device. Background Art

[0002] In high-power applications such as automotive powertrains, data centers, cloud computing, and artificial intelligence, wide bandgap (WBG) semiconductors are commonly used for power switching operations. In high-voltage applications, a cascaded switching device having a normally-on switching device and a normally-off switching device connected in series is often used. The normally-on switching device is a high-voltage transistor (HVT), such as a SiC / GaN JFET. The normally-off switching device is a low-voltage transistor (LVT), such as a Si MOSFET.

[0003] Generally, in an existing cascaded configuration circuit, the switching transition rate (dV / dt) of the drain voltage at the drain terminal of the cascaded switching device cannot be controlled, resulting in excessive ringing or high electromagnetic interference, which is not conducive to the stability of the system. In addition, during the switching process, due to the high voltage spike at the drain terminal of the cascaded switching device, the voltage value at the drain terminal of the normally-off switching device may be higher than the safe operating voltage, resulting in higher power losses.

[0004] Therefore, it is desirable to provide a method to control the switching transition rate of the drain voltage of the cascaded switching device. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a cascaded switching device is provided. The cascaded switching device includes a normally-on switching device, a normally-off switching device, and a gate driver. The normally-on switching device has a first terminal, a second terminal, and a control terminal. The normally-off switching device has a first terminal, a second terminal, and a control terminal. The first terminal of the normally-off switching device is coupled to the second terminal of the normally-on switching device, and the control terminal of the normally-off switching device is coupled to the control terminal of the normally-on switching device. The gate driver is configured to provide a gate drive signal to the control terminal of the normally-on switching device to control the switching transition rate of the voltage at the first terminal of the normally-on switching device. The normally-on switching device is turned on or off in response to the gate drive signal.

[0006] According to another embodiment of the present disclosure, a power switching device is provided. The power switching device includes a first transistor, a second transistor, and a gate driver. The first transistor has a first source, a first drain, and a first gate. The second transistor has a second source, a second drain, and a second gate. The gate driver is configured to provide a gate drive signal to the first gate of the first transistor to control the switching transition rate of the voltage at the first drain of the first transistor. The first transistor is turned on or off in response to the gate drive signal.

[0007] According to another embodiment of the present disclosure, a gate driver is provided for driving a cascaded switching device having a normally-on switching device and a normally-off switching device. The gate driver includes a driving circuit. The driving circuit is configured to provide gate driving signals to the control terminals of the normally-on switching device and the normally-off switching device to control the switching transition rate of the voltage at the first terminal of the normally-on switching device. The normally-on switching device is turned on or off in response to the gate driving signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure can be further understood with reference to the following detailed description and the accompanying drawings, in which like elements are denoted by like reference numerals. These drawings are for illustrative purposes only and may show only a part of the device and are not necessarily drawn to scale.

[0009] Figures 1A - 1D A schematic diagram of an existing cascaded switching device is shown;

[0010] Figure 2 A cascaded switching device according to an embodiment of the present disclosure is shown;

[0011] Figure 3 A cascaded switching device according to an embodiment of the present disclosure is shown;

[0012] Figure 4 A cascaded switching device according to another embodiment of the present disclosure is shown;

[0013] Figure 5 A cascaded switching device according to still another embodiment of the present disclosure is shown;

[0014] Figure 6 A cascaded switching device according to still another embodiment of the present disclosure is shown;

[0015] Figure 7 A gate driver signal simulation waveform diagram according to an embodiment of the present disclosure as shown in Figure 6 is shown;

[0016] Figure 8 A power switching device according to still another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0017] Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the present invention.

[0018] Throughout the specification and claims, references to "an embodiment", "embodiments", "an example" or "examples" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the invention. Thus, the phrases "in an embodiment", "in embodiments", "an example" or "examples" that appear throughout the specification do not necessarily all refer to the same embodiment or example. Additionally, the particular features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Those skilled in the art will understand that the meanings of the above terms are not necessarily limiting of these terms, but rather provide illustrative examples for these terms. It should be noted that when an element is "connected to" or "coupled to" another element, it means that the element is directly connected to or coupled to the other element, or indirectly connected to or coupled to the other element through another element. The particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable elements to provide the described function. Further, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0019] Figure 1A A schematic diagram of an existing cascaded switch device 100 is shown. As shown in FIG. 1, the cascaded switch device 100 includes a normally-on switch device 160 and a normally-off switch device 170. In one embodiment, the normally-on switch device 160 is a junction field-effect transistor (JFET) J1. In one embodiment, the normally-off switch device 170 is a metal-oxide-semiconductor field-effect transistor (MOSFET) M1. The JFET J1 has a first terminal 12 (e.g., drain), a second terminal 14 (e.g., source), and a control terminal 16 (e.g., gate). The MOSFET M1 has a first terminal 22 (e.g., drain), a second terminal 24 (e.g., source), and a control terminal 26 (e.g., gate).

[0020] The JFET J1 and the MOSFET M1 are connected in series. Specifically, the first terminal 12 (e.g., drain) of the JFET J1 is coupled to a first node N1, the second terminal 14 (e.g., source) of the JFET J1 is coupled to the first terminal 22 (e.g., drain) of the MOSFET M1, and the second terminal 24 (e.g., source) of the MOSFET M1 is coupled to a second node N2.

[0021] As Figure 1AAs shown, the control terminal 16 of JFET J1 is coupled to ground. In one embodiment, the cascode switching device 100 further includes a drive circuit 110. The drive circuit 110 is used to provide a drive signal S D to control MOSFET M1. The drive signal S D is provided to the control terminal of MOSFET M1 to turn on or off MOSFET M1, and control the operation of JFET J1 according to the operating conditions of MOSFET M1. When MOSFET M1 is turned off, the source terminal of JFET J1 (i.e., the drain-source voltage (V DS )) of MOSFET M1) is at a high level. Therefore, the gate-source voltage of JFET J1 is reverse-biased and reaches the pinch-off voltage of the JFET, resulting in the turn-off of JFET J1. When MOSFET M1 is turned on, JFET J1 will also be turned on.

[0022] As Figure 1B shown, the gate terminal of SiC JFET J1 is coupled to the source terminal of Si MOSFET M1. Similarly, when MOSFET M1 is turned on, JFET J1 will also be turned on. When MOSFET M1 is turned off, JFET J1 is turned off.

[0023] For the existing cascode switching devices 100 or 102, the switching transition rate (dV / dt) of the drain voltage is controlled by adjusting the charging / discharging current from the gate terminal of MOSFET M1 to the drain terminal of JFET J1 through the Miller capacitance. As Figure 1C shown, the Miller capacitance includes the capacitance C GDM between the gate terminal and the drain terminal of MOSFET M1, the capacitance C GSJ between the gate terminal and the source terminal of JFET J1, and the capacitance C GDJ between the gate terminal and the drain terminal of JFET J1. However, since the capacitance C GDJ of JFET J1 is connected across the drain voltage of JFET J1 and the fixed bias voltage of the source terminal of MOSFET M1. Therefore, the charging and discharging of the capacitance C GDJ is independent of the current at the gate terminal 26 of MOSFET M1, making it difficult to directly control the switching transition rate.

[0024] To control the switching transition rate, a gate resistor R1 is connected to the gate terminal of MOSFET M1 (as Figure 1D shown) to slow down the switching speed. However, since the switching speed of MOSFET M1 is significantly slowed down, the on / off delay time becomes larger.

[0025] Figure 2Shows a cascaded switching device 200 according to an embodiment of the present disclosure. The cascaded switching device 200 includes a normally-on switching device 260 and a normally-off switching device 270.

[0026] As Figure 2 shown, the normally-on switching device 260 is connected in series with the normally-off switching device 270. Specifically, a first end 62 of the normally-on switching device 260 is coupled to a first node N1, a second end 64 of the normally-on switching device 260 is coupled to a first end 72 of the normally-off switching device 270, and a second end 74 of the normally-off switching device 270 is coupled to a second node N2. A control end 76 of the normally-off switching device 270 is coupled to a control end 66 of the normally-on switching device 260.

[0027] In one embodiment, the normally-on switching device 260 is a Junction Field-Effect Transistor (JFET) J1. In one embodiment, the normally-off switching device 270 is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) M1. The JFET J1 has a first end 62 (e.g., a drain), a second end 64 (e.g., a source), and a control end 66 (e.g., a gate). The MOSFET M1 has a first end 72 (e.g., a drain), a second end 74 (e.g., a source), and a control end 76 (e.g., a gate). The JFET J1 is a high-voltage normally-on (depletion mode) device, while the MOSFET M1 is a low-voltage normally-off (enhancement mode) device. For example, the JFET J1 can withstand a high voltage level higher than 100V; and the MOSFET M1 operates at a voltage level lower than 100V.

[0028] In one embodiment, the normally-on switching device 260 includes a wide-bandgap (WBG) semiconductor switch. In one embodiment, the WBG semiconductor switch includes a silicon carbide (SiC) material. In another embodiment, the WBG semiconductor switch includes a gallium nitride (GaN) material. In other embodiments, the WBG semiconductor switch includes a WBG semiconductor material with a bandgap greater than the silicon bandgap, such as diamond, III-V semiconductor materials, and II-VI semiconductor materials. The III-V semiconductor materials basically include one element of Group III and one element of Group V, such as boron nitride (BN), aluminum nitride (AlN), aluminum phosphide (AlP), gallium phosphide (GaP), and gallium arsenide (GaAs). The II-VI semiconductor materials may include a metal element of Group IIA or Group IIB in the periodic table and a non-metal element of Group VI, such as cadmium sulfide (CdS), cadmium telluride (CdTe), zinc oxide (ZnO), zinc sulfide (ZnS), and zinc selenide (ZnSe).

[0029] In another embodiment, the normally-on switching device 260 includes a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), having a first terminal (e.g., drain), a second terminal (e.g., source), and a control terminal (e.g., gate). In another embodiment, the normally-on switching device 260 includes a High Electron Mobility Transistor (HEMT).

[0030] In one embodiment, the normally-off switching device 270 is fabricated on a silicon (Si) substrate. The normally-off switching device 270 includes a Bipolar Junction Transistor (BJT), a Field-Effect Transistor (FET), or an Insulated-Gate Bipolar Transistor (IGBT), a MOSFET, a HEMT, a JFET, a Gate Turn-off Thyristor (GTO), or a Gate-Commutated Thyristor (GCT).

[0031] In one embodiment, the cascaded switching device 200 further includes a gate driver 210. In one embodiment, the gate driver 210 is fabricated on a silicon (Si) substrate. In one embodiment, the cascaded switching device 200 is an Integrated Circuit (IC). For example, the JFET J1 is integrated on a SiC die, and the gate driver 210 and the MOSFET M1 are integrated on a Si die and co-packaged with the SiC die. In another embodiment, the JFET J1 is integrated on one IC, and the gate driver 210 and the MOSFET M1 are integrated in another IC.

[0032] In one embodiment, the cascaded switch device 200 is a power switch device used in a switched-mode power supply. For example, the power switch device is one of the switches in a boost converter. In another example, the power switch device is one of the switches in a buck converter. In yet another example, the power switch device is one of the switches in a buck-boost converter. In one embodiment, the power switch device is one of the switches in a switched-capacitor circuit. In another embodiment, the power switch device is a load switch. In other examples, the power switch device is one of the switches in an LLC converter. In some other examples, the power switch device is one of the switches in a bridge circuit (half-bridge or full-bridge). In some other embodiments, the power switch device is a synchronous rectifier. In some embodiments, the power switch device may include more WBG semiconductor switches for the above-mentioned switched-mode power supply. Accordingly, the gate driver 210 provides corresponding drive signals to the WBG semiconductor switches.

[0033] In one embodiment, the power switch device is an IC with multiple pins. For example, the Vcc pin is used to receive the power supply voltage, the GND pin is used to couple to the reference ground, the N1 pin is coupled to the first end (e.g., drain) of the normally-on switch device, and the N2 pin is coupled to the second end (e.g., source) of the normally-off switch device. In some embodiments, the power switch device further includes one or more pins for receiving and / or transmitting enable signals, detection signals, monitoring signals, control signals, and / or data.

[0034] The gate driver 210 is used to provide the gate drive signal S D to the control terminal 66 of the normally-on switch device 260 to control the switching rate (dV / dt) of the voltage at the first end 62 of the normally-on switch device 260. The normally-on switch device 260 turns on and off in response to the gate drive signal S D Specifically, the operation of the JFET J1 is directly controlled according to the gate drive signal S D When the MOSFET M1 is turned off, the JFET J1 is also turned off. When the MOSFET M1 is turned on, the JFET J1 is also turned on.

[0035] However, when the gate terminal of the JFET J1 is coupled to the gate terminal of the MOSFET M1, a large current may flow to the gate terminal of the JFET J1. Due to the gate leakage current I GL passing through the pn junction of the JFET J1 (e.g., Figure 3 the diodes D GDJ and D GSJ ), device damage may occur. In one embodiment, the gate driver further includes a current-limiting circuit to limit the gate current I G .

[0036] Figure 4 shows a cascode switching device 400 according to another embodiment of the present disclosure. As Figure 4 shown, the gate driver 410 includes a driving circuit 412 and a current limiting circuit 414. The current limiting circuit 414 is used to provide a limited current flowing through the control terminal (such as, the gate) of the normally-on switching device (such as, JFET J1). In one embodiment, the current limiting circuit 414 is a current source.

[0037] Figure 5 shows a cascode switching device 500 according to yet another embodiment of the present disclosure. As Figure 5 shown, the gate driver 510 includes a driving circuit 512 and a voltage drop circuit 516. The gate driver 510 is used to provide a driving signal S D1 to the gate terminal of the MOSFET M1. The voltage drop circuit 516 is coupled between the gate terminal of the JFET J1 and the gate terminal of the MOSFET M1. That is, the voltage drop circuit 516 is used to provide the gate driving signal S D2 to the gate terminal of the JFET J1, and the gate driving signal is lower than the driving signal (for example, S D2 = S D1 -ΔV, where ΔV is the voltage drop). For example, when the gate voltage of the MOSFET M1 is 3.3V, the gate voltage of the JFET J1 is 2.5V, so the gate voltage of the JFET J1 can be smaller.

[0038] In one embodiment, the voltage drop circuit 516 is a switch (such as, a MOSFET). However, the content of the present disclosure is not limited thereto. The voltage drop circuit 516 may include a resistor, a diode, and / or a transistor.

[0039] Figure 6 shows a cascode switching device 600 according to yet another embodiment of the present disclosure. As Figure 6 shown, the gate driver 610 includes a driving circuit 612, a current limiting circuit 614, a switch S1, and a timing circuit 618. When the MOSFET M1 conducts in response to the driving signal S D , the timing circuit 618 is used to provide a control signal S T to turn on the switch S1.

[0040] Figure 7 shows a signal simulation waveform diagram of the gate driver 610 as Figure 6 shown according to an embodiment of the present disclosure. At the moment t1, the driving signal S D provided by the driving circuit 612 switches from low level to high level to turn on the MOSFET M1. At the same time, the timing circuit 618 provides a high-level control signal S T to turn on the switch S1. Correspondingly, as the gate voltage V of the MOSFET M1GM With the increase of, the gate voltage V of JFET J1 GJ also increases (at a lower voltage value, e.g., V GJ = V GM - ΔV, where ΔV is the voltage drop of switch S1). During the conduction of MOSFET M1, that is, when the drain voltage V of MOSFET M1 SW switches from high level to low level, due to the conduction of switch S1, a larger current can charge the capacitance C between the gate terminal and the drain terminal of JFET J1 GDJ . That is to say, the gate current I G is allowed to have a larger value to quickly charge the capacitance and change the drain voltage of JFET J1, so as to have a higher switching speed. After a period of time T1, at time t2, the timing circuit 618 provides a low-level control signal S T to turn off switch S1. At the same time, the current limiting circuit 614 limits the gate current I flowing to the gate terminal of JFET J1 G .

[0041] Figure 8 FIG. shows a power switch device 800 according to another embodiment of the present disclosure. As Figure 8 shown, the power switch device includes a first transistor J1, a second transistor M1, and a gate driver 880. The gate driver 880 includes a driving circuit 810, a current source 820, a timing circuit 830, and a transistor MS. The driving circuit 810 is used to provide a driving signal S D to the gate of transistor M1. In one embodiment, the driving circuit 810 includes a first driver 812 and a second driver 814. The first driver 812 and the second driver 814 have different driving capabilities or driving strengths. The driving capability or driving strength is related to the time required for power switch switching (e.g., from off to on, or from on to off), that is, the switching transition rate. For example, a higher driving capability is used to achieve a faster switching speed, while a lower driving capability is used to achieve a slower switching speed. The driving capability or driving strength is determined by the ratio between the current conducted by the driver and the voltage at the output terminal of the driver. For example, in order to obtain a higher driving strength, a transistor with a larger W / L ratio needs to be used, where W is the channel width of the transistor and L is the channel length of the transistor.

[0042] The current source 820 is used to provide a limiting current I flowing to the gate of transistor J1 G . In one example, the current source 820 is implemented by a current mirror including transistors M 11 , M 12 and a reference current source I REF .

[0043] The transistor MS is coupled between the gate of the transistor J1 and the gate of the transistor M1. The transistor MS is turned on to provide a gate drive signal to the gate of the transistor J1, and the voltage of the gate drive signal is lower than the voltage of the drive signal S D of.

[0044] The timing circuit 830 is configured to provide the control signal S when the transistor M1 is turned on (e.g., based on the PWM signal of the transistor M1) T to turn on the transistor MS. The timing circuit 830 is further configured to provide the control signal S after the transistor M1 has been turned on for a period of time (e.g., T1) T to turn off the transistor MS.

[0045] Although Figures 2 - 6 the cascaded switching devices of Figure 8 and the power switching devices only show series-connected normally-on switching devices and normally-off switching devices. However, the present disclosure is not limited thereto. The cascaded switching devices may include one or more resistors, capacitors, and other components, as well as circuits coupled to the source, gate, or drain of the normally-on switching devices or the normally-off switching devices.

[0046] Based on the above, the present disclosure provides various cascaded switching devices, power switching devices, and their gate drivers to control the switching transition rate of the normally-on switching devices. Although the present invention has been described with reference to several exemplary embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be broadly construed within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A cascade switch device, comprising: A normally-on switch device having a first terminal, a second terminal and a control terminal; A normally-off switch device having a first end, a second end and a control end, wherein the first end of the normally-off switch device is coupled to the second end of the normally-on switch device, and the control end of the normally-off switch device is coupled to the control end of the normally-on switch device; as well as A gate driver, configured to provide a gate drive signal to a control terminal of the normally-on switching device to control a switching conversion rate of a voltage at a first terminal of the normally-on switching device; The normally-on switch device is turned on or off in response to a gate drive signal.

2. The cascade switch device of claim 1, wherein the gate driver comprises: The current limiting circuit is used to provide a limited current flowing to the control terminal of the normally-on switching device.

3. The cascade switch device of claim 1 , wherein the gate driver comprises: A driving circuit, used for providing a driving signal to a control terminal of a normally-off switching device; as well as The voltage drop circuit is coupled between the control end of the normally-on switching device and the control end of the normally-off switching device, wherein the voltage drop circuit is used to provide a gate drive signal to the control end of the normally-on switching device, and the voltage of the gate drive signal is lower than the voltage of the drive signal.

4. The cascade switch device of claim 3, wherein the voltage drop circuit comprises a switch, and the gate driver further comprises: The timing circuit is used to provide a control signal to turn on the normally-off switch device when the normally-off switch device is turned on in response to the driving signal.

5. The cascade switch device as claimed in claim 4, wherein the timing circuit is further used to provide a control signal to turn off the normally-off switch device after a period of time has passed since the normally-off switch device was turned on.

6. The cascade switch device of claim 4, wherein the gate driver further comprises: The current limiting circuit is used to provide a limited current flowing to the control terminal of the normally-on switching device after a period of time.

7. The cascade switch device of claim 1, wherein the normally-on switch device comprises a wide-bandgap (WBG) semiconductor switch, and the WBG semiconductor switch is integrated on a first die, and the gate driver and the normally-off switch device are integrated on a second die.

8. A power switching device, comprising: A first transistor having a first source, a first drain and a first gate; a second transistor having a second source, a second drain, and a second gate; as well as a gate driver for providing a gate drive signal to a first gate of the first transistor to control a switching conversion rate of a voltage at a first drain of the first transistor; The first transistor is turned on or off in response to a gate driving signal.

9. The power switching device of claim 8, wherein the gate driver comprises: The current source is used to provide a limited current flowing to the first gate of the first transistor.

10. The power switch device of claim 8, wherein the gate driver comprises: a driving circuit, configured to provide a driving signal to a second gate of the second transistor; as well as The third transistor is coupled between the first gate of the first transistor and the second gate of the second transistor, wherein the third transistor is turned on to provide a gate driving signal to the first gate of the first transistor, and the voltage of the gate driving signal is lower than the voltage of the driving signal.

11. The power switch device of claim 10, wherein the gate driver further comprises: The timing circuit is used for providing a control signal to turn on the third transistor when the second transistor is turned on in response to the driving signal. 12 . The power switch device as claimed in claim 11 , wherein the timing circuit is further configured to provide a control signal to turn off the third transistor after the second transistor is turned on and a period of time has passed.

13. The power switch device of claim 11, wherein the gate driver further comprises: The current source is used for providing a limited current flowing to the first gate of the first transistor after a period of time.

14. The power switching device of claim 11, wherein the first transistor comprises a Junction Field-Effect Transistor (JFET), and the second transistor comprises a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

15. The power switch device of claim 11, wherein the first transistor is integrated on a WBG die, and the gate driver and the second transistor are integrated on a second die.

16. A gate driver for driving a cascaded switching device having a normally-on switching device and a normally-off switching device, wherein the gate driver comprises: A driving circuit for providing a gate driving signal to a control terminal of the normally-on switching device and a control terminal of the normally-off switching device to control a switching conversion rate of a voltage at a first terminal of the normally-on switching device; The normally-on switch device is turned on or off in response to a gate drive signal.

17. The gate driver according to claim 16, further comprising: The current limiting circuit is used to provide a limited current flowing to the control terminal of the normally-on switching device.

18. The gate driver according to claim 16, further comprising: The voltage drop circuit is coupled between the control end of the normally-on switch device and the control end of the normally-off switch device, wherein the voltage drop circuit is used to receive a drive signal and provide a gate drive signal to the control end of the normally-on switch device, and the voltage of the gate drive signal is lower than the voltage of the drive signal.

19. The gate driver of claim 18, wherein the voltage drop circuit comprises a switch, and the gate driver further comprises: The timing circuit is used to provide a control signal to turn on the normally-off switch device when the normally-off switch device is turned on in response to the driving signal.

20. The gate driver as claimed in claim 19, wherein the timing circuit is further configured to provide a control signal to turn off the normally-off switch device after a period of time has passed since the normally-off switch device was turned on.

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