A GaN integrated chip and device

Abstract

The present invention discloses a GaN integrated chip and device. The GaN integrated chip includes a depletion-mode power switch tube and a startup circuit. The depletion-mode power switch tube has a first source electrode, a first drain electrode, and a first gate electrode. The startup circuit includes at least a startup device, a capacitor structure, and a diode structure. The startup device has a second source electrode. One end of the first source electrode is electrically connected to the positive electrode of the diode structure, and the negative electrode of the diode structure is electrically connected to one end of the second source electrode. The negative electrode of the diode structure is also electrically connected to one end of the capacitor structure. During startup, the startup device is in an on state. After startup, the startup device is in an off state. The startup circuit is used to power the IC during startup, and the first source electrode is used to continuously power the IC after startup. The GaN integrated chip and device of the present invention greatly simplify the structure of the startup circuit and the power supply circuit after startup, which helps reduce costs and improve device reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and in particular relates to a GaN integrated chip and a device comprising the GaN integrated chip. Background Art

[0002] In the prior art, AC / DC power supply control chips are often powered by an additional auxiliary winding. Due to the low efficiency of the startup circuit, after the power supply is started, the startup circuit is often turned off and power is switched to the auxiliary winding of the transformer to supply the control chip. The voltage in the auxiliary winding with a fixed number of turns will change with the output voltage, and an additional voltage stabilization circuit is often required. This makes the power supply structure design complex and the cost high.

[0003] At the same time, cascaded GaN devices often experience capacitance matching issues at the moment of turn-off, causing the Si MOS lower tube voltage to overshoot, reaching or approaching avalanche, which affects the reliability of the device. Summary of the Invention

[0004] In view of this, in order to overcome the shortcomings of the prior art, the purpose of the present invention is to provide a GaN integrated chip and device, which realizes the monolithic integration of a depletion-mode power switch tube and a high-voltage startup circuit (start-up circuit), replaces the power supply method of the auxiliary winding, simplifies the circuit structure, and helps reduce costs.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A GaN integrated chip includes a depletion-mode power switch tube and a startup circuit, wherein the depletion-mode power switch tube has a first source electrode, a first drain electrode, and a first gate electrode; the startup circuit includes at least a startup device, a capacitor structure, and a diode structure; the startup device has a second source electrode, one end of the first source electrode is electrically connected to the positive electrode of the diode structure, the cathode of the diode structure is electrically connected to one end of the second source electrode, and the cathode of the diode structure is also electrically connected to one end of the capacitor structure; during startup, the startup device is in an on state; after startup, the startup device is in an off state;

[0007] The startup circuit is used to power the IC during startup, and the first source electrode of the depletion-mode power switch is used to continuously power the IC after startup. The diode structure ensures unidirectional current flow; when the depletion-mode power switch begins switching, the power supply path is switched to the first source electrode. The capacitor structure allows a certain voltage difference to be generated across it to shut down the startup device.

[0008] By integrating the depletion-mode power switch tube with the startup circuit on a single chip, the power supply method of the auxiliary winding is replaced after startup. The power is obtained from the first source electrode end of the depletion-mode power switch tube with the shortest loop. At the same time, after startup, the first source electrode end of the depletion-mode power switch tube continues to supply power to the IC (Integrated Circuit). This greatly simplifies the structure of the startup circuit and the power supply circuit after startup, which is conducive to reducing costs. At the same time, it avoids the voltage overshoot problem of the Si MOS bottom tube of the cascaded GaN device at the moment of shutdown.

[0009] According to some preferred embodiments of the present invention, the startup device further has a second drain electrode and a second gate electrode, and the first source electrode, the first drain electrode, the first gate electrode, the second source electrode, the second drain electrode and the second gate electrode are all used as output terminals.

[0010] According to some preferred embodiments of the present invention, the startup circuit includes a startup device, a capacitor structure, and a diode structure, the second gate electrode is used to connect to a control output terminal having a source-controlled startup function, and one end of the capacitor structure is used to be grounded. In some embodiments of the present invention, the second drain electrode is used as an output terminal to connect to a high level, the second gate electrode is used as an output terminal to connect to a control output terminal having a source-controlled startup function, the second source electrode is used as an output terminal to power the IC during startup, the first drain electrode is used as an output terminal to be connected to a main loop of an external circuit, the first gate electrode is used as an output terminal to be connected to a third source electrode of a low-voltage enhancement MOS chip and then used together as a source terminal, the first source electrode is used as an output terminal to be connected to the third drain electrode of the low-voltage enhancement MOS chip to form a cascade device, and one end of the capacitor structure is used as an output terminal to be grounded.

[0011] According to some preferred implementation aspects of the present invention, the startup circuit includes a startup device, a capacitor structure, a diode structure, and a first resistor structure.

[0012] According to some preferred implementation aspects of the present invention, two ends of the first resistance structure are electrically connected to two ends of the capacitor structure, respectively, and the capacitor structure is also electrically connected to the second gate electrode.

[0013] According to some preferred embodiments of the present invention, the second gate electrode is connected to ground. In some embodiments of the present invention, the second drain electrode is used as an output terminal for connecting to a high level, the second gate electrode is used as an output terminal for grounding, the second source electrode is used as an output terminal for powering the IC during startup, the first drain electrode is used as an output terminal for accessing the main loop of an external circuit, the first gate electrode is used as an output terminal for connecting to the third source electrode of a low-voltage enhancement-mode MOS chip and then serving as a source terminal together, and the first source electrode is used as an output terminal for connecting to the third drain electrode of the low-voltage enhancement-mode MOS chip to form a cascaded device.

[0014] According to some preferred implementation aspects of the present invention, the startup circuit further includes a second resistance structure.

[0015] According to some preferred implementation aspects of the present invention, the first resistance structure is further electrically connected to one end of the second resistance structure, and the other end of the second resistance structure is used as an output end.

[0016] According to some preferred embodiments of the present invention, the second resistor structure is configured to serve as an output terminal, one end of which is electrically connected to the source electrode of the cascaded low-voltage enhancement-mode MOS chip. In some embodiments of the present invention, the second drain electrode is configured to serve as an output terminal for connecting to a high level, the second gate electrode is configured to serve as an output terminal for grounding (used as the ground terminal on the startup circuit side, and also as the ground terminal on the cascaded device side after passing through the current-sense resistor), the second source electrode is configured to serve as an output terminal for powering the IC during startup, the first drain electrode is configured to serve as an output terminal for connection to the main loop of the external circuit, the first gate electrode is configured to serve as an output terminal for connecting to the third source electrode of the low-voltage enhancement-mode MOS chip and then serving together as a source terminal, the first source electrode is configured to serve as an output terminal for connecting to the third drain electrode of the low-voltage enhancement-mode MOS chip, forming a cascaded device; and the second resistor structure is configured to serve as an output terminal, one end of which is electrically connected to the source electrode of the cascaded low-voltage enhancement-mode MOS chip.

[0017] According to some preferred embodiments of the present invention, the second resistor structure is used as a current-sense resistor. In some embodiments of the present invention, the introduction of a current-sense resistor can further simplify and reduce peripheral circuits in a PCB board, thereby reducing loop parasitic parameters while lowering costs, thereby improving electromagnetic interference.

[0018] According to some preferred embodiments of the present invention, the startup circuit further includes a third resistor structure connected in series with the second drain electrode. In some embodiments of the present invention, both the first resistor structure and the third resistor structure are used for current limiting and voltage division to prevent excessive current from damaging the startup device.

[0019] The present invention further provides a device comprising a low-voltage enhancement mode MOS chip and the GaN integrated chip as described above, wherein the device is formed by cascading the low-voltage enhancement mode MOS chip and the GaN integrated chip.

[0020] According to some preferred embodiments of the present invention, including a source terminal, a drain terminal and a gate terminal, the low-voltage enhancement MOS chip has a third source electrode, a third drain electrode and a third gate electrode, the first gate electrode and the third source electrode are connected and used together as the source terminal, the third gate electrode is used as the gate terminal, and the first drain electrode is used as the drain terminal.

[0021] Due to the adoption of the above technical solutions, the present invention is beneficial compared to the prior art in that: a GaN integrated chip and device of the present invention integrates a depletion-mode power switch tube with a startup circuit into a single chip. After startup, the power is taken from the first source electrode end of the depletion-mode power switch tube in the shortest loop, replacing the auxiliary winding power supply method. At the same time, after startup, the first source electrode end of the depletion-mode power switch tube continues to supply power to the IC. This greatly simplifies the structure of the startup circuit and the power supply circuit after startup, which is conducive to reducing costs. At the same time, it avoids the voltage overshoot problem of the Si MOS bottom tube at the moment of shutdown in the device formed by cascading the GaN integrated chip and the low-voltage enhancement MOS chip, which is conducive to improving the reliability of the device. In addition, since the depletion-mode power switch tube generates heat, integrating the startup circuit around it is conducive to expanding the device size and significantly optimizing the thermal resistance of the depletion-mode power switch tube, thereby improving its performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 Schematic diagram of the top view of the cascaded devices in Example 1 of the present invention;

[0024] Figure 2 Schematic diagram of the top view of the cascaded devices in Example 2 of the present invention;

[0025] Figure 3 Schematic diagram of the top view of the cascaded devices in Example 3 of the present invention;

[0026] Figure 4 for Figure 1 Schematic cross-section along the dotted line A;

[0027] Figure 5 for Figure 1 Schematic cross-section along the dotted line B;

[0028] Figure 6 for Figure 1 Schematic cross-section along the dotted line C;

[0029] Figure 7 for Figure 1 Schematic cross-section along the dotted line D;

[0030] Figure 8 for Figure 1 Schematic cross-section along the dotted line E;

[0031] Figure 9 for Figure 2 Schematic cross-section along the dotted line F;

[0032] Figure 10 for Figure 3 A schematic cross-sectional view along the dotted line G;

[0033] Figure 11 : is an equivalent circuit diagram of the GaN integrated chip in Example 1 of the present invention;

[0034] Figure 12 : is an equivalent circuit diagram of the GaN integrated chip in Example 2 of the present invention;

[0035] Figure 13 : is an equivalent circuit diagram of the GaN integrated chip in Example 3 of the present invention;

[0036] The accompanying drawings are numerals: GaN integrated chip 100, low-voltage enhancement MOS chip 200, depletion-mode power switch tube 101, startup device 102, capacitor structure 103, diode structure 104, first resistor structure 105, second resistor structure 106, third resistor structure 107, substrate 108, nucleation layer 1091, buffer layer 1092, channel layer 1093, barrier layer 1094, cap layer 1095, first dielectric layer 110, second dielectric layer 111, third dielectric layer 112;

[0037] First source electrode-1, first drain electrode-2, first gate electrode-3, second source electrode-4, second drain electrode-5, second gate electrode-6, third source electrode-7, third drain electrode-8, third gate electrode-9, first source electrode ohmic metal-10, first drain electrode ohmic metal-11, first gate electrode metal-12, second source electrode ohmic metal-13, second drain electrode ohmic metal-14, second gate electrode metal-15, first ohmic metal-16, second ohmic metal-17, third ohmic metal-18, Schottky metal-19, first field plate-20, second field plate-21, third field plate-22, fourth field plate-23, first gold Metal connecting strip-24, second metal connecting strip-25, third metal connecting strip-26, fourth metal connecting strip-27, fifth metal connecting strip-28, sixth metal connecting strip-29, seventh metal connecting strip-30, eighth metal connecting strip-31, ninth metal connecting strip-32, first connecting segment-33, second connecting segment-34, third connecting segment-35, lower electrode-36, upper electrode-37, capacitor electrode-38, diode electrode-39, first resistor-40, second resistor-41, third resistor-42, first resistor electrode-43, second resistor electrode-44, third resistor electrode-45, bonding wire-46, pin-47. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0039] A cascaded device according to the present invention includes a low-voltage enhancement-mode MOS chip 200 and a GaN integrated chip 100. The cascaded device is formed by cascading the low-voltage enhancement-mode MOS chip 200 and the GaN integrated chip 100. The GaN integrated chip 100 includes a depletion-mode power switch 101, a startup circuit, and, from bottom to top, a substrate 108, a stacked structure, a first dielectric layer 110, a second dielectric layer 111, and a third dielectric layer 112. The startup circuit includes at least a startup device 102, a capacitor structure 103, and a diode structure 104. The depletion-mode power switch 101 has a first source electrode 1, a first drain electrode 2, and a first gate electrode 3. The startup device 102 has a second source electrode 4, a second drain electrode 5, and a second gate electrode 6. The low-voltage enhancement-mode MOS chip 200 has a third source electrode 7, a third drain electrode 8, and a third gate electrode 9. The cascaded device has a source terminal, a drain terminal, and a gate terminal. In actual packaging, the first source electrode 1 is connected to the third drain electrode 8 through a bonding wire 46, the first gate electrode 3 and the third source electrode 7 are connected and used together as the source terminal, the third gate electrode 9 is used as the gate terminal, and the first drain electrode 2 is used as the drain terminal.

[0040] In the cascade-type device of the present invention, the startup device 102 is in the on state during startup, and is in the off state after startup; the startup circuit is used to power the IC during startup, and the first source electrode 1 of the depletion-type power switch tube 101 is used to continuously power the IC after startup.

[0041] Furthermore, in some embodiments of the present invention, the startup circuit only includes a startup device 102, a capacitor structure 103, and a diode structure 104. One end of the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104, the negative electrode of the diode structure 104 is electrically connected to one end of the second source electrode 4, and the negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103. The second drain electrode 5 is used as an output terminal to connect to a high level, the second gate electrode 6 is used as an output terminal to connect to a control output terminal having a source-controlled startup function, the second source electrode 4 is used as an output terminal to power the IC during startup, the first drain electrode 2 is used as an output terminal to be connected to the main loop of an external circuit, the first gate electrode 3 is used as an output terminal to be connected to the third source electrode 7 and then used together as a source terminal, the first source electrode 1 is used as an output terminal to be connected to the third drain electrode 8, and the other end of the capacitor structure 103 is used as an output terminal to be grounded.

[0042] In some other embodiments of the present invention, the startup circuit includes a startup device 102, a capacitor structure 103, a diode structure 104, and a first resistor structure 105. One end of the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104, the negative electrode of the diode structure 104 is electrically connected to one end of the second source electrode 4, the negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103, the two ends of the first resistor structure 105 are respectively electrically connected to the two ends of the capacitor structure 103, and the capacitor structure 103 is also electrically connected to the second gate electrode 6. The second drain electrode 5 is used as an output end to connect to a high level, the second gate electrode 6 is used as an output end to connect to ground, the second source electrode 4 is used as an output end to power the IC during startup, the first drain electrode 2 is used as an output end to connect to the main loop of the external circuit, the first gate electrode 3 is used as an output end to connect to the third source electrode 7 and then serve as a source end, and the first source electrode 1 is used as an output end to connect to the third drain electrode 8.

[0043] In some other embodiments of the present invention, the startup circuit includes a startup device 102 , a capacitor structure 103 , a diode structure 104 , a first resistor structure 105 , and a second resistor structure 106 . The second resistor structure 106 is used as a current-sense resistor; one end of the first source electrode 1 is electrically connected to the anode of the diode structure 104, the cathode of the diode structure 104 is electrically connected to one end of the second source electrode 4, and the cathode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103. The two ends of the first resistor structure 105 are respectively electrically connected to the two ends of the capacitor structure 103, and the capacitor structure 103 is also electrically connected to the second gate electrode 6. The first resistor structure 105 is also electrically connected to one end of the second resistor structure 106. The other end of the second resistor structure 106 is used as an output end to be electrically connected to the third source electrode 7; the second drain electrode 5 is used as an output end to connect to a high level, the second gate electrode 6 is used as an output end to be grounded, the second source electrode 4 is used as an output end to power the IC at startup, the first drain electrode 2 is used as an output end to be connected to the main loop of the external circuit, the first gate electrode 3 is used as an output end to be connected to the third source electrode 7 and then used together as a source end, and the first source electrode 1 is used as an output end to be connected to the third drain electrode 8.

[0044] Furthermore, the startup circuit of the present invention may further include a third resistor structure 107 , which is connected in series with the second drain electrode 5 to perform current limiting and voltage dividing functions.

[0045] The structure of the cascade device of the present invention is described in detail below. Example 1

[0046] like Figure 1As shown, the cascade device in this embodiment is formed by cascading a low-voltage enhancement MOS chip 200 and a GaN integrated chip 100, wherein the GaN integrated chip 100 includes a depletion-mode power switch tube 101, a startup circuit, and a substrate 108, a stacked structure, a first dielectric layer 110, a second dielectric layer 111, and a third dielectric layer 112 arranged in sequence from bottom to top. The stacked structure includes a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095 arranged in sequence from bottom to top. The cascade device has a source terminal, a drain terminal, and a gate terminal.

[0047] like Figure 1 and Figure 4 As shown, the depletion-mode power switch tube 101 includes a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a first source electrode ohmic metal 10, a first drain electrode ohmic metal 11, a first gate electrode metal 12, a first field plate 20, a second field plate 21, a first metal connecting bar 24, a second metal connecting bar 25 and a third metal connecting bar 26. The first source electrode ohmic metal 10 and the first drain electrode ohmic metal 11 are both located in the barrier layer 1094 and the cap layer 1095; the first gate electrode metal 12 is located in the first dielectric layer 110, the first field plate 20 is located in the second dielectric layer 111, and the second field plate 21 is located in the third dielectric layer 112; the first source electrode 1, the first drain electrode 2 and the first gate electrode 3 are all located above the third dielectric layer 112; the first metal connecting bar 24, the second metal connecting bar 25 and the third metal connecting bar 26 all pass through the first dielectric layer 110, the second dielectric layer 111 and the third dielectric layer 112, the two ends of the first metal connecting bar 24 are respectively connected to the first source electrode ohmic metal 10 and the first source electrode 1, the two ends of the second metal connecting bar 25 are respectively connected to the first drain electrode ohmic metal 11 and the first drain electrode 2, and the two ends of the third metal connecting bar 26 are respectively connected to the first gate electrode metal 12 and the first gate electrode 3. In this embodiment, the depletion-mode power switch tube 101 is provided with a plurality of first source electrode ohmic metals 10 and corresponding first metal connecting strips 24, a plurality of first drain electrode ohmic metals 11 and corresponding second metal connecting strips 25. The plurality of first source electrode ohmic metals 10 are electrically connected to the first source electrode 1 at the same time through the plurality of first metal connecting strips 24, and the plurality of first drain electrode ohmic metals 11 are electrically connected to the first drain electrode 2 at the same time through the plurality of second metal connecting strips 25.

[0048] Furthermore, if Figure 1 and Figure 5As shown, the startup circuit of this embodiment includes a startup device 102, a capacitor structure 103, a diode structure 104, and a third resistor structure 107. The startup device 102 includes a second source electrode 4, a second drain electrode 5, a second gate electrode 6, a second source electrode ohmic metal 13, a second drain electrode ohmic metal 14, a second gate electrode metal 15, a third field plate 22, a fourth field plate 23, a fourth metal connecting bar 27, a fifth metal connecting bar 28, and a sixth metal connecting bar 29. The second source electrode ohmic metal 13 and the second drain electrode ohmic metal 14 are both located in the barrier layer 1094 and the cap layer 1095; the second gate electrode metal 15 is located in the first dielectric layer 110, the third field plate 22 is located in the second dielectric layer 111, and the fourth field plate 23 is located in the third dielectric layer 112; the second source electrode 4, the second drain electrode 5 and the second gate electrode 6 are all located above the third dielectric layer 112; the fourth metal connecting bar 27, the fifth metal connecting bar 28 and the sixth metal connecting bar 29 all pass through the first dielectric layer 110, the second dielectric layer 111 and the third dielectric layer 112, the two ends of the fourth metal connecting bar 27 are respectively connected to the second source electrode ohmic metal 13 and the second source electrode 4, the two ends of the fifth metal connecting bar 28 are respectively connected to the second drain electrode ohmic metal 14 and the second drain electrode 5, and the two ends of the sixth metal connecting bar 29 are respectively connected to the second gate electrode metal 15 and the second gate electrode 6. In this embodiment, the startup device 102 has one second source ohmic metal electrode 13 and one corresponding fourth metal connecting bar 27 , and one second drain ohmic metal electrode 14 and one corresponding fifth metal connecting bar 28 .

[0049] like Figure 1 and Figure 6 As shown, the capacitor structure 103 of this embodiment includes a lower electrode 36, an upper electrode 37, two capacitor electrodes 38, a seventh metal connecting strip 30 located on one side of the lower electrode 36, and an eighth metal connecting strip 31 located on one side of the upper electrode 37. The lower electrode 36 is located in the second dielectric layer 111, the upper electrode 37 is located in the third dielectric layer 112, and both capacitor electrodes 38 are located above the third dielectric layer 112. The seventh metal connecting strip 30 penetrates the second dielectric layer 111 and the third dielectric layer 112, and its two ends are respectively connected to the lower electrode 36 and one capacitor electrode 38. The eighth metal connecting strip 31 penetrates the third dielectric layer 112, and its two ends are respectively connected to the upper electrode 37 and the other capacitor electrode 38.

[0050] like Figure 1 and Figure 7As shown, the diode structure 104 includes a first ohmic metal 16, a Schottky metal 19, two diode electrodes 39, and two ninth metal connecting strips 32. The first ohmic metal 16 and the Schottky metal 19 are both located in the barrier layer 1094 and the cap layer 1095. The two diode electrodes 39 are both located above the third dielectric layer 112. The two ninth metal connecting strips 32 penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of one ninth metal connecting strip 32 are respectively connected to the first ohmic metal 16 and one diode electrode 39 to form the cathode of the diode structure 104. The two ends of the other ninth metal connecting strip 32 are respectively connected to the Schottky metal 19 and the other diode electrode 39 to form the anode of the diode structure 104.

[0051] like Figure 1 and Figure 8 As shown, the third resistor structure 107 is arranged on one side of the second drain electrode 5 of the startup device 102. The third resistor structure 107 includes a third resistor 42, a second ohmic metal 17 located on both sides of the third resistor 42, two third resistor electrodes 45, and two first connecting segments 33. The third resistor structure 107 is connected in series with the second drain electrode 5. Among them, the third resistor 42 is located in the channel layer 1093, the two second ohmic metals 17 are located in the barrier layer 1094 and the cap layer 1095, the two third resistor electrodes 45 are located above the third dielectric layer 112, and the two first connecting segments 33 pass through the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each first connecting segment 33 are respectively connected to a corresponding second ohmic metal 17 and a third resistor electrode 45. In this embodiment, the resistance value of the third resistor 42 is 1×10 3 ~5×10 7 Ω.

[0052] Further, if Figure 1 and Figure 12 As shown, in the GaN integrated chip 100 of this embodiment, one end of the first source electrode 1 is connected to a diode electrode 39 corresponding to the positive electrode of the diode structure 104 so that the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104, one end of the second source electrode 4 is connected to a diode electrode 39 corresponding to the negative electrode of the diode structure 104 so that the second source electrode 4 is electrically connected to the negative electrode of the diode structure 104, a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 is connected to a diode electrode 39 corresponding to the negative electrode of the diode structure 104 so that the negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103, and one of the third resistor electrodes 45 is connected to the second drain electrode 5 so that the third resistor structure 107 is connected in series with the second drain electrode 5.

[0053] Furthermore, the low voltage enhancement mode MOS chip 200 has a third source electrode 7, a third drain electrode 8 and a third gate electrode 9. The startup network formed in this embodiment is suitable for some active control startup circuits, such as the IW1699 main control IC, whose ASU (Active The Start-Up pin can control the shutdown of the startup device 102. When the GaN integrated chip 100 of this embodiment is actually packaged with the low-voltage enhancement MOS chip 200, the first source electrode 1 is connected to the third drain electrode 8 through a bonding wire 46; the first gate electrode 3 is connected to the third source electrode 7 through a bonding wire 46, so that one end of the first gate electrode 3 is used as an output end and is connected to the third source electrode 7 and then used together as a source end; at the same time, the third source electrode 7 is connected to a corresponding pin 47 through a bonding wire 46; one end of the third gate electrode 9 is connected to a corresponding pin 47 through a bonding wire 46, so that the third gate electrode 9 is used as a gate end; one end of the first drain electrode 2 is connected to a corresponding pin 47 through a bonding wire 46, so that one end of the first drain electrode 2 is used as an output end to be connected to the main loop of the external circuit (the first drain electrode 2 is used as the drain end); the second drain electrode 5 is connected away from the second drain electrode 5. One end of a third resistor electrode 45 is connected to a corresponding pin 47 via a bonding wire 46. Since the second drain electrode 5 in this embodiment is connected in series with the third resistor structure 107, one end of another third resistor electrode 45 in the third resistor structure 107 that is not connected to the second drain electrode 5 is used as an output end to connect to a high level; one end of the second gate electrode 6 is connected to a corresponding pin 47 via a bonding wire 46, so that one end of the second gate electrode 6 is used as an output end to connect to the control output end ASU having a source control startup function; one end of the second source electrode 4 is connected to a corresponding pin 47 via a bonding wire 46, so that one end of the second source electrode 4 is used as an output end to power the IC when the computer is started; one end of the capacitor electrode 38 is connected to a corresponding pin 47 via a bonding wire 46, so that one end of the capacitor electrode 38 corresponding to the lower electrode 36 in the capacitor structure 103 is used as an output end for grounding.

[0054] During startup, startup device 102 is in the on state. Current flows through startup device 102, charging capacitor structure 103. The capacitor voltage continues to rise, which in turn increases the potential at one end of second source electrode 4. Until the IC begins operating, current flows from third resistor structure 107 through the channel of startup device 102 to second source electrode 4. After the startup process completes, the driver chip begins normal operation, and depletion-mode power switch 101 begins switching. At the moment of switching off, the instantaneous potential of first source electrode 1 is higher than the potential of second source electrode 4 of startup device 102. At this point, current flows from first drain electrode 2 of depletion-mode power switch 101, through its channel, from first source electrode 1, through diode structure 104, and finally to second source electrode 4, thereby powering the control chip. When the IC is powered normally, the ASU pin outputs a low level, pulling down the gate potential of startup device 102, thereby shutting down startup device 102. From then on, the startup circuit experiences virtually no power loss.

[0055] The above circuit is also applicable to ICs without ASU pins. It only requires building an external gate pull-down loop.

[0056] This embodiment also provides a method for preparing the GaN integrated chip 100, which specifically includes the following steps:

[0057] Step 1: Nitride epitaxial growth is performed on substrate 108 to sequentially form a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095. Materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 1091, buffer layer 1092, channel layer 1093, barrier layer 1094, and cap layer 1095 form a stacked structure, thus forming a complete semiconductor epitaxial layer structure. This structure can generate a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 1093 and the barrier layer 1094, generating a conductive channel. Substrate 108 can be made of one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing Group III nitride materials.

[0058] Step 2: Through photoresist protection, patterning is performed on the top of the cap layer 1095 and ion material is injected to destroy the two-dimensional electron gas to form an isolation area. The protected non-injected area is the continuous area chip active area where the first source electrode 1, the first drain electrode 2 and the first gate electrode 3 exist, the continuous area chip active area where the second source electrode 4, the second drain electrode 5 and the second gate electrode 6 exist, and the area where the capacitor structure 103, the diode structure 104 and the third resistor structure 107 are formed, and the third resistor 42 is formed.

[0059] Step 3: Graphic etching is performed on the cap layer 1095 to form a first source electrode ohmic hole and a first drain electrode ohmic hole, and at the same time, a second source electrode ohmic hole and a second drain electrode ohmic hole are etched to form a first positive electrode hole and a negative electrode hole. At the same time, graphic etching is performed on both sides of the third resistor 42 to form two first ohmic contact holes.

[0060] Step 4: Fill the first source electrode ohmic hole, the first drain electrode ohmic hole, the second source electrode ohmic hole, the second drain electrode ohmic hole, the cathode hole, and the two first ohmic contact holes with metal to form the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, and the second ohmic metal 17 on both sides of the third resistor 42, and perform annealing. At this time, the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, and the two second ohmic metals 17 respectively form ohmic contacts with the epitaxial material below. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0061] Step 5: Deposit one or more combinations of SiN, SiO2, SiON, Al2O3 on the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16 and the second ohmic metal 17 to form a first dielectric layer 110, and etch out a first gate groove and a second gate groove respectively, and at the same time etch out a second anode hole at the position of the first anode hole covered by the first dielectric layer 110.

[0062] Step 6: Fill metal above the first dielectric layer 110 to completely cover the first gate groove, the second gate groove and the second anode hole, and etch to form the first gate electrode metal 12 (the portion located in the first gate groove) and the first field plate 20, and at the same time, etch to form the second gate electrode metal 15 (the portion located in the second gate groove) and the third field plate 22, and at the same time, etch to form the Schottky metal 19, and at the same time, etch to form the lower electrode 36.

[0063] Step 7: Deposit one or more combinations of SiN, SiO 2 , SiON, and Al 2 O 3 on the first gate electrode metal 12 , the second gate electrode metal 15 , and the bottom electrode 36 to form a second dielectric layer 111 .

[0064] Step 8: Fill metal above the second dielectric layer 111 and etch to form a second field plate 21, a fourth field plate 23 and an upper electrode 37, and then deposit one or more combinations of SiN, SiO2, SiON, Al2O3 above the second field plate 21, the fourth field plate 23 and the upper electrode 37 to form a third dielectric layer 112.

[0065] Step 9: Etching downward from the third dielectric layer 112 to form a first source electrode through hole, a first drain electrode through hole, a first gate electrode through hole, a second source electrode through hole, a second drain electrode through hole, a second gate electrode through hole, two first through holes, two second through holes and two third through holes, wherein the first source electrode through hole, the first drain electrode through hole, the first gate electrode through hole, the second source electrode through hole, the second drain electrode through hole, the second gate electrode through hole, the two second through holes and the two third through holes all pass through the first dielectric layer 110, the second dielectric layer 111 and the third dielectric layer 112, one first through hole passes through the third dielectric layer 112 and the second dielectric layer 111, and the other first through hole passes through the third dielectric layer 112.

[0066] Step 10: Fill metal into the first source electrode through hole, the first drain electrode through hole, the first gate electrode through hole, the second source electrode through hole, the second drain electrode through hole, the second gate electrode through hole, the two first through holes, the two second through holes and the two third through holes to form a first metal connecting bar 24, a second metal connecting bar 25, a third metal connecting bar 26, a fourth metal connecting bar 27, a fifth metal connecting bar 28, a sixth metal connecting bar 29, a seventh metal connecting bar 30, an eighth metal connecting bar 31, two ninth metal connecting bars 32 and two first connecting segments 33 respectively.

[0067] Step 11: Fill the third dielectric layer 112 with metal and etch to form a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a second source electrode 4, a second drain electrode 5, a second gate electrode 6, two capacitor electrodes 38, two diode electrodes 39 and two third resistor electrodes 45. Among them, the two ends of the first metal connecting strip 24 are electrically connected to the first source electrode 1 and the first source electrode ohmic metal 10 respectively, the two ends of the second metal connecting strip 25 are electrically connected to the first drain electrode 2 and the first drain electrode ohmic metal 11 respectively, and the two ends of the third metal connecting strip 26 are electrically connected to the first gate electrode 3 and the first gate electrode metal 12 respectively, forming a depletion-mode power switch tube 101; the two ends of the fourth metal connecting strip 27 are electrically connected to the second source electrode 4 and the second source electrode ohmic metal 13 respectively, the two ends of the fifth metal connecting strip 28 are electrically connected to the second drain electrode 5 and the second drain electrode ohmic metal 14 respectively, and the two ends of the sixth metal connecting strip 29 are electrically connected to the second gate electrode 6 and the second gate electrode metal 15 respectively. The first and second connecting segments 33 are electrically connected to each other, and the second and second ohmic metals 17 are electrically connected to form a third resistor structure 107.

[0068] Step 12: Connect one end of the first source electrode 1 to a diode electrode 39 corresponding to the positive electrode of the diode structure 104, connect one end of the second source electrode 4 to a diode electrode 39 corresponding to the negative electrode of the diode structure 104, connect a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 to a diode electrode 39 corresponding to the negative electrode of the diode structure 104, and connect one of the third resistor electrodes 45 to the second drain electrode 5 to obtain the GaN integrated chip 100 of this embodiment. Example 2

[0069] like Figure 2As shown, the cascade device in this embodiment is formed by cascading a low-voltage enhancement MOS chip 200 and a GaN integrated chip 100, wherein the GaN integrated chip 100 includes a depletion-mode power switch tube 101, a startup circuit, and a substrate 108, a stacked structure, a first dielectric layer 110, a second dielectric layer 111, and a third dielectric layer 112 arranged in sequence from bottom to top. The stacked structure includes a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095 arranged in sequence from bottom to top. The cascade device has a source terminal, a drain terminal, and a gate terminal.

[0070] Furthermore, the structure of the depletion-mode power switch tube 101 of this embodiment is the same as that of Example 1, including a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a first source electrode ohmic metal 10, a first drain electrode ohmic metal 11, a first gate electrode metal 12, a first field plate 20, a second field plate 21, a first metal connecting bar 24, a second metal connecting bar 25 and a third metal connecting bar 26. The first source electrode ohmic metal 10 and the first drain electrode ohmic metal 11 are both located in the barrier layer 1094 and the cap layer 1095; the first gate electrode metal 12 is located in the first dielectric layer 110, the first field plate 20 is located in the second dielectric layer 111, and the second field plate 21 is located in the third dielectric layer 112; the first source electrode 1, the first drain electrode 2 and the first gate electrode 3 are all located above the third dielectric layer 112; the first metal connecting bar 24, the second metal connecting bar 25 and the third metal connecting bar 26 all pass through the first dielectric layer 110, the second dielectric layer 111 and the third dielectric layer 112, the two ends of the first metal connecting bar 24 are respectively connected to the first source electrode ohmic metal 10 and the first source electrode 1, the two ends of the second metal connecting bar 25 are respectively connected to the first drain electrode ohmic metal 11 and the first drain electrode 2, and the two ends of the third metal connecting bar 26 are respectively connected to the first gate electrode metal 12 and the first gate electrode 3. In this embodiment, the depletion-mode power switch tube 101 is provided with a plurality of first source electrode ohmic metals 10 and corresponding first metal connecting strips 24, a plurality of first drain electrode ohmic metals 11 and corresponding second metal connecting strips 25. The plurality of first source electrode ohmic metals 10 are electrically connected to the first source electrode 1 at the same time through the plurality of first metal connecting strips 24, and the plurality of first drain electrode ohmic metals 11 are electrically connected to the first drain electrode 2 at the same time through the plurality of second metal connecting strips 25.

[0071] Further, if Figure 2As shown, the startup circuit of this embodiment includes a startup device 102, a capacitor structure 103, a diode structure 104, a third resistor structure 107, and a first resistor structure 105. The startup device 102 includes a second source electrode 4, a second drain electrode 5, a second gate electrode 6, a second source electrode ohmic metal 13, a second drain electrode ohmic metal 14, a second gate electrode metal 15, a third field plate 22, a fourth field plate 23, a fourth metal connecting bar 27, a fifth metal connecting bar 28, and a sixth metal connecting bar 29. Among them, the second source electrode ohmic metal 13 and the second drain electrode ohmic metal 14 are both located in the barrier layer 1094 and the cap layer 1095; the second gate electrode metal 15 is located in the first dielectric layer 110, the third field plate 22 is located in the second dielectric layer 111, and the fourth field plate 23 is located in the third dielectric layer 112; the second source electrode 4, the second drain electrode 5 and the second gate electrode 6 are all located above the third dielectric layer 112; the fourth metal connecting bar 27, the fifth metal connecting bar 28 and the sixth metal connecting bar 29 all pass through the first dielectric layer 110, the second dielectric layer 111 and the third dielectric layer 112, the two ends of the fourth metal connecting bar 27 are respectively connected to the second source electrode ohmic metal 13 and the second source electrode 4, the two ends of the fifth metal connecting bar 28 are respectively connected to the second drain electrode ohmic metal 14 and the second drain electrode 5, and the two ends of the sixth metal connecting bar 29 are respectively connected to the second gate electrode metal 15 and the second gate electrode 6. In this embodiment, the startup device 102 has one second source ohmic metal electrode 13 and one corresponding fourth metal connecting bar 27 , and one second drain ohmic metal electrode 14 and one corresponding fifth metal connecting bar 28 .

[0072] The capacitor structure 103 of this embodiment includes a lower electrode 36, an upper electrode 37, two capacitor electrodes 38, a seventh metal connecting strip 30 located on one side of the lower electrode 36, and an eighth metal connecting strip 31 located on one side of the upper electrode 37. Specifically, the lower electrode 36 is located in the second dielectric layer 111, the upper electrode 37 is located in the third dielectric layer 112, and both capacitor electrodes 38 are located above the third dielectric layer 112. The seventh metal connecting strip 30 penetrates the second dielectric layer 111 and the third dielectric layer 112, and its two ends are respectively connected to the lower electrode 36 and one capacitor electrode 38. The eighth metal connecting strip 31 penetrates the third dielectric layer 112, and its two ends are respectively connected to the upper electrode 37 and the other capacitor electrode 38.

[0073] The diode structure 104 includes a first ohmic metal 16, a Schottky metal 19, two diode electrodes 39, and two ninth metal connecting strips 32. The first ohmic metal 16 and the Schottky metal 19 are both located in the barrier layer 1094 and the cap layer 1095. The two diode electrodes 39 are both located above the third dielectric layer 112. The two ninth metal connecting strips 32 penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of one ninth metal connecting strip 32 are respectively connected to the first ohmic metal 16 and one diode electrode 39 to form the cathode of the diode structure 104. The two ends of the other ninth metal connecting strip 32 are respectively connected to the Schottky metal 19 and the other diode electrode 39 to form the anode of the diode structure 104.

[0074] The third resistor structure 107 is disposed on one side of the second drain electrode 5 of the startup device 102. The third resistor structure 107 includes a third resistor 42, a second ohmic metal 17 located on both sides of the third resistor 42, two third resistor electrodes 45, and two first connecting segments 33. The third resistor structure 107 is connected in series with the second drain electrode 5. The third resistor 42 is located in the channel layer 1093, the two second ohmic metals 17 are located in the barrier layer 1094 and the cap layer 1095, the two third resistor electrodes 45 are located above the third dielectric layer 112, and the two first connecting segments 33 penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each first connecting segment 33 are respectively connected to a corresponding second ohmic metal 17 and a third resistor electrode 45. In this embodiment, the resistance value of the third resistor 42 is 1×10 3 ~5×10 7 Ω.

[0075] like Figure 2 and Figure 9 As shown, the first resistor structure 105 of this embodiment is arranged on one side of the capacitor structure 103 and has the same structure as the third resistor structure 107. Specifically, the first resistor structure 105 includes a first resistor 40, a third ohmic metal 18 located on both sides of the first resistor 40, two first resistor electrodes 43, and two second connecting segments 34. Among them, the first resistor 40 is located in the channel layer 1093, the two third ohmic metals 18 are both located in the barrier layer 1094 and the cap layer 1095, the two first resistor electrodes 43 are both located above the third dielectric layer 112, and the two second connecting segments 34 both penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each second connecting segment 34 are respectively connected to a corresponding third ohmic metal 18 and a first resistor electrode 43. In this embodiment, the resistance value of the first resistor 40 is 1×10 3 ~5×10 7 Ω.

[0076] Further, if Figure 2 and Figure 12 As shown, in the GaN integrated chip 100 of this embodiment, one end of the first source electrode 1 is connected to a diode electrode 39 corresponding to the positive electrode of the diode structure 104 so that the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104, one end of the second source electrode 4 is connected to a diode electrode 39 corresponding to the negative electrode of the diode structure 104 so that the second source electrode 4 is electrically connected to the negative electrode of the diode structure 104, and a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 is connected to a diode electrode 39 corresponding to the negative electrode of the diode structure 104 so that the diode structure 104 The negative electrode is also electrically connected to one end of the capacitor structure 103, one of the third resistor electrodes 45 is connected to the second drain electrode 5 so that the third resistor structure 107 is connected in series with the second drain electrode 5, and the two ends of a capacitor electrode 38 corresponding to the lower electrode 36 of the capacitor structure 103 are respectively connected to the second gate electrode 6 and a first resistor electrode 43 close to it, and the other first resistor electrode 43 is connected to a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103, so that the capacitor structure 103 is also electrically connected to the second gate electrode 6 and the capacitor structure 103 is electrically connected to the first resistor structure 105.

[0077] Furthermore, the low-voltage enhancement MOS chip 200 has a third source electrode 7, a third drain electrode 8, and a third gate electrode 9. The startup network formed in this embodiment is suitable for a general startup circuit. When the GaN integrated chip 100 of this embodiment is actually packaged with the low-voltage enhancement MOS chip 200, the first source electrode 1 is connected to the third drain electrode 8 via a bonding wire 46; the first gate electrode 3 is connected to the third source electrode 7 via a bonding wire 46, so that one end of the first gate electrode 3 is used as an output end to be connected to the third source electrode 7 and then used together as a source end; at the same time, the third source electrode 7 is connected to a corresponding pin 47 via a bonding wire 46; one end of the first drain electrode 2 is connected to a corresponding pin 47 via a bonding wire 46, so that one end of the first drain electrode 2 is used as an output end to be connected to the main loop of the external circuit (the first drain electrode 2 is used as a drain end); the third gate electrode 9 is connected to the corresponding pin 47 via a bonding wire 46. One end is connected to a corresponding pin 47 via a bonding wire 46, so that the third gate electrode 9 is used as a gate terminal; one end of a third resistor electrode 45 away from the second drain electrode 5 is connected to a corresponding pin 47 via a bonding wire 46. Since the second drain electrode 5 in this embodiment is connected in series with a third resistor structure 107, one end of another third resistor electrode 45 in the third resistor structure 107 that is not connected to the second drain electrode 5 is used as an output terminal to connect to a high level; one end of the second gate electrode 6 is connected to a corresponding pin 47 via a bonding wire 46, so that one end of the second gate electrode 6 is used for grounding; one end of the second source electrode 4 is connected to a corresponding pin 47 via a bonding wire 46, so that one end of the second source electrode 4 is used as an output terminal to power the IC when the computer is started.

[0078] During startup, startup device 102 is in the on state, and current flows through the device to charge capacitor structure 103. The capacitor voltage continues to rise, that is, the potential at one end of second source electrode 4 increases, until the IC begins operation. At this time, current flows from third resistor structure 107 through the channel of startup device 102 to second source electrode 4. After the startup process is completed, the driver chip begins normal operation, and the depletion-mode power switch 101 begins switching. At this time, due to the instantaneous potential of the first source electrode 1 at the moment of its switching off, the potential of the second source electrode 4 of startup device 102 is higher than that of the first source electrode 4 of startup device 102. Therefore, at this time, the current is converted to flow from the first drain electrode 2 of the depletion-mode power switch 101, through its channel, and then from its first source electrode 1 through the diode structure 104, and finally to the second source electrode 4, which is used to power the control chip. At the same time, the negative electrode potential of the diode structure 104 will also raise the potential of the second source electrode 4 of the startup device 102, so that the voltage between the second gate electrode 6 and the second source electrode 4 of the startup device 102 is greater than its turn-off voltage, thereby making the startup device 102 in the turn-off state, and its circuit has almost no power loss.

[0079] This embodiment also provides a method for preparing the above-mentioned GaN integrated chip 100, which specifically includes the following steps:

[0080] Step 1: Nitride epitaxial growth is performed on substrate 108 to sequentially form a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095. Materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 1091, buffer layer 1092, channel layer 1093, barrier layer 1094, and cap layer 1095 form a stacked structure, thus forming a complete semiconductor epitaxial layer structure. This structure can generate a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 1093 and the barrier layer 1094, generating a conductive channel. Substrate 108 can be made of one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing Group III nitride materials.

[0081] Step 2: Through photoresist protection, patterning is performed on the top of the cap layer 1095 and ion material is injected to destroy the two-dimensional electron gas to form an isolation area. The protected non-injected area is the continuous area chip active area where the first source electrode 1, the first drain electrode 2 and the first gate electrode 3 exist, the continuous area chip active area where the second source electrode 4, the second drain electrode 5 and the second gate electrode 6 exist, and the area where the capacitor structure 103, the diode structure 104, the third resistor structure 107 and the first resistor structure 105 are formed, and the third resistor 42 and the first resistor 40 are formed.

[0082] Step 3: Graphic etching is performed on the cap layer 1095 to form a first source electrode ohmic hole and a first drain electrode ohmic hole, and at the same time, etching is performed to form a second source electrode ohmic hole and a second drain electrode ohmic hole, and at the same time, etching is performed to form a first positive electrode hole and a negative electrode hole. At the same time, graphic etching is performed on both sides of the third resistor 42 to form two first ohmic contact holes, and at the same time, graphic etching is performed on both sides of the first resistor 40 to form two second ohmic contact holes.

[0083] Step 4: Filling the first source electrode ohmic hole, the first drain electrode ohmic hole, the second source electrode ohmic hole, the second drain electrode ohmic hole, the cathode hole, the two first ohmic contact holes, and the two second ohmic contact holes with metal to form the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the second ohmic metal 17 on both sides of the third resistor 42, and the third ohmic metal 18 on both sides of the first resistor 40, respectively. Annealing is then performed to ensure that the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the two second ohmic metals 17, and the two third ohmic metals 18 form ohmic contacts with the underlying epitaxial material. The metal may include one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0084] Step 5: Deposit one or more combinations of SiN, SiO2, SiON, Al2O3 over the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the second ohmic metal 17, and the third ohmic metal 18 to form a first dielectric layer 110, and etch out a first gate groove and a second gate groove respectively, and at the same time etch out a second anode hole at the position of the first anode hole covered by the first dielectric layer 110.

[0085] Step 6: Fill metal above the first dielectric layer 110 to completely cover the first gate groove, the second gate groove and the second anode hole, and etch to form the first gate electrode metal 12 (the portion located in the first gate groove) and the first field plate 20, and at the same time, etch to form the second gate electrode metal 15 (the portion located in the second gate groove) and the third field plate 22, and at the same time, etch to form the Schottky metal 19, and at the same time, etch to form the lower electrode 36.

[0086] Step 7: Deposit one or more combinations of SiN, SiO 2 , SiON, and Al 2 O 3 on the first gate electrode metal 12 , the second gate electrode metal 15 , and the bottom electrode 36 to form a second dielectric layer 111 .

[0087] Step 8: Fill metal above the second dielectric layer 111 and etch to form a second field plate 21, a fourth field plate 23 and an upper electrode 37, and then deposit one or more combinations of SiN, SiO2, SiON, Al2O3 above the second field plate 21, the fourth field plate 23 and the upper electrode 37 to form a third dielectric layer 112.

[0088] Step 9: Etching downward from the third dielectric layer 112 to form a first source electrode through hole, a first drain electrode through hole, a first gate electrode through hole, a second source electrode through hole, a second drain electrode through hole, a second gate electrode through hole, two first through holes, two second through holes, two third through holes and two fourth through holes, wherein the first source electrode through hole, the first drain electrode through hole, the first gate electrode through hole, the second source electrode through hole, the second drain electrode through hole, the second gate electrode through hole, the two second through holes, the two third through holes and the two fourth through holes all pass through the first dielectric layer 110, the second dielectric layer 111 and the third dielectric layer 112, one first through hole passes through the third dielectric layer 112 and the second dielectric layer 111, and the other first through hole passes through the third dielectric layer 112.

[0089] Step 10: Fill metal into the first source electrode through hole, the first drain electrode through hole, the first gate electrode through hole, the second source electrode through hole, the second drain electrode through hole, the second gate electrode through hole, the two first through holes, the two second through holes, the two third through holes and the two fourth through holes to form a first metal connecting bar 24, a second metal connecting bar 25, a third metal connecting bar 26, a fourth metal connecting bar 27, a fifth metal connecting bar 28, a sixth metal connecting bar 29, a seventh metal connecting bar 30, an eighth metal connecting bar 31, two ninth metal connecting bars 32, two first connecting segments 33 and two second connecting segments 34 respectively.

[0090] Step 11: Fill metal above the third dielectric layer 112 and etch to form a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a second source electrode 4, a second drain electrode 5, a second gate electrode 6, two capacitor electrodes 38, two diode electrodes 39, two third resistor electrodes 45 and two first resistor electrodes 43. Among them, the two ends of the first metal connecting strip 24 are electrically connected to the first source electrode 1 and the first source electrode ohmic metal 10 respectively, the two ends of the second metal connecting strip 25 are electrically connected to the first drain electrode 2 and the first drain electrode ohmic metal 11 respectively, and the two ends of the third metal connecting strip 26 are electrically connected to the first gate electrode 3 and the first gate electrode metal 12 respectively, forming a depletion-mode power switch tube 101; the two ends of the fourth metal connecting strip 27 are electrically connected to the second source electrode 4 and the second source electrode ohmic metal 13 respectively, the two ends of the fifth metal connecting strip 28 are electrically connected to the second drain electrode 5 and the second drain electrode ohmic metal 14 respectively, and the two ends of the sixth metal connecting strip 29 are electrically connected to the second gate electrode 6 and the second gate electrode metal 15 respectively, forming a startup device 102; the two ends of the seventh metal connecting strip 30 are electrically connected to the second source electrode 4 and the second source electrode ohmic metal 13 respectively, and the two ends of the fifth metal connecting strip 28 are electrically connected to the second drain electrode 5 and the second drain electrode ohmic metal 14 respectively. The two ends are electrically connected to a capacitor electrode 38 and a lower electrode 36 respectively, and the two ends of the eighth metal connecting strip 31 are electrically connected to another capacitor electrode 38 and an upper electrode 37 respectively, forming a capacitor structure 103; the two ends of a ninth metal connecting strip 32 are electrically connected to a diode electrode 39 and a first ohmic metal 16 respectively, and the two ends of another ninth metal connecting strip 32 are electrically connected to a diode electrode 39 and a Schottky metal 19 respectively, forming a diode structure 104; the two ends of each first connecting segment 33 are respectively connected to the corresponding third resistor electrode 45 and the second ohmic metal 17, forming a third resistor structure 107; the two ends of each second connecting segment 34 are respectively connected to the corresponding first resistor electrode 43 and the third ohmic metal 18, forming a first resistor structure 105.

[0091] Step 12: Connect one end of the first source electrode 1 to a diode electrode 39 corresponding to the positive electrode of the diode structure 104, connect one end of the second source electrode 4 to a diode electrode 39 corresponding to the negative electrode of the diode structure 104, connect a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 to a diode electrode 39 corresponding to the negative electrode of the diode structure 104, connect one of the third resistor electrodes 45 to the second drain electrode 5, connect the two ends of a capacitor electrode 38 corresponding to the lower electrode 36 of the capacitor structure 103 to the second gate electrode 6 and a first resistor electrode 43 close to it respectively, and connect the other first resistor electrode 43 to a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103, to obtain the GaN integrated chip 100 of this embodiment. Example 3

[0092] like Figure 3As shown, the cascade device in this embodiment is formed by cascading a low-voltage enhancement MOS chip 200 and a GaN integrated chip 100, wherein the GaN integrated chip 100 includes a depletion-mode power switch tube 101, a startup circuit, and a substrate 108, a stacked structure, a first dielectric layer 110, a second dielectric layer 111, and a third dielectric layer 112 arranged in sequence from bottom to top. The stacked structure includes a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095 arranged in sequence from bottom to top. The cascade device has a source terminal, a drain terminal, and a gate terminal.

[0093] Furthermore, the structure of the depletion-mode power switch tube 101 of this embodiment is the same as that of Example 1, including a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a first source electrode ohmic metal 10, a first drain electrode ohmic metal 11, a first gate electrode metal 12, a first field plate 20, a second field plate 21, a first metal connecting bar 24, a second metal connecting bar 25 and a third metal connecting bar 26. Among them, the first source electrode ohmic metal 10 and the first drain electrode ohmic metal 11 are both located in the barrier layer 1094 and the cap layer 1095; the first gate electrode metal 12 is located in the first dielectric layer 110, the first field plate 20 is located in the second dielectric layer 111, and the second field plate 21 is located in the third dielectric layer 112; the first source electrode 1, the first drain electrode 2 and the first gate electrode 3 are all located above the third dielectric layer 112; the first metal connecting bar 24, the second metal connecting bar 25 and the third metal connecting bar 26 all pass through the first dielectric layer 110, the second dielectric layer 111 and the third dielectric layer 112, the two ends of the first metal connecting bar 24 are respectively connected to the first source electrode ohmic metal 10 and the first source electrode 1, the two ends of the second metal connecting bar 25 are respectively connected to the first drain electrode ohmic metal 11 and the first drain electrode 2, and the two ends of the third metal connecting bar 26 are respectively connected to the first gate electrode metal 12 and the first gate electrode 3. In this embodiment, the depletion-mode power switch tube 101 is provided with a plurality of first source electrode ohmic metals 10 and corresponding first metal connecting strips 24, a plurality of first drain electrode ohmic metals 11 and corresponding second metal connecting strips 25. The plurality of first source electrode ohmic metals 10 are electrically connected to the first source electrode 1 at the same time through the plurality of first metal connecting strips 24, and the plurality of first drain electrode ohmic metals 11 are electrically connected to the first drain electrode 2 at the same time through the plurality of second metal connecting strips 25.

[0094] Furthermore, if Figure 3As shown, the startup circuit of this embodiment includes a startup device 102, a capacitor structure 103, a diode structure 104, a third resistor structure 107, a first resistor structure 105, and a second resistor structure 106. The startup device 102 includes a second source electrode 4, a second drain electrode 5, a second gate electrode 6, a second source electrode ohmic metal 13, a second drain electrode ohmic metal 14, a second gate electrode metal 15, a third field plate 22, a fourth field plate 23, a fourth metal connecting bar 27, a fifth metal connecting bar 28, and a sixth metal connecting bar 29. Among them, the second source electrode ohmic metal 13 and the second drain electrode ohmic metal 14 are both located in the barrier layer 1094 and the cap layer 1095; the second gate electrode metal 15 is located in the first dielectric layer 110, the third field plate 22 is located in the second dielectric layer 111, and the fourth field plate 23 is located in the third dielectric layer 112; the second source electrode 4, the second drain electrode 5 and the second gate electrode 6 are all located above the third dielectric layer 112; the fourth metal connecting bar 27, the fifth metal connecting bar 28 and the sixth metal connecting bar 29 all pass through the first dielectric layer 110, the second dielectric layer 111 and the third dielectric layer 112, the two ends of the fourth metal connecting bar 27 are respectively connected to the second source electrode ohmic metal 13 and the second source electrode 4, the two ends of the fifth metal connecting bar 28 are respectively connected to the second drain electrode ohmic metal 14 and the second drain electrode 5, and the two ends of the sixth metal connecting bar 29 are respectively connected to the second gate electrode metal 15 and the second gate electrode 6. In this embodiment, the startup device 102 has one second source ohmic metal electrode 13 and one corresponding fourth metal connecting bar 27 , and one second drain ohmic metal electrode 14 and one corresponding fifth metal connecting bar 28 .

[0095] The capacitor structure 103 of this embodiment includes a lower electrode 36, an upper electrode 37, two capacitor electrodes 38, a seventh metal connecting strip 30 located on one side of the lower electrode 36, and an eighth metal connecting strip 31 located on one side of the upper electrode 37. Specifically, the lower electrode 36 is located in the second dielectric layer 111, the upper electrode 37 is located in the third dielectric layer 112, and both capacitor electrodes 38 are located above the third dielectric layer 112. The seventh metal connecting strip 30 penetrates the second dielectric layer 111 and the third dielectric layer 112, and its two ends are respectively connected to the lower electrode 36 and one capacitor electrode 38. The eighth metal connecting strip 31 penetrates the third dielectric layer 112, and its two ends are respectively connected to the upper electrode 37 and the other capacitor electrode 38.

[0096] The diode structure 104 includes a first ohmic metal 16, a Schottky metal 19, two diode electrodes 39, and two ninth metal connecting strips 32. The first ohmic metal 16 and the Schottky metal 19 are both located in the barrier layer 1094 and the cap layer 1095. The two diode electrodes 39 are both located above the third dielectric layer 112. The two ninth metal connecting strips 32 penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of one ninth metal connecting strip 32 are respectively connected to the first ohmic metal 16 and one diode electrode 39 to form the cathode of the diode structure 104. The two ends of the other ninth metal connecting strip 32 are respectively connected to the Schottky metal 19 and the other diode electrode 39 to form the anode of the diode structure 104.

[0097] The third resistor structure 107 is disposed on one side of the second drain electrode 5 of the startup device 102. The third resistor structure 107 includes a third resistor 42, a second ohmic metal 17 located on both sides of the third resistor 42, two third resistor electrodes 45, and two first connecting segments 33. The third resistor structure 107 is connected in series with the second drain electrode 5. The third resistor 42 is located in the channel layer 1093, the two second ohmic metals 17 are located in the barrier layer 1094 and the cap layer 1095, the two third resistor electrodes 45 are located above the third dielectric layer 112, and the two first connecting segments 33 penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each first connecting segment 33 are respectively connected to a corresponding second ohmic metal 17 and a third resistor electrode 45. In this embodiment, the resistance value of the third resistor 42 is 1×10 3 ~5×10 7 Ω.

[0098] The first resistor structure 105 of this embodiment is arranged on one side of the capacitor structure 103 and has the same structure as the third resistor structure 107. Specifically, the first resistor structure 105 includes a first resistor 40, a third ohmic metal 18 located on both sides of the first resistor 40, two first resistor electrodes 43, and two second connecting segments 34. Among them, the first resistor 40 is located in the channel layer 1093, the two third ohmic metals 18 are both located in the barrier layer 1094 and the cap layer 1095, the two first resistor electrodes 43 are both located above the third dielectric layer 112, and the two second connecting segments 34 both penetrate the first dielectric layer 110, the second dielectric layer 111, and the third dielectric layer 112. The two ends of each second connecting segment 34 are respectively connected to a corresponding third ohmic metal 18 and a first resistor electrode 43. In this embodiment, the resistance value of the first resistor 40 is 1×10 3 ~5×10 7 Ω.

[0099] like Figure 3 and Figure 10As shown, the second resistor structure 106 of this embodiment is arranged on a side of the first resistor structure 105 away from the capacitor structure 103. Specifically, the second resistor structure 106 includes a second resistor 41, a third connecting segment 35 located on both sides of the second resistor 41, and two second resistor electrodes 44. Among them, the second resistor 41 is located in the third dielectric layer 112, the two second resistor electrodes 44 are both located above the third dielectric layer 112, the two third connecting segments 35 both penetrate the third dielectric layer 112, and the two ends of each third connecting segment 35 are respectively connected to a corresponding second resistor 41 and a second resistor electrode 44. In this embodiment, the second resistor 41 is a current-sense resistor. The current-sense resistor can further simplify and reduce the peripheral circuits in the PCB board, reducing the cost while reducing the loop parasitic parameters, which is conducive to improving electromagnetic interference.

[0100] Further, if Figure 3 and Figure 13 As shown, in the GaN integrated chip 100 of this embodiment, one end of the first source electrode 1 is connected to a diode electrode 39 corresponding to the positive electrode of the diode structure 104 so that the first source electrode 1 is electrically connected to the positive electrode of the diode structure 104, one end of the second source electrode 4 is connected to a diode electrode 39 corresponding to the negative electrode of the diode structure 104 so that the second source electrode 4 is electrically connected to the negative electrode of the diode structure 104, a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 is connected to a diode electrode 39 corresponding to the negative electrode of the diode structure 104 so that the negative electrode of the diode structure 104 is also electrically connected to one end of the capacitor structure 103, one of the third resistor electrodes 45 is connected to the second drain electrode 5 so that the third resistor structure 107 is connected in series with the second drain electrode 5, and the lower electrode 37 of the capacitor structure 103 is connected to the third resistor electrode 45. Two ends of a capacitor electrode 38 corresponding to 36 are respectively connected to the second gate electrode 6 and a first resistor electrode 43 adjacent thereto, and another first resistor electrode 43 is connected to a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103, so that the capacitor structure 103 is also electrically connected to the second gate electrode 6 and the capacitor structure 103 is electrically connected to the first resistor structure 105. Then, a second resistor electrode 44 of the second resistor structure 106 away from the depletion-mode power switch tube 101 is connected to a first resistor electrode 43 adjacent thereto (the first resistor electrode 43 connected to the capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103), so that one end of the second resistor structure 106 is electrically connected to one end of the first resistor structure 105, and the other second resistor electrode 44 of the second resistor structure 106 serves as an output end.

[0101] Furthermore, the low-voltage enhancement mode MOS chip 200 has a third source electrode 7 , a third drain electrode 8 and a third gate electrode 9 . When the GaN integrated chip 100 of this embodiment is actually packaged with the low-voltage enhancement-mode MOS chip 200, the first source electrode 1 is connected to the third drain electrode 8 via a bonding wire 46. The first gate electrode 3 is connected to the third source electrode 7 via a bonding wire 46, so that the first gate electrode 3 and the third source electrode 7, after being connected, serve together as a source terminal. One end of the first drain electrode 2 is connected to a corresponding pin 47 via a bonding wire 46, so that one end of the first drain electrode 2 serves as an output terminal for connection to the main loop of an external circuit (the first drain electrode 2 serves as a drain terminal). Simultaneously, the third source electrode 7 is connected to a second resistor electrode 44 in the second resistor structure 106, which is close to the depletion-mode power switch 101, via a bonding wire 46, so that one end of the second resistor structure 106 serves as an output terminal for connection to the third source electrode 7. In addition, one end of the other second resistor electrode 44 in the second resistor structure 106 of this embodiment serves as a ground terminal on the startup circuit side, and also serves as a ground terminal on the depletion-mode power switch 101 side after passing through the second resistor structure 106. One end of the third gate electrode 9 is connected to a corresponding pin 47 via a bonding wire 46, so that the third gate electrode 9 is used as a gate terminal; one end of a third resistor electrode 45 away from the second drain electrode 5 is connected to a corresponding pin 47 via a bonding wire 46. Since the second drain electrode 5 in this embodiment is connected in series with a third resistor structure 107, one end of another third resistor electrode 45 in the third resistor structure 107 that is not connected to the second drain electrode 5 is used as an output terminal to connect to a high level; one end of the second gate electrode 6 is connected to a corresponding pin 47 via a bonding wire 46, so that one end of the second gate electrode 6 is used for grounding; one end of the second source electrode 4 is connected to a corresponding pin 47 via a bonding wire 46, so that one end of the second source electrode 4 is used as an output terminal to power the IC when the computer is started.

[0102] The operating principle of the GaN integrated chip 100 in this embodiment during and after startup is the same as that in Example 2. Compared with Example 2, this embodiment introduces a second resistor structure 106 (current-sense resistor), which is conducive to further simplifying and reducing peripheral circuits in the PCB. While reducing costs, it can also reduce loop parasitic parameters, which is conducive to improving electromagnetic interference.

[0103] This embodiment provides a method for preparing the above-mentioned GaN integrated chip 100, which specifically includes the following steps:

[0104] Step 1: Nitride epitaxial growth is performed on substrate 108 to sequentially form a nucleation layer 1091, a buffer layer 1092, a channel layer 1093, a barrier layer 1094, and a cap layer 1095. Materials include Group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 1091, buffer layer 1092, channel layer 1093, barrier layer 1094, and cap layer 1095 form a stacked structure, thus forming a complete semiconductor epitaxial layer structure. This structure can generate a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 1093 and the barrier layer 1094, generating a conductive channel. Substrate 108 can be made of one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing Group III nitride materials.

[0105] Step 2: Through photoresist protection, patterning is performed on the top of the cap layer 1095 and ion material is injected to destroy the two-dimensional electron gas to form an isolation area. The protected non-injected area is the continuous area chip active area where the first source electrode 1, the first drain electrode 2 and the first gate electrode 3 exist, the continuous area chip active area where the second source electrode 4, the second drain electrode 5 and the second gate electrode 6 exist, and the area where the capacitor structure 103, the diode structure 104, the third resistor structure 107, the first resistor structure 105 and the second resistor structure 106 are formed, and the third resistor 42 and the first resistor 40 are formed.

[0106] Step 3: Graphic etching is performed on the cap layer 1095 to form a first source electrode ohmic hole and a first drain electrode ohmic hole, and at the same time, etching is performed to form a second source electrode ohmic hole and a second drain electrode ohmic hole, and at the same time, etching is performed to form a first positive electrode hole and a negative electrode hole. At the same time, graphic etching is performed on both sides of the third resistor 42 to form two first ohmic contact holes, and at the same time, graphic etching is performed on both sides of the first resistor 40 to form two second ohmic contact holes.

[0107] Step 4: Filling the first source electrode ohmic hole, the first drain electrode ohmic hole, the second source electrode ohmic hole, the second drain electrode ohmic hole, the cathode hole, the two first ohmic contact holes, and the two second ohmic contact holes with metal to form the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the second ohmic metal 17 on both sides of the third resistor 42, and the third ohmic metal 18 on both sides of the first resistor 40, respectively. Annealing is then performed to ensure that the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the two second ohmic metals 17, and the two third ohmic metals 18 form ohmic contacts with the underlying epitaxial material. The metal may include one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0108] Step 5: Deposit one or more combinations of SiN, SiO2, SiON, Al2O3 over the first source electrode ohmic metal 10, the first drain electrode ohmic metal 11, the second source electrode ohmic metal 13, the second drain electrode ohmic metal 14, the first ohmic metal 16, the second ohmic metal 17, and the third ohmic metal 18 to form a first dielectric layer 110, and etch out a first gate groove and a second gate groove respectively, and at the same time etch out a second anode hole at the position of the first anode hole covered by the first dielectric layer 110.

[0109] Step 6: Fill metal above the first dielectric layer 110 to completely cover the first gate groove, the second gate groove and the second anode hole, and etch to form the first gate electrode metal 12 (the portion located in the first gate groove) and the first field plate 20, and at the same time, etch to form the second gate electrode metal 15 (the portion located in the second gate groove) and the third field plate 22, and at the same time, etch to form the Schottky metal 19, and at the same time, etch to form the lower electrode 36.

[0110] Step 7: Deposit one or more combinations of SiN, SiO 2 , SiON, and Al 2 O 3 on the first gate electrode metal 12 , the second gate electrode metal 15 , and the bottom electrode 36 to form a second dielectric layer 111 .

[0111] Step 8: Metal is filled and etched over the second dielectric layer 111 to form the second field plate 21, the fourth field plate 23, the top electrode 37, and the second resistor 41. Furthermore, one or more combinations of SiN, SiO2, SiON, and Al2O3 are deposited over the second field plate 21, the fourth field plate 23, the top electrode 37, and the second resistor 41 to form the third dielectric layer 112. The second resistor 41 is generally made of an alloy or single-layer metal with a low temperature coefficient, high stability, and low resistivity, including one or more combinations of Cu-Mn-Ni, Cu-Ni, Ni-Cr, Ni-Cr-Al-Cu, Cu, and Al.

[0112] Step 9: Etching downward from the third dielectric layer 112 to form a first source electrode through hole, a first drain electrode through hole, a first gate electrode through hole, a second source electrode through hole, a second drain electrode through hole, a second gate electrode through hole, two first through holes, two second through holes, two third through holes, two fourth through holes and two fifth through holes, wherein the first source electrode through hole, the first drain electrode through hole, the first gate electrode through hole, the second source electrode through hole, the second drain electrode through hole, the second gate electrode through hole, the two second through holes, the two third through holes and the two fourth through holes all pass through the first dielectric layer 110, the second dielectric layer 111 and the third dielectric layer 112, one first through hole passes through the third dielectric layer 112 and the second dielectric layer 111, another first through hole passes through the third dielectric layer 112, and the two fifth through holes all pass through the third dielectric layer 112.

[0113] Step 10: Fill metal into the first source electrode through hole, the first drain electrode through hole, the first gate electrode through hole, the second source electrode through hole, the second drain electrode through hole, the second gate electrode through hole, the two first through holes, the two second through holes, the two third through holes, the two fourth through holes and the two fifth through holes to form a first metal connecting bar 24, a second metal connecting bar 25, a third metal connecting bar 26, a fourth metal connecting bar 27, a fifth metal connecting bar 28, a sixth metal connecting bar 29, a seventh metal connecting bar 30, an eighth metal connecting bar 31, two ninth metal connecting bars 32, two first connecting segments 33, two second connecting segments 34 and two third connecting segments 35 respectively.

[0114] Step 11: Fill metal above the third dielectric layer 112 and etch to form a first source electrode 1, a first drain electrode 2, a first gate electrode 3, a second source electrode 4, a second drain electrode 5, a second gate electrode 6, two capacitor electrodes 38, two diode electrodes 39, two third resistor electrodes 45, two first resistor electrodes 43 and two second resistor electrodes 44. Among them, the two ends of the first metal connecting strip 24 are electrically connected to the first source electrode 1 and the first source electrode ohmic metal 10, respectively; the two ends of the second metal connecting strip 25 are electrically connected to the first drain electrode 2 and the first drain electrode ohmic metal 11, respectively; the two ends of the third metal connecting strip 26 are electrically connected to the first gate electrode 3 and the first gate electrode metal 12, respectively, forming a depletion-mode power switch tube 101; the two ends of the fourth metal connecting strip 27 are electrically connected to the second source electrode 4 and the second source electrode ohmic metal 13, respectively; the two ends of the fifth metal connecting strip 28 are electrically connected to the second drain electrode 5 and the second drain electrode ohmic metal 14, respectively; the two ends of the sixth metal connecting strip 29 are electrically connected to the second gate electrode 6 and the second gate electrode metal 15, respectively, forming a startup device 102; the two ends of the seventh metal connecting strip 30 are electrically connected to a capacitor electrode 38 and the lower electrode 36, respectively; The two ends of the metal connecting strip 31 are electrically connected to another capacitor electrode 38 and the upper electrode 37, respectively, to form a capacitor structure 103; the two ends of a ninth metal connecting strip 32 are electrically connected to a diode electrode 39 and the first ohmic metal 16, respectively, and the two ends of another ninth metal connecting strip 32 are electrically connected to a diode electrode 39 and the Schottky metal 19, respectively, to form a diode structure 104; the two ends of each first connecting segment 33 are respectively connected to the corresponding third resistor electrode 45 and the second ohmic metal 17, respectively, to form a third resistor structure 107; the two ends of each second connecting segment 34 are respectively connected to the corresponding first resistor electrode 43 and the third ohmic metal 18, respectively, to form a first resistor structure 105; the two ends of each third connecting segment 35 are respectively connected to the corresponding second resistor electrode 44 and one end of the second resistor 41, respectively, to form a second resistor structure 106.

[0115] Step 12: Connect one end of the first source electrode 1 to a diode electrode 39 corresponding to the positive electrode of the diode structure 104, connect one end of the second source electrode 4 to a diode electrode 39 corresponding to the negative electrode of the diode structure 104, connect a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103 to a diode electrode 39 corresponding to the negative electrode of the diode structure 104, connect one of the third resistor electrodes 45 to the second drain electrode 5, connect the two ends of a capacitor electrode 38 corresponding to the lower electrode 36 of the capacitor structure 103 to the second gate electrode 6 and a first resistor electrode 43 close to it, respectively, connect the other first resistor electrode 43 to a capacitor electrode 38 corresponding to the upper electrode 37 of the capacitor structure 103, connect a second resistor electrode 44 of the second resistor structure 106 away from the depletion-mode power switch tube 101 to a first resistor electrode 43 close to it, and use the other second resistor electrode 44 of the second resistor structure 106 as the output end to obtain the GaN integrated chip 100 of this embodiment.

[0116] The above embodiments of the present invention are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications made in accordance with the spirit of the present invention are intended to be included in the scope of protection of the present invention.

Claims

1. A GaN integrated chip, characterized in that: The invention comprises a depletion-type power switch tube and a startup circuit, wherein the depletion-type power switch tube has a first source electrode, a first drain electrode, and a first gate electrode. The startup circuit comprises at least a startup device, a capacitor structure, and a diode structure. The startup device has a second source electrode, one end of the first source electrode is electrically connected to the positive electrode of the diode structure, the cathode of the diode structure is electrically connected to one end of the second source electrode, and the cathode of the diode structure is also electrically connected to one end of the capacitor structure. During startup, the startup device is in an on state, and after startup, the startup device is in an off state. The startup circuit is used to supply power to the integrated circuit (IC) during startup, and the first source electrode of the depletion-type power switch tube is used to continuously supply power to the integrated circuit (IC) after startup.

2. The GaN integrated chip according to claim 1, characterized in that: The startup device further has a second drain electrode and a second gate electrode, and the first source electrode, the first drain electrode, the first gate electrode, the second source electrode, the second drain electrode and the second gate electrode are all used as connection interfaces.

3. The GaN integrated chip according to claim 2, characterized in that: The startup circuit includes a startup device, a capacitor structure and a diode structure. The second gate electrode is used to connect to a control output terminal having a source-controlled startup function. One end of the capacitor structure is used to be grounded.

4. The GaN integrated chip according to claim 2, characterized in that: The startup circuit includes a startup device, a capacitor structure, a diode structure and a first resistor structure.

5. The GaN integrated chip according to claim 4, characterized in that: Two ends of the first resistance structure are electrically connected to two ends of the capacitor structure respectively, and the capacitor structure is also electrically connected to the second gate electrode.

6. The GaN integrated chip according to claim 5, characterized in that: The second gate electrode is used for grounding.

7. The GaN integrated chip according to claim 6, characterized in that: The startup circuit further includes a second resistance structure.

8. The GaN integrated chip according to claim 7, characterized in that: The first resistance structure is also electrically connected to one end of the second resistance structure, and the other end of the second resistance structure is used as a connection interface.

9. The GaN integrated chip according to claim 8, characterized in that: The second resistor structure is used to serve as a connection interface with one end electrically connected to the source electrode of the cascaded low-voltage enhancement mode MOS chip.

10. The GaN integrated chip according to claim 9, characterized in that: The second resistor structure is used as a current-sense resistor.

11. The GaN integrated chip according to claim 2, characterized in that: The startup circuit further includes a third resistance structure connected in series with the second drain electrode.

12. A device, characterized in that The device comprises a low-voltage enhancement mode MOS chip and a GaN integrated chip according to any one of claims 1 to 11, wherein the device is formed by cascading the low-voltage enhancement mode MOS chip and the GaN integrated chip.

13. A device according to claim 12, characterized in that: The low-voltage enhancement MOS chip comprises a source terminal, a drain terminal and a gate terminal. The low-voltage enhancement MOS chip has a third source electrode, a third drain electrode and a third gate electrode. The first gate electrode and the third source electrode are connected and used together as the source terminal. The third gate electrode is used as the gate terminal. The first drain electrode is used as the drain terminal.

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