Computer system and method for arithmetic decoding

Abstract

Embodiments of the present disclosure relate to a computer system and method for arithmetic decoding. A computer system for performing arithmetic decoding includes one or more memories configured to store an array of coefficients and a value interval. The computer system includes circuitry configured to perform a comparison of coefficients of the coefficient array to a value interval, and count the same and consecutive results of the comparison. The computer system also includes a digital signal processor configured to determine a value of a symbol associated with the array of coefficients based on the count of the same and consecutive results.

Description

Technical Field

[0001] The embodiments and implementations relate to arithmetic decoding. Background Art

[0002] Arithmetic coding is a data compression technique commonly used in computing and signal processing. Unlike traditional binary coding where each symbol is represented by a fixed number of bits, arithmetic coding allows the use of fractions of intervals of real numbers to represent symbols.

[0003] Arithmetic coding has the advantage of being able to compress data efficiently based on the probabilities of symbols. The most frequent symbols will occupy a smaller fraction of the interval, while the lowest frequency symbols will occupy a larger fraction, enabling more efficient data compression.

[0004] Specifically, arithmetic coding is used by the "LC3" (which stands for "Low Complexity Communication Codec") audio encoder-decoder. Arithmetic coding is then used to compress audio data, and then arithmetic decoding is used to recover the original audio data from the compressed representation.

[0005] Specifically, arithmetic coding implements different steps. First, probabilities are assigned to symbols. Specifically, before encoding begins, each symbol in the message is assigned a probability. The probability can be based on the statistics of the frequency of the symbol's occurrence in the message.

[0006] After that, an initial interval is defined at the start of the encoding process. The message is then rolled through symbol by symbol. At each step, the current interval is divided into sub-intervals, the sizes of which are proportional to the probabilities of the symbols. The sub-interval corresponding to the symbol currently being processed is selected to represent that symbol. The current interval then becomes the selected sub-interval.

[0007] Once all symbols have been encoded, the binary representation of the real number in the final interval is extracted. This binary representation is the compressed message.

[0008] Once the message has been compressed by arithmetic coding, the original message can be recovered by arithmetic decoding, reversing the steps implemented during arithmetic coding.

[0009] Specifically, arithmetic decoding includes initializing the initial interval used during encoding based on the probabilities associated with the symbols.

[0010] Once the initial interval has been reconstructed, iterative decoding of the symbols can begin. The decoder starts reading the bits of the binary representation of the compressed message one by one, and at each step, adjusts the interval based on the sequence of bits read. It should consider the probabilities associated with the symbols to determine which sub-interval corresponds to the symbol being decoded.

[0011] Using each iteration, the decoder compares the current interval with sub - intervals corresponding to each possible symbol. When a sub - interval corresponds to the current interval, the decoder identifies the symbol associated with that sub - interval as the decoded symbol.

[0012] More specifically, using each iteration, the comparison is performed between the start value of the interval and a value calculated by multiplying the length of the interval by a coefficient. Each coefficient corresponds to a value associated with a symbol. The sequence of tests is performed until a comparison result corresponding to a test validity condition is obtained. In order to decode a symbol, the number of tests performed is a value between 1 and the number of possible symbols. Summary of the Invention

[0013] Known methods for performing arithmetic decoding require performing branches at each iteration. These numerous branches increase the time required to perform arithmetic decoding. Thus, such arithmetic decoding is not very efficient.

[0014] Therefore, there is a need to propose solutions that allow arithmetic decoding to be performed more quickly.

[0015] In some embodiments, a computer system is proposed that includes: a data memory configured to store an array of coefficients; a digital signal processor configured to execute a computer program including instructions that allow arithmetic decoding to be performed based on the array of coefficients and an interval of values; and a circuit configured to: perform a comparison based on a coefficient of the array of coefficients and the interval of values, and count identical and consecutive results of the comparison, the digital signal processor being configured to determine the value of a symbol associated with the array of coefficients according to the number of identical and consecutive results counted by the dedicated circuit.

[0016] Using a circuit dedicated to arithmetic decoding integrated into the digital signal processor allows accelerating arithmetic decoding by reducing the number of loops of the digital signal processor for performing arithmetic decoding. In this way, the power consumption for performing arithmetic decoding can also be reduced. Furthermore, the fact of first performing all comparisons associated with each coefficient in the table before calculating the value of the symbol avoids having to perform a large number of branches during the comparison with known solutions.

[0017] In some embodiments, the dedicated circuit includes a first block configured to calculate a comparison variable and allow storing the result of the comparison, the result of each comparison corresponding to a bit of the comparison variable.

[0018] In some embodiments, the first block is configured to perform at least two comparisons in parallel based on at least two consecutive coefficients of the coefficient array and an interval of values.

[0019] Thus, in such a computer system, the fact that all comparisons associated with each coefficient in the array of coefficients are initially performed before the value of the symbol is computed enables the comparisons to be done in parallel. This thus allows for an acceleration of arithmetic decoding.

[0020] In some embodiments, the first block includes at least two parallel branches allowing the two comparisons to be performed simultaneously, each branch including: a multiplier circuit configured to perform a multiplication between the coefficient of the two successive coefficients and the length of the interval of the given number of the values that have been shifted by a number of bits, the given number of bits being specifically between 0 and the number of bits used to define the length of the interval (e.g., the given number of bits is equal to 10); and a comparator circuit configured to compare the result of the multiplication with the start value of the interval of values.

[0021] In some embodiments, the first block further includes a circuit for updating a comparison variable, the circuit for updating the comparison variable being configured to incorporate the result of the comparison performed by each comparator circuit into the comparison variable.

[0022] In some embodiments, the dedicated circuit further includes a second block configured to implement a state machine configured to count consecutive identical results stored in the comparison variable by analyzing the bits of the comparison variable.

[0023] In some embodiments, the result of each comparison performed by the first block is progressively stored on the right side of the comparison variable. The state machine implemented by the second block is then configured to count the number of identical comparison results starting from the rightmost bit in the comparison variable.

[0024] In some embodiments, the result of each comparison performed by the first block is progressively stored on the left side of the comparison variable. The state machine implemented by the second block is then configured to count the number of identical comparison results starting from the leftmost bit in the comparison variable.

[0025] In some embodiments, the computer program includes instructions which, when executed by a digital signal processor, cause the digital signal processor to: implement a first block to perform comparisons in parallel according to each coefficient of the coefficient array and the interval, the result of each comparison being stored in a comparison variable, then implement a second block to count consecutive identical results stored in the comparison variable by analyzing the bits of the comparison variable once all comparisons have been performed, and then compute the value of the symbol associated with the coefficient array based on the number of counted consecutive identical results.

[0026] In some embodiments, a method implemented by a computer system is provided. The method includes: executing, by a digital signal processor of the computer system, a computer program that includes instructions that permit performing arithmetic decoding based on an array of coefficients stored in a data memory of the computer system and an interval of values. The arithmetic decoding includes: implementing circuitry of the computer system dedicated to the arithmetic decoding to: perform comparisons based on coefficients of the array of coefficients and the interval of values, then count identical and consecutive results of the comparisons, and then determine, by the digital signal processor, a value of a symbol associated with the array of coefficients based on a number of the identical and consecutive results counted by the dedicated circuitry.

[0027] In some embodiments, implementing the dedicated circuitry includes implementing a first block of the dedicated circuitry that is configured to compute a comparison variable that permits storing results of the comparisons, with a result of each comparison corresponding to a bit of the comparison variable.

[0028] In some embodiments, the first block is adapted to perform at least two comparisons in parallel based on at least two consecutive coefficients of the array of coefficients and the interval of values.

[0029] In some embodiments, implementing the first block includes implementing at least two parallel branches that are adapted to perform the two comparisons simultaneously. Implementing each branch includes: implementing a multiplier circuit that is configured to perform a multiplication between a coefficient of the two consecutive coefficients and a length of the interval of values shifted by a given number of bits, the given number of bits being specifically between 0 and a number of bits used to define the length of the interval; and implementing a comparator circuit that is configured to compare a result of the multiplication with a starting value of the interval of values.

[0030] In some embodiments, implementing the first block further includes implementing circuitry for updating the comparison variable to incorporate results of the comparisons performed by each comparator circuit into the comparison variable.

[0031] In some embodiments, implementing the dedicated circuitry further includes implementing a second block that is configured to execute a state machine that is adapted to count consecutive identical results stored in the comparison variable by analyzing bits of the comparison variable.

[0032] In some embodiments, a result of each comparison performed by the first block is progressively stored on a right side of the comparison variable. The state machine implemented by the second block is then adapted to count a number of identical comparison results starting from a rightmost bit in the comparison variable.

[0033] In some embodiments, the result of each comparison performed by the first block is progressively stored on the left side of a comparison variable. A state machine implemented by the second block is then adapted to count the number of identical comparison results starting from the leftmost bit in the comparison variable.

[0034] In some embodiments, the execution of the computer program causes: implementing a first block to perform comparisons in parallel according to each coefficient of the array of coefficients with the interval, the result of each comparison being stored in a comparison variable, and then implementing a second block to count the consecutive identical results stored in the comparison variable by analyzing the bits of the comparison variable once all comparisons have been performed, and then calculating, by a digital signal processor, the value of a sign associated with the array of coefficients based on the number of counted consecutive identical results. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other advantages and features of the present disclosure will become apparent upon reading the detailed description of embodiments which are in no way limiting and according to the accompanying drawings, in which:

[0036] Figure 1 is a block diagram illustrating a computer system for arithmetic decoding in some embodiments.

[0037] Figure 2 is a logic circuit diagram illustrating logic for performing comparisons of two consecutive values of an array of coefficients with a value range in parallel in some embodiments.

[0038] Figure 3 is a block diagram illustrating logic for counting trailing zero bits of a comparison variable in some embodiments.

[0039] Figure 4 is a block diagram illustrating logic for determining the value of a sign based on an array of coefficients associated with the sign in some embodiments.

[0040] Figure 5 is a block diagram illustrating a computer system for arithmetic decoding in some embodiments.

[0041] Figure 6 is a logic circuit diagram illustrating logic for performing comparisons of two consecutive values of an array of coefficients with a value range in parallel in some embodiments.

[0042] Figure 7 is a block diagram illustrating logic for counting leading zero bits of a comparison variable in some embodiments.

[0043] Figure 8 is a block diagram illustrating logic for determining the value of a sign based on an array of coefficients associated with the sign in some embodiments.

[0044] Figure 9 It is a tabular diagram showing the content of the coefficient array associated with symbols in some embodiments. Detailed implementation

[0045] Figure 1 Illustrates a first embodiment of a computer system SYS1. The computer system SYS1 includes a central processing unit CPU1, a main memory MMEM1, and a digital signal processor DSP1 (also known as "Digital signal processor" in English), as well as a data memory MEM1 and a program memory MEMP1. The DSP1 includes a control unit CU1 (also known as "Control Unit and Register File" in English) having a data register file RF1, and an arithmetic logic unit ALU1 (also known as "Arithmetic and Logic Unit" in English). The arithmetic logic unit ALU1 includes a circuit HWC1, and the circuit HWC1 is dedicated to the acceleration of arithmetic decoding. The computer system SYS1 can be a system-on-chip.

[0046] The digital signal processor DSP1 is configured to execute a computer program PRG1, and the computer program PRG1 includes instructions that allow arithmetic decoding to be performed.

[0047] The computer program PRG1 can be stored in the program memory MEMP1 of the computer system SYS1.

[0048] The digital signal processor DSP1 includes a first register R11, and the first register R11 is configured to store a variable CBITS containing a comparison result.

[0049] The digital signal processor DSP1 further includes a second register R21, and the second register R21 is configured to store a value range length RGE and the starting value LW of the value range. The length RGE and the value LW can be concatenated into a single binary word RGELW in the second register R21.

[0050] The digital signal processor DSP1 further includes a third register R31, and the third register R31 is configured to store two concatenated coefficients.

[0051] The digital signal processor DSP1 further includes a fourth register R41, and the fourth register R41 is configured to store a right zero bit counter TZC_C.

[0052] Specifically, the circuit HWC1 can be obtained according to the "RTL" (which means "Register Transfer Level" in English) code.

[0053] The dedicated circuit HWC1 includes a first block VMULT1, and the first block VMULT1 is configured to perform calculations and tests in a vector manner (i.e., in parallel) during arithmetic decoding. The first block VMULT1 is illustrated in Figure 2 the figure.

[0054] Specifically, the first block VMULT1 is configured to receive the variable CBITS stored in the first register R11 as an input. The first block VMULT1 is also configured to receive the word RGELW stored in the second register R21 as an input, and the word RGELW includes the range length RGE and the range start value LW. The range length RGE and the value LW may be concatenated in the same word received as an input. The first block VMULT1 is also configured to receive two concatenated coefficients CUM_FREQ2 as inputs.

[0055] The first block VMULT1 includes a first shift circuit SFT11. The first shift circuit SFT11 is configured to receive the word RGELW, and the word RGELW includes the range length RGE and the concatenated value LW. The first shift circuit is configured to shift the word 42 bits to the right. This allows the output of 32 bits associated with the range start value LW, and then shift the value of the range length RGE 10 bits to the right to obtain a temporary value TMP.

[0056] The first block VMULT1 further includes a first logic gate AND11 of the "AND" type. The first "AND" type logic gate AND11 is configured to receive the word RGELW including the concatenated range length RGE and the value LW and a first mask MSK11 having a hexadecimal value of "0xFFFFFFFF". The first "AND" type logic gate AND11 allows the first mask MSK11 to be applied to the word RGELW received as an input to recover the range start value LW.

[0057] The first block VMULT1 further includes a second shift circuit SFT21. The second shift circuit SFT21 is configured to receive two concatenated coefficients CUM_FREQ2 and shift the two concatenated coefficients CUM_FREQ2 16 bits to the right to retain only the odd coefficients C_O1.

[0058] The first block VMULT1 further includes a second "AND" type logic gate AND21. The second "AND" type logic gate AND21 is configured to receive two concatenated coefficients CUM_FREQ2 and a second mask MSK21 having a hexadecimal value of "0xFFFF". The second "AND" type logic gate AND21 allows the second mask MSK21 to be applied to the value CIM_FREQ2 to recover the even coefficients C_E1.

[0059] The first VMULT1 also includes two parallel branches BRCH11 and BRCH21. The first branch BRCH11 includes a first multiplier circuit MLT11 and a first comparator circuit CMP11. The second branch BRCH21 includes a second multiplier circuit MLT21 and a second comparator circuit CMP21. The two branches BRCH11 and BRCH21 allow two multiplications to be performed in parallel and then two comparison tests to be performed based on two different coefficients C_O1 and C_E1 derived from two cascaded coefficients CUM_FREQ2.

[0060] Specifically, the first multiplier circuit MLT11 is configured to receive the temporary value TMP generated at the output of the first shift circuit SFT11 and the odd coefficient C_O1 as inputs. The first multiplier circuit MLT11 is then configured to multiply the temporary value TMP by the odd coefficient C_O1.

[0061] The second multiplier circuit MLT21 is configured to receive the temporary value TMP generated at the output of the first shift circuit SFT11 and the even coefficient C_E1 as inputs. The second multiplier circuit MLT21 is then configured to multiply the temporary value TMP by the even coefficient C_E1.

[0062] The first comparator circuit CMP11 is configured to receive the result of the multiplication performed by the first multiplier circuit MLT11 and the interval start value LW. The first comparator circuit CMP11 is then configured to compare the result of the multiplication with the interval start value LW to see if the interval start value LW is greater than or equal to the result of the multiplication. If the value LW is greater than or equal to the result of the multiplication, the first comparator circuit CMP11 generates a comparison bit b1 equal to 1. If the value LW is less than the result of the multiplication, the first comparator circuit CMP11 generates a comparison bit b1 equal to 0.

[0063] The second comparator circuit CMP21 is configured to receive the result of the multiplication performed by the second multiplier circuit MLT21 and the interval start value LW. The second comparator circuit CMP21 is then configured to compare the result of the multiplication with the interval start value LW to see if the interval start value LW is greater than or equal to the result of the multiplication. If the value LW is greater than or equal to the result of the multiplication, the first comparator circuit CMP21 generates a comparison bit b0 equal to 1. If the value LW is less than the result of the multiplication, the first comparator circuit CMP21 generates a comparison bit b0 equal to 0.

[0064] The first block VMULT1 further includes a circuit CUPDT1 for updating the variable CBITS. The circuit CUPDT1 for updating the variable CBITS allows the comparison bits b1 and b0 to be incorporated into the right side of the old variable CBITS received as an input from the first block VMULT1.

[0065] Specifically, the update circuit CUPDT1 includes a third shift circuit SFT31, which is configured to shift the variable CBITS received as an input from the first block VMULT1 one bit to the left.

[0066] The update circuit CUPDT1 further includes a first "OR" type logic gate OR11, which is configured to perform an "OR" type operation between the variable CBITS shifted by one bit and the comparison bit b0. Thus, the first "OR" type logic gate OR11 allows the comparison bit b0 to be incorporated into the variable CBITS. This allows the temporary CIBTS variable CBITS_T to be obtained.

[0067] The update circuit CUPDT1 further includes a fourth shift circuit SFT41, which is configured to shift the temporary variable CBITS_T incorporated with the comparison bit b0 one bit to the left.

[0068] The update circuit CUPDT1 further includes a second "OR" type logic gate OR21, which is configured to perform an "OR" type operation between the comparison bit b1 and the temporary variable CBITS_T incorporated with the comparison bit b0. Thus, the second "OR" type logic gate OR21 allows the comparison bit b1 to be incorporated into the temporary variable CBITS_T. This allows the updated variable CBITS with the comparison bits b0 and b1 incorporated into the right side of the variable CBITS to be obtained. Thereafter, the new variable CBITS can be stored in the register R11 of the digital signal processor DSP1.

[0069] The dedicated circuit HWC1 includes a second block TZC, which is configured to receive the variable CBITS stored in the first register R11. The second block TZC is configured to implement a state machine, and the state machine allows a process of counting the number of zero bits in the right side of the variable CBITS to be performed. Such a method is illustrated in Figure 3 is illustrated.

[0070] The counting method includes an initialization step 30. The initialization step 30 allows the index i to be initialized at 0, the stop variable STP to be initialized at 0, the zero bit counter TZC_C to be initialized at 0, and the variable CB to be initialized with the value of the variable CBITS.

[0071] After that, the counting method includes a first comparison step 31. This first comparison step 31 is adapted to compare whether the value of index i is less than 32.

[0072] If the value of index i is less than 32, the method then includes a second comparison step 32. This second comparison step 32 is adapted to compare whether the value of the least significant bit CB[0] of variable CB (i.e., the rightmost bit in variable CB) is equal to 1.

[0073] If the value of the least significant bit CB[0] of variable CB is different from 1, specifically equal to 0, the method then includes a third comparison step 33. This third comparison step 33 is adapted to compare whether the stop variable STP is equal to 0.

[0074] If the stop variable STP is equal to 0, the method includes step 34: incrementing the zero bit counter TZC_C.

[0075] After that, the method includes step 36: incrementing index i and shifting variable CB. In this step 36, the value of index i is incremented by 1 and variable CB is shifted one bit to the right.

[0076] After that, the method repeats from the first comparison step 31.

[0077] If in step 32, the value of the least significant bit CB[0] of variable CB is equal to 1, the method includes step 35: updating the stop variable STP. In this step 35, the stop value STP is set to 1. After that, the method continues with the aforementioned step 36 of incrementing index i and shifting variable CB.

[0078] If in step 33, the value of the stop variable STP is different from 0, specifically equal to 1, the method continues at step 36 of incrementing index i and shifting variable CB.

[0079] If in step 31, the value of index i is equal to 32, the value of the zero bit counter is written to register R41.

[0080] As previously mentioned, the digital signal processor DSP1 is configured to execute the computer program PRG1, and the computer program PRG1 includes instructions that allow arithmetic decoding to be performed. Specifically, the execution of the instructions causes the digital signal processor DSP1 to execute the function DEC_SYMB1. This function DEC_SYMB1 is illustrated in Figure 4 is illustrated.

[0081] The function DEC_SYMB1 is configured to determine the value of a symbol according to a coefficient array CUM_FREQ2_TAB[], which is associated with the symbol and stored in the data memory MEM1 of a digital signal processor DSP1. To align each vector of two 16-bit elements of the 32-bit array, the array is organized according to the parity of the number of symbols NUMSYM as Figure 9 shown. Zero elements are inserted at the beginning of each array. When NUMSYM is even, an additional element with hexadecimal value 0xFFFF is added at the end of the array.

[0082] More specifically, the decoding method includes an initialization step 40 before determining the value of the symbol according to the coefficient array CUM_FREQ2_TAB[].

[0083] In this step 40, a pointer CUM_FREQ2_PTR is initialized to point to the address of the coefficient array CUM_FREQ2_TAB[2]. In addition, a variable CBITS is initialized to 1. The length RGE of the value range and the interval start value LW are concatenated in the same word RGELW stored in a register R11. An index j is defined as 0.

[0084] Once the initialization is completed, the value of the symbol can be decoded using the following method.

[0085] The method includes a test step in which the index j is compared with the number of iterations n_itera to be performed. Specifically, the number of iterations n_itera to be performed depends on the number of possible symbols.

[0086] If the number of possible symbols is odd, the number of iterations to be performed is calculated by the following formula:

[0087] n_itera = (NUMSYM - 1) / 2, where n_itera is the number of iterations to be performed and numsym is the number of possible symbols.

[0088] If the number of possible symbols is even, the number of iterations to be performed is calculated by the following formula:

[0089] n_itera = NUMSYM / 2, where n_itera is the number of iterations to be performed and numsym is the number of possible symbols.

[0090] If the index j is less than the number of iterations n_itera to be performed, the method includes step 42: allowing multiplication and comparison to be performed in parallel according to two coefficients of the coefficient array.

[0091] Step 42 includes reading a pair of coefficients and then updating the pointer CUM_FREQ2_PTR to point to the coefficient following the two read coefficients.

[0092] Thereafter, step 42 includes calculating a new value CBITS by implementing a first block VMULT1 of circuit HWC1. Specifically, the first block VMULT1 is implemented with the current value CBITS, the word RGELW, and the two previously read coefficients CUM_FREQ2 as inputs.

[0093] The first block VMULT1 is used to perform a multiplication between the read coefficient CUM_FREQ2 and the RGE value of the interval length shifted right by 10 bits, and then to perform a comparison between the result of these multiplications and the value LW at the start of the interval. The result of these comparisons corresponds to the comparison bits b0 and b1 incorporated in the new variable CBITS.

[0094] Next, step 42 includes incrementing the index j by 1.

[0095] Thereafter, the method continues at step 41 to re-iterate the operations implemented by the first block VMULT1 for each coefficient of the array CUM_FREQ[] until the index j reaches the number of increments to be performed.

[0096] When the index j reaches the number of increments to be performed in step 41, the method includes step 43: calculating a value VAL. Specifically, this value VAL is calculated by implementing a second block TZC to determine the number of zeros on the right side in the finally calculated variable CBITS.

[0097] Specifically, if the number of possible symbols is odd, the value of the symbol is calculated by the following formula:

[0098] VAL = (NUMSYM - 1) - TZC(CBITS), where NUMSYM is the even number of possible symbols and TZC(CBITS) is the function implemented by the second block TZC based on the variable CBITS.

[0099] If the number of possible symbols is even, the value of the symbol is calculated by the following formula:

[0100] VAL = NUMSYM - TZC(CBITS), where NUMSYM is the odd number of possible symbols and TZC(CBITS) is the function implemented by the second block TZC based on the variable CBITS.

[0101] Thereafter, the symbol can be decoded from the value VAL calculated according to the interval defined by the interval length RGE and the interval start value.

[0102] In such an arithmetic decoding method, the fact that all comparisons associated with each coefficient in the array of coefficients are first performed before calculating the value of the symbol allows the comparisons to be done in parallel. Thus, this allows for an acceleration of the arithmetic decoding.

[0103] Figure 5 FIG. illustrates a second embodiment of the computer system SYS2. The computer system SYS2 is similar to Figure 1 the computer system SYS1. Specifically, the computer system SYS2 includes a central processing unit CPU2, a main memory MMEM2, and a digital signal processor DSP2 (also referred to as “Digital signal processor” in English), as well as a data memory MEM2 and a program memory MEMP2. The digital signal processor DSP2 includes a control unit CU2 (also referred to as “Control Unit and Register File” in English) having a data register file RF2, and an arithmetic and logic unit ALU2 (also referred to as “Arithmetic and Logic Unit” in English). The arithmetic logic unit ALU2 includes a circuit HWC2 dedicated to accelerating arithmetic and integrated decoding. The computer system SYS2 may be a system-on-chip.

[0104] The digital signal processor DSP2 is configured to execute a computer program PRG2, and the computer program PRG2 includes instructions that allow arithmetic decoding to be performed. The computer program PRG2 may be stored in the program memory MEMP2 of the computer system SYS2.

[0105] The digital signal processor DSP2 includes a first register R12, and the first register R12 is configured to store a comparison variable CBITS.

[0106] The digital signal processor DSP2 further includes a second register R22, and the second register R22 is configured to store a value interval length RGE and the starting value LW of the value interval. The length RGE and the value LW may be concatenated as a single binary word RGELW in the second register R22.

[0107] The digital signal processor DSP2 further includes a third register R32, and the third register R32 is configured to store two concatenated coefficients CUM_FREQ2.

[0108] The digital signal processor DSP2 further includes a fourth register R42, and the fourth register R42 is configured to store a left zero bit counter LZC_C in the variable CBITS.

[0109] Specifically, the circuit HWC2 can be integrated into the digital signal processor DSP2. Specifically, such a circuit HWC2 can be obtained according to the "RTL" (which means "Register Transfer Level" in English) code.

[0110] The dedicated circuit HWC2 includes a first block VMULT2, and the first block VMULT2 is configured to perform calculations and tests in a vector manner (i.e., in parallel) during arithmetic decoding. The first block VMULT2 is illustrated in Figure 6 this.

[0111] Specifically, the first block VMULT2 is configured to receive the variable CBITS stored in the first register R12 as an input. The first block VMULT2 is also configured to receive the interval length RGE and the interval start value LW as inputs. The interval length RGE and the value LW can be concatenated in the same word RGELW stored in the register R22. The first block VMULT2 is also configured to receive two concatenated coefficients CUM_FREQ2 as inputs.

[0112] The first block VMULT2 includes a first shift circuit SFT12. The first shift circuit SFT12 is configured to receive the word RGELW, and the word RGELW includes the interval length RGE and the concatenated value LW. The first shift circuit SFT12 is configured to shift the word 42 bits to the right. This allows the output of 32 bits associated with the interval start value LW, and then shift the value of the interval length RGE 10 bits to the right to obtain a temporary value TMP.

[0113] The first block VMULT2 further includes a first "AND" type logic gate AND12. The first "AND" type logic gate AND12 is configured to receive the word RGELW including the interval length RGE and the concatenated value LW and a first mask MSK12 with a hexadecimal value of "0xFFFFFFFF". The first "AND" type logic gate AND12 allows applying the first mask MSK12 to the word RGELW received as an input to recover the interval start value LW.

[0114] The first block VMULT2 further includes a second shift circuit SFT22. The second shift circuit SFT22 is configured to receive two concatenated coefficients CUM_FREQ2 and shift the two concatenated coefficients CUM_FREQ2 16 bits to the right to only retain the odd coefficients C_O2 of the two concatenated coefficients CUM_FREQ2.

[0115] The first block VMULT2 also includes a second "AND"-type logic gate AND22. The second "AND"-type logic gate AND22 is configured to receive two cascaded coefficients CUM_FREQ2 and a second mask having a hexadecimal value of "0xFFFF". The second "AND"-type logic gate AND22 allows the second mask to be applied to the two cascaded coefficients CUM_FREQ2 to recover the even coefficients C_E2 of the two cascaded coefficients CUM_FREQ2.

[0116] The first block VMULT2 also includes two parallel branches BRCH12 and BRCH22. The first branch BRCH12 includes a first multiplier circuit MLT12 and a first comparator circuit CMP12. The second branch BRCH22 includes a second multiplier circuit MLT22 and a second comparator circuit CMP22. The two branches BRCH12 and BRCH22 allow two multiplications to be performed in parallel and then two comparison tests to be performed using two different coefficients C_O2, C_E2 derived from the two cascaded coefficients CUM_FREQ2.

[0117] Specifically, the first multiplier circuit MLT12 is configured to receive as inputs a temporary value TMP generated at the output of the first shift circuit SFT12 and the odd coefficient C_O2. The first multiplier circuit MLT12 is then configured to multiply the temporary value TMP by the odd coefficient C_O2.

[0118] The second multiplier circuit MLT22 is configured to receive as inputs a temporary value TMP generated at the output of the first shift circuit SFT12 and the even coefficient C_E2. The second multiplier circuit MLT22 is then configured to multiply the temporary value TMP by the even coefficient C_E2.

[0119] The first comparator circuit CMP12 is configured to receive the result of the multiplication performed by the first multiplier circuit MLT12 and the interval start value LW. The first comparator circuit CMP12 is then configured to compare the result of the multiplication with the interval start value LW to see if the interval start value LW is greater than or equal to the result of the multiplication. If the value LW is greater than or equal to the result of the multiplication, the first comparator circuit CMP12 generates a comparison bit b1 equal to 1. If the value LW is less than the result of the multiplication, the first comparator circuit CMP12 generates a comparison bit b1 equal to 0.

[0120] The second comparator circuit CMP22 is configured to receive the result of the multiplication performed by the second multiplier circuit MLT22 and the interval start value LW. The second comparator circuit CMP22 is then configured to compare the result of the multiplication with the interval start value LW to see if the interval start value LW is greater than or equal to the result of the multiplication. If the value LW is greater than or equal to the result of the multiplication, the first comparator circuit CMP22 generates a comparison bit b1 equal to 1. If the value LW is less than the result of the multiplication, the first comparator circuit CMP22 generates a comparison bit b1 equal to 0.

[0121] The first block VMULT2 further includes a circuit CUPDT2 for updating the variable CBITS. The circuit CUPDT2 for updating the variable CBITS allows the comparison bits b1 and b0 to be incorporated into the right side of the old variable CBITS received as an input from the first block VMULT2.

[0122] Specifically, the update circuit CUPDT2 includes a third shift circuit SFT32, which is configured to shift the variable CBITS received as an input one bit to the right.

[0123] The update circuit CUPDT2 includes a fourth shift circuit SFT42, which is configured to shift the comparison bit b0 31 bits to the left.

[0124] The update circuit CUPDT2 further includes a first "OR" type logic gate OR12, which is configured to perform an "OR" type operation between the variable CBITS shifted one bit and the shifted comparison bit b0. Thus, the first "OR" type logic gate OR12 allows the comparison bit b0 to be incorporated into the left side in the variable CBITS. This allows the temporary variable CBITS_T to be obtained.

[0125] The update circuit CUPDT2 further includes a fifth shift circuit SFT52, which is configured to shift the temporary variable CBITS_T incorporated with the comparison bit b0 one bit to the right.

[0126] The update circuit CUPDT2 includes a sixth shift circuit SFT62, which is configured to shift the comparison bit b1 31 bits to the left.

[0127] The update circuit CUPDT2 further includes an "OR" type second logic gate OR22, and the "OR" type second logic gate OR22 is configured to perform an "OR" type operation between the shifted comparison bit b1 and the temporary variable CBITS_T incorporating the comparison bit b0 shifted one bit to the right. Thus, the second "OR" type logic gate OR22 allows the comparison bit b1 to be incorporated on the left side in the temporary variable CBITS_T. This allows obtaining the updated variable CBITS incorporating the comparison bits b0 and b1 on the left side of the variable CBITS. Thereafter, the new variable CBITS can be stored in the register R12 of the digital signal processor DSP2.

[0128] The dedicated circuit HWC2 includes a second block LZC, and the second block LZC is configured to receive the variable CBITS stored in the first register R12. The second block LZC is configured to implement a state machine, and the state machine allows performing a process of counting the number of zeros on the left side in the variable CBITS. Such a counting method is illustrated in Figure 7 herein.

[0129] The counting method includes an initialization step 70. The initialization step 70 allows initializing the index i to 0, initializing the stop variable STP to 0, initializing the left zero bit counter LZC_C to 0, and initializing the variable CB to the value of the variable CBITS.

[0130] Thereafter, the counting method includes a first comparison step 71. The first comparison step 71 is adapted to compare whether the value of the index i is less than 32.

[0131] If the value of the index is less than 32, the method then includes a second comparison step 72. The second comparison step 72 is adapted to shift the variable CB by a number of bits equal to 31 - i, and then apply a mask with a hexadecimal value of 0x1 to the shifted variable CB. The second comparison step 72 is also adapted to then compare whether the value obtained after applying the mask to the shifted variable CB is equal to 1.

[0132] If the value obtained after applying the mask to the shifted variable CB is different from 1, specifically equal to 0, the method includes a subsequent third comparison step 73. The third comparison step 73 is adapted to compare whether the stop variable STP is equal to 0.

[0133] If the stop variable STP is equal to 0, the method includes step 74: incrementing the left zero bit counter LZC_C.

[0134] Thereafter, the method includes step 76: incrementing the index i. In this step, the value of the index i is incremented by 1.

[0135] Thereafter, the method iterates again from the first comparison step 71.

[0136] If, in step 72, the value obtained after applying the mask to the shifted variable CB is equal to 1, the method includes step 75: updating the stop variable STP. In this step 75, the stop value STP is set to 1. Thereafter, the method continues with said step 76 of incrementing the index i.

[0137] If, in step 73, the value of the stop variable STP is different from 0, specifically equal to 1, the method continues with step 76 of incrementing the index i.

[0138] If, in step 71, the value of the index i is equal to 32, the value of the left zero counter LZC_C is stored in register R42.

[0139] As previously mentioned, the digital signal processor DSP2 is configured to execute the computer program PRG2, and the computer program PRG2 includes instructions that allow arithmetic decoding to be performed. Specifically, the execution of said instructions causes the digital signal processor DSP2 to execute the function DEC_SYMB2. This function DEC_SYMB2 is illustrated in Figure 8 in.

[0140] This function DEC_SYMB2 is configured to determine the value of a symbol according to the coefficient array CUM_FREQ2_TAB[], and the coefficient array CUM_FREQ2_TAB[] is associated with this symbol and is stored in the data memory MEM2 of the digital signal processor DSP2. In order to align each vector of 2 16-bit elements of this 32-bit array, the array is organized according to the parity of the number of symbols NUMSYM as Figure 9 shown. Zero elements are inserted at the beginning of each array. When NUMSYM is even, an additional element with a hexadecimal value of 0xFFFF is added at the end of the array.

[0141] More specifically, the decoding method includes an initialization step 80 before determining the value of the symbol according to the coefficient array CUM_FREQ2_TAB[].

[0142] In this step 80, the pointer CUM_FREQ2_PTR is initialized to point to the address of the coefficient array CUM_FREQ2_TAB[2]. In addition, the variable CBITS is initialized to 1. The length RGE of the value interval and the interval start value LW are concatenated in the same word RGELW. The index j is set to 0.

[0143] Once the initialization is complete, the symbol can be decoded by the following method.

[0144] The method includes a test step 81, in which an index j is compared with the number of iterations n_itera to be performed. Specifically, the number of iterations n_itera to be performed depends on the number of possible symbols.

[0145] If the number of possible symbols is odd, the number of iterations to be performed is calculated by the following formula:

[0146] n_itera = (numsym - 1) / 2, where n_itera is the number of iterations to be performed and numsym is the number of possible symbols.

[0147] If the number of possible symbols is even, the number of iterations to be performed is calculated by the following formula:

[0148] n_itera = numsym / 2, where n_itera is the number of iterations to be performed and numsym is the number of possible symbols.

[0149] If the index j is less than the number of iterations to be performed, the method includes step 82, which allows multiplication and comparison to be performed in parallel based on two coefficients from the coefficient array.

[0150] Step 82 includes updating the pointer CUM_FREQ2_PTR to point to the coefficient after the two coefficients read.

[0151] After that, step 82 includes calculating a new value CBITS by implementing the first block VMULT2 of the circuit HWC2. Specifically, the first block takes the current value CBITS, the word RGELW, and the two previously read coefficients CUM_FREQ2 as inputs.

[0152] Implementing the first block VMULT2 allows performing multiplication between the coefficient read and the interval length value shifted right by 10 bits, and then performing a comparison between the result of these multiplications and the interval start value. The results of these comparisons correspond to the comparison bits b0 and b1 incorporated in the new variable CBITS.

[0153] Step 82 then includes a step of incrementing the index j. In this step, the index j is incremented by 1.

[0154] After that, the method continues at step 81 to repeat the operations implemented by the first block VMULT2 for each coefficient of the array CUM_FREQ[] until the index j reaches the number of increments to be performed.

[0155] When the index j reaches the number of increments to be executed in step 81, the method includes step 83: calculating a value VAL. Specifically, this value VAL is calculated by implementing a second block of LZC to determine the number of zeros on the right side in the calculated last variable CBITS.

[0156] Specifically, if the number of possible symbols is odd, the value of the symbol is calculated by the following formula:

[0157] VAL = (NUMSYM - 1) - LZC(CBITS), where NUMSYM is the even number of possible symbols and LZC(CBITS) is a function implemented by the second block of LZC based on the variable CBITS.

[0158] If the number of possible symbols is even, the value of the symbol is calculated by the following formula:

[0159] VAL = NUMSYM - LZC(CBITS), where NUMSYM is the odd number of possible symbols and LZC(CBITS) is a function implemented by the second block of LZC based on the variable CBITS.

[0160] After that, the symbol can be decoded from the value VAL calculated according to the interval defined by the interval length RGE and the interval start value.

[0161] In such an arithmetic decoding method, the fact that all comparisons associated with each coefficient in the array of coefficients are first performed before calculating the value of the symbol allows the comparisons to be done in parallel. Therefore, this allows for accelerating the arithmetic decoding.

[0162] Of course, the embodiments are susceptible to various variations and modifications that those skilled in the art will think of. Specifically, the digital signal processor DSP2 can be configured to implement by itself the functions performed by the second block of LZC. Thus, in this case, it is not necessary to provide such a second block in a dedicated circuit. This can save space in the computer system SYS2.

[0163] In addition, the first blocks VMULT1 and VMULT2 can correspondingly have more branches than the two branches BRCH11, BRCH21 and BRCH12, BRCH22 to perform a greater number of multiplications and comparisons simultaneously, so as to process all the coefficients in the coefficient array CUM_FREQ2_TAB faster.

[0164] The previously described arithmetic decoding method can generally be implemented in the context of audio signal decoding for the decoder LC3. The symbol to be decoded then corresponds to the audio data.

[0165] A computer system can be generally summarized as including: a data memory (MEM), the data memory (MEM) being configured to store a coefficient array (CUM_FREQ2_TAB[]); digital signal processors (DSP1, DSP2), the digital signal processors (DSP1, DSP2) being configured to execute computer programs (PRG1, PRG2), the computer programs (PRG1, PRG2) including instructions that allow arithmetic decoding to be performed based on the coefficient array and a value range; a circuit (HWC1, HWC2) dedicated to the arithmetic decoding, the circuit being configured to: perform a comparison based on the coefficients of the coefficient array and the value range, and then count the same and consecutive results of the comparison, the digital signal processors (DSP1, DSP2) being configured to determine the value of a symbol associated with the coefficient array based on the number of the same and consecutive results counted by the dedicated circuit.

[0166] The dedicated circuit (HCW1, HCW2) may include a first block (VMULT1, VMULT2), the first block (VMULT1, VMULT2) being configured to calculate a comparison variable (CBITS), the comparison variable (CBITS) allowing the result of the comparison to be stored, the result of each comparison corresponding to a bit of the comparison variable (CBITS).

[0167] The first block (VMULT1, VMULT2) may be configured to perform at least two comparisons in parallel based on at least two consecutive coefficients (C_O1, C_E1, C_O2, C_E2) of the coefficient array and a range of values.

[0168] The first block (VMULT1, VMULT2) may include at least two parallel branches (BRCH11, BRCH21, BRCH12, BRCH22), the at least two parallel branches allowing the two comparisons to be performed simultaneously, each branch including: a multiplier circuit (MLT11, MLT21, MLT12, MLT22), the multiplier circuit being configured to perform a multiplication between a coefficient among the two consecutive coefficients (C_O1, C_E1, C_O2, C_E2) and the length (RGE) of the value range shifted by a given number of bits, the given number of bits being specifically between 0 and the number of bits used to define the length of the range; a comparator circuit (CMP11, CMP21, CMP12, CMP22), the comparator circuit being configured to compare the multiplication result with the starting value (LW) of the value range.

[0169] The first block may further include a circuit (CUPDT1, CUPDT2) for updating the comparison variable, the circuit for updating the comparison variable being configured to incorporate the result of the comparison performed by each comparator circuit into the comparison variable (CBITS).

[0170] The dedicated circuits (HCW1, HCW2) may also include a second block (TZC, LZC), which is configured to implement a state machine that is configured to count consecutive identical results stored in the comparison variable (CBITS) by analyzing bits of the comparison variable (CBITS).

[0171] The result of each comparison performed by the first block (VMULT1) may be progressively stored on the right side in the comparison variable (CBITS), and the state machine implemented by the second block (TZC) may be configured to count the number of identical comparison results starting from the rightmost bit in the comparison variable (CBITS).

[0172] The result of each comparison performed by the first block (VMULT2) may be progressively stored on the left side in the comparison variable (CBITS), and the state machine implemented by the second block (LZC) may be configured to count the number of identical comparison results starting from the leftmost bit in the comparison variable (CBITS).

[0173] The computer programs (PRG1, PRG2) may include instructions that, when executed by the digital signal processors (DSP1, DSP2), cause the digital signal processors (DSP1, DSP2) to: implement the first blocks (VMULT1, VMULT2) to perform comparisons in parallel according to each coefficient in the coefficient array and the interval, with the result of each comparison being stored in the comparison variable (CBITS); then implement the second blocks (TZC, LZC) to count consecutive identical results stored in the comparison variable (CBITS) by analyzing bits of the comparison variable (CBITS) once all comparisons have been performed; and then calculate the value (VAL) of the sign associated with the coefficient array based on the number of counted consecutive identical results.

[0174] A method implemented by a computer system (SYS1, SYS2), the method can be generally summarized as including: a digital signal processor (DSP1, DSP2) of the computer system (SYS1, SYS2) executes a computer program (PRG1, PRG2), the computer program (PRG1, PRG2) includes instructions, and the instructions allow arithmetic decoding to be performed according to a coefficient array and a value range stored in the data memory of the computer system (SYS1, SYS2), and the arithmetic decoding includes: implementing a circuit (HWC1, HWC2) dedicated to the arithmetic decoding in the computer system to: perform a comparison based on the coefficients of the coefficient array and the value range, then count the same and consecutive results of the comparison, and then the digital signal processor (DSP1, DSP2) determines the value of the symbol associated with the coefficient array according to the number of the same and consecutive results counted by the dedicated circuit.

[0175] Implementing the dedicated circuit (HCW1, HCW2) may include implementing a first block (VMULT1, VMULT2) of the dedicated circuit, and the first block is used to calculate a comparison variable (CBITS), and the comparison variable (CBITS) allows storing the result of the comparison, and the result of each comparison corresponds to a bit of the comparison variable (CBITS).

[0176] Implementing the first block (VMULT1, VMULT2) may be adapted to perform at least two comparisons in parallel according to at least two consecutive coefficients (C_O1, C_E1, C_O2, C_E2) of the coefficient array and the value range.

[0177] Implementing the first block (VMULT1, VMULT2) may include implementing at least two parallel branches (BRCH11, BRCH21, BRCH12, BRCH22), and the at least two parallel branches (BRCH11, BRCH21, BRCH12, BRCH22) are adapted to perform the two comparisons simultaneously. Implementing each branch includes: implementing a multiplier circuit (MLT11, MLT21, MLT12, MLT22), and the multiplier circuit (MLT11, MLT21, MLT12, MLT22) is used to perform a multiplication between one of the two consecutive coefficients (C_O1, C_E1, C_O2, C_E2) and the length (RGE) of the value range shifted by a given number of bits, and the given number of bits is specifically between 0 and the number of bits used to define the length of the interval; implementing a comparator circuit (CMP11, CMP21, CMP12, CMP22), and the comparator circuit (CMP11, CMP21, CMP12, CMP22) is used to compare the result of the multiplication with the start value (LW) of the value range.

[0178] Implementing the first block (VMULT1, VMULT2) may also include implementing circuitry (CUPDT1, CUPDT2) for updating a comparison variable to incorporate the results of comparisons performed by each comparator circuit into the comparison variable (CBITS).

[0179] Implementing the dedicated circuitry (HCW1, HCW2) may also include implementing a second block (TZC, LZC) for performing a state machine adapted to count consecutive identical results stored in the comparison variable (CBITS) by analyzing bits of the comparison variable (CBITS).

[0180] The result of each comparison performed by the first block (VMULT1) may be progressively stored on the right side in the comparison variable (CBITS), and the state machine implemented by the second block (TZC) may be adapted to count the number of identical comparison results starting from the rightmost bit in the comparison variable (CBITS).

[0181] The result of each comparison performed by the first block (VMULT2) may be progressively stored on the left side in the comparison variable (CBITS), and the state machine implemented by the second block (LZC) may be adapted to count the number of identical comparison results starting from the leftmost bit in the comparison variable (CBITS).

[0182] Executing the computer program may cause: implementing the first block (VMULT1, VMULT2) to perform comparisons in parallel according to each coefficient of the coefficient array and the interval, the result of each comparison being stored in the comparison variable (CBITS), then implementing the second block (TZC, LZC) to count consecutive identical results stored in the comparison variable (CBITS) by analyzing bits of the comparison variable (CBITS) once all comparisons have been performed, and then calculating, by a digital signal processor (DSP1, DSP2), the value (VAL) of the symbol associated with the coefficient array based on the counted number of consecutive identical results.

[0183] The various embodiments described above may be combined to provide additional embodiments. These and other changes may be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to such claims. Thus, the claims are not limited by the present disclosure.

Claims

1. A system comprising: one or more memories configured to store arrays of coefficients and intervals of values; A circuit, the circuit being configured as: performing a comparison based on the coefficients of the array of coefficients and the interval of the value; and counting identical and consecutive results of said comparisons; as well as A digital signal processor performs arithmetic decoding by being configured to determine a value of a symbol associated with the array of coefficients based on a count of identical and consecutive said results. 2 . The system of claim 1 , wherein the circuit is configured to calculate a comparison variable that stores the results of the comparisons, wherein the result of each comparison corresponds to a bit of the comparison variable. 3 . The system of claim 2 , wherein the circuit is configured to perform at least two comparisons in parallel based on at least two consecutive coefficients of the array of coefficients and the range of values.

4. The system of claim 3, wherein the circuit comprises at least two parallel branches, the at least two parallel branches allowing the at least two comparisons to be performed in parallel, each parallel branch comprising: a multiplier circuit configured to multiply the coefficient of the two consecutive coefficients by the length of the interval of values ​​shifted by a given number of bits, wherein the given number of bits is between 0 and the number of bits used to define the length of the interval of values; and A comparator circuit is configured to compare the result of the multiplication with a start value of the interval of values. 5 . The system of claim 4 , wherein the circuit is configured to update the comparison variable based on the result of the comparison performed by each comparator circuit. 6 . The system of claim 2 , wherein the circuit is configured to implement a state machine that counts the consecutive identical results stored in the comparison variable by analyzing bits of the comparison variable.

7. The system of claim 6 , wherein the result of each comparison performed by the first block is stored progressively in bits to the right of the comparison variable, and wherein the state machine is configured to count the number of consecutive identical comparison results starting from the rightmost bit of the comparison variable.

8. The system of claim 6, wherein the result of each comparison is stored stepwise in bits on the left side of the comparison variable, and wherein the state machine is configured to count the number of consecutive identical comparison results starting from the leftmost bit of the comparison variable.

9. The system of claim 6, wherein the digital signal processor comprises the circuit and is further configured to: performing in parallel a comparison of each coefficient of the array of coefficients with the interval of values, wherein the result of each comparison is stored in the comparison variable; counting consecutive identical results stored in the comparison variable by analyzing the bits of the comparison variable; and A value of the symbol associated with the array of coefficients is calculated based on the count of consecutive identical results.

10. One or more non-transitory computer-readable media storing instructions executable by one or more processors to perform actions comprising: Comparisons are performed based on the coefficients of the array of coefficients and the interval of values; counting identical and consecutive results of said comparisons; as well as A value of a sign associated with the array of coefficients is determined based on a count of the results that are identical and consecutive.

11. The one or more non-transitory computer readable media of claim 10, the actions further comprising: A comparison variable is calculated to store the result of the comparison, the result of each comparison corresponding to one bit of the comparison variable.

12. The one or more non-transitory computer readable media of claim 11, the actions further comprising: At least two comparisons of at least two consecutive coefficients of the array of coefficients with the interval of values ​​are performed in parallel.

13. The one or more non-transitory computer-readable media of claim 12, wherein performing the at least two comparisons in parallel comprises: multiplying a coefficient of the at least two consecutive coefficients by the length of the interval of values ​​shifted by a given number of bits, the given number of bits being between 0 and the number of bits used to define the length of the interval of values; and The result of the multiplication is compared to the start value of the interval of values.

14. The one or more non-transitory computer-readable media of claim 13, wherein performing the at least two comparisons in parallel comprises: The comparison variable is updated based on the results of the at least two comparisons.

15. The one or more non-transitory computer-readable media of claim 11, wherein counting identical and consecutive results of the comparison comprises: A state machine is executed, the state machine being adapted to count the consecutive identical results stored in the comparison variable by analyzing the bits of the comparison variable.

16. The one or more non-transitory computer-readable media of claim 15, wherein the result of each comparison is stored incrementally to the right in the comparison variable, and wherein counting the consecutive identical results comprises: The number of the same comparison results is counted starting from the rightmost bit of the comparison variable.

17. The one or more non-transitory computer-readable media of claim 15, wherein the result of each comparison is stored incrementally to the left in the comparison variable, and wherein counting the consecutive identical results comprises: The number of the consecutive identical comparison results is counted starting from the leftmost bit of the comparison variable.

18. The one or more non-transitory computer readable media of claim 11, the actions further comprising: comparing the coefficients of the array of coefficients to the interval in parallel; storing the result of each comparison in the comparison variable; counting the consecutive identical results stored in the comparison variable by analyzing the bits of the comparison variable; as well as The value of the symbol associated with the array of coefficients is calculated based on the count of consecutive identical results.

19. A method comprising: Comparisons are performed based on the coefficients of the array of coefficients and the interval of values; counting identical and consecutive results of said comparisons; as well as A sign associated with the array of coefficients is determined based on a count of the results that are identical and consecutive.

20. The method of claim 19, wherein performing comparison based on the coefficients of the array of coefficients and the intervals of values ​​comprises: At least two consecutive coefficients of the array of coefficients are compared in parallel to the interval of values.

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