A radio frequency front-end module and a radio frequency chip

Abstract

The present invention is applicable to the field of radio frequency technology, and particularly relates to a radio frequency front-end module and a radio frequency chip. The radio frequency front-end module includes: a substrate and a first chip, a second chip, a third chip, and a fourth chip fixed to the substrate; the first chip is used for signal amplification processing of a first-band radio frequency signal and a second-band radio frequency signal; the second chip is used for signal amplification processing of the first-band radio frequency signal; the third chip is used for signal amplification processing of the second-band radio frequency signal; the fourth chip is used for filtering processing of the first-band radio frequency signal and the second-band radio frequency signal. Compared with the prior art, the radio frequency front-end module proposed by the present invention can achieve efficient coordination of dual-band transmission and reception circuits under a compact structure, and at the same time, by integrating filter and bypass function designs, simplifies the power control process of the radio frequency front-end module and reduces radiation and energy consumption, effectively improving the reliability and service life of the radio frequency front-end module.

Description

Technical Field

[0001] The present invention is applicable to the field of radio frequency technology, and particularly relates to a radio frequency front-end module and a radio frequency chip. Background Art

[0002] In modern wireless communication systems, Time Division Duplexing (TDD) technology is widely used in scenarios such as WIFI. It realizes bidirectional signal transmission through the same frequency band, posing higher requirements for the design of radio frequency front-end modules (FEM). Traditional radio frequency front-end modules usually consist of core circuits such as radio frequency switches, Power Amplifiers (PA), and Low Noise Amplifiers (LNA) to achieve the switching of transmission and reception functions and signal processing. However, with the growth of multi-band communication requirements (such as support for dual bands of WIFI 2.4GHz and 5GHz), the existing technical solutions face the following limitations:

[0003] Insufficient multi-band integration: The existing radio frequency front-end module designs mostly adopt discrete architectures, and independent transmit and receive circuits need to be configured for different frequency bands (such as 2.4GHz and 5GHz). This not only increases the module size and cost but also introduces additional signal losses and interference due to the complex interconnection design between circuits, affecting system performance.

[0004] Complex transmit power control: To achieve dynamic adjustment of transmit power for different frequency bands in the existing radio frequency front-end modules, independent control modules and feedback loops need to be configured for each frequency band. Such designs not only increase the consumption of hardware resources but also lead to increased power consumption due to the complexity of multi-signal coordination, and are prone to problems of excessive electromagnetic radiation.

[0005] Energy consumption and reliability issues: The complex control logic and redundant circuit design of the discrete multi-band architecture result in relatively high overall energy consumption. At the same time, the long-term high-load operation of devices may accelerate aging, affecting the service life of the radio frequency front-end module.

[0006] Therefore, there is an urgent need for a new radio frequency front-end module and radio frequency chip to solve the above technical problems. Summary of the Invention

[0007] The present invention provides a radio frequency front-end module and a radio frequency chip, aiming to effectively reduce the complexity of implementing transmit power control of the radio frequency front-end module, reduce radiation, lower energy consumption, and improve the service life.

[0008] In a first aspect, the present invention provides a radio frequency front-end module, which includes: a substrate and a first chip, a second chip, a third chip, and a fourth chip fixed to the substrate;

[0009] The first end of the first chip is connected to the first antenna terminal, the second end of the first chip is connected to the second antenna terminal, the third end of the first chip is connected to the first signal switching terminal, the fourth end of the first chip is connected to the second signal switching terminal, the fifth end of the first chip is connected to the input terminal of the second chip, the sixth end of the first chip is connected to the input terminal of the third chip, the seventh end of the first chip is connected to the output terminal of the second chip, the eighth end of the first chip is connected to the output terminal of the third chip, the ninth end of the first chip is connected to the first end of the fourth chip, and the tenth end of the first chip is connected to the second end of the fourth chip; the first chip is used for inputting / outputting radio frequency signals in the first frequency band or inputting / outputting radio frequency signals in the second frequency band and performing signal amplification processing on the radio frequency signals in the first frequency band and the radio frequency signals in the second frequency band;

[0010] The second chip is used for performing signal amplification processing on the radio frequency signals in the first frequency band;

[0011] The third chip is used for performing signal amplification processing on the radio frequency signals in the second frequency band;

[0012] The third end of the fourth chip is connected to the first frequency band signal terminal, the fourth end of the fourth chip is connected to the second frequency band signal terminal, and the fourth chip is used for inputting / outputting the radio frequency signals in the first frequency band or inputting / outputting the radio frequency signals in the second frequency band and performing filtering processing on the radio frequency signals in the first frequency band and the radio frequency signals in the second frequency band.

[0013] Preferably, the first chip includes a control logic circuit unit, a first radio frequency switch circuit unit, a second radio frequency switch circuit unit, a first frequency band low-noise amplifier unit, and a second frequency band low-noise amplifier unit;

[0014] The control logic circuit unit is used for receiving an external control signal and controlling the first radio frequency switch circuit unit and the second radio frequency switch circuit unit according to the external control signal;

[0015] The first pin of the first radio frequency switch circuit unit serves as the first end of the first chip, the second pin of the first radio frequency switch circuit unit serves as the second end of the first chip, the third pin of the first radio frequency switch circuit unit serves as the third end of the first chip, the fourth pin of the first radio frequency switch circuit unit serves as the seventh end of the first chip, the fifth pin of the first radio frequency switch circuit unit is connected to the input end of the first band low noise amplifier unit, the sixth pin of the first radio frequency switch circuit unit is connected to the fifth pin of the second radio frequency switch circuit unit, the seventh pin of the first radio frequency switch circuit unit is connected to the input end of the second band low noise amplifier unit, the eighth pin of the first radio frequency switch circuit unit serves as the eighth end of the first chip, and the ninth pin of the first radio frequency switch circuit unit serves as the fourth end of the first chip;

[0016] The first pin of the second radio frequency switch circuit unit serves as the ninth end of the first chip, the second pin of the second radio frequency switch circuit unit serves as the tenth end of the first chip, the third pin of the second radio frequency switch circuit unit serves as the sixth end of the first chip, the fourth pin of the second radio frequency switch circuit unit is connected to the output end of the second band low noise amplifier unit, the sixth pin of the second radio frequency switch circuit unit is connected to the output end of the first band low noise amplifier unit, and the seventh pin of the second radio frequency switch circuit unit serves as the fifth end of the first chip;

[0017] The first band low noise amplifier unit is used to perform signal amplification processing on the first band radio frequency signal;

[0018] The second band low noise amplifier unit is used to perform signal amplification processing on the second band radio frequency signal.

[0019] Preferably, the second chip includes a first bias and temperature compensation circuit unit, a first input matching circuit unit, a first power amplifier unit, and a first output matching circuit unit;

[0020] The first bias and temperature compensation circuit unit is used to provide a bias voltage for the first power amplifier unit;

[0021] The input end of the first input matching circuit unit serves as the input end of the second chip, the output end of the first input matching circuit unit is connected to the input end of the first power amplifier unit, the output end of the first power amplifier unit is connected to the output end of the first output matching circuit unit, and the output end of the first output matching circuit unit serves as the output end of the second chip.

[0022] Preferably, the third chip includes a second bias and temperature compensation circuit unit, a second input matching circuit unit, a second power amplifier unit, and a second output matching circuit unit;

[0023] The second bias and temperature compensation circuit unit is used to provide a bias voltage for the second power amplifier unit;

[0024] The input end of the second input matching circuit unit serves as the input end of the third chip. The output end of the second input matching circuit unit is connected to the input end of the second power amplifier unit. The output end of the second power amplifier unit is connected to the output end of the second output matching circuit unit. The output end of the second output matching circuit unit serves as the output end of the third chip.

[0025] Preferably, the fourth chip includes a first band filter unit and a second band filter unit;

[0026] The first end of the first band filter unit serves as one end of the fourth chip, and the second end of the first band filter unit serves as the third end of the fourth chip;

[0027] The first end of the second band filter unit serves as the second end of the fourth chip, and the second end of the second band filter unit serves as the fourth end of the fourth chip.

[0028] Preferably, the frequency band of the first band radio frequency signal is the 2.4G frequency band.

[0029] Preferably, the frequency band of the second band radio frequency signal is the 5G frequency band.

[0030] In a second aspect, the present invention further provides a radio frequency chip, which includes the radio frequency front-end module as described in any one of the above embodiments.

[0031] Compared with the prior art, the radio frequency front-end module proposed by the present invention can achieve efficient coordination of the dual-band transmission and reception circuits under a compact structure. At the same time, through the integrated filter and bypass function design, the power control process of the radio frequency front-end module is simplified, and the radiation and energy consumption are reduced, effectively improving the reliability and service life of the radio frequency front-end module. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention will be described in detail below with reference to the drawings. Through the detailed description in combination with the following drawings, the above or other aspects of the present invention will become clearer and easier to understand. In the drawings:

[0033] Figure 1 is a schematic circuit structure diagram of the radio frequency front-end module provided by the embodiment of the present invention.

[0034] In the figure, 100 is a radio frequency front-end module; 1 is a first chip; 11 is a control logic circuit unit; 12 is a first radio frequency switch circuit unit; 13 is a second radio frequency switch circuit unit; 14 is a first-band low-noise amplifier unit; 15 is a second-band low-noise amplifier unit; 2 is a second chip; 21 is a first bias and temperature compensation circuit unit; 22 is a first input matching circuit unit; 23 is a first power amplifier unit; 24 is a first output matching circuit unit; 3 is a third chip; 31 is a second bias and temperature compensation circuit unit; 32 is a second input matching circuit unit; 33 is a second power amplifier unit; 34 is a second output matching circuit unit; 4 is a fourth chip; 41 is a first-band filter unit; 42 is a second-band filter unit; 5 is a substrate. Detailed implementation manners

[0035] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0036] Embodiment 1

[0037] Please refer to Figure 1 , the present invention provides a radio frequency front-end module 100, and the radio frequency front-end module 100 includes: a substrate 5 and a first chip 1 (Die1), a second chip 2 (Die2), a third chip 3 (Die3), and a fourth chip 4 (Die4) fixed to the substrate 5;

[0038] A first end of the first chip 1 is connected to a first antenna terminal ANT0, a second end of the first chip 1 is connected to a second antenna terminal ANT1, a third end of the first chip 1 is connected to a first signal switching terminal Tuner0, a fourth end of the first chip 1 is connected to a second signal switching terminal Tuner1, a fifth end of the first chip 1 is connected to an input end of the second chip 2, a sixth end of the first chip 1 is connected to an input end of the third chip 3, a seventh end of the first chip 1 is connected to an output end of the second chip 2, an eighth end of the first chip 1 is connected to an output end of the third chip 3, a ninth end of the first chip 1 is connected to a first end of the fourth chip 4, and a tenth end of the first chip 1 is connected to a second end of the fourth chip 4; the first chip 1 is configured to input / output a first-band radio frequency signal or input / output a second-band radio frequency signal and perform signal amplification processing on the first-band radio frequency signal and the second-band radio frequency signal;

[0039] The second chip 2 is configured to perform signal amplification processing on the first-band radio frequency signal;

[0040] The third chip 3 is used to amplify the second-band radio frequency signal;

[0041] The third terminal of the fourth chip 4 is connected to the first-band signal terminal 2G TRX (the first-band signal terminal is used for inputting and outputting 2G signals), the fourth terminal of the fourth chip 4 is connected to the second-band signal terminal 5G TRX (the second-band signal terminal port is used for inputting and outputting 5G signals), and the fourth chip 4 is used for inputting / outputting the first-band radio frequency signal or inputting / outputting the second-band radio frequency signal, and filtering the first-band radio frequency signal and the second-band radio frequency signal.

[0042] In the embodiment of the present invention, the first chip 1 includes a control logic circuit unit 11, a first radio frequency switch circuit unit 12 (SW1), a second radio frequency switch circuit unit 13 (SW2), a first-band low noise amplifier unit 14 (LNA1), and a second-band low noise amplifier unit 15 (LNA2). Specifically, the first chip 1 generally adopts SOI (Silicon-on-Insulator) or PHEMT (Pseudomorphic High Electron Mobility Transistor) process, but is not limited to the above two processes. The control logic circuit unit 11 controls the working states of internal circuits according to externally input instructions; the external instruction hardware interface can be GPIO (General Purpose Input / Output), MIPI (Mobile Industry Processor Interface), or other methods. Among them, the first radio frequency switch circuit unit 12 is a double-pole seven-throw radio frequency switch (DP7T). Among them, the first pin SW1-1 and the second pin SW1-2 of the first radio frequency switch circuit unit 12 form the first group of the first radio frequency switch circuit unit 12, and the third pin SW1-3, the fourth pin SW1-4, the fifth pin SW1-5, the sixth pin SW1-6, the seventh pin SW1-7, the eighth pin SW1-8, and the ninth pin SW1-9 of the first radio frequency switch circuit unit 12 form the second group of the first radio frequency switch circuit unit 12; a controlled connection can be achieved between the first group and the second group of the first radio frequency switch circuit unit 12.

[0043] The second radio frequency switch circuit unit 13 is a double-pole five-throw radio frequency switch (DP5T). Among them, the first pin SW2-1 and the second pin SW2-2 of the second radio frequency switch circuit unit 13 form the first group of the second radio frequency switch circuit unit 13, and the third pin SW2-3, the fourth pin SW2-4, the fifth pin SW2-5, the sixth pin SW2-6, and the seventh pin SW2-7 form the second group of the second radio frequency switch circuit unit 13; a controlled connection can be achieved between the first group and the second group of the second radio frequency switch circuit unit 13.

[0044] The control logic circuit unit 11 is used to receive an external control signal GPIO / MIPI and control the first radio frequency switch circuit unit 12 and the second radio frequency switch circuit unit 13 according to the external control signal GPIO / MIPI;

[0045] The first pin SW1-1 of the first radio frequency switch circuit unit 12 serves as the first end of the first chip 1, the second pin SW1-2 of the first radio frequency switch circuit unit 12 serves as the second end of the first chip 1, the third pin SW1-3 of the first radio frequency switch circuit unit 12 serves as the third end of the first chip 1, the fourth pin SW1-4 of the first radio frequency switch circuit unit 12 serves as the seventh end of the first chip 1, the fifth pin SW1-5 of the first radio frequency switch circuit unit 12 is connected to the input end of the first-band low-noise amplifier unit 14, the sixth pin SW1-6 of the first radio frequency switch circuit unit 12 is connected to the fifth pin SW2-5 of the second radio frequency switch circuit unit 13, the seventh pin SW1-7 of the first radio frequency switch circuit unit 12 is connected to the input end of the second-band low-noise amplifier unit 15, the eighth pin SW1-8 of the first radio frequency switch circuit unit 12 serves as the eighth end of the first chip 1, and the ninth pin SW1-9 of the first radio frequency switch circuit unit 12 serves as the fourth end of the first chip 1;

[0046] The first pin SW2-1 of the second radio frequency switch circuit unit 13 serves as the ninth end of the first chip 1, the second pin SW2-2 of the second radio frequency switch circuit unit 13 serves as the tenth end of the first chip 1, the third pin SW2-3 of the second radio frequency switch circuit unit 13 serves as the sixth end of the first chip 1, the fourth pin SW2-4 of the second radio frequency switch circuit unit 13 is connected to the output end of the second-band low-noise amplifier unit 15, the sixth pin SW2-6 of the second radio frequency switch circuit unit 13 is connected to the output end of the first-band low-noise amplifier unit 14, and the seventh pin SW2-7 of the second radio frequency switch circuit unit 13 serves as the fifth end of the first chip 1;

[0047] The first - band low - noise amplifier unit 14 is used to amplify the first - band radio - frequency signal; wherein, the first - band low - noise amplifier unit 14 is a 2G - band low - noise amplifier, which is used to amplify the input 2G - band received signal.

[0048] The second - band low - noise amplifier unit 15 is used to amplify the second - band radio - frequency signal. The second - band low - noise amplifier unit 15 is a 5G - band low - noise amplifier, which is used to amplify the input 5G - band received signal.

[0049] In the embodiment of the present invention, the second chip 2 adopts the HBT process, but is not limited to this process. The second chip 2 includes a first bias and temperature compensation circuit unit 21, a first input matching circuit unit 22, a first power amplifier unit 23 (PA1), and a first output matching circuit unit 24;

[0050] The first bias and temperature compensation circuit unit 21 is used to provide a bias voltage for the first power amplifier unit 23;

[0051] The input end of the first input matching circuit unit 22 serves as the input end of the second chip 2. The output end of the first input matching circuit unit 22 is connected to the input end of the first power amplifier unit 23. The output end of the first power amplifier unit 23 is connected to the output end of the first output matching circuit unit 24. The output end of the first output matching circuit unit 24 serves as the output end of the second chip 2. Specifically, the first input matching circuit unit 22 is used to achieve the optimal matching between the output impedance of the seventh pin SW2 - 7 of the second radio - frequency switch circuit unit 13 and the input impedance of the first power amplifier unit 23. The first output matching circuit unit 24 is used to achieve the optimal matching between the input impedance of the fourth pin SW1 - 4 of the first radio - frequency switch circuit unit 12 and the output impedance of the first power amplifier unit 23. The first power amplifier unit 23 is used to amplify the input 2G - band transmitted signal, and its gain is usually between several dB and dozens of dB. The first power amplifier unit 23 is powered by an external DC power supply, and the external DC power supply is introduced from the VCC pin of the module. The first bias and temperature compensation circuit unit 21 is used to provide a DC bias voltage for the first power amplifier unit 23 and perform temperature compensation, so that the gain of the first power amplifier unit 23 is stable at different ambient temperatures.

[0052] In the embodiment of the present invention, the third chip 3 includes a second bias and temperature compensation circuit unit 31, a second input matching circuit unit 32, a second power amplifier unit 33, and a second output matching circuit unit 34;

[0053] The second bias and temperature compensation circuit unit 31 is used to provide a bias voltage for the second power amplifier unit 33;

[0054] The input end of the second input matching circuit unit 32 serves as the input end of the third chip 3. The output end of the second input matching circuit unit 32 is connected to the input end of the second power amplifier unit 33. The output end of the second power amplifier unit 33 is connected to the output end of the second output matching circuit unit 34. The output end of the second output matching circuit unit 34 serves as the output end of the third chip 3. Specifically, the second input matching circuit unit 32 is used to achieve the optimal matching between the output impedance of the third pin SW2-3 of the second RF switch circuit unit 13 and the input impedance of the second power amplifier unit 33. The second output matching circuit unit 34 is used to achieve the optimal matching between the input impedance of the eighth pin SW1-8 of the first RF switch circuit unit 12 and the output impedance of the second power amplifier unit 33. The second power amplifier unit 33 is used to amplify the input 5G band transmission signal, and its gain is usually between several dB and dozens of dB. The second power amplifier unit 33 is powered by an external DC power supply, and the external direct power supply is introduced from the VCC pin of the module. The second bias and temperature compensation circuit unit 31 is used to provide a DC bias voltage for the second power amplifier unit 33 and perform temperature compensation, so that the gain of the second power amplifier unit 33 is stable at different ambient temperatures.

[0055] In the embodiment of the present invention, the fourth chip can be manufactured by SAW (Surface Acoustic Wave) process or other processes. Since the SAW process has mature technology, high circuit Q value, strong out-of-band rejection ability, and low insertion loss, it often becomes the preferred process for filters. The fourth chip includes a first band filter unit 41 (Filter1) and a second band filter unit 42 (Filter2);

[0056] The first end of the first band filter unit 41 serves as one end of the fourth chip 4, and the second end of the first band filter unit 41 serves as the third end of the fourth chip 4;

[0057] The first end of the second band filter unit 42 serves as the second end of the fourth chip 4, and the second end of the second band filter unit 42 serves as the fourth end of the fourth chip 4.

[0058] Specifically, the 2G band filtering is achieved through the first band filter unit 41, and the 5G band filtering is achieved through the second band filter unit 42. By independently filtering the input and output signals of each band, the out-of-band spurious signals are reduced and the signal quality is improved.

[0059] Specifically, in the embodiment of the present invention, the frequency band of the first-band radio frequency signal is the 2.4G frequency band, and the frequency band of the second-band radio frequency signal is the 5G frequency band. It should be noted that other two radio frequency signals with different frequency bands are also feasible, not limited to the 2.4G frequency band and the 5G frequency band.

[0060] The first chip 1, the second chip 2, the third chip 3, and the fourth chip 4 can be fixed on the substrate 5 or the frame by different methods, such as silver paste fixing, solder ball welding, etc. The substrate 5 is in the form of a multi-layer circuit board or a frame. The chips can be electrically connected by metal fine wires (Bonding Wire) between chips and between chips and the substrate, or by solder balls in the flip-chip mounting method.

[0061] Specifically, the above circuit has different working modes under the action of an external control signal. Different signal paths exist in different working modes to meet different working requirements. The specific situation of the working modes is as follows:

[0062] Working mode 1:

[0063] The first power amplifier unit 23 works and outputs to the first antenna terminal ANT0, and the second signal switching terminal Tuner1 is connected to the second antenna terminal ANT1.

[0064] The 2G transmission signal is input from the first-band signal terminal 2G TRX to the first-band filter unit 41. After being filtered by the first-band filter unit 41, it is output from the first end of the first-band filter unit 41 to the first pin SW2-1 of the second radio frequency switch circuit unit 13. Under the action of the control logic circuit unit, the first pin SW2-1 of the second radio frequency switch circuit unit 13 is connected to the seventh pin SW2-7 of the second radio frequency switch circuit unit 13. Therefore, the transmission signal is output from the second radio frequency switch circuit unit 13 SW2 to the first input matching circuit unit 22, and after impedance matching, it enters the first power amplifier unit 23. At the same time, the first bias and temperature compensation circuit unit 21 outputs a bias signal under the control of the control logic circuit unit 11, and the first power amplifier unit 23 works. The input signal is amplified and impedance-matched by the first power amplifier unit 23 and then output to the fourth pin SW1-4 of the first radio frequency switch circuit unit 12. Under the action of the control logic circuit unit 11, the fourth pin SW1-4 of the first radio frequency switch circuit unit 12 is connected to the first pin SW1-1 of the first radio frequency switch circuit unit 12, and the ninth pin SW1-9 of the first radio frequency switch circuit unit 12 is connected to the second pin SW1-2 of the first radio frequency switch circuit unit 12. The output signal of the first power amplifier unit 23 passes through the first radio frequency switch circuit unit 12 and is output from the first pin SW1-1 of the first radio frequency switch circuit unit 12 to the first antenna terminal ANT0.

[0065] Working mode 2:

[0066] The first power amplifier unit 23 works and outputs to the second antenna terminal ANT1. The first signal switching terminal Tuner0 is connected to the first antenna terminal ANT0.

[0067] The 2G transmission signal is input from the first frequency band signal terminal 2G TRX to the second terminal of the first frequency band filter unit 41. After being filtered by the first frequency band filter unit 41, it is output from the first terminal of the first frequency band filter unit 41 to the first pin SW2-1 of the second radio frequency switch circuit unit 13. Under the action of the control logic circuit unit 11, the first pin SW2-1 of the second radio frequency switch circuit unit 13 is connected to the seventh pin SW2-7 of the second radio frequency switch circuit unit 13. Therefore, the transmission signal is output to the first input matching circuit unit 22 through the second radio frequency switch circuit unit 13, and enters the first power amplifier unit 23 after impedance matching. At the same time, the first bias and temperature compensation circuit unit 21 outputs a bias signal under the control of the control logic circuit unit 11, and the first power amplifier unit 23 works. After being amplified and impedance-matched by the first power amplifier unit 23, the input signal is output to the fourth pin SW1-4 of the first radio frequency switch circuit unit 12. Under the action of the control logic circuit unit 11, the fourth pin SW1-4 of the first radio frequency switch circuit unit 12 is connected to the second pin SW1-2 of the first radio frequency switch circuit unit 12, and the third pin SW1-3 of the first radio frequency switch circuit unit 12 is connected to the first pin SW1-1 of the first radio frequency switch circuit unit 12. The output signal of the first power amplifier unit 23 passes through the first radio frequency switch circuit unit 12 and is output from the second pin SW1-2 of the first radio frequency switch circuit unit 12 to the second antenna terminal ANT1.

[0068] Working mode 3:

[0069] The first frequency band low noise amplifier unit 14 works and is input from the first antenna terminal ANT0. The second signal switching terminal Tuner1 is connected to the second antenna terminal ANT1.

[0070] The 2G received radio frequency signal is input from the first antenna terminal ANT0 to the first pin SW1-1 of the first radio frequency switch circuit unit 12. Under the action of the control logic circuit unit 11, the first pin SW1-1 of the first radio frequency switch circuit unit 12 is connected to the fifth pin SW1-5 of the first radio frequency switch circuit unit 12. Therefore, the received radio frequency signal is output from the first radio frequency switch circuit unit 12 to the input end of the first band low-noise amplifier unit 14. After being amplified by the first band low-noise amplifier unit 14, it is output to the sixth pin SW2-6 of the second radio frequency switch circuit unit 13. Under the action of the control logic circuit unit 11, the sixth pin SW2-6 of the second radio frequency switch circuit unit 13 is connected to the first pin SW2-1 of the second radio frequency switch circuit unit 13, and then sent to the first end of the first band filter unit 41; after being filtered by the first band filter unit 41, it is sent out from the first band signal section 2G TRX. At the same time, under the action of the control logic circuit unit 11, the ninth pin SW1-9 of the first radio frequency switch circuit unit 12 is connected to the second pin SW1-2 of the first radio frequency switch circuit unit 12.

[0071] Operating mode 4:

[0072] The first band low-noise amplifier unit 14 operates, and is input from the second antenna terminal ANT1. The first signal switching terminal Tuner0 is connected to the first antenna terminal ANT0.

[0073] The 2G received radio frequency signal is input from the second antenna terminal ANT1 port to the second pin SW1-2 of the first radio frequency switch circuit unit 12. Under the action of the control logic circuit unit 11, the second pin SW1-2 of the first radio frequency switch circuit unit 12 is connected to the fifth pin SW1-5 of the first radio frequency switch circuit unit 12. Therefore, the received signal is output from the first radio frequency switch circuit unit 12 to the input end of the first band low-noise amplifier unit 14. After being amplified by the first band low-noise amplifier unit 14, it is output to the sixth pin SW2-6 of the second radio frequency switch circuit unit 13. Under the action of the control logic circuit unit 11, the sixth pin SW2-6 of the second radio frequency switch circuit unit 13 is connected to the first pin SW2-1 of the second radio frequency switch circuit unit 13, and then sent to the first band filter unit 41; after being filtered by the first band filter unit 41, it is sent out from the first band signal terminal 2G TRX. At the same time, under the action of the control logic circuit unit 11, the third pin SW1-3 of the first radio frequency switch circuit unit 12 is connected to the first pin SW1-1 of the first radio frequency switch circuit unit 12.

[0074] Operating mode 5:

[0075] The second power amplifier unit 33 operates and outputs to the first antenna terminal ANT0. The second signal switching terminal Tuner1 is connected to the second antenna terminal ANT1.

[0076] The 5G transmission signal is input from the second frequency band signal terminal 5G TRX to the second frequency band filter unit 42. After being filtered by the second frequency band filter unit 42, it is output from the second frequency band filter unit 42 to the second pin SW2-2 of the second radio frequency switch circuit unit 13. Under the action of the control logic circuit unit 11, the second pin SW2-2 of the second radio frequency switch circuit unit 13 is connected to the third pin SW2-3 of the second radio frequency switch circuit unit 13. Therefore, the transmission signal is output from the second radio frequency switch circuit unit 13 to the input matching of the second power amplifier unit 33, and after impedance matching, it enters the second power amplifier unit 33. At the same time, the second bias and temperature compensation circuit unit 31 outputs a bias signal under the control of the control logic circuit unit 11, and the second power amplifier unit 33 operates. The input signal is amplified and impedance-matched by the second power amplifier unit 33 and then output to the eighth pin SW1-8 of the first radio frequency switch circuit unit 12. Under the action of the control logic circuit unit 11, the eighth pin SW1-8 of the first radio frequency switch circuit unit 12 is connected to the first pin SW1-1 of the first radio frequency switch circuit unit 12, and the ninth pin SW1-9 of the first radio frequency switch circuit unit 12 is connected to the second pin SW1-2 of the first radio frequency switch circuit unit 12. The output signal of the second power amplifier unit 33 passes through the first radio frequency switch circuit unit 12 and is output from the first pin SW1-1 of the first radio frequency switch circuit unit 12 to the first antenna terminal ANT0.

[0077] Operating mode 6:

[0078] The second power amplifier unit 33 operates and outputs to the second antenna terminal ANT1. The first signal switching terminal Tuner0 is connected to the first antenna terminal ANT0.

[0079] The 5G transmission signal is input from the second - band signal terminal 5G TRX to the second - band filter unit 42. After being filtered by the second - band filter unit 42, it is output from the second - band filter unit 42 to the second pin SW2 - 2 of the second RF switch circuit unit 13. Under the action of the control logic circuit unit 11, the second pin SW2 - 2 of the second RF switch circuit unit 13 is connected to the third pin SW2 - 3 of the second RF switch circuit unit 13. Therefore, the transmission signal is output from the second RF switch circuit unit 13 to the input matching of the second power amplifier unit 33. After impedance matching, it enters the second power amplifier unit 33. At the same time, the second bias and temperature compensation circuit unit 31 outputs a bias signal under the control of the control logic circuit unit 11, and the second power amplifier unit 33 operates. The input signal is amplified and impedance - matched by the second power amplifier unit 33 and then output to the eighth pin SW1 - 8 of the first RF switch circuit unit 12. Under the action of the control logic circuit unit 11, the eighth pin SW1 - 8 of the first RF switch circuit unit 12 is connected to the second pin SW1 - 2 of the first RF switch circuit unit 12, and the third pin SW1 - 3 of the first RF switch circuit unit 12 is connected to the first pin SW1 - 1 of the first RF switch circuit unit 12. The output signal of the second power amplifier unit 33 passes through the first RF switch circuit unit 12 and is output from the second pin SW1 - 2 of the first RF switch circuit unit 12 to the second antenna terminal ANT1.

[0080] Operating mode 7:

[0081] The second - band low - noise amplifier unit 15 operates and is input from the first antenna terminal ANT0. The second signal switching terminal Tuner1 is connected to the second antenna terminal ANT1.

[0082] The 5G received signal is input from the first antenna terminal ANT0 to the first pin SW1-1 of the first radio frequency switch circuit unit 12. Under the action of the control logic circuit unit 11, the first pin SW1-1 of the first radio frequency switch circuit unit 12 is connected to the seventh pin SW1-7 of the first radio frequency switch circuit unit 12. Therefore, the received signal is output from the first radio frequency switch circuit unit 12 to the input end of the second-band low-noise amplifier unit 15. After being amplified by the second-band low-noise amplifier unit 15, it is output to the fourth pin SW2-4 of the second radio frequency switch circuit unit 13. Under the action of the control logic circuit unit 11, the fourth pin SW2-4 of the second radio frequency switch circuit unit 13 is connected to the second pin SW2-2 of the second radio frequency switch circuit unit 13, and then sent to the second-band filter unit 42; after being filtered by the second-band filter unit 42, it is sent out from the second-band signal terminal 5G TRX. At the same time, under the action of the control logic circuit unit 11, the ninth pin SW1-9 of the first radio frequency switch circuit unit 12 is connected to the second pin SW1-2 of the first radio frequency switch circuit unit 12.

[0083] Operating mode 8:

[0084] The second-band low-noise amplifier unit 15 works, and is input from the second antenna terminal ANT1, and the first signal switching terminal Tuner0 is connected to the first antenna terminal ANT0.

[0085] The 5G received signal is input from the second antenna terminal ANT1 to the second pin SW1-2 of the first radio frequency switch circuit unit 12. Under the action of the control logic circuit unit 11, the second pin SW1-2 of the first radio frequency switch circuit unit 12 is connected to the seventh pin SW1-7 of the first radio frequency switch circuit unit 12. Therefore, the received signal is output from the first radio frequency switch circuit unit 12 to the input end of the second-band low-noise amplifier unit 15. After being amplified by the second-band low-noise amplifier unit 15, it is output to the fourth pin SW2-4 of the second radio frequency switch circuit unit 13. Under the action of the control logic circuit unit 11, the fourth pin SW2-4 of the second radio frequency switch circuit unit 13 is connected to the second pin SW2-2 of the second radio frequency switch circuit unit 13, and then sent to the second-band filter unit 42; after being filtered by the second-band filter unit 42, it is sent out from the second-band signal terminal 5G TRX. At the same time, under the action of the control logic circuit unit 11, the third pin SW1-3 of the first radio frequency switch circuit unit 12 is connected to the first pin SW1-1 of the first radio frequency switch circuit unit 12.

[0086] Operating mode 9:

[0087] The first - band signal terminal 2G TRX is bypassed and input / output through the first antenna terminal ANT0. The second signal switching terminal Tuner1 is connected to the second antenna terminal ANT1.

[0088] The 2G transmit signal is input from the first - band signal terminal 2GTRX to the first - band filter unit 41. After being filtered by the first - band filter unit 41, it is output from the first - band filter unit 41 to the first pin SW2 - 1 of the second RF switch circuit unit 13. Under the action of the control logic circuit unit 11, the first pin SW2 - 1 of the second RF switch circuit unit 13 is connected to the fifth pin SW2 - 5 of the second RF switch circuit unit 13, and then output to the sixth pin SW1 - 6 of the first RF switch circuit unit 12. Under the action of the control logic circuit unit 11, the sixth pin SW1 - 6 of the first RF switch circuit unit 12 is connected to the first pin SW1 - 1 of the first RF switch circuit unit 12, and the ninth pin SW1 - 9 of the first RF switch circuit unit 12 is connected to the second pin SW1 - 2 of the first RF switch circuit unit 12. The 2G transmit output signal passes through the first RF switch circuit unit 12 and is output from the first pin SW1 - 1 of the first RF switch circuit unit 12 to the first antenna terminal ANT0.

[0089] The 2G receive signal is input from the first antenna terminal ANT0 to the first pin SW1 - 1 of the first RF switch circuit unit 12. Under the action of the control logic circuit unit 11, the first pin SW1 - 1 of the first RF switch circuit unit 12 is connected to the sixth pin SW1 - 6 of the first RF switch circuit unit 12, and then output to the fifth pin SW2 - 5 of the second RF switch circuit unit 13. Under the action of the control logic circuit unit 11, the fifth pin SW2 - 5 of the second RF switch circuit unit 13 is connected to the first pin SW2 - 1 of the second RF switch circuit unit 13 and then sent to the first - band filter unit 41. After being filtered by the first - band filter unit 41, it is sent out from the first - band signal terminal 2GTRX.

[0090] Operating mode 10:

[0091] The first - band signal terminal 2G TRX is bypassed and input / output through the second antenna terminal ANT1. The first signal switching terminal Tuner0 is connected to the first antenna terminal ANT0.

[0092] The 2G transmission signal is input from the first frequency band signal terminal 2GTRX to the first frequency band filter unit 41. After being filtered by the first frequency band filter unit 41, it is output from the first frequency band filter unit 41 to the first pin SW2-1 of the second RF switch circuit unit 13. Under the action of the control logic circuit unit 11, the first pin SW2-1 of the second RF switch circuit unit 13 is connected to the fifth pin SW2-5 of the second RF switch circuit unit 13, and then output to the sixth pin SW1-6 of the first RF switch circuit unit 12. Under the action of the control logic circuit unit 11, the sixth pin SW1-6 of the first RF switch circuit unit 12 is connected to the second pin SW1-2 of the first RF switch circuit unit 12, and the third pin SW1-3 of the first RF switch circuit unit 12 is connected to the first pin SW1-1 of the first RF switch circuit unit 12. The 2G transmission output signal passes through the first RF switch circuit unit 12 and is output from the second pin SW1-2 of the first RF switch circuit unit 12 to the second antenna terminal ANT1.

[0093] The 2G reception signal is input from the second antenna terminal ANT1 to the second pin SW1-2 of the first RF switch circuit unit 12. Under the action of the control logic circuit unit 11, the second pin SW1-2 of the first RF switch circuit unit 12 is connected to the sixth pin SW1-6 of the first RF switch circuit unit 12, and then output to the fifth pin SW2-5 of the second RF switch circuit unit 13. Under the action of the control logic circuit unit 11, the fifth pin SW2-5 of the second RF switch circuit unit 13 is connected to the first pin SW2-1 of the second RF switch circuit unit 13, and then sent to the first frequency band filter unit 41; after being filtered by the first frequency band filter unit 41, it is sent out from the first frequency band signal terminal 2GTRX.

[0094] Operating mode 11:

[0095] The second frequency band signal terminal 5G TRX is bypassed, and input and output are performed by the first antenna terminal ANT0. The second signal switching terminal Tuner1 is connected to the second antenna terminal ANT1.

[0096] The 5G transmission signal is input from the second signal switching end 5GTRX to the second band filter unit 42. After being filtered by the second band filter unit 42, it is output from the second band filter unit 42 to the second pin SW2-2 of the second RF switch circuit unit 13. Under the action of the control logic circuit unit 11, the second pin SW2-2 of the second RF switch circuit unit 13 is connected to the fifth pin SW2-5 of the second RF switch circuit unit 13, and then output to the sixth pin SW1-6 of the first RF switch circuit unit 12. Under the action of the control logic circuit unit 11, the sixth pin SW1-6 of the first RF switch circuit unit 12 is connected to the first pin SW1-1 of the first RF switch circuit unit 12, and the ninth pin SW1-9 of the first RF switch circuit unit 12 is connected to the second pin SW1-2 of the first RF switch circuit unit 12. The 5G transmission output signal passes through the first RF switch circuit unit 12 and is output from the first pin SW1-1 of the first RF switch circuit unit 12 to the first antenna terminal ANT0.

[0097] The 5G reception signal is input from the first antenna terminal ANT0 port to the first pin SW1-1 of the first RF switch circuit unit 12. Under the action of the control logic circuit unit 11, the first pin SW1-1 of the first RF switch circuit unit 12 is connected to the sixth pin SW1-6 of the first RF switch circuit unit 12, and then output to the fifth pin SW2-5 of the second RF switch circuit unit 13. Under the action of the control logic circuit unit 11, the fifth pin SW2-5 of the second RF switch circuit unit 13 is connected to the second pin SW2-2 of the second RF switch circuit unit 13 and then sent to the second band filter unit 42; after being filtered by the second band filter unit 42, it is sent out from the second band signal end 5GTRX.

[0098] Operating mode 12:

[0099] The second band signal end 5G TRX is bypassed, and the input and output are through the second antenna terminal ANT1. The first signal switching end Tuner0 is connected to the first antenna terminal ANT0.

[0100] The 5G transmission signal is input from the second frequency band signal terminal 5GTRX to the second frequency band filter unit 42. After being filtered by the second frequency band filter unit 42, it is output from the second frequency band filter unit 42 to the second pin SW2-2 of the second radio frequency switch circuit unit 13. Under the action of the control logic circuit unit 11, the second pin SW2-2 of the second radio frequency switch circuit unit 13 is connected to the fifth pin SW2-5 of the second radio frequency switch circuit unit 13, and then output to the sixth pin SW1-6 of the first radio frequency switch circuit unit 12. Under the action of the control logic circuit unit 11, the sixth pin SW1-6 of the first radio frequency switch circuit unit 12 is connected to the second pin SW1-2 of the first radio frequency switch circuit unit 12, and the third pin SW1-3 of the first radio frequency switch circuit unit 12 is connected to the first pin SW1-1 of the first radio frequency switch circuit unit 12. The 5G transmission output signal passes through the first radio frequency switch circuit unit 12 and is output from the second pin SW1-2 of the first radio frequency switch circuit unit 12 to the second antenna terminal ANT1.

[0101] The 5G reception signal is input from the second antenna terminal ANT1 port to the second pin SW1-2 of the first radio frequency switch circuit unit 12. Under the action of the control logic circuit unit 11, the second pin SW1-2 of the first radio frequency switch circuit unit 12 is connected to the sixth pin SW1-6 of the first radio frequency switch circuit unit 12, and then output to the fifth pin SW2-5 of the second radio frequency switch circuit unit 13. Under the action of the control logic circuit unit 11, the fifth pin SW2-5 of the second radio frequency switch circuit unit 13 is connected to the second pin SW2-2 of the second radio frequency switch circuit unit 13 and then sent to the second frequency band filter unit 42; after being filtered by the second frequency band filter unit 42, it is sent out from the second frequency band signal terminal 5GTRX.

[0102] Compared with the prior art, the radio frequency front-end module proposed by the present invention can achieve efficient coordination of the dual-frequency transmission and reception circuits under a compact structure. At the same time, through the integrated filter and bypass function design, the power control process of the radio frequency front-end module is simplified, and the radiation and energy consumption are reduced, effectively improving the reliability and service life of the radio frequency front-end module.

[0103] Embodiment 2

[0104] The embodiment of the present invention also provides a radio frequency chip, which includes the radio frequency front-end module 100 as described in the above embodiment and can achieve the same technical effects. Refer to the description in the above embodiment, and details are not described herein again.

[0105] It should be noted that in this text, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including such element.

[0106] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiments of the present invention. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can still make many equivalent changes in form without departing from the purpose of the present invention and the scope protected by the claims, and all of them fall within the protection scope of the present invention.

Claims

1. A radio frequency front-end module, characterized in that, The radio frequency front-end module includes: a substrate, and a first chip, a second chip, a third chip, and a fourth chip fixed to the substrate; A first end of the first chip is connected to a first antenna terminal, a second end of the first chip is connected to a second antenna terminal, a third end of the first chip is connected to a first signal switching terminal, a fourth end of the first chip is connected to a second signal switching terminal, a fifth end of the first chip is connected to an input end of the second chip, a sixth end of the first chip is connected to an input end of the third chip, a seventh end of the first chip is connected to an output end of the second chip, an eighth end of the first chip is connected to an output end of the third chip, a ninth end of the first chip is connected to a first end of the fourth chip, and a tenth end of the first chip is connected to a second end of the fourth chip; the first chip is configured to input / output a first-band radio frequency signal or input / output a second-band radio frequency signal and perform signal amplification processing on the first-band radio frequency signal and the second-band radio frequency signal; The second chip is configured to perform signal amplification processing on the first-band radio frequency signal; The third chip is configured to perform signal amplification processing on the second-band radio frequency signal; A third end of the fourth chip is connected to a first-band signal terminal, a fourth end of the fourth chip is connected to a second-band signal terminal, and the fourth chip is configured to input / output the first-band radio frequency signal or input / output the second-band radio frequency signal and perform filtering processing on the first-band radio frequency signal and the second-band radio frequency signal.

2. The RF front-end module according to claim 1, wherein The first chip includes a control logic circuit unit, a first radio frequency switch circuit unit, a second radio frequency switch circuit unit, a first-band low-noise amplifier unit, and a second-band low-noise amplifier unit; The control logic circuit unit is configured to receive an external control signal and control the first radio frequency switch circuit unit and the second radio frequency switch circuit unit according to the external control signal; A first pin of the first radio frequency switch circuit unit serves as the first end of the first chip, a second pin of the first radio frequency switch circuit unit serves as the second end of the first chip, a third pin of the first radio frequency switch circuit unit serves as the third end of the first chip, a fourth pin of the first radio frequency switch circuit unit serves as the seventh end of the first chip, a fifth pin of the first radio frequency switch circuit unit is connected to an input end of the first-band low-noise amplifier unit, a sixth pin of the first radio frequency switch circuit unit is connected to a fifth pin of the second radio frequency switch circuit unit, a seventh pin of the first radio frequency switch circuit unit is connected to an input end of the second-band low-noise amplifier unit, an eighth pin of the first radio frequency switch circuit unit serves as the eighth end of the first chip, and a ninth pin of the first radio frequency switch circuit unit serves as the fourth end of the first chip; The first pin of the second radio frequency switch circuit unit serves as the ninth terminal of the first chip, the second pin of the second radio frequency switch circuit unit serves as the tenth terminal of the first chip, the third pin of the second radio frequency switch circuit unit serves as the sixth terminal of the first chip, the fourth pin of the second radio frequency switch circuit unit is connected to the output terminal of the second band low-noise amplifier unit, the sixth pin of the second radio frequency switch circuit unit is connected to the output terminal of the first band low-noise amplifier unit, and the seventh pin of the second radio frequency switch circuit unit serves as the fifth terminal of the first chip; The first band low-noise amplifier unit is used to amplify the first band radio frequency signal; The second band low-noise amplifier unit is used to amplify the second band radio frequency signal.

3. The RF front-end module according to claim 1, wherein, The second chip includes a first bias and temperature compensation circuit unit, a first input matching circuit unit, a first power amplifier unit, and a first output matching circuit unit; The first bias and temperature compensation circuit unit is used to provide a bias voltage and temperature compensation for the first power amplifier unit; The input terminal of the first input matching circuit unit serves as the input terminal of the second chip, the output terminal of the first input matching circuit unit is connected to the input terminal of the first power amplifier unit, the output terminal of the first power amplifier unit is connected to the output terminal of the first output matching circuit unit, and the output terminal of the first output matching circuit unit serves as the output terminal of the second chip.

4. The RF front-end module according to claim 1, wherein The third chip includes a second bias and temperature compensation circuit unit, a second input matching circuit unit, a second power amplifier unit, and a second output matching circuit unit; The second bias and temperature compensation circuit unit is used to provide a bias voltage and temperature compensation for the second power amplifier unit; The input terminal of the second input matching circuit unit serves as the input terminal of the third chip, the output terminal of the second input matching circuit unit is connected to the input terminal of the second power amplifier unit, the output terminal of the second power amplifier unit is connected to the output terminal of the second output matching circuit unit, and the output terminal of the second output matching circuit unit serves as the output terminal of the third chip.

5. The RF front-end module according to claim 1, wherein The fourth chip includes a first band filter unit and a second band filter unit; The first terminal of the first band filter unit serves as one end of the fourth chip, and the second terminal of the first band filter unit serves as the third terminal of the fourth chip; The first terminal of the second band filter unit serves as the second end of the fourth chip, and the second terminal of the second band filter unit serves as the fourth end of the fourth chip.

6. The RF front-end module according to claim 1, wherein The frequency band of the first band radio frequency signal is the 2.4G frequency band.

7. The RF front-end module according to claim 1, wherein The frequency band of the second band radio frequency signal is the 5G frequency band.

8. A radio frequency chip, characterized in that, The radio frequency chip includes the radio frequency front-end module according to any one of claims 1-7.

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