Printed wiring board

Abstract

The invention provides a printed wiring board having high quality. A printed wiring board according to an embodiment includes: an uppermost conductor layer having an electrode on which an electronic component is mounted; a first build-up portion disposed under the uppermost conductor layer; and a third build-up portion disposed below the first build-up portion. The first laminated part has a plurality of first conductor layers and a plurality of first resin insulating layers, the first conductor layers and the first resin insulating layers are alternately laminated, and the third laminated part has a plurality of third conductor layers and a plurality of third resin insulating layers, the third conductor layers and the third resin insulating layers are alternately laminated, and the third resin insulating layers and the third resin insulating layers are alternately laminated. The first conductor layer is formed of a first seed layer formed using sputtering and a first electroplated layer formed under the first seed layer, and the third conductor layer is formed of a third seed layer formed using electroless plating and a third electroplated layer formed under the third seed layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a printed wiring board. Background Art

[0002] Patent Document 1 discloses a method for manufacturing a printed wiring board, which includes: forming an opening for forming a via hole in an interlayer resin insulating layer; and forming an alloy layer on the surface of the interlayer insulating layer having the opening for forming a via hole by sputtering.

[0003] Patent Document 1: Japanese Patent Laid-Open No. 2000-124602

[0004] Problems of Patent Document 1

[0005] Sputtering is performed in a vacuum. In the case of forming a printed wiring board including a plurality of conductor layers, it is considered that forming the seed layers of all the conductor layers by sputtering affects the productivity. It is considered that the production cost becomes high. Summary of the Invention

[0006] The printed wiring board of the present invention has: a topmost conductor layer having an electrode for mounting an electronic component; a first laminated portion disposed under the topmost conductor layer; and a third laminated portion disposed under the first laminated portion. The first laminated portion has a plurality of first conductor layers and a plurality of first resin insulating layers, which are alternately laminated, the third laminated portion has a plurality of third conductor layers and a plurality of third resin insulating layers, which are alternately laminated, the first conductor layer is formed of a first seed layer formed by sputtering and a first plating layer formed under the first seed layer, and the third conductor layer is formed of a third seed layer formed by electroless plating and a third plating layer formed under the third seed layer.

[0007] The printed wiring board according to an embodiment of the present invention has a first conductor layer and a third conductor layer. The first conductor layer includes a first seed layer formed by sputtering, and the third conductor layer includes a third seed layer formed by electroless plating. Therefore, the seed layers of all the conductor layers are not formed by sputtering. It is difficult to reduce the productivity of the printed wiring board. The embodiment can suppress the production cost. Brief Description of the Drawings

[0008] Figure 1 is a cross-sectional view schematically showing a printed wiring board according to an embodiment.

[0009] Figure 2 is an enlarged cross-sectional view schematically showing a part of a printed wiring board according to an embodiment.

[0010] Figure 3It is an enlarged cross-sectional view schematically showing a part of a printed wiring board according to an embodiment.

[0011] Figure 4 It is an enlarged cross-sectional view schematically showing a part of a printed wiring board according to an embodiment.

[0012] Figure 5 It is an enlarged cross-sectional view schematically showing a part of a printed wiring board according to an embodiment.

[0013] Reference Numeral Explanation

[0014] 2: Printed wiring board; 10: uppermost conductor layer; 12a - 12f: electrodes; 20: first stacked portion; 22: first conductor layer; 24: first resin insulating layer; 40: second stacked portion; 42: second conductor layer; 44: second resin insulating layer; 60: third stacked portion; 62: third conductor layer; 64: third resin insulating layer; 67: reinforcing material; 70: third via conductor; 90a - 90f: protrusions; 120: first seed layer; 122: first plating layer; 140: second seed layer; 142: second plating layer; 160: third seed layer; 162: third plating layer; B: void; E1: first electronic component; E2: second electronic component. Detailed Embodiment

[0015] [Printed Wiring Board 2 of the Embodiment]

[0016] Figure 1 It is a cross-sectional view showing the printed wiring board 2 according to the embodiment. Figure 2 and Figure 3 It is an enlarged cross-sectional view showing a part of the printed wiring board 2 according to the embodiment. As Figure 1 shown, the printed wiring board 2 has an upper surface 2a and a lower surface 2b on the side opposite to the upper surface 2a. The upper surface 2a has a first mounting area A1 for mounting the first electronic component E1 and a second mounting area A2 for mounting the second electronic component E2. The first mounting area A1 is located directly below the first electronic component E1. The second mounting area A2 is located directly below the second electronic component E2. Examples of the first electronic component E1 and the second electronic component E2 are electronic components such as logic ICs and memories. Examples of the logic IC are microprocessors, digital signal processors (DSPs), etc.

[0017] The printed wiring board 2 has a third stacked portion 60, a second stacked portion 40, a first stacked portion 20, the uppermost conductor layer 10, a solder resist layer 80, and projections 90a to 90f. The printed wiring board 2 does not have a core substrate. The printed wiring board 2 is an asymmetric substrate. The first stacked portion 20 is disposed below the uppermost conductor layer 10. The first stacked portion 20 is disposed directly below the uppermost conductor layer 10. The second stacked portion 40 is disposed below the first stacked portion 20. The third stacked portion 60 is disposed below the second stacked portion 40. The solder resist layer 80 is disposed on the uppermost conductor layer 10 and the first stacked portion 20. The projections 90a to 90f are formed in openings 82 penetrating the solder resist layer 80 and on the solder resist layer 80. The first electronic component E1 and the second electronic component E2 are mounted on the printed wiring board 2 via the projections 90a to 90f. In the embodiment, the second stacked portion 40 can be deleted. In this case, the printed wiring board is formed by the third stacked portion 60, the first stacked portion 20 on the third stacked portion 60, the uppermost conductor layer 10 on the first stacked portion 20, the first stacked portion 20, the solder resist layer 80 on the uppermost conductor layer 10, and the projections 90a to 90f.

[0018] The uppermost conductor layer 10 includes electrodes 12a to 12f for mounting the electronic components E1, E2. The electrodes 12a to 12c are electrically connected to the first electronic component E1. The electrodes 12d to 12f are electrically connected to the second electronic component E2. The uppermost conductor layer 10 is mainly formed of copper. The projections 90a to 90f are formed on the respective electrodes 12a to 12f. The projections 90a to 90f are formed by soldering or plating. The first electronic component E1 and the second electronic component E2 are mounted on the projections 90a to 90f. The first electronic component E1 and the second electronic component E2 are mounted on the electrodes 12a to 12f via the projections 90a to 90f.

[0019] The third stacked portion 60 has a plurality of third conductor layers 62, a plurality of third resin insulating layers 64, and a plurality of third via conductors 70. The third conductor layers 62 and the third resin insulating layers 64 are alternately stacked. The third via conductors 70 are formed in third openings 66 penetrating the respective third resin insulating layers 64. Adjacent third conductor layers 62 are connected by the third via conductors 70. In Figure 1 this case, the number of the third conductor layers 62 and the number of the third resin insulating layers 64 are 2. The number of the third conductor layers 62 and the number of the third resin insulating layers 64 may also be 3 or more.

[0020] The third conductor layer 62 is mainly formed of copper. The third conductor layer 62 is formed of a third seed layer 160 and a third plating layer 162 under the third seed layer 160. The third seed layer 160 is formed by electroless plating. An example of electroless plating is electroless copper plating. The third conductor layer 62 includes an upper third conductor layer 62a and a lower third conductor layer 62b. The upper third conductor layer 62a and the lower third conductor layer 62b sandwich a third resin insulating layer 64. The upper third conductor layer 62a is closer to the uppermost conductor layer 10 than the lower third conductor layer 62b. The upper third conductor layer 62a has a pad 63a. The lower third conductor layer 62b has a pad 63b.

[0021] The third resin insulating layer 64 is formed using a thermosetting resin. An example of the thermosetting resin is an epoxy resin. The third resin insulating layer 64 may also include inorganic particles such as silica. The third resin insulating layer 64 includes an upper third resin insulating layer 64a and a lower third resin insulating layer 64b. The lower third resin insulating layer 64b is the lowermost resin insulating layer. The third resin insulating layer 64 includes a reinforcing material 67 made of fibers. An example of the reinforcing material 67 made of fibers is a glass cloth or the like.

[0022] As Figure 1 and Figure 2 shown, a third via conductor 70 is formed within a third opening 66. Figure 2 is Figure 1 an enlarged view of the portion shown as II in

[0023] Figure 2Shows a third opening 66 that exposes two third conductor layers 62 in the third stacked portion 60 and one third conductor layer 62 (62a) within the two third conductor layers 62, and a third via conductor 70 (70b) formed within the one third opening 66. Figure 2 The third opening 66 in Figure 2 penetrates through a third resin insulating layer 64 (64b) and reaches the third conductor layer 62a. Figure 3 Is Figure 2 An enlarged view of a part of. Figure 3 Shows a connection portion CT between the third via conductor 70b and the third conductor layer 62a. Via the connection portion CT, the third conductor layer 62 exposed through the third opening 66 and the third via conductor 70 filling the third opening 66 are connected. In Figure 2 And Figure 3 As a representative example of the third via conductor 70, the lower third via conductor 70b is depicted, and as representative examples of the third conductor layer 62, the upper third conductor layer 62a and the lower third conductor layer 62b are depicted. As Figure 2 And Figure 3 Shown, the third conductor layer 62 and the third via conductor 70 have a void B. The void B exists in at least one of a first portion, a second portion, and a third portion. The first portion is within a seed layer formed of an electroless plating layer. An example of the seed layer formed of an electroless plating layer is the third seed layer 160. The second portion is a boundary portion between the seed layer formed of an electroless plating layer and the electroplated layer. An example of the second portion is the boundary portion between the third seed layer 160 and the third electroplated layer 162. The second portion can include a second portion within the conductor layer and a second portion within the via conductor. The second portion within the conductor layer is formed at the interface between the electroplated layer forming the conductor layer and the seed layer formed of the electroless plating layer constituting the conductor layer. The interface between the electroplated layer and the seed layer formed of the electroless plating layer within one conductor layer is an example of the second portion within the conductor layer. An example of the second portion within the conductor layer is the interface between the third electroplated layer 162 forming the third conductor layer 62 and the third seed layer 160 forming the third conductor layer 62. The second portion within the via conductor is formed at the interface between the electroplated layer forming the via conductor and the seed layer formed of the electroless plating layer constituting the via conductor. The interface between the electroplated layer and the seed layer formed of the electroless plating layer within one via conductor layer is an example of the second portion within the via conductor layer. An example of the second portion within the via conductor layer is the interface between the third electroplated layer 162 forming the third via conductor 70 and the third seed layer 160 forming the third via conductor 70. The third portion includes the connection portion CT between the conductor layer and the via conductor including the seed layer formed of an electroless plating layer. The connection portion CT is as Figure 2 And Figure 3As shown. The third part includes the interface between the conductor layer exposed through the opening (the opening for the via conductor) and the via conductor formed within the opening (the opening for the via conductor). The third part includes the boundary portion between the pad included in the conductor layer and the via conductor including the seed layer formed of the electroless plating layer. The third part includes the boundary portion between the pad included in the conductor layer and the seed layer formed of the electroless plating layer that forms the via conductor. The boundary portion between the third seed layer 160 that forms the third via conductor 70 and the pad 63a is an example of the third part. There is a void B in the first part. In this case, it is preferable that there is no void B in the second part and the third part. Or, there is a void B in the second part. In this case, it is preferable that there is no void B in the first part and the third part. Or, there is a void B in the third part. In this case, it is preferable that there is no void B in the first part and the second part. Or, there is a void B in the first part and the second part. In this case, it is preferable that there is no void B in the third part. Or, there is a void B in the first part and the third part. In this case, it is preferable that there is no void B in the second part. Or, there is a void B in the second part and the third part. In this case, it is preferable that there is no void B in the first part. Or, there is a void B in the first part, the second part, and the third part.

[0024] Preferably, the upper third conductor layer 62a, the upper third via conductor 70a, the lower third conductor layer 62b, and the lower third via conductor 70b have the void B.

[0025] As Figure 1 As shown, the second stacked portion 40 has a plurality of second conductor layers 42, a plurality of second resin insulating layers 44, and a plurality of second via conductors 50. The second conductor layers 42 and the second resin insulating layers 44 are alternately stacked. The second via conductors 50 are formed within second openings 46 that penetrate through the respective second resin insulating layers 44. Adjacent second conductor layers 42 are connected by the second via conductors 50. In Figure 1 , the number of the second conductor layers 42 and the number of the second resin insulating layers 44 are 2. The number of the second conductor layers 42 and the number of the second resin insulating layers 44 may also be 3 or more.

[0026] The second conductor layer 42 is mainly formed of copper. The second conductor layer 42 is formed of a second seed layer 140 and a second electroplated layer 142 under the second seed layer 140. The second seed layer 140 is formed by electroless plating. The second conductor layer 42 includes an upper second conductor layer 42a and a lower second conductor layer 42b. The upper second conductor layer 42a has a pad 43a. The lower second conductor layer 42b has a pad 43b. The lower second conductor layer 42b can also serve as the lowermost second conductor layer within the second stacked portion 40.

[0027] The second resin insulating layer 44 is formed of a thermosetting resin. Examples of the thermosetting resin are epoxy resins. The second resin insulating layer 44 may also contain inorganic particles such as silica. The second resin insulating layer 44 includes an upper second resin insulating layer 44a and a lower second resin insulating layer 44b. The second resin insulating layer 44 does not include a reinforcing material made of fibers. The lower second resin insulating layer 44b can also serve as the lowermost second resin insulating layer within the second stacked portion 40.

[0028] The second via conductor 50 is formed within the second opening 46. The second via conductor 50 includes an upper second via conductor 50a and a lower second via conductor 50b. The lower second via conductor 50b connects the upper second conductor layer 42a and the lower second conductor layer 42b. The upper second via conductor 50a connects the upper second conductor layer 42a and the first conductor layer 22 (the lower first conductor layer 22b) within the first stacked portion 20. The second via conductor 50 is formed of a second seed layer 140 and a second plating layer 142 under the second seed layer 140. The second seed layer 140 forming the second via conductor 50 and the second seed layer 140 forming the second conductor layer 42 are common. The second seed layer 140 forming the second via conductor 50 and the second seed layer 140 forming the second conductor layer 42 are formed simultaneously. The second plating layer 142 forming the second via conductor 50 and the second plating layer 142 forming the second conductor layer 42 are common. The second plating layer 142 forming the second via conductor 50 and the second plating layer 142 forming the second conductor layer 42 are formed simultaneously.

[0029] The second conductor layer 42 has the same void B as the third conductor layer 62. The second conductor layer 42 has a void B at the same position as the third conductor layer 62. The second via conductor 50 has the same void B as the third via conductor 70. The second via conductor 50 has a void B at the same position as the third via conductor 70.

[0030] The first stacked portion 20 has a plurality of first conductor layers 22, a plurality of first resin insulating layers 24, and a plurality of first via conductors 30. The first conductor layers 22 and the first resin insulating layers 24 are alternately stacked. The first via conductors 30 are formed within first openings 26 that penetrate through each of the first resin insulating layers 24. Adjacent first conductor layers 22 are connected by the first via conductors 30. In Figure 1 this case, the number of first conductor layers 22 and the number of first resin insulating layers 24 are 2. The number of first conductor layers 22 and the number of first resin insulating layers 24 may also be 3 or more.

[0031] The first conductor layer 22 is mainly formed of copper. The first conductor layer 22 is formed of a first seed layer 120 and a first plating layer 122 under the first seed layer 120. The first seed layer 120 is formed by sputtering. The first conductor layer 22 includes an upper first conductor layer 22a and a lower first conductor layer 22b. The upper first conductor layer 22a has a pad 23a and a connection wiring 25a. The lower first conductor layer 22b has a pad 23b and a connection wiring 25b.

[0032] The first resin insulating layer 24 is formed using a thermosetting resin. Examples of the thermosetting resin are epoxy resins. The first resin insulating layer 24 may also contain inorganic particles such as silica. The first resin insulating layer 24 includes an upper first resin insulating layer 24a and a lower first resin insulating layer 24b. The upper first resin insulating layer 24a is the uppermost resin insulating layer in contact with the uppermost conductor layer 10. The first resin insulating layer 24 does not contain a reinforcing material made of fibers.

[0033] The first via conductor 30 is formed in the first opening 26. The first via conductor 30 includes an upper first via conductor 30a and a lower first via conductor 30b. The lower first via conductor 30b connects the upper first conductor layer 22a and the lower first conductor layer 22b. The upper first via conductor 30a connects the upper first conductor layer 22a and the electrodes 12a to 12f in the uppermost conductor layer 10. The first via conductor 30 is formed of a first seed layer 120 and a first plating layer 122 under the first seed layer 120. The first seed layer 120 forming the first via conductor 30 and the first seed layer 120 forming the first conductor layer 22 are common. The first seed layer 120 forming the first via conductor 30 and the first seed layer 120 forming the first conductor layer 22 are formed simultaneously. The first plating layer 122 forming the first via conductor 30 and the first plating layer 122 forming the first conductor layer 22 are common. The first plating layer 122 forming the first via conductor 30 and the first plating layer 122 forming the first conductor layer 22 are formed simultaneously.

[0034] The first conductor layer 22 and the first via conductor 30 do not have voids. The first conductor layer 22 is formed of a first seed layer 120 and a first electroplated layer 122 under the first seed layer 120. The first seed layer 120 is formed by sputtering, and the first electroplated layer 122 is formed by electroplating. There are no voids at the boundary between the first seed layer (the first layer) 120 forming the first conductor layer 22 and the first electroplated layer (the second layer) 122 forming the first conductor layer 22. The first layer and the second layer are in contact. There are no voids within the first seed layer 120 formed by sputtering. There are no voids at the boundary between the first via conductor 30 and the pad 23a. There are no voids at the boundary between the first seed layer 120 forming the first via conductor 30 and the pad 23a. The pad 23a is one of the conductor circuits forming the first conductor layer 22. The first opening 26 penetrates the first resin insulating layer 24 and reaches the pad 23a. There are no voids at the boundary between the first seed layer 120 forming the first via conductor 30 and the uppermost conductor layer 10. There are no voids at the boundary between the first seed layer 120 forming the first via conductor 30 and the electrodes 12a to 12f. The first opening 26 penetrates the uppermost resin insulating layer 24a and reaches the uppermost conductor layer 10 including the electrodes 12a to 12f. The first via conductor 30 fills the first opening 26. There are no voids at the boundary between the first seed layer (the third layer) 120 forming the first via conductor 30 and the first electroplated layer (the fourth layer) 122 forming the first via conductor 30. The third layer and the fourth layer are in contact.

[0035] The first stacked portion 20 has a plurality of first conductor layers 22. Several of the plurality of first conductor layers 22 have connection wirings 25a, 25b. More than half of the plurality of first conductor layers 22 can have connection wirings 25a, 25b. For example, the number of first conductor layers 22 having connection wirings 25a, 25b is 3 or more and 7 or less. As Figure 1 shown, all of the first conductor layers 22 may also have connection wirings 25a, 25b. Data is transmitted from the first electronic component E1 to the second electronic component E2 via the connection wirings 25a, 25b. The connection wirings 25a, 25b are part of the path for sending data from the first electronic component E1 to the second electronic component E2. The path includes the first via conductor 30 in addition to the connection wirings 25a, 25b. Since the connection wirings 25a, 25b and the first via conductor 30 forming the path do not contain void B, the path can transmit high-speed data. In addition, when data is transmitted via the path, the printed wiring board 2 of the embodiment can reduce transmission loss.

[0036] In an embodiment, the first seed layer 120 of the first conductor layer 22 having the connection wirings 25a and 25b is formed by sputtering. The second seed layer 140 of the second conductor layer 42 not having the connection wirings is formed by electroless plating. The third seed layer 160 of the third conductor layer 62 not having the connection wirings is formed by electroless plating.

[0037] The first stacked portion 20 has connection wirings including a seed layer formed by sputtering and a resin insulating layer not including a reinforcing material made of fibers. The second stacked portion 40 has a conductor layer including a seed layer formed by electroless plating and a resin insulating layer not including a reinforcing material made of fibers. The second stacked portion 40 does not have connection wirings. The third stacked portion 60 has a conductor layer including a seed layer formed by electroless plating and a resin insulating layer including a reinforcing material made of fibers. The third stacked portion 60 does not have connection wirings.

[0038] The thickness of the third resin insulating layer 64 is greater than the thickness of the second resin insulating layer 44. The thickness of the second resin insulating layer 44 is greater than the thickness of the first resin insulating layer 24. The thickness of the third resin insulating layer 64 is, for example, 90 μm or more and 110 μm or less. The thickness of the second resin insulating layer 44 is, for example, 20 μm or more and 25 μm or less. The thickness of the first resin insulating layer 24 is, for example, 8 μm or more and 12 μm or less. The thickness of the third resin insulating layer 64 is substantially the same as the distance between the third conductor layer 62 sandwiching one third resin insulating layer 64. The thickness of the second resin insulating layer 44 is substantially the same as the distance between the second conductor layer 42 sandwiching one second resin insulating layer 44. The thickness of the first resin insulating layer 24 is substantially the same as the distance between the first conductor layer 22 sandwiching one first resin insulating layer 24.

[0039] The thickness of the third conductor layer 62 is greater than the thickness of the second conductor layer 42. The thickness of the second conductor layer 42 is greater than the thickness of the first conductor layer 22. The thickness of the third conductor layer 62 is, for example, 10 μm or more and 30 μm or less. The thickness of the second conductor layer 42 is, for example, 13 μm or more and 17 μm or less. The thickness of the first conductor layer 22 is, for example, 3 μm or more and 7 μm or less. The thickness of the third conductor layer 62 is measured using the third conductor layer 62 sandwiched by the third resin insulating layer 64. The thickness of the second conductor layer 42 is measured using the second conductor layer 42 sandwiched by the second resin insulating layer 44. The thickness of the first conductor layer 22 is measured using the first conductor layer 22 sandwiched by the first resin insulating layer 24.

[0040] The thickness of the printed wiring board 2 is 0.5 mm or more and 0.7 mm or less. The length of the short side of the printed wiring board 2 is 70 mm or more, and the length of the long side is 250 mm or less.

[0041] The seed layer for forming the conductor layer with connection wirings is formed by sputtering. The seed layer for forming the conductor layer without connection wirings is formed by electroless plating. The seed layer for the conductor layer with connection wirings is a sputtered seed layer, and the seed layer for the conductor layer without connection wirings is an electroless-plated seed layer. An example of the seed layer formed by electroless plating (electroless-plated seed layer) is a seed layer formed by electroless copper plating.

[0042] For example, a seed layer in contact with a resin insulating layer without a reinforcing material made of fibers is formed by sputtering. The seed layer formed by sputtering (sputtered seed layer) preferably contains copper and aluminum. The sputtered seed layer can contain copper, aluminum, and silicon. For example, a seed layer in contact with a resin insulating layer having a reinforcing material made of fibers is formed by electroless plating. An example of electroless plating is electroless copper plating. For example, the seed layer in contact with the resin insulating layer without a reinforcing material made of fibers is a sputtered seed layer, and the seed layer in contact with the resin insulating layer having a reinforcing material made of fibers is an electroless-plated seed layer.

[0043] It is preferable that voids exist in the electroless-plated seed layer. The conductor layer containing the electroless-plated seed layer (electroless-plated conductor layer) preferably has voids at the boundary portion between the electroless-plated seed layer for forming the electroless-plated conductor layer and the electroplated layer for forming the electroless-plated conductor layer. The via conductor containing the electroless-plated seed layer (electroless-plated via conductor) preferably has voids at the boundary portion between the electroless-plated seed layer for forming the electroless-plated via conductor and the electroplated layer for forming the electroless-plated via conductor. It is preferable that voids exist at the boundary portion between the electroless-plated seed layer of the electroless-plated via conductor and the pad. As Figure 4 shown, the boundary portion between the electroless-plated seed layer 302 and the electroplated layer 304 in the electroless-plated conductor layer 300 is the first boundary portion 501. The boundary portion between the electroless-plated seed layer 302 and the electroplated layer 304 in the electroless-plated via conductor 310 is the first boundary portion 501. The boundary portion between the electroless-plated seed layer 302 of the electroless-plated via conductor 310 and the pad 320 is the second boundary portion 502.

[0044] The first boundary portion 501 is included in the second portion. The first boundary portion 501 can include the second portion in the conductor layer and the second portion in the via conductor. An example of the second portion in the conductor layer is the second portion in the third conductor layer. An example of the second portion in the via conductor is the second portion in the third via conductor. The conductor layer having the second portion in the conductor layer contains the electroless-plated seed layer. The via conductor having the second portion in the via conductor contains the electroless-plated seed layer. The second boundary portion 502 is included in the third portion. The via conductor forming the second boundary portion 502 contains the electroless-plated seed layer.

[0045] Preferably, there are no voids in the sputtered seed layer. The conductor layer including the sputtered seed layer (sputtered conductor layer) preferably has no voids at the boundary portion between the sputtered seed layer forming the sputtered conductor layer and the electroplated layer forming the sputtered conductor layer. The via conductor including the sputtered seed layer (sputtered via conductor) preferably has no voids at the boundary portion between the sputtered seed layer forming the sputtered via conductor and the electroplated layer forming the sputtered via conductor. Preferably, there are no voids at the boundary portion between the sputtered seed layer of the sputtered via conductor and the pad. Preferably, there are no voids at the boundary portion between the sputtered seed layer of the sputtered via conductor and the electrode. As Figure 5 shown, the boundary portion between the sputtered seed layer 402 and the electroplated layer 404 in the sputtered conductor layer 400 is the third boundary portion 503. The boundary portion between the sputtered seed layer 402 and the electroplated layer 404 in the sputtered via conductor 410 is the third boundary portion 503. The boundary portion between the sputtered seed layer 402 of the sputtered via conductor 410 and the pad 420 is the fourth boundary portion 504. The boundary portion between the sputtered seed layer 402 of the sputtered via conductor 410 and the electrodes 12a to 12f is the fourth boundary portion 504.

[0046] The printed wiring board 2 of the embodiment is formed of a lowermost stacked portion having a lowermost conductor layer, an uppermost stacked portion formed on the lowermost stacked portion, and an uppermost conductor layer formed on the uppermost stacked portion. The conductor layer forming the lowermost stacked portion includes an electroless plating seed layer and does not include connection wirings. The conductor layer forming the uppermost stacked portion includes a sputtered seed layer and includes connection wirings. The resin insulating layer forming the lowermost stacked portion includes a reinforcing material made of fibers, and the resin insulating layer forming the uppermost stacked portion does not include a reinforcing material made of fibers. An example of the uppermost stacked portion is the first stacked portion 20, and an example of the lowermost stacked portion is the third stacked portion 60.

[0047] [Manufacturing Method of Printed Wiring Board 2 of the Embodiment]

[0048] The uppermost conductor layer 10 is formed on the support plate. A first stacked portion 20 is formed on the support plate and the uppermost conductor layer 10. The first seed layer 120 of the first conductor layer 22 is formed by sputtering. There are no voids in the first conductor layer 22 and the first via conductor 30. A second stacked portion 40 is formed on the first stacked portion 20. The second seed layer 140 of the second conductor layer 42 is formed by electroless plating. When the second seed layer 140 is formed by electroless plating, for example, gas (such as hydrogen gas) generated during the electroless plating process enters the substrate midway. After the second seed layer 140 is formed, heat is applied to the substrate midway. By adjusting the heating conditions, void B is formed in at least one of the first portion, the second portion, and the third portion within the second stacked portion 40. A third stacked portion 60 is formed on the second stacked portion 40. The third seed layer 160 of the third conductor layer 62 is formed by electroless plating. The third seed layer 160 is formed by the same method as the second seed layer 140. Void B is formed in at least one of the first portion, the second portion, and the third portion within the third stacked portion 60. The support plate is removed. The uppermost resin insulating layer 24a belongs to the first resin insulating layer 24 and is located directly below the uppermost conductor layer 10. The uppermost resin insulating layer 24a is in contact with the uppermost conductor layer 10. The substrate midway is arranged with the uppermost conductor layer 10 and the uppermost resin insulating layer 24a facing upward. A solder resist layer 80 and bumps 90a to 90f are formed on the uppermost conductor layer 10 and the uppermost resin insulating layer 24a. The printed wiring board 2 is obtained. An example of electroplating is electroplating copper, and an example of the electroplated layer is an electroplated copper layer. An example of electroless plating is electroless copper plating.

[0049] In the embodiment, the seed layers of all the conductor layers are not formed by sputtering. Therefore, even if the production process includes sputtering, the embodiment can improve the productivity. The embodiment can suppress the production cost.

[0050] The principle of electroless plating is different from that of sputtering. Therefore, it is difficult to make the adhesion (the first adhesion) between the electroless plating seed layer and the electroplated layer on the electroless plating seed layer the same as the adhesion (the second adhesion) between the sputtered seed layer and the electroplated layer on the sputtered seed layer. It is difficult to make the adhesion (the third adhesion) between the pad and the electroless plating seed layer on the pad the same as the adhesion (the fourth adhesion) between the pad and the sputtered seed layer on the pad. When using a printed wiring board, the printed wiring board is subjected to multiple stresses. If the second adhesion is lower than the first adhesion, stress is likely to concentrate on the boundary between the sputtered seed layer and the electroplated layer. Or, stress is likely to concentrate on the sputtered seed layer. If the fourth adhesion is lower than the third adhesion, stress is likely to concentrate on the boundary between the pad and the sputtered seed layer. Stress is likely to concentrate on the boundary between the electrode and the sputtered seed layer. Therefore, due to stress, the following defects are likely to occur. For example, peeling occurs between the sputtered seed layer and the electroplated layer. Or, peeling occurs between the pad and the sputtered seed layer. Or, the connection resistance between the via conductor including the pad and the sputtered seed layer becomes high. Or, the connection resistance between the electrode and the via conductor including the sputtered seed layer becomes high. Or, cracks are generated in the sputtered seed layer.

[0051] The electroless plating seed layer is formed in a liquid. Therefore, even if the surface to be plated has irregularities, the electroless plating seed layer easily follows the irregularities. In addition, even if the surface to be plated has a large recess, the electroless plating layer easily forms within the large recess. In contrast, in sputtering, particles fly out from the target. Moreover, these particles tend to travel straight. Therefore, it is considered that if the surface to be sputtered has irregularities, the deviation in the thickness of the sputtered seed layer is large. In addition, when the surface to be sputtered has a large recess, it is difficult for the sputtered seed layer to grow on the large recess wall and bottom. A sputtered seed layer is formed on the surface to be sputtered. However, in the embodiment, the conductor layer including the seed layer (e.g., the third seed layer 160) formed by electroless plating has a void B at at least one of the first portion and the second portion. The via conductor including the seed layer formed by electroless plating has a void B at at least one of the first portion, the second portion, and the third portion. In contrast, the conductor layer including the sputtered seed layer (e.g., the first seed layer 120) does not have a void B at both the first portion and the second portion. The via conductor including the sputtered seed layer does not have a void B at any of the first portion, the second portion, and the third portion. Therefore, substantially equal stress easily acts on the first boundary portion 501 and the third boundary portion 503. Substantially the same stress easily acts on the second boundary portion 502 and the fourth boundary portion 504. Substantially equal stress easily acts on the first boundary portion 501, the second boundary portion 502, the third boundary portion 503, and the fourth boundary portion 504. Even if the printed wiring board 2 of the embodiment is stressed multiple times, it is difficult for peeling to occur between the seed layer and the electroplated layer. It is difficult for peeling to occur between the pad and the via conductor. It is difficult for peeling to occur between the electrode and the via conductor. Cracks are not easily generated within the seed layer. The connection resistance between the pad and the via conductor is stable over a long period. The connection resistance between the electrode and the via conductor is stable over a long period. There is provided a printed wiring board 2 having high connection reliability.

[0052] The resin insulating layer 64 forming the third stacked portion 60 has a reinforcing material 67 made of fibers, and the resin insulating layer 24 forming the first stacked portion 20 does not have a reinforcing material 67 made of fibers. The printed wiring board 2 of the embodiment is an asymmetric wiring board. Therefore, the printed wiring board 2 of the embodiment is likely to have a large warpage. Electronic components E1 and E2 are mounted on the first stacked portion 20. When the electronic components E1 and E2 are mounted on the first stacked portion 20, a semiconductor device is formed by the printed wiring board 2 of the embodiment and the electronic components E1 and E2. When the semiconductor device is subjected to a thermal cycle, the third stacked portion 60 is likely to have a larger warpage than the first stacked portion 20. Since the third stacked portion 60 is farther from the electronic components E1 and E2 than the first stacked portion 20, it is considered that the third stacked portion 60 is likely to have a larger warpage. However, at least one of the conductor layer (third conductor layer) 62 and the via conductor (third via conductor) 70 in the third stacked portion 60 has a void B at at least one of the first portion, the second portion, and the third portion. The stress is relieved by the void B. Therefore, even when the semiconductor device is subjected to a thermal cycle, the embodiment can provide a printed wiring board 2 having high connection reliability. If the conductor layer (first conductor layer) 22 and the via conductor (first via conductor) 30 in the first stacked portion 20 have a void B, the first stacked portion 20 is close to the electronic components E1 and E2, so the void B in the first stacked portion 20 expands due to the heat emitted from the electronic components E1 and E2. In this case, the connection reliability of the wiring in the first stacked portion 20 is reduced. The wiring in the first stacked portion 20 includes the first conductor layer 22 and the first via conductor 30. Since the conductor layer 22 and the via conductor 30 in the first stacked portion 20 forming the printed wiring board 2 of the embodiment do not have a void B, such an adverse situation is not likely to occur.

[0053] [Another example 1 of the printed wiring board 2 of the embodiment]

[0054] In another example 1, the second conductor layer 42 and the second via conductor 50 do not contain voids. The second seed layer 140 is formed by sputtering. There is no void B at the boundary portion between the second seed layer 140 formed by sputtering and the second plating layer 142 formed by electroplating. The second conductor layer 42 is formed by the second seed layer 140 formed by sputtering and the second plating layer 142 formed by electroplating. The second via conductor 50 is formed by the second seed layer 140 formed by sputtering and the second plating layer 142 formed by electroplating. There is no void in the second seed layer 140 formed by sputtering. There is no void at the boundary portion between the second via conductor 50b and the pad 43a.

[0055] Up and down are based on Figure 1and used. The conductor layer formed by the seed layer and the electroplated layer on the seed layer is the same conductor layer as the conductor layer formed by the seed layer and the electroplated layer under the seed layer. The via conductor formed by the seed layer and the electroplated layer on the seed layer is the same via conductor as the via conductor formed by the seed layer and the electroplated layer under the seed layer.

Claims

1. A printed wiring board comprising: an uppermost conductor layer having electrodes for mounting electronic components; A first build-up portion disposed below the uppermost conductor layer; and A third buildup portion is disposed below the first buildup portion, in, The first build-up portion includes a plurality of first conductor layers and a plurality of first resin insulating layers, wherein the first conductor layers and the first resin insulating layers are alternately stacked. The third build-up portion includes a plurality of third conductor layers and a plurality of third resin insulating layers, wherein the third conductor layers and the third resin insulating layers are alternately stacked. The first conductor layer is formed of a first seed layer formed by sputtering and a first electroplating layer formed under the first seed layer. The third conductor layer is formed of a third seed layer formed using chemical plating and a third electroplating layer formed under the third seed layer.

2. The printed wiring board according to claim 1, wherein The third conductor layer has a gap in the third seed layer, that is, a first portion, or in a boundary portion between the third seed layer and the third electroplating layer, that is, a second portion. The first conductor layer has no voids in the first seed layer and at a boundary portion between the first seed layer and the first plating layer.

3. The printed wiring board according to claim 2, wherein The gap exists in both the first portion and the second portion.

4. The printed wiring board according to claim 1, wherein The third conductor layer includes an upper third conductor layer and a lower third conductor layer sandwiching one of the third resin insulating layers. The third laminated portion comprises: an opening that passes through the third resin insulating layer sandwiched by the upper third conductor layer and the lower third conductor layer and reaches a pad included in the upper third conductor layer; as well as a third via conductor formed in the opening to connect the pad to the third conductor layer on the lower side, The third via conductor is formed by the third seed layer and the third plating layer connected to the pad, and a connection portion between the pad and the third via conductor has a gap. The void exists in the third seed layer, that is, the first portion, or in the boundary portion between the third seed layer and the third electroplating layer, that is, the second portion, or in the boundary portion between the third seed layer and the pad, that is, the third portion. The first conductor layer has no voids within the first seed layer and at a boundary portion between the first seed layer and the first plating layer.

5. The printed wiring board according to claim 4, wherein The gap exists in both the second portion and the third portion, or in all of the first portion, the second portion, and the third portion.

6. The printed wiring board according to claim 1, wherein The printed wiring board further includes a second build-up portion disposed between the first build-up portion and the third build-up portion. The second build-up portion includes a plurality of second conductor layers and a plurality of second resin insulating layers, wherein the second conductor layers and the second resin insulating layers are alternately stacked. The second conductor layer is formed of a second seed layer formed using chemical plating and a second electroplating layer formed under the second seed layer, The second conductor layer has a gap in the second seed layer or at a boundary portion between the second seed layer and the second plating layer.

7. The printed wiring board according to claim 1, wherein The third resin insulating layer includes a reinforcing material, The first resin insulation layer does not include the reinforcement material.

8. The printed wiring board according to claim 1, wherein The thickness of the third resin insulating layer is greater than the thickness of the first resin insulating layer, The thickness of the third conductor layer is greater than that of the first conductor layer.

9. The printed wiring board according to claim 1, wherein The first resin insulating layer includes an uppermost resin insulating layer in contact with the uppermost conductive layer, The third resin insulation layer includes a lowermost resin insulation layer.

10. The printed wiring board according to claim 1, wherein The printed wiring board further includes a bump formed on the electrode.

11. The printed wiring board according to claim 10, wherein The protrusions are formed by welding or plating.

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