Semiconductor structure, forming method thereof and memory system
By stacking dielectric layers on the semiconductor layer and etching to form trench and isolation structures, the active structure is formed using epitaxial growth process in the trench, which solves the problems of poor trench uniformity and easy structure bending and deformation during the vertical channel transistor formation process, and improves process controllability and structural reliability.
Patent Information
- Application Number
- CN202311779648.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-20
AI Technical Summary
During the formation of vertical channel transistors arranged in arrays, there are problems such as poor trench uniformity, easy bending and deforming of the semiconductor structure, and easy void formation between the isolation structure and the semiconductor layer, resulting in increased process difficulty and reduced structural reliability.
By stacking dielectric layers on the semiconductor layer and forming alternately arranged trench and isolation structures using etching techniques, the semiconductor layer is exposed to form an active structure in the trench. The material selection and etching conditions of the dielectric layer are designed to enable the semiconductor layer to act as an etch stop layer, improve the controllability and uniformity of the trench, and form an active structure in the trench through an epitaxial growth process.
The uniformity of the trench and the dimensional consistency of the active structure are achieved, the risk of bending deformation of the semiconductor structure is reduced, and the controllability of the subsequent process and the reliability of the semiconductor structure are improved.
Smart Images
Figure CN120187003A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure, a method for forming the same, and a memory system. Background Art
[0002] Compared with planar transistors, vertical-channel transistors occupy less area, so the integration degree of a memory array can be improved. Taking a Dynamic Random Access Memory (DRAM) as an example, vertical-channel transistors arranged in an array can be formed first, and then a capacitive structure extending in the vertical direction can be formed on each vertical-channel transistor to form a DRAM memory array.
[0003] However, there are still many problems in the formation process of vertical-channel transistors arranged in an array. Summary of the Invention
[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for forming the same, and a memory system to solve at least one problem existing in the prior art.
[0005] To achieve the above object, the technical solutions of the embodiments of the present disclosure are implemented as follows:
[0006] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, the forming method including:
[0007] Providing a substrate, the substrate including a semiconductor layer and a dielectric layer stacked in a first direction; the first direction is the thickness direction of the substrate;
[0008] Etching the dielectric layer to form trenches and isolation structures arranged alternately in a second direction; the trenches expose the semiconductor layer; the second direction is perpendicular to the first direction;
[0009] Forming an active structure in the trenches.
[0010] In an optional embodiment, the etching the dielectric layer includes:
[0011] Etching the dielectric layer along the first direction and extending into the semiconductor layer; the bottom surface of the trench is lower than the top surface of the semiconductor layer.
[0012] In an optional embodiment, the size of the dielectric layer in the first direction ranges from 250 nanometers to 350 nanometers.
[0013] In an optional embodiment, the distance between the bottom surface of the trench and the top surface of the semiconductor layer in the first direction ranges from 5 nanometers to 20 nanometers.
[0014] In an alternative embodiment, the material of the dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride; the semiconductor layer includes a substrate.
[0015] In an alternative embodiment, forming the active structure in the trench includes:
[0016] Performing an epitaxial growth process to form an epitaxial layer in the trench.
[0017] In an alternative embodiment, forming the active structure in the trench further includes:
[0018] Doping the epitaxial layer to form the active structure; the active structure includes a first electrode structure, a channel structure, and a second electrode structure arranged along the first direction.
[0019] In an alternative embodiment, forming the active structure in the trench further includes:
[0020] During the process of performing the epitaxial growth process, the reaction gas of the epitaxial growth process at least includes a silicon source gas and a doping gas to form a doped epitaxial layer in the trench, and the doped epitaxial layer constitutes the active structure.
[0021] In an alternative embodiment, the material of the active structure includes silicon and / or silicon germanide.
[0022] In an alternative embodiment, the forming method further includes:
[0023] Before etching the dielectric layer, forming a patterned mask layer on the dielectric layer;
[0024] Etching the dielectric layer further includes:
[0025] Etching the dielectric layer using the patterned mask layer as a mask.
[0026] In an alternative embodiment, the forming method further includes:
[0027] Removing the semiconductor layer and a part of the active structure from the sides of the semiconductor layer opposite to each other along the first direction and away from the isolation structure, and exposing the isolation structure and the first end of the two ends of the active structure opposite to each other along the first direction;
[0028] Forming a bit line structure on the sides of the first electrode structure opposite to each other along the first direction and away from the second electrode structure; the bit line structure is connected to the first end.
[0029] In an alternative embodiment, the forming method further includes:
[0030] A capacitive contact structure and a capacitive structure are formed on one side of the second electrode structure away from the first electrode structure among the two opposite sides along the first direction; one end of the capacitive contact structure is connected to the second end of the two opposite ends of the active structure along the first direction; the other end of the capacitive contact structure is connected to the capacitive structure; the size of the second end of the active structure in the second direction is larger than the size of the first end of the active structure in the second direction.
[0031] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, which includes:
[0032] An active structure that extends along a first direction and is arranged along a second direction; the first direction is perpendicular to the second direction;
[0033] A bit line structure that is connected to the first end of the two opposite ends of the active structure along the first direction;
[0034] A capacitive structure and a capacitive contact structure, one end of the capacitive contact structure is connected to the second end of the two opposite ends of the active structure along the first direction; the other end of the capacitive contact structure is connected to the capacitive structure; the size of the second end of the active structure in the second direction is larger than the size of the first end of the active structure in the second direction.
[0035] In an optional implementation manner, the active structure includes a first electrode structure, a channel structure, and a second electrode structure arranged along the first direction; the first electrode structure is connected to the bit line structure, and the second electrode structure is connected to the capacitive contact structure.
[0036] In a third aspect, an embodiment of the present disclosure provides a memory system, which includes:
[0037] At least one semiconductor structure according to any one of the above embodiments;
[0038] A controller, coupled to the semiconductor structure and configured to control the semiconductor structure.
[0039] In the technical solution provided by the present disclosure, in order to form an active structure of a vertical channel transistor, a dielectric layer located on a semiconductor layer may be etched first to form a trench and an isolation structure, and then an active structure may be formed in the trench by using an epitaxial growth process. On the one hand, during the process of etching the dielectric layer, the semiconductor layer can serve as an etch stop layer, thereby improving the controllability and uniformity of the trench, making the dimensions of the active structure formed in the trench substantially the same in the first direction and in the second direction, so as to further reduce the process difficulty of forming a bit line structure from the back side subsequently; on the other hand, due to the relatively large Young's modulus of the material of the dielectric layer, the isolation structure is not easily deformed, thereby reducing the risk of bending deformation of the semiconductor structure after the trench is etched; on the other hand, in the finally formed semiconductor structure, the size of the second end of the active structure connected to the capacitor contact structure in the second direction is larger than the size of the first end of the active structure connected to the bit line structure in the second direction, and there can be a larger contact area and a smaller contact resistance between the active structure and the capacitor contact structure in the semiconductor structure, thereby improving the control ability of the vertical channel transistor for the capacitor structure and improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 Structural schematic of the formation process of a semiconductor structure provided for some examples Figure 1 ;
[0041] Figure 2 Structural schematic of the formation process of a semiconductor structure provided for some examples Figure 2 ;
[0042] Figure 3 Structural schematic of the formation process of a semiconductor structure provided for some examples Figure 3 ;
[0043] Figure 4 Structural schematic of the formation process of a semiconductor structure provided for some examples Figure 4 ;
[0044] Figure 5 Flow schematic of the method for forming a semiconductor structure provided by an embodiment of the present disclosure;
[0045] Figure 6 Structural schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 1 ;
[0046] Figure 7 Structural schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 2 ;
[0047] Figure 8Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 3 ;
[0048] Figure 9 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 4 ;
[0049] Figure 10 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 5 ;
[0050] Figure 11 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 6 ;
[0051] Figure 12 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 7 ;
[0052] Figure 13 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 8 ;
[0053] Figure 14 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 9 ;
[0054] Figure 15 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 10 ;
[0055] Figure 16 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 10 One;
[0056] Figure 17 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 10 Two;
[0057] Figure 18 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 10 Three;
[0058] Figure 19 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 10 Four;
[0059] Figure 20 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 10 Five;
[0060] Figure 21 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 10 Six;
[0061] Figure 22 Structural schematic of the formation process of the semiconductor structure provided by the embodiments of the present disclosure Figure 10 Seven;
[0062] Figure 23 Schematic of the memory system provided by the embodiments of the present disclosure Figure 1 ;
[0063] Figure 24 Schematic of the memory system provided by the embodiments of the present disclosure Figure 2 . Detailed implementation manners
[0064] Hereinafter, the exemplary embodiments disclosed by the present disclosure will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific implementation manners set forth herein. On the contrary, these implementation manners are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.
[0065] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known to the art are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.
[0066] In the drawings, the same reference numerals denote the same elements throughout.
[0067] It should be understood that the spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship between one element or feature shown in the drawings and other elements or features. It should be understood that, in addition to the orientation shown in the drawings, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawing is flipped, then the element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" the other elements or features. Therefore, the exemplary terms "under" and "below" may include both the upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial description terms used herein are correspondingly interpreted.
[0068] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.
[0069] In some embodiments, vertical channel transistors can be utilized to improve the integration density of a memory array. Taking DRAM as an example, vertical channel transistors arranged in an array can be formed first, and then a capacitive structure extending in the vertical direction can be formed on each vertical channel transistor to form a DRAM memory array. When forming the vertical channel transistors arranged in an array, an active structure of the vertical channel transistors can be formed by etching a semiconductor substrate, and the active structure extends in the thickness direction of the semiconductor substrate.
[0070] Figures 1 to 4 A schematic structural view of a semiconductor structure formation process provided for some examples, wherein, Figure 2 is Figure 1 a top view. With reference to Figures 1 to 3 , a mask pattern 102 can be formed on a semiconductor substrate 101 through a pattern transfer process, and then the semiconductor substrate 101 can be etched using the mask pattern 102 as a mask to form a plurality of semiconductor walls 103 and trenches 104 located between adjacent semiconductor walls 103 in the semiconductor substrate 101, and the semiconductor walls 103 can serve as the formation regions of the active structures of the vertical channel transistors. With reference to Figure 3 and Figure 4 , a dielectric material can be filled in the trenches 104 through a deposition process to form an isolation structure 105.
[0071] In the above example, as Figure 3As shown, during the process of etching the semiconductor substrate 101 to form the trenches 104, since there is no etch stop layer in the semiconductor substrate 101, it may lead to poor uniformity of the trenches 104 formed in the semiconductor substrate 101. Specifically, the depths of the multiple trenches 104 in the Z direction are different, and the dimensions of the bottoms of the trenches 104 in the X direction are also different. On the one hand, it will affect the uniformity of the finally formed vertical channel transistors. On the other hand, it will also increase the difficulty of exposing the active structure by back thinning in the subsequent process. In addition, due to the small Young's modulus of the material of the semiconductor substrate 101 (such as single crystal silicon), the semiconductor wall 103 is prone to deformation, which may lead to further deterioration of the uniformity of the trenches 104 and further increase the difficulty of the subsequent process. Further, during the process of filling the trenches 104 with a dielectric material by a deposition process, for the trenches 104 with larger dimensions in the Z direction, voids are likely to form between the isolation structures 105 formed therein and the semiconductor wall 103, and this situation is also not conducive to the execution of the subsequent process.
[0072] Therefore, how to optimize the formation process of vertical channel transistors has become an urgent problem to be solved at present. In this regard, the present disclosure provides the following embodiments.
[0073] The present disclosure provides a method for forming a semiconductor structure. Figure 5 As shown in the flowchart of the method for forming a semiconductor structure provided by an embodiment of the present disclosure, Figure 5 As shown, the method for forming a semiconductor structure includes the following steps:
[0074] Step S10: Provide a substrate, the substrate including a semiconductor layer and a dielectric layer stacked and arranged in a first direction; the first direction is the thickness direction of the substrate;
[0075] Step S20: Etch the dielectric layer to form trenches and isolation structures alternately arranged in a second direction; the trenches expose the semiconductor layer; the second direction is perpendicular to the first direction;
[0076] Step S30: Form an active structure in the trenches.
[0077] Figures 6 to 22 As shown in the structural schematic diagram of the semiconductor structure formation process provided by an embodiment of the present disclosure, hereinafter, the method for forming a semiconductor structure provided by the present disclosure will be described in detail with reference to Figures 5 to 22 In the embodiments of the present disclosure, the first direction may be the Z direction, and the second direction may be the X direction.
[0078] In some embodiments, with reference to
[0079] In some embodiments, with reference to Figure 6, perform step S10 to provide a substrate 200, where the substrate 200 includes a semiconductor layer 201 and a dielectric layer 202 stacked in a first direction.
[0080] In some specific examples, the semiconductor layer 201 can be a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.) or a compound semiconductor material substrate (such as a germanium-silicon substrate, etc.).
[0081] In some specific examples, the material of the dielectric layer 202 can be at least one of dielectric materials such as silicon oxide, silicon nitride, or silicon oxynitride.
[0082] In some specific examples, the size of the dielectric layer 202 in the first direction ranges from 250 nanometers to 350 nanometers.
[0083] In some embodiments, with reference to Figures 7 to 15 , before performing step S20, the method for forming a semiconductor structure further includes: performing a Self-Aligned Double Patterning (SADP) process to form a first patterned mask layer 206 on the dielectric layer 202.
[0084] In some embodiments, with reference to Figure 7 , the method for forming a semiconductor structure includes: sequentially forming a first mask layer 203 and a second mask layer 204 on the dielectric layer 202, where the second mask layer 204 includes a first sub-mask layer 2041 and a second sub-mask layer 2042.
[0085] In some specific examples, the material of the first mask layer 203 includes but is not limited to polysilicon; the material of the first sub-mask layer 2041 includes but is not limited to amorphous carbon; the material of the second sub-mask layer 2042 includes but is not limited to silicon oxynitride.
[0086] In some specific examples, the first mask layer 203 and the second mask layer 204 can be formed by a deposition process.
[0087] In the embodiments of the present disclosure, the deposition processes include but are not limited to Chemical Vapor Deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD). The etching processes include but are not limited to Plasma Etching (PE), Sputtering Etching (SE), Ion Beam Etching (IBE), and Reactive Ion Etching (RIE).
[0088] In some embodiments, with reference to Figures 7 to 9 , Figure 9 being Figure 8 a top view of, the method for forming a semiconductor structure includes: etching the second mask layer 204 to form a second patterned mask layer 205. With reference to Figure 9 , the second patterned mask layer 205 includes a plurality of strip patterns extending in a third direction and arranged in a second direction, where the third direction may be the Y direction.
[0089] In some embodiments, with reference to Figure 10 and Figure 11 , Figure 11 being Figure 10 a top view of, the method for forming a semiconductor structure includes: forming an oxide layer 301 covering the side surfaces and the top surface of the first mask layer 203 and the second patterned mask layer 205.
[0090] In some specific examples, the oxide layer 301 can be formed by an atomic layer deposition process, and the material of the oxide layer 301 includes but is not limited to silicon oxide.
[0091] In some embodiments, with reference to Figure 12 and Figure 13 , Figure 13 being Figure 12 a top view of, the method for forming a semiconductor structure includes: removing the oxide layer 301 covering the top surface of the first mask layer 203 and the top surface of the second patterned mask layer 205, and removing the second patterned mask layer 205 to form a plurality of sidewall structures 302. As shown in Figure 13As shown, the projection of the sidewall structure 302 on the semiconductor layer 201 in the first direction includes a plurality of annular patterns arranged in the second direction.
[0092] In some embodiments, referring to Figure 14 and Figure 15 , Figure 15 is Figure 14 a top view of Figure 15 . A method for forming a semiconductor structure includes: etching a first mask layer 203 using the sidewall structure 302 as a mask to transfer the annular pattern of the sidewall structure 302 into the first mask layer 203, and then removing opposite ends of the annular pattern in the third direction to form a first patterned mask layer 206. As shown in
[0093] In some embodiments, referring to Figure 16 and Figure 17 , Figure 17 is Figure 16 a top view of
[0094] Performing step S20, etching the dielectric layer 202 using the first patterned mask layer 206 as a mask to form trenches 402 and isolation structures 401 arranged alternately in the second direction, and the trenches 402 expose the semiconductor layer 201.
[0095] In some specific examples, the distance between the bottom surface of the trench 402 and the top surface of the semiconductor layer 201 in the first direction ranges from 5 nanometers to 20 nanometers.
[0096] In some specific examples, the material of the dielectric layer 202 includes silicon oxide, and the material of the semiconductor layer 201 includes single crystal silicon. During the process of etching the dielectric layer 202, etching conditions with a higher etching rate for the dielectric layer 202 and a lower etching rate for the semiconductor layer 201 can be used, that is, a higher etching selectivity between the dielectric layer 202 and the semiconductor layer 201 can be achieved. Thus, the semiconductor layer 201 can be used as an etching stop layer, and the bottom of the etched trench 402 stops in the semiconductor layer 201, thereby improving the controllability and uniformity of the trench 402, such that the dimensions of the plurality of trenches 402 in the first direction and in the second direction are substantially the same. In addition, due to the relatively large Young's modulus of the material of the dielectric layer 202, the isolation structure 401 is not easily deformed, thereby reducing the risk of bending deformation of the semiconductor structure after forming the trench 402 by etching the dielectric layer 202.
[0097] In some embodiments, with reference to Figure 16 and Figures 18 to 20 , step S30 is performed to form an active structure 405 in the trench 402.
[0098] In some embodiments, with reference to Figure 16 and Figure 18 and Figure 19 , Figure 19 is a top view of Figure 18 . The specific process of performing step S30 may include: performing an epitaxial growth process to form an epitaxial layer 404 in the trench 402.
[0099] In some specific examples, the reaction gas for the epitaxial growth process includes at least a silicon source gas and / or a germanium source gas. The reaction gas can decompose on the surface of the semiconductor layer 201 exposed by the trench 402 to form an initial epitaxial layer. The initial epitaxial layer can continue to grow until the trench 402 is completely filled to form an epitaxial layer 404 in the trench 402. The material of the epitaxial layer 404 may include silicon, germanium, or silicon germanide.
[0100] In some embodiments, after performing the epitaxial growth process, a chemical mechanical polishing (CMP) process needs to be performed to make the top surface of the epitaxial layer 404 flush with the top surface of the isolation structure 401.
[0101] In some embodiments, with reference to Figure 20 and Figure 21 , Figure 21 is a top view of Figure 20 . The specific process of performing step S30 may include: doping the epitaxial layer 404 to form an active structure 405. The active structure 405 includes a first electrode structure 4051, a channel structure 4052, and a second electrode structure 4053 arranged along a first direction. As shown in Figure 21 , before or after doping the epitaxial layer 404, the epitaxial layer 404 and the isolation structure 401 may also be etched to form a trench 406 extending in a second direction. The trench 406 and the isolation structure 401 can divide the epitaxial layer 404 into a plurality of active structures 405 extending along the first direction and arranged in an array along the second direction and a third direction. It should be noted that, for the convenience of observing the formation position of the trench 406, the semiconductor layer 201 exposed at the bottom of the trench 406 is omitted in Figure 21 .
[0102] In some specific examples, the epitaxial layer 404 can be doped by an ion implantation process. Specifically, the two opposite ends of the epitaxial layer 404 in the first direction can be N-type doped to form a first electrode structure 4051 and a second electrode structure 4053, and the middle region of the epitaxial layer 404 in the first direction can be P-type doped to form a channel structure 4052; or, the two opposite ends of the epitaxial layer 404 in the first direction can be P-type doped to form a first electrode structure 4051 and a second electrode structure 4053, and the middle region of the epitaxial layer 404 in the first direction can be N-type doped to form a channel structure 4052.
[0103] In some other embodiments, during the epitaxial growth process, the reaction gas at least includes a silicon source gas and a doping gas to form a doped epitaxial layer in the trench 402, and the doped epitaxial layer constitutes the active structure 405. Specifically, in the first stage of the epitaxial growth process, the reaction gas can include a silicon source gas and an N-type doping gas, such as phosphine (PH3) or phosphorus trichloride (PCl3), so that an N-type doped epitaxial layer can be formed in the trench 402; in the second stage of the epitaxial growth process, the reaction gas can include a silicon source gas and a P-type doping gas, such as diborane (B2H6) or boron trichloride (BCl3), so that a P-type doped epitaxial layer can be formed on the N-type doped epitaxial layer; in the third stage of the epitaxial growth process, the reaction gas can include a silicon source gas and an N-type doping gas, so that an N-type doped epitaxial layer can be formed on the P-type doped epitaxial layer. Among them, the N-type doped epitaxial layer formed in the first stage can constitute the first electrode structure 4051, the P-type doped epitaxial layer formed in the second stage can constitute the channel structure 4052, and the N-type doped epitaxial layer formed in the third stage can constitute the second electrode structure 4053. In addition, a P-type doped epitaxial layer, an N-type doped epitaxial layer, and a P-type doped epitaxial layer can be formed in sequence to constitute the first electrode structure 4051, the channel structure 4052, and the second electrode structure 4053.
[0104] In the embodiments of the present disclosure, the dielectric layer 202 formed on the semiconductor layer 201 is first etched to form a trench 402 and an isolation structure 401, and then an epitaxial layer 404 is formed by an epitaxial growth process to fill the trench 402, and the epitaxial layer 404 is used as the formation region of the active structure 405. Thus, it is not necessary to form the isolation structure 401 by a deposition process, and the risk of forming voids between the isolation structure 401 and the semiconductor layer 201 can be effectively reduced.
[0105] In some embodiments, referring to Figure 22, The method for forming a semiconductor structure may further include: forming a capacitive contact structure 501 and a capacitive structure 502 on a side of the second electrode structure 4053 opposite to the first electrode structure 4051 in the first direction and away from the first electrode structure 4051. One end of the capacitive contact structure 501 is connected to the second electrode structure 4053, and the other end of the capacitive contact structure 501 is connected to the capacitive structure 502. Here, the capacitive structure 502 can be connected to the second electrode structure 4053 through the capacitive contact structure 501.
[0106] In some embodiments, with reference to Figure 20 and Figure 22 , The method for forming a semiconductor structure may further include: removing the semiconductor layer 201 and a part of the active structure 405 from two sides of the semiconductor layer 201 opposite to each other in the first direction and away from the isolation structure 401, and exposing the isolation structure 401 and the first electrode structure 4051 in the active structure 405; forming bit line structures 503 on two sides of the first electrode structure 4051 opposite to each other in the first direction and away from the second electrode structure 4053. The bit line structures 503 extend in the second direction and are connected to the first electrode structures 4051 in a plurality of active structures 405 arranged in the second direction.
[0107] In the embodiments of the present disclosure, with reference to Figure 16 , Figure 18 and Figure 20 , During the execution of step S20, the trench 402 formed by etching the dielectric layer 202 may have a structure with a wider top and a narrower bottom, that is, in the first direction, its dimension in the second direction increases from bottom to top. Therefore, after the execution of step S30, in the first direction, the dimension of the active structure 405 in the second direction increases from bottom to top. Refer to Figure 22 , After forming the capacitive contact structure 501, the capacitive structure 502 and the bit line structure 503, the bit line structure 503 is connected to the first end of the two ends of the active structure 405 opposite to each other in the first direction, one end of the capacitive contact structure 501 is connected to the second end of the two ends of the active structure 405 opposite to each other in the first direction, and the dimension of the second end of the active structure 405 connected to the capacitive contact structure 501 in the second direction is larger than the dimension of the first end of the active structure 405 connected to the bit line structure 503 in the second direction.
[0108] It can be understood that when forming the capacitive contact structure 501, it is necessary to first etch the dielectric layer to form a through hole exposing the top surface of the second electrode structure 4053. Since the top end of the active structure 405 has a larger dimension in the second direction, the formation of this through hole can have a larger process window, and the contact area between the capacitive contact structure 501 and the second electrode structure 4053 can be increased without changing the number of capacitive structures per unit area, thereby improving the reliability of the formed capacitive contact structure 501.
[0109] In an embodiment of the present disclosure, after performing step S20, the bottom surface of the formed isolation structure 401 is flush. The semiconductor layer 201 and a part of the active structure 405 can be removed from one side of the two opposite sides of the semiconductor layer 201 along the first direction away from the isolation structure 401 by a chemical mechanical polishing process, and the bottom surface of the isolation structure 401 is used as a polishing stop layer. In addition, since the semiconductor layer 201 can be used as an etching stop layer for the etching medium layer 202 during the execution of step S20, the bottom surfaces of the formed trenches 402 are substantially flush, and the bottom surfaces of the finally formed active structures 405 are also substantially flush. Therefore, during the execution of the chemical mechanical polishing process, the distribution of the material composition on the same polishing surface is relatively uniform, which is conducive to forming a flat polishing surface, making the bottom surface of the remaining active structure 405 flush with the bottom surface of the isolation structure 401. Thus, not only can the process difficulty of the polishing process be reduced, but also the process difficulty of forming the bit line structure 503 can be further reduced.
[0110] It should be noted that for the convenience of observation, Figure 22 other structures except the active structure 405, the capacitor contact structure 501, the capacitor structure 502, and the bit line structure 503 are omitted. It can be understood that before forming the capacitor structure 502 and the bit line structure 503, the method for forming the semiconductor structure further includes forming a word line structure. The word line structure can extend along the third direction, and the word line structure can be located on one side, two sides, three sides, or surround the channel structure 4052 in the active structures 405 arranged along the third direction. In addition, it may further include forming a gate dielectric layer located between the word line structure and the channel structure 4052. The word line structure can be used as the gate of a vertical channel transistor, and together with the active structure 405, it constitutes a vertical channel transistor. A vertical channel transistor and the connected capacitor structure 502 together constitute a DRAM memory cell.
[0111] Based on a concept similar to the above semiconductor structure, the present disclosure also provides a semiconductor structure, Figure 22 which is a schematic diagram of the semiconductor structure provided by the present disclosure. As Figure 22 shown, the semiconductor structure includes: an active structure 405, the active structure 405 extends along the first direction and is arranged along the second direction; a bit line structure 503, the bit line structure 503 is connected to the first end of the two opposite ends of the active structure 405 along the first direction; a capacitor structure 502 and a capacitor contact structure 501, one end of the capacitor contact structure 501 is connected to the second end of the two opposite ends of the active structure 405 along the first direction; the other end of the capacitor contact structure 501 is connected to the capacitor structure 502.
[0112] In the embodiments of the present disclosure, the active structure 405 has a structure that is wider at the top and narrower at the bottom, that is, the size of the second end of the active structure 405 connected to the capacitive contact structure 501 in the second direction is greater than the size of the first end of the active structure 405 connected to the bit line structure 503 in the second direction.
[0113] In some embodiments, the active structure 405 includes a first electrode structure 4051, a channel structure 4052, and a second electrode structure 4053 arranged along the first direction, wherein the first electrode structure 4051 is connected to the bit line structure 503, and the second electrode structure 4053 is connected to the capacitive contact structure 501.
[0114] In some specific examples, the material of the active structure 405 may include silicon and / or silicon germanide.
[0115] In the embodiments of the present disclosure, the active structure of the vertical channel transistor has a structure that is wider at the top and narrower at the bottom. The size of the end of the active structure connected to the capacitive structure in the second direction is greater than the size of the end of the active structure connected to the bit line structure in the second direction. Thus, compared with the active structure that is narrower at the top and wider at the bottom, when the number of memory cells per unit area remains unchanged, the active structure in the semiconductor structure provided by the embodiments of the present disclosure has a larger contact area and a smaller contact resistance with the capacitive contact structure, thereby improving the control ability of the vertical channel transistor over the capacitive structure and enhancing the reliability of the semiconductor structure.
[0116] The present disclosure also provides a memory system, which includes: at least one semiconductor structure in any of the above embodiments; a controller coupled to the semiconductor structure and configured to control the semiconductor structure.
[0117] In some specific examples, Figure 23 For a schematic diagram of the memory system, as Figure 23 shown, the memory system includes at least one memory device 601 and a controller 602. The controller 602 is coupled to the memory device 601 and configured to control the memory device 601. The semiconductor structure in any of the above embodiments can be the memory device 601 or can be part of the memory device 601.
[0118] In some other specific examples, Figure 24 For a schematic diagram of the memory system, as Figure 24 shown, the memory system 700 may include at least one buffer memory device 701, at least one non-volatile memory device 702, and a controller 703. The controller 703 may be coupled to both the buffer memory device 701 and the non-volatile memory device 702. The semiconductor structure in any of the above embodiments can be the buffer memory device 701 or can be part of the buffer memory device 701.
[0119] In a specific example, Figure 24 the memory system 700 shown may be a solid state drive (SSD), and the non-volatile memory device 702 may serve as the storage medium in the SSD. The non-volatile memory device 702 includes, but is not limited to, a NAND-type memory device. The buffer memory device 701 may serve as a memory device with a caching function in the SSD and may be used to buffer data or an address mapping table, etc., to improve the performance of the SSD.
[0120] In several method embodiments provided by the present disclosure, the disclosed methods can be arbitrarily combined without conflict to obtain new method embodiments.
[0121] In several device embodiments provided by the present disclosure, the disclosed features can be arbitrarily combined without conflict to obtain new device embodiments.
[0122] As described above, the above are only specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of the present disclosure.
Claims
1. A method for forming a semiconductor structure, characterized in that, The forming method includes: Providing a substrate, which includes a semiconductor layer and a dielectric layer stacked and arranged in a first direction; the first direction is the thickness direction of the substrate; Etching the dielectric layer to form trenches and isolation structures alternately arranged in a second direction; the trenches expose the semiconductor layer; the second direction is perpendicular to the first direction; Forming an active structure in the trenches.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The etching of the dielectric layer includes: Etching the dielectric layer along the first direction and extending into the semiconductor layer; the bottom surface of the trench is lower than the top surface of the semiconductor layer.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The size of the dielectric layer in the first direction ranges from 250 nanometers to 350 nanometers.
4. The method for forming a semiconductor structure according to claim 2, characterized in that, The spacing between the bottom surface of the trench and the top surface of the semiconductor layer in the first direction ranges from 5 nanometers to 20 nanometers.
5. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the dielectric layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride; the semiconductor layer includes a substrate.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, The forming of the active structure in the trenches includes: Performing an epitaxial growth process to form an epitaxial layer in the trenches.
7. The method for forming a semiconductor structure according to claim 6, characterized in that, The forming of the active structure in the trenches further includes: Doping the epitaxial layer to form the active structure; the active structure includes a first electrode structure, a channel structure, and a second electrode structure arranged in the first direction.
8. The method for forming a semiconductor structure according to claim 6, characterized in that, The forming of the active structure in the trenches further includes: During the epitaxial growth process, the reaction gas of the epitaxial growth process at least includes a silicon source gas and a doping gas to form a doped epitaxial layer in the trenches, and the doped epitaxial layer constitutes the active structure.
9. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the active structure includes silicon and / or silicon germanide.
10. The method for forming a semiconductor structure according to claim 1, characterized in that, The forming method further includes: Forming a patterned mask layer on the dielectric layer before etching the dielectric layer; The etching of the dielectric layer further includes: Etching the dielectric layer using the patterned mask layer as a mask.
11. The method for forming a semiconductor structure according to claim 7, characterized in that, The forming method further includes: Removing the semiconductor layer and a part of the active structure from the sides of the semiconductor layer opposite to each other in the first direction and away from the isolation structure, and exposing the isolation structure and the first end of the two ends of the active structure opposite to each other in the first direction; Forming a bit line structure on the sides of the first electrode structure opposite to each other in the first direction and away from the second electrode structure; the bit line structure is connected to the first end.
12. The method for forming a semiconductor structure according to claim 11, characterized in that, The forming method further includes: Forming a capacitor contact structure and a capacitor structure on the sides of the second electrode structure opposite to each other in the first direction and away from the first electrode structure; one end of the capacitor contact structure is connected to the second end of the two ends of the active structure opposite to each other in the first direction; the other end of the capacitor contact structure is connected to the capacitor structure; the size of the second end of the active structure in the second direction is larger than the size of the first end of the active structure in the second direction.
13. A semiconductor structure, characterized in that, Including: An active structure, which extends in a first direction and is arranged in a second direction; The first direction is perpendicular to the second direction; A bit line structure, the bit line structure being connected to a first end of two opposite ends of the active structure along the first direction; A capacitor structure and a capacitor contact structure, one end of the capacitor contact structure being connected to a second end of two opposite ends of the active structure along the first direction; the other end of the capacitor contact structure being connected to the capacitor structure; the size of the second end of the active structure in the second direction being larger than the size of the first end of the active structure in the second direction.
14. The semiconductor structure according to claim 13, characterized in that, The active structure includes a first electrode structure, a channel structure, and a second electrode structure arranged along the first direction; the first electrode structure is connected to the bit line structure, and the second electrode structure is connected to the capacitor contact structure.
15. A memory system, characterized in that, Comprising: At least one semiconductor structure according to any one of claims 13 to 14; A controller, coupled to the semiconductor structure and configured to control the semiconductor structure.