Formation method of semiconductor structure

Abstract

According to the forming method of the semiconductor structure, a provided substrate comprises a unit storage area and a logic area, a plurality of spaced stacked gate structures are formed in the unit storage area, a first gate material layer covers the stacked gate structures and the unit storage area and the logic area in the substrate, and a protection layer is formed on the first gate material layer of the logic area. In the process of etching the flat structure and the first gate material layer of the unit storage region, the protection layer protects the first gate material layer of the logic region from being etched, and the first gate material layer higher than the logic region in the unit storage region and the flat structure are removed. The top of the remaining first gate material layer of the unit storage area is flush with the top of the first gate material layer of the logic area, and in the process of etching the first gate material layers of the unit storage area and the logic area, gate structures of the unit storage area and the logic area are easy to form at the same time. Therefore, the logic region and the unit storage region are successfully integrated on the same substrate, and the yield of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Art

[0002] Non-volatile memory is a storage technology that can retain data even after power is turned off. Non-volatile memory plays an important role in modern technology and life. Its importance is reflected in the following aspects: Data persistence: Non-volatile memory ensures that data is retained even after power is turned off, preventing data loss and ensuring system reliability. High-speed read and write: Non-volatile memories such as flash memory provide fast data read and write speeds, improving device performance and response capabilities. Large-capacity storage: Modern non-volatile memories can provide huge storage capacities to meet the growing data storage needs. Low power consumption: Compared with volatile memory, non-volatile memory generally has lower power consumption, which helps to extend battery life and reduce energy consumption. Programmability: Some non-volatile memories (such as EEPROM and Flash) have programmability, allowing data modification and update, providing flexibility and customizability.

[0003] Split-gate non-volatile memory cells are known in the art, where two different portions of the channel region are controlled by two different gates (floating gate and select gate). The memory cell further includes a control gate structure above the floating gate and an erase gate above the source region. Split-gate memory cells are advantageous because the operating voltage is relatively low, which means that the on-board power supply can be smaller and more efficient. Split-gate memory cells are disadvantageous because the memory cell size is enlarged to accommodate two separate gates that are laterally shifted to control two separate portions of the channel region. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to optimize the electrical performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a unit storage area and a logic area; forming a plurality of spaced-apart stacked gate structures on the unit storage area of the substrate; forming a first gate material layer covering the stacked gate structures and the unit storage area and the logic area in the substrate; forming a protective layer on the first gate material layer in the logic area; forming a planar structure on the first gate material layer and the protective layer; performing an etching process on the planar structure and the first gate material layer in the unit storage area, during the etching process, the protective layer is used to protect the first gate material layer in the logic area, so that the tops of the remaining first gate material layer in the unit storage area and the first gate material layer in the logic area are flush; after the etching process, removing the protective layer; after removing the protective layer, etching the first gate material layer to form a gate structure on the unit storage area and the logic area of the substrate.

[0006] Optionally, the material of the protective layer includes: silicon oxide, silicon nitride or silicon oxynitride.

[0007] Optionally, in the step of forming the protective layer on the first gate material layer in the logic area, the thickness of the protective layer is 750 angstroms to 950 angstroms.

[0008] Optionally, the step of forming the protective layer on the first gate material layer in the logic area includes: forming a protective material layer on the first gate material layer in the unit storage area and the logic area; removing the protective material layer in the unit storage area, and the remaining protective material layer located in the logic area serves as the protective layer.

[0009] Optionally, a wet etching process is used to remove the protective material layer in the unit storage area.

[0010] Optionally, the etching solution used in the steps of the wet etching process includes: hydrofluoric acid solution.

[0011] Optionally, a furnace tube process is used to form the protective material layer.

[0012] Optionally, the etching process includes: performing a first etching step with the protective layer as the etching stop position, for etching the planar structure and a part of the thickness of the first gate material layer; after the first etching step, performing a second etching step to etch the remaining first gate material layer and the planar structure in the unit storage area with the protective layer as a mask.

[0013] Optionally, the step of forming a planar structure on the first gate material layer and the protective layer includes: forming a second gate material layer on the first gate material layer. In the step of forming the second gate material layer on the first gate material layer, the materials of the second gate material layer and the first gate material layer are the same; forming a planar material film on the second gate material layer, and the planar material film has a planar top surface.

[0014] Optionally, the material of the planar material film includes a bottom anti-reflection coating.

[0015] Optionally, the first etching step includes: a plurality of etching combinations performed cyclically. The etching combination includes: performing a first sub-etching step, in which the etching rate of the planar material film is greater than the etching rate of the second gate material layer in the first sub-etching step; performing a second sub-etching step, in which the etching rate of the second gate material layer is greater than the etching rate of the planar material film in the second sub-etching step.

[0016] Optionally, both the first sub-etching step and the second sub-etching step are maskless dry etching processes or both are wet etching processes; or the first sub-etching step is a maskless dry etching process and the second sub-etching step is a wet etching process; or the first sub-etching step is a wet etching process and the second sub-etching step is a maskless dry etching process.

[0017] Optionally, in the second etching step, using the protective layer as a mask, the remaining first gate material layer and the planar structure in the unit storage area are etched by a dry etching process.

[0018] Optionally, in the step of etching the remaining first gate material layer and the planar structure in the unit storage area using the protective layer as a mask, the top of the stacked gate structure is used as the etching stop position.

[0019] Optionally, in the step of forming the first gate material layer on the stacked gate structure and the unit storage area and the logic area of the substrate, the thickness of the first gate material layer is equal to the height of the stacked gate structure; in the step of performing the etching process, the planar structure in the logic area and the unit storage area, and the first gate material layer in the unit storage area that is higher than the stacked gate structure are removed.

[0020] Optionally, the protective layer is removed by a wet etching process.

[0021] Optionally, in the step of forming a plurality of phase-separated stacked gate structures on the unit storage area of the substrate, the stacked gate structures include: a floating gate structure, an inter-gate dielectric layer located on the floating gate structure, and a control gate structure located on the inter-gate dielectric layer; in the step of forming a gate structure on the unit storage area and the logic area of the substrate, the tops of the gate structures in the unit storage area and the logic area are flush.

[0022] Optionally, in the step of forming a first gate material layer covering the stacked gate structures and the unit storage area and the logic area in the substrate, the thickness of the first gate material layer is 1500 angstroms to 2000 angstroms.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0024] In the method for forming a semiconductor structure provided by the embodiment of the present invention, the substrate includes a unit storage area and a logic area, a plurality of phase-separated stacked gate structures are formed in the unit storage area, and the formed first gate material layer covers the stacked gate structures and the unit storage area and the logic area in the substrate. It is easy to occur that the top of the first gate material layer on the stacked gate structures is higher than the top of the first gate material layer in the logic area. In the embodiment of the present invention, a protective layer is formed on the first gate material layer in the logic area. During the etching process of the flat structure and the first gate material layer in the unit storage area, the protective layer protects the first gate material layer in the logic area from being etched, while the first gate material layer and the flat structure in the unit storage area that are higher than the first gate material layer in the logic area are removed, so that the top of the remaining first gate material layer in the unit storage area is flush with the top of the first gate material layer in the logic area. During the etching process of the first gate material layer with flush tops in the unit storage area and the logic area, the gate structures in the unit storage area and the logic area are etched and formed simultaneously, and it is not easy to occur that the gate structure in the logic area has been formed, but there is still a part of the first gate material layer remaining at the bottom of the gate structure in the unit storage area. In summary, the method for forming a semiconductor structure provided by the embodiment of the present invention enables the successful integration of the logic area and the unit storage area on the same substrate, and at the same time improves the yield of the semiconductor structure. Description of the Drawings

[0025] Figures 1 to 3 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;

[0026] Figures 4 to 12 Schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the invention. Detailed Embodiments

[0027] As can be seen from the background art, the currently formed semiconductor structures still have problems with poor performance. Now, the reasons for the poor device performance will be analyzed in combination with a method for forming a semiconductor structure.

[0028] Reference Figures 1 to 3 shows a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0029] As Figure 1 shown, a substrate 1 is provided, and the substrate 1 includes a unit storage area I and a logic area II; a plurality of spaced-apart stacked gate structures 2 are formed on the unit storage area I of the substrate 1.

[0030] As Figure 2 shown, a gate material layer 3 covering the stacked gate structures 2 and the unit storage area I and the logic area II of the substrate 1 is formed.

[0031] As Figure 3 shown, the gate material layer 3 is etched to form a gate structure 4 on the unit storage area I and the logic area II of the substrate 1.

[0032] In order to improve the integration of semiconductor structures, more and more semiconductor processes embed the unit storage area in the logic area. Usually, a plurality of spaced-apart stacked gate structures 2 are only formed in the unit storage area I of the substrate 1, and no stacked gate structures 2 are formed in the logic area II. Due to the stacking effect of the film layer, during the process of forming the gate material layer 3 covering the stacked gate structures 2 and the unit storage area I and the logic area II of the substrate 1, the top of the gate material layer 3 on the stacked gate structures 2 will be higher than the top of the gate material layer 3 in the logic area II. Furthermore, during the process of etching the gate material layer 3, when the gate structure 4 in the logic area II has been formed, there will still be a remaining part of the gate material layer 3 with a certain thickness at the bottom of the gate structure 4 in the unit storage area I (as shown in the circle in Figure 3 ), resulting in a low yield of the semiconductor structure.

[0033] To solve the above technical problem, in the method for forming a semiconductor structure provided by an embodiment of the present invention, the substrate includes a unit storage area and a logic area. A plurality of spaced-apart stacked gate structures are formed in the unit storage area. The formed first gate material layer covers the stacked gate structures and the unit storage area and the logic area in the substrate. It is easy to occur that the top of the first gate material layer on the stacked gate structure is higher than the top of the first gate material layer in the logic area. In the embodiment of the present invention, a protective layer is formed on the first gate material layer in the logic area. During the etching process of the flat structure and the first gate material layer in the unit storage area, the protective layer protects the first gate material layer in the logic area from being etched, while the first gate material layer and the flat structure in the unit storage area that are higher than the first gate material layer in the logic area are removed, so that the top of the remaining first gate material layer in the unit storage area is flush with the top of the first gate material layer in the logic area. During the etching process of the first gate material layer with flush tops in the unit storage area and the logic area, the gate structures in the unit storage area and the logic area are etched and formed simultaneously, and it is not easy to occur that the gate structure in the logic area has been formed, but there is still a part of the first gate material layer remaining at the bottom of the gate structure in the unit storage area. In summary, the method for forming a semiconductor structure provided by the embodiment of the present invention enables the successful integration of the logic area and the unit storage area on the same substrate, and at the same time improves the yield of the semiconductor structure.

[0034] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description will be made on the specific embodiments of the embodiments of the present invention with reference to the accompanying drawings.

[0035] Figures 4 to 12 Schematic diagrams of the structures corresponding to the steps in an embodiment of the method for forming a semiconductor structure according to an embodiment of the invention.

[0036] Reference Figure 4 , a substrate 100 is provided, and the substrate 100 includes a unit storage area I and a logic area II.

[0037] The substrate 100 provides a process operation basis for the process of forming a semiconductor structure. The semiconductor structure belongs to a non-volatile storage device. Specifically, the semiconductor structure is a split-gate memory structure.

[0038] In this embodiment, the unit storage area I and the logic area II are located on the same substrate 100, which is beneficial to improving the integration and performance of the semiconductor structure to be formed.

[0039] The unit storage area I refers to the part of the substrate 100 used for storing data, and is usually used for non-volatile memory (NVM) applications. The unit storage area I usually has a specific storage cell structure and circuit design to meet the requirements of data storage. The unit storage area I is used to form a split-gate memory structure subsequently, and each split-gate memory structure can store one or more bits of data.

[0040] Logic region II refers to the logic circuit part in the chip, which is used to implement specific functions and computing tasks. The logic region II contains various logic circuit elements, such as logic gates, registers, counters, etc., for processing and operating data. Correspondingly, an isolation structure (not marked in the figure) is formed in the substrate 100 of the logic region II to isolate different circuit elements.

[0041] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium. The substrate can also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0042] Continue to refer to Figure 4 , a plurality of spaced-apart stacked gate structures 200 are formed on the unit storage region I of the substrate 100.

[0043] The stacked gate structure 200 acts as a storage unit and functions in data read, write, and erase operations.

[0044] In this embodiment, a plurality of spaced-apart stacked gate structures 200 can be divided into a plurality of stacked gate groups 300. A low-voltage region 100A is provided between adjacent stacked gate groups 300. The low-voltage region 100A is used to form a select gate and a drain subsequently. The stacked gate group 300 includes at least two stacked gate structures 200. The region between adjacent stacked gate structures 200 in the same stacked gate group 300 is a high-voltage region 100B, and the high-voltage region 100B is used to form an erase gate structure subsequently.

[0045] It should be noted that, in order to be able to form a select gate and a drain in the low-voltage region 100A smoothly and an erase gate structure in the high-voltage region 100B smoothly subsequently, taking the extension direction perpendicular to the sidewall of the stacked gate structure 200 as the transverse direction, the transverse dimension of the low-voltage region 100A is larger than the transverse dimension of the high-voltage region 100B.

[0046] Specifically, in the step of forming a plurality of spaced-apart stacked gate structures 200 on the unit storage region I of the substrate 100, the stacked gate structure 200 includes: a floating gate structure 201, an inter-gate dielectric layer 202 located on the floating gate structure 201, and a control gate structure 203 (Control Gate, CG) located on the inter-gate dielectric layer 202.

[0047] The floating gate structure 201 is a cell structure used to store data and maintain the data state as a memory cell. By storing or not storing electrons in the floating gate structure 201, the memory cell is in the state after storing information or erasing information.

[0048] In this embodiment, the material of the floating gate structure 201 is polysilicon. The floating gate structure 201 is doped with N-type ions. The N-type ions include one or more of phosphorus, arsenic, and antimony.

[0049] The N-type ions make the write threshold voltage and the erase threshold voltage of the floating gate structure 201 differ greatly. During the use of the memory cell, the voltage fluctuation applied across the floating gate structure 201 will not affect the normal write or erase operation of the floating gate structure 201.

[0050] The control gate structure 203 is used to be electrically connected to the outside to control the longitudinal electric field of the floating gate structure 201. During the read operation, the data stored in the floating gate structure 201 is read; during the write operation, the injection or movement of the electron flow in the floating gate structure 201 is controlled to change the charge state of the floating gate structure 201; during the erase operation, the control gate structure 203 and the erase gate work together to create an erase electric field.

[0051] The control gate structure 203 is used to inject electrons into the floating gate structure 201 or pull electrons out of the floating gate structure 201 during the data writing or erasing process of the memory cell. When reading the data of the memory cell, by applying a working voltage to the control gate structure 203, the on / off state of the channel region at the bottom of the floating gate structure 201 is controlled by using the charged state of the floating gate structure 201.

[0052] In this embodiment, the material of the control gate structure 203 is polysilicon (poly).

[0053] It should be noted that the control gate structure 203 is doped with P-type ions, so that the control gate structure 203 is not easily in the depletion state, and further the control gate structure 203 is in the conductive state. The P-type ions include one or more of boron, gallium, and indium.

[0054] The inter-gate dielectric layer 202 is used to electrically isolate the floating gate structure 201 and the control gate structure 203.

[0055] In this embodiment, the material of the inter-gate dielectric layer 202 is a dielectric material. Specifically, the material of the inter-gate dielectric layer 202 includes one or both of silicon oxide and silicon nitride. In this embodiment, the inter-gate dielectric layer 202 includes a sandwich structure composed of a first silicon oxide layer 2021, a first silicon nitride layer 2022, and a second silicon oxide layer 2023 (ONO).

[0056] The semiconductor structure further includes: a floating gate dielectric layer 101 (Floating Gate oxide), located between the substrate 100 and the stacked gate structure 200, for isolating the stacked gate structure 200 and the substrate 100.

[0057] In this embodiment, the material of the floating gate dielectric layer 101 is a dielectric material, such as silicon oxide. In other embodiments, the floating gate dielectric layer may also be a stack composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0058] It should be noted that the stacked gate structure 200 further includes: a hard mask layer 204, located on top of the control gate structure 203.

[0059] The hard mask layer 204 is used as an etching mask to protect the control gate structure 203.

[0060] In this embodiment, the hard mask layer 204 includes a third silicon oxide layer 2041 and a second silicon nitride layer 2042.

[0061] Reference Figure 5 , a first gate material layer 103 is formed to cover the stacked gate structure 200 and the unit storage area I and the logic area II in the substrate 100.

[0062] The first gate material layer 103 is prepared for subsequent etching to form a gate structure.

[0063] In this embodiment, the material of the first gate material layer 103 includes polysilicon (poly).

[0064] In this embodiment, the first gate material layer 103 is formed by a furnace tube process. In other embodiments, a chemical vapor deposition process may also be used to form the first gate material layer.

[0065] It should be noted that during the furnace tube process, the process temperature should not be too high or too low. If the process temperature is too high, it may cause a change in the lattice expansion rate of the deposited first gate material layer 103, thereby resulting in instability of the first gate material layer 103 and a decrease in the thin film deposition quality. If the process temperature is too low, it will cause a decrease in the crystallinity and compactness of the formed first gate material layer 103, and also result in an overly slow deposition formation rate of the first gate material layer 103, prolonging the formation cycle of the first gate material layer 103. In this embodiment, during the furnace tube process, the process temperature is 550°C to 650°C.

[0066] It should be noted that in the step of forming the first gate material layer 103, the first gate material layer 103 should not be too thick or too thin. If the first gate material layer 103 is too thick, it will take too much process time and materials to form the first gate material layer 103, and it will also take too much process time to etch the first gate material layer 103 to form the gate structure subsequently, which is not conducive to shortening the preparation cycle of the semiconductor structure. If the first gate material layer 103 is too thin, when the top of the first gate material layer 103 is lower than the top of the stacked gate structure 200, the subsequent etching of the first gate material layer 103 cannot form the gate structure required by the process. In this embodiment, in the step of forming the first gate material layer 103 covering the stacked gate structure 200 and the unit storage area I and the logic area II in the substrate 100, the thickness of the first gate material layer 103 is 1500 angstroms to 2000 angstroms.

[0067] In this embodiment, in the step of forming the first gate material layer 103 on the stacked gate structure 200 and the unit storage area I and the logic area II of the substrate 100, the thickness of the first gate material layer 103 is equal to the height of the stacked gate structure 200, which can make the height of the gate structure formed by etching the first gate material layer 103 subsequently equal to the height of the stacked gate structure 200.

[0068] It should be noted that multiple spaced-apart stacked gate structures 200 are formed in the unit storage area I. During the formation of the first gate material layer 103, due to the stacking effect of the film layer, it is easy to occur that the top of the first gate material layer 103 on the stacked gate structure 200 is higher than the top of the first gate material layer 103 in the logic area II.

[0069] It should also be noted that in the step of forming the first gate material layer 103, since the lateral dimension of the low-pressure area 100A is large, the film layer stacking effect of the low-pressure area 100A is small, and the top of the first gate material layer 103 with a partial lateral dimension in the low-pressure area 100A is flush with the top of the stacked gate structure 200; the lateral dimension of the high-pressure area 100B is small, so the film layer stacking effect of the high-pressure area 100B is large, and the top of the first gate material layer 103 in the high-pressure area 100B is higher than the top of the stacked gate structure 200.

[0070] The method for forming the semiconductor structure further includes: after forming multiple spaced-apart stacked gate structures 200 on the unit storage area I of the substrate 100, before forming the first gate material layer 103 subsequently, an oxide layer 102 is also formed on the sidewalls and the top of the stacked gate structure 200, and on the substrate 100 of the unit storage area I and the logic area II.

[0071] The oxide layer 102 is used to play the role of electrical isolation.

[0072] In this embodiment, the oxide layer 102 is formed by chemical vapor deposition. In other embodiments, the oxide layer may also be formed by a furnace tube process.

[0073] It should be noted that in the step of forming the first gate material layer 103, since the stacked gate structure 200 is not formed in the logic region II, the first gate material layer 103 in the logic region II is formed on the relatively flat oxide layer 102.

[0074] Reference Figure 6 and Figure 7 , a protective layer 104 is formed on the first gate material layer 103 in the logic region II (as shown in Figure 7 ).

[0075] In the embodiment of the present invention, by forming the protective layer 104 on the first gate material layer 103 in the logic region II, and then forming a planar structure on the first gate material layer 103 and the protective layer 104, during the etching process of the planar structure and the first gate material layer 103 in the unit storage area I, the protective layer 104 protects the first gate material layer 103 in the logic region II from being etched, while the first gate material layer 103 in the unit storage area I is etched, so that the top of the remaining first gate material layer 103 in the unit storage area I is flush with the top of the first gate material layer 103 in the logic region II. During the subsequent etching process of the first gate material layer 103 with flush tops in the unit storage area I and the logic region II, the gate structures in the unit storage area I and the logic region II are etched and formed simultaneously, and it is not easy to have a situation where the gate structure in the logic region II has been formed, but there is still a part of the first gate material layer 103 remaining at the bottom of the gate structure in the unit storage area I, which is beneficial to improving the electrical performance of the semiconductor structure. In summary, the method for forming the semiconductor structure provided by the embodiment of the present invention enables the successful integration of the logic region and the unit storage area on the same substrate, and at the same time improves the yield of the semiconductor structure.

[0076] In this embodiment, the material of the protective layer 104 includes: silicon oxide. Silicon oxide is a dielectric material commonly used in the process, with low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and process cost of forming the protective layer 104; in addition, silicon oxide is also easy to remove, which is beneficial to reducing the difficulty of removing the protective layer 104 subsequently. In other embodiments, the material of the protective layer may also be other insulating materials such as silicon nitride and silicon oxynitride.

[0077] In this embodiment, the step of forming the protective layer 104 on the first gate material layer 103 in the logic region II includes: forming a protective material layer 105 on the first gate material layer 103 in the unit storage region I and the logic region II; removing the protective material layer 105 in the unit storage region I, and the remaining protective material layer 105 in the logic region II serves as the protective layer 104.

[0078] In this embodiment, a furnace tube process is used to form the protective material layer 105. The protective material layer 105 formed by the furnace tube process has good thickness uniformity and density, which is beneficial to ensuring the formation quality of the protective layer 104 formed by etching the protective material layer 105 subsequently.

[0079] It should be noted that during the deposition of the protective material layer 105 in the furnace tube process, the precursor used is TEOS (tetraethyl orthosilicate), and TEOS will be converted into silicon oxide at high temperature.

[0080] The method for forming the semiconductor structure further includes: after forming the protective material layer 105 on the first gate material layer 103 in the unit storage region I and the logic region II, and before removing the protective material layer 105 in the unit storage region I, forming a shielding layer 106 on the first gate material layer 103 in the logic region II, and removing the protective material layer 105 in the unit storage region I using the shielding layer 106 as a mask.

[0081] In this embodiment, the material of the shielding layer 106 includes photoresist.

[0082] In this embodiment, a wet etching process is used to remove the protective material layer 105 in the unit storage region I. The wet etching process is isotropic etching. The wet etching process has a high etching rate, simple operation, and low process cost.

[0083] It should be noted that the material of the protective material layer 105 is silicon oxide. Correspondingly, the etching solution used in the wet etching process includes hydrofluoric acid solution.

[0084] It should be noted that in the step of forming the protective layer 104 on the first gate material layer 103 in the logic region II, the protective layer 104 should not be too thick or too thin. If the protective layer 104 is too thick, the corresponding protective material layer 105 formed on the first gate material layer 103 in the unit storage region I and the logic region II will be too thick, and it will take too much time to deposit and form the protective material layer 105. Subsequently, removing the protective material layer 105 in the unit storage region I and forming the protective layer 104 will also take too much time, resulting in too long a formation time for the protective layer 104. If the protective layer 104 is too thin, the protective layer 104 is easily removed, and the protective layer 104 cannot provide good protection for the first gate material layer 103 in the logic region II. In this embodiment, in the step of forming the protective layer 104 on the first gate material layer 103 in the logic region II, the thickness of the protective layer 104 is 750 angstroms to 950 angstroms.

[0085] The method for forming the semiconductor structure further includes: etching the protective material layer 105, and after forming the protective layer 104, removing the masking layer 106.

[0086] In this embodiment, the material of the masking layer 106 includes photoresist, and accordingly, an ashing process is used to remove the masking layer 106.

[0087] Reference Figure 8 , a planar structure 107 is formed on the first gate material layer 103 and the protective layer 104.

[0088] The planar structure 107 has a flat surface, that is, the top of the planar structure 107 in the logic region II is flush with the top of the planar structure 107 in the unit storage region I.

[0089] Specifically, the step of forming the planar structure 107 on the first gate material layer 103 and the protective layer 104 includes: forming a second gate material layer 1072 on the first gate material layer 103; forming a planar material film 1071 on the second gate material layer 1072, and the planar material film 1071 has a flat top surface.

[0090] The material of the planar material film 1071 itself has a flat characteristic, and it is located at the top of the planar structure 107, which is beneficial to making the top of the planar structure 107 flat.

[0091] In this embodiment, the material of the planar material film 1071 includes a Bottom Anti-Reflection Coating (BARC). The bottom anti-reflection coating has high fluidity, so that the top of the formed planar material film 1071 is relatively flat. In addition, the bottom anti-reflection coating also has the advantage of being easily removed.

[0092] In this embodiment, the flat material film 1071 is formed by a spin coating process.

[0093] The first gate material layer 103 in the unit storage area I is uneven. The second gate material layer 1072 is located on the first gate material layer 103. The second gate material layer 1072 is formed in the recess of the first gate material layer 103. Since the materials of the second gate material layer 1072 and the first gate material layer 103 are the same, when etching the first gate material layer 103 and the second gate material layer 1072 on the same horizontal plane in the subsequent etching process, the first gate material layer 103 and the second gate material layer 1072 have the same etching rate. Compared with the case where the flat structure only includes the flat material film and the etching rates of the first gate material layer and the flat material film are different when etching the first gate material layer and the flat material film on the same horizontal plane, it is easy to make the remaining first gate material layer 103 in the unit storage area I flush with the top of the first gate material layer in the logic area II.

[0094] In this embodiment, the material of the second gate material layer 1072 includes polysilicon (poly). The second gate material layer 1072 is formed by a furnace tube process. In other embodiments, a chemical vapor deposition process may also be used to form the second gate material layer.

[0095] It should also be noted that since the top of the first gate material layer 103 with a partial lateral dimension in the low-pressure area 100A is flush with the top of the stacked gate structure 200; while the top of the first gate material layer 103 in the high-pressure area 100B is higher than the top of the stacked gate structure 200. This makes the top of the second gate material layer 1072 in the low-pressure area 100A lower than the top of the second gate material layer 1072 in the high-pressure area 100B in the step of forming the second gate material layer 1072.

[0096] Reference Figure 9 and Figure 10 , the flat structure 107 and the first gate material layer 103 in the unit storage area I are etched. During the etching process, the protective layer 104 is used to protect the first gate material layer 103 in the logic area II.

[0097] In an embodiment of the present invention, a protective layer 104 is formed on the first gate material layer 103 in the logic region II. During the etching process of the flat structure 107 and the first gate material layer 103 in the unit storage region I, the protective layer 104 protects the first gate material layer 103 in the logic region II from being etched, while the first gate material layer 103 and the flat structure 107 in the unit storage region I that are higher than the first gate material layer 103 in the logic region II are removed, so that the top of the remaining first gate material layer 103 in the unit storage region I is flush with the top of the first gate material layer 103 in the logic region II. During the etching process of the first gate material layer 103 with flush tops in the unit storage region I and the logic region II, the gate structures in the unit storage region I and the logic region II are etched and formed simultaneously, and it is not easy to have a situation where the gate structure in the logic region II has been formed, but there is still a part of the first gate material layer 103 remaining at the bottom of the gate structure in the unit storage region I. In summary, the method for forming a semiconductor structure provided by the embodiment of the present invention enables the logic region II to be successfully integrated with the unit storage region I on the same substrate 100, and at the same time improves the yield of the semiconductor structure.

[0098] As Figure 9 shown, the etching process includes: a first etching step with the protective layer 104 as the etching stop position, which is used to etch the flat structure 107 and a part of the thickness of the first gate material layer 103.

[0099] In the first etching step, by adjusting the etching rates of the flat material film 1071, the second gate material layer 1072, and the first gate material layer 103, the overall flatness of the gate material layer (including the material of the first gate material layer 103 and the material of the second gate material layer 1072) in the unit storage region I is improved.

[0100] Specifically, the first etching step includes: a plurality of etching combinations performed cyclically, and each etching combination includes: performing a first sub-etching step in which the etching rate of the flat material film 1071 is greater than the etching rate of the second gate material layer 1072; performing a second sub-etching step in which the etching rate of the second gate material layer 1072 is greater than the etching rate of the flat material film 1071.

[0101] Because the material of the second gate material layer 1072 is the same as that of the first gate material layer 103, the first etching step makes the flat material film 1071 easy to be quickly consumed, while making the consumption rates of the first gate material layer 103 and the second gate material layer 1072 too slow. The second etching step makes the first gate material layer 103 and the second gate material layer 1072 easy to be quickly consumed, while making the consumption rate of the flat material film 1071 too slow. By performing the first etching step and the second etching step in a cross-cycle manner, the overall flatness of the gate material layer (including the material of the first gate material layer 103 and the material of the second gate material layer 1072) in the unit storage area I can be finally improved.

[0102] In this embodiment, both the first etching step and the second etching step are maskless dry etching processes or both are wet etching processes. Maskless dry etching and wet etching processes do not require a mask, which is beneficial to improving the efficiency of the first etching step. In other embodiments, the first etching step is a maskless dry etching process, and the second etching step is a wet etching process. In some other embodiments, the first etching step is a wet etching process, and the second etching step is a maskless dry etching process.

[0103] Specifically, in this embodiment, the etching gas used in the first etching step includes one or more of Cl2, HBr, and HCl, and the etching gas used in the second etching step includes one or more of C4F8, C5F8, and C4F6.

[0104] It should be noted that the first etching step stops etching at the top of the protective layer 104, so that in the subsequent second etching step, the remaining first gate material layer 103 and the flat structure 107 in the unit storage area I are etched using the protective layer 104 as a mask.

[0105] As Figure 10 shown, the etching process further includes: after the first etching step, a second etching step is performed to etch the remaining first gate material layer 103 and the flat structure 107 in the unit storage area I using the protective layer 104 as a mask.

[0106] Etching the remaining first gate material layer 103 and the flat structure 107 in the unit storage area I using the protective layer 104 as a mask is used to remove the flat structure 107 and the first gate material layer 103 that are higher than the stacked structure, so that the top of the first gate material layer 103 in the unit memory is flush with the top of the first gate material layer 103 in the logic area II.

[0107] It should be noted that in the step of etching the remaining first gate material layer 103 and the planar structure 107 in the unit storage area I with the protection layer 104 as a mask, the oxide layer 102 on the top of the stacked gate structure 200 is removed.

[0108] In this embodiment, with the protection layer 104 as a mask, a dry etching process is used to etch the remaining first gate material layer 103 and the planar structure 107 in the unit storage area I, and in the step of etching the remaining first gate material layer 103 and the planar structure 107 in the unit storage area I with the protection layer 104 as a mask, the top of the stacked gate structure 200 is used as the etching stop position.

[0109] The dry etching process is easy to control. During the etching process, it can accurately identify the top of the stacked gate structure 200 as the etching stop position, and it is easy to precisely remove the remaining first gate material layer 103 and the planar structure 107 in the unit storage area I without damaging the stacked gate structure 200. Moreover, the dry etching process can remove the oxide layer 102 while removing the first gate material layer 103 and the planar structure 107 by changing the etching gas.

[0110] Reference Figure 11 After the etching treatment, the protection layer 104 is removed.

[0111] Removing the protection layer 104 prepares for etching the first gate material layer 103 to form a gate structure on the unit storage area I and the logic area II of the substrate 100.

[0112] In this embodiment, a wet etching process is used to remove the protection layer 104. The wet etching process has a high etching rate, simple operation, and low process cost.

[0113] In this embodiment, the material of the protection layer 104 includes silicon oxide. Correspondingly, the wet etching solution includes a hydrogen fluoride solution.

[0114] Reference Figure 12 After removing the protection layer 104, the first gate material layer 103 is etched to form a gate structure (not labeled) on the unit storage area I and the logic area II of the substrate 100.

[0115] Since the top of the remaining first gate material layer 103 in the unit storage area I is flush with the top of the first gate material layer 103 in the logic area II, during the process of etching the first gate material layer 103 with flush tops in the unit storage area I and the logic area II, the gate structures in the unit storage area I and the logic area II are etched and formed simultaneously, and it is not easy to have a situation where the gate structure in the logic area II has been formed, but there is still a part of the first gate material layer 103 remaining at the bottom of the gate structure in the unit storage area I. In summary, the method for forming a semiconductor structure provided by the embodiment of the present invention enables the logic area II to be successfully integrated with the unit storage area I on the same substrate 100, and at the same time improves the yield of the semiconductor structure.

[0116] In this embodiment, in the step of forming a gate structure on the unit storage area I and the logic area II of the substrate 100, the tops of the gate structures in the unit storage area I and the logic area II are flush.

[0117] In this embodiment, in the unit storage area I, the gate structure in the high-voltage area 100B of the substrate 100 serves as an erase gate structure 205 (Erase Gate, EG), and the gate structure in the low-voltage area 100A of the substrate 100 serves as a select gate 206 (Select Gate, EG). The gate structure in the logic area II is used to provide a working voltage for the memory in the unit storage area I.

[0118] The erase gate structure 205 is used to implement signal erasure of the memory. By applying a high voltage to the end of the erase gate structure 205, due to the coupling capacitance effect between the erase gate structure 205 and the floating gate structure 201, a potential difference is formed on the gate dielectric layer 202 therebetween, and electrons in the floating gate structure 201 can be pulled into the erase gate structure 205 through tunneling. As the electrons in the floating gate structure 201 are pulled out, the potential of the floating gate structure 201 increases, and the gap between its potential and the erase gate structure 205 will narrow, weakening the potential difference of the gate dielectric layer 202. Finally, the electrons in the floating gate structure 201 are completely pulled out, realizing signal erasure of the memory.

[0119] The main function of the select gate 206 is to perform write and read operations on specific memory cells, which are usually composed of a floating gate structure 201, a control gate structure 203, and an erase gate structure 205. The presence of the select gate 206 also provides electrical isolation for the memory cells to ensure that only the selected memory cells are affected by the operation. The select gate 206 also helps to enhance data protection and security of the memory. By controlling the voltage of the select gate 206, unauthorized access or unwanted operations can be prevented, improving data security.

[0120] In this embodiment, the materials of the erase gate structure 205 and the select gate 206 both include polysilicon.

[0121] The semiconductor structure can be formed by the formation method described in the foregoing embodiments, or can be formed by other formation methods. For the specific description of the semiconductor structure in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.

[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a unit storage area and a logic area; Forming a plurality of spaced-apart stacked gate structures on the unit storage area of the substrate; Forming a first gate material layer covering the stacked gate structures and the unit storage area and the logic area in the substrate; Forming a protective layer on the first gate material layer in the logic area; Forming a planarized structure on the first gate material layer and the protective layer; Etching the planarized structure and the first gate material layer in the unit storage area. During the etching process, the protective layer is used to protect the first gate material layer in the logic area, so that the top of the remaining first gate material layer in the unit storage area is flush with the top of the first gate material layer in the logic area; After the etching process, removing the protective layer; After removing the protective layer, etching the first gate material layer to form a gate structure on the unit storage area and the logic area of the substrate.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the protective layer includes: silicon oxide, silicon nitride or silicon oxynitride.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of forming the protective layer on the first gate material layer in the logic area, the thickness of the protective layer is 750 angstroms to 950 angstroms.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of forming the protective layer on the first gate material layer in the logic area includes: Forming a protective material layer on the first gate material layer in the unit storage area and the logic area; Removing the protective material layer in the unit storage area, and the remaining protective material layer located in the logic area serves as the protective layer.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, Using a wet etching process to remove the protective material layer in the unit storage area.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The etching solution used in the steps of the wet etching process includes: hydrofluoric acid solution.

7. The method for forming a semiconductor structure according to claim 4, characterized in that, Using a furnace tube process to form the protective material layer.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The etching process includes: Performing a first etching step with the protective layer as the etching stop position, for etching the planarized structure and a part of the thickness of the first gate material layer; After the first etching step, performing a second etching step to etch the remaining first gate material layer and the planarized structure in the unit storage area with the protective layer as a mask.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, The step of forming a planarized structure on the first gate material layer and the protective layer includes: Forming a second gate material layer on the first gate material layer. In the step of forming the second gate material layer on the first gate material layer, the material of the second gate material layer is the same as that of the first gate material layer; Forming a planarizing material film on the second gate material layer, and the planarizing material film has a flat top surface.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The material of the planarizing material film includes a bottom anti-reflection coating.

11. The method for forming a semiconductor structure according to claim 9, characterized in that, The first etching step includes: a plurality of etching combinations performed cyclically, and the etching combination includes: Performing a first sub-etching step, in which the etching rate of the planarizing material film is greater than the etching rate of the second gate material layer in the first sub-etching step; Performing a second sub-etching step, in which the etching rate of the second gate material layer is greater than the etching rate of the planarizing material film in the second sub-etching step.

12. The method for forming a semiconductor structure according to claim 11, wherein, Both the first sub-etching step and the second sub-etching step are a maskless dry etching process or both are a wet etching process; Alternatively, the first sub-etching step is a maskless dry etching process, and the second sub-etching step is a wet etching process; Alternatively, the first sub-etching step is a wet etching process, and the second sub-etching step is a maskless dry etching process.

13. The method for forming a semiconductor structure according to claim 8, wherein, In the second etching step, using the protective layer as a mask, a dry etching process is used to etch the remaining first gate material layer and the planar structure in the unit storage area.

14. The method for forming a semiconductor structure according to claim 8, wherein, In the step of etching the remaining first gate material layer and the planar structure in the unit storage area with the protective layer as a mask, the top of the stacked gate structure is used as the etching stop position.

15. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming a first gate material layer on the stacked gate structure and the unit storage area and the logic area of the substrate, the thickness of the first gate material layer is equal to the height of the stacked gate structure; In the step of performing the etching process, the planar structure in the logic area and the unit storage area, and the first gate material layer in the unit storage area that is higher than the stacked gate structure are removed.

16. The method for forming a semiconductor structure according to claim 1, wherein, The protective layer is removed by a wet etching process.

17. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming a plurality of stacked gate structures spaced apart from each other on the unit storage area of the substrate, the stacked gate structure includes: a floating gate structure, an inter-gate dielectric layer located on the floating gate structure, and a control gate structure located on the inter-gate dielectric layer; In the step of forming a gate structure on the unit storage area and the logic area of the substrate, the tops of the gate structures in the unit storage area and the gate structures in the logic area are flush.

18. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming a first gate material layer covering the stacked gate structure and the unit storage area and the logic area in the substrate, the thickness of the first gate material layer is 1500 angstroms to 2000 angstroms.

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