Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes: a substrate including a cell region and a peripheral region; a plurality of data storage patterns on the cell region, and each data storage pattern including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked; and a magnetic shielding layer at the cell region and between the data storage patterns. The magnetic shielding layer has a top surface recessed toward the substrate between the data storage patterns.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0187365, filed with the Korean Intellectual Property Office on December 20, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to a semiconductor device and a method of manufacturing a semiconductor device. Background art

[0004] As electronic products tend to be high - speed and / or low - power consumption, the demand for high - speed and low operating voltage of semiconductor memory devices included in electronic products is increasing. To meet these demands, magnetic memory devices have been developed as semiconductor memory devices. Since magnetic memory devices operate at high speed and have non - volatile characteristics, these devices have attracted considerable attention as next - generation semiconductor memory devices.

[0005] Generally, a magnetic memory device may include a magnetic tunnel junction (MTJ) pattern. The magnetic tunnel junction pattern includes two magnetic structures and an insulating layer interposed therebetween. The resistance of the magnetic tunnel junction pattern varies according to the magnetization directions of the two magnetic structures. For example, the magnetic tunnel junction pattern has a high resistance when the magnetization directions of the two magnetic structures are antiparallel, and has a low resistance when the magnetization directions of the two magnetic structures are parallel. The magnetic memory device may utilize the resistance difference between the high resistance and the low resistance of the magnetic tunnel junction pattern to write and read data. Summary of the invention

[0006] The present disclosure provides a semiconductor device capable of reducing the influence of an external magnetic field and a method of manufacturing a semiconductor device.

[0007] The present disclosure provides a simplified method of manufacturing a magnetoresistive RAM (MRAM) semiconductor device.

[0008] In a general aspect, a semiconductor device includes: a substrate including a cell region and a peripheral region; a plurality of data storage patterns on the cell region, each of the data storage patterns including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked; and a magnetic shielding layer on the cell region and located between the data storage patterns. The magnetic shielding layer surrounds side surfaces of the data storage patterns. The magnetic shielding layer may have a top surface that is recessed toward the substrate between the data storage patterns.

[0009] In another general aspect, a semiconductor device includes: a substrate including a cell region, a peripheral region, and a boundary region located between the cell region and the peripheral region; a first lower dielectric layer on the substrate; a second lower dielectric layer on the first lower dielectric layer over the cell region and the boundary region; a plurality of data storage patterns on the second lower dielectric layer over the cell region, the data storage patterns including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode stacked in sequence; a capping dielectric layer on the second lower dielectric layer, the capping dielectric layer surrounding side surfaces of the data storage patterns; a magnetic shielding layer on the capping dielectric layer, the magnetic shielding layer surrounding side surfaces of the data storage patterns; a cell dielectric layer on the cell region and the boundary region, the cell dielectric layer covering the data storage patterns and the magnetic shielding layer; a peripheral dielectric layer on the first lower dielectric layer over the peripheral region; and a plurality of peripheral wiring patterns in the peripheral dielectric layer, the peripheral wiring patterns passing through the first lower dielectric layer over the peripheral region. The magnetic shielding layer may have a top surface that is recessed toward the substrate between the data storage patterns.

[0010] In another general aspect, a method of manufacturing a semiconductor device includes: providing a substrate including a cell region, a peripheral region, and a boundary region located between the cell region and the peripheral region; forming a wiring dielectric layer and a plurality of wiring structures passing through the wiring dielectric layer on the substrate; sequentially stacking a first lower dielectric layer and a second lower dielectric layer extending from the cell region to the boundary region and the peripheral region on the wiring dielectric layer; forming a plurality of data storage patterns on the cell region, each of the plurality of data storage patterns including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode stacked in sequence on the second lower dielectric layer; forming a capping dielectric layer on the second lower dielectric layer over the cell region and the boundary region, the capping dielectric layer covering top and side surfaces of the data storage patterns; depositing a metal layer conformally covering a top surface of the capping dielectric layer; and wet etching a portion of the metal layer to form a magnetic shielding layer having a top surface that is recessed toward the substrate between the data storage patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a circuit diagram showing a unit memory cell of a semiconductor device is shown.

[0012] Figure 2 A plan view of an example of a semiconductor device is shown.

[0013] Figure 3A A cross-sectional view taken along line Figure 2 I-I' is shown.

[0014] Figure 3B An example of showingFigure 2 A perspective view of some components of the semiconductor device depicted in

[0015] Figure 4A and Figure 4B A cross-sectional view showing an example of a magnetic tunnel junction pattern in a semiconductor device.

[0016] Figure 5 Shows Figure 3A An enlarged view of part A of

[0017] Figures 6 to 14 Shows a cross-sectional view taken along line I-I' of Figure 2 An example of a method for manufacturing a semiconductor device. Detailed Description

[0018] Figure 1 An example of a circuit diagram showing a unit memory cell of a semiconductor device.

[0019] Referring to Figure 1 , the unit memory cell MC includes a memory element ME and a selection element SE. The memory element ME and the selection element SE can be electrically connected in series with each other. The memory element ME can be connected between the bit line BL and the selection element SE. The selection element SE can be connected between the memory element ME and the source line SL and can be controlled by the word line WL. The selection element SE can include, for example, a bipolar transistor or a metal oxide semiconductor (MOS) field effect transistor.

[0020] The memory element ME can include a magnetic tunnel junction pattern MTJ, which includes magnetic patterns MP1 and MP2 spaced apart from each other, and also includes a tunnel barrier pattern TBP located between the magnetic patterns MP1 and MP2. One of the magnetic patterns MP1 and MP2 (e.g., magnetic pattern MP1) can be a reference magnetic pattern, whose magnetization direction is fixed in a normal use environment regardless of the external magnetic field. The other of the magnetic patterns MP1 and MP2 (e.g., magnetic pattern MP2) can be a free magnetic pattern, whose magnetization direction changes between two stable magnetization directions due to an external magnetic field. The magnetic tunnel junction pattern MTJ can have a resistance, whose value is much larger when the magnetization directions of the reference magnetic pattern and the free magnetic pattern are antiparallel to each other than when the magnetization directions of the reference magnetic pattern and the free magnetic pattern are parallel to each other. For example, the resistance of the magnetic tunnel junction pattern MTJ can be controlled by changing the magnetization direction of the free magnetic pattern. The memory element ME can use the resistance difference depending on the magnetization directions of the reference magnetic pattern and the free magnetic pattern, and this mechanism can enable the unit memory cell MC to store data therein.

[0021] Figure 2A plan view showing an example of a semiconductor device. Figure 3A Shows a cross-sectional view taken along Figure 2 line I-I' of. Figure 3B Shows a perspective view of some components of the semiconductor device depicted in Figure 2 . Figure 4A And Figure 4B Shows a cross-sectional view showing an example of a magnetic tunnel junction pattern in a semiconductor device. Figure 5 Shows an enlarged view of part A showing Figure 3A .

[0022] Referring to Figure 2 , Figure 3A And Figure 3B , the substrate 100 includes a cell region CR, a peripheral region PR, and a boundary region BR located between the cell region CR and the peripheral region PR. The substrate 100 may be a semiconductor substrate including silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), or gallium arsenide (GaAs). The cell region CR may be a region of the substrate 100 on which Figure 1 memory cells MC are provided, and the peripheral region PR may be another region of the substrate 100 on which peripheral circuits for driving the memory cells MC are provided. The boundary region BR may be yet another region of the substrate 100 provided between the cell region CR and the peripheral region PR.

[0023] A wiring structure (e.g., wiring lines 102 and wiring contacts 104) may be provided on the substrate 100. The wiring structure may be provided on the cell region CR and the peripheral region PR of the substrate 100. The wiring structure may include wiring lines 102 vertically spaced apart from the substrate 100 and wiring contacts 104 connected to the wiring lines 102. The wiring lines 102 may be spaced apart from the top surface 100U of the substrate 100 in a direction perpendicular to the top surface 100U of the substrate 100. The wiring contacts 104 may be provided between the substrate 100 and the wiring lines 102. Each of the wiring lines 102 may be electrically connected to the substrate 100 through a corresponding one of the wiring contacts 104. The wiring lines 102 and the wiring contacts 104 may include a metal (e.g., copper).

[0024] Select elements (see SE in Figure 1 ) may be provided on the cell region CR of the substrate 100, and peripheral transistors constituting the peripheral circuits may be provided on the peripheral region PR of the substrate 100. The select elements and the peripheral transistors may be, for example, field effect transistors. Each of the wiring lines 102 may be electrically connected to a terminal (e.g., a source terminal, a drain terminal, or a gate terminal) of a corresponding one of the select elements or the peripheral transistors through a corresponding one of the wiring contacts 104.

[0025] The wiring dielectric layer 110 may be disposed on the substrate 100 to cover the wiring structure (e.g., the wiring line 102 and the wiring contact 104). The wiring dielectric layer 110 may be disposed on the cell region CR of the substrate 100 and may extend onto the boundary region BR and the peripheral region PR of the substrate 100. The wiring dielectric layer 110 may expose the top surface of the topmost wiring line in the wiring line 102. For example, the wiring dielectric layer 110 may have a top surface that is substantially coplanar with the top surface of the topmost wiring line 102. The wiring dielectric layer 110 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0026] The first lower dielectric layer 120 may be disposed on the wiring dielectric layer 110 and may cover the exposed top surface of the topmost wiring line 102. The first lower dielectric layer 120 may be disposed on the wiring dielectric layer 110 in the cell region CR and may extend onto the wiring dielectric layer 110 in the boundary region BR and the peripheral region PR. The first lower dielectric layer 120 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0027] The second lower dielectric layer 130 may be disposed on the first lower dielectric layer 120. The second lower dielectric layer 130 may be disposed on the first lower dielectric layer 120 in the cell region CR and may extend onto the first lower dielectric layer 120 in the boundary region BR. The second lower dielectric layer 130 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0028] The second lower dielectric layer 130 may include a material different from that of the first lower dielectric layer 120. The first lower dielectric layer 120 may include silicon carbonitride (e.g., SiCN), and the second lower dielectric layer 130 may include silicon oxide (e.g., tetraethyl orthosilicate (TEOS)).

[0029] The data storage pattern DS may be disposed on the second lower dielectric layer 130 in the cell region CR. The data storage patterns DS may be spaced apart from each other in a first direction D1 and a second direction D2 that intersect each other and are parallel to the top surface 100U of the substrate 100.

[0030] The second underlying dielectric layer 130 on the cell region CR may have a top surface 130RU that is recessed toward the substrate 100 between the data storage patterns DS. The recessed top surface 130RU of the second underlying dielectric layer 130 on the cell region CR may be at a level lower than the level of the uppermost surface 130U1 of the second underlying dielectric layer 130 on the cell region CR. In the present specification, the term "level" may refer to the height from the top surface 100U of the substrate 100 in a third direction D3 perpendicular to the top surface 100U of the substrate 100.

[0031] The second underlying dielectric layer 130 on the boundary region BR may have a top surface 130RUa that is recessed toward the substrate 100. The recessed top surface 130RUa of the second underlying dielectric layer 130 on the boundary region BR may be at a height lower than the height of the uppermost surface 130U1 of the second underlying dielectric layer 130 on the cell region CR. In some embodiments, the recessed top surface 130RUa of the second underlying dielectric layer 130 on the boundary region BR may be at the same height as the recessed top surface 130RU of the second underlying dielectric layer 130 on the cell region CR.

[0032] The lower electrode contacts 140 may be disposed in the second underlying dielectric layer 130 on the cell region CR and may be spaced apart from each other in a first direction D1 and a second direction D2. The lower electrode contacts 140 may be disposed correspondingly under the data storage patterns DS and electrically connected to the data storage patterns DS. Each of the lower electrode contacts 140 may penetrate the first underlying dielectric layer 120 and the second underlying dielectric layer 130 on the cell region CR and may be connected to a corresponding one of the uppermost wiring lines 102. Each of the data storage patterns DS may be electrically connected to a terminal (e.g., a drain terminal) of a corresponding selection element through a corresponding lower electrode contact 140 and a corresponding uppermost wiring line 102.

[0033] The top surface 140U of the lower electrode contact 140 may be at a height higher than the height of the recessed top surface 130RU of the second underlying dielectric layer 130 on the cell region CR. The top surface 140U of the lower electrode contact 140 may be at the same height as the uppermost surface 130U1 of the second underlying dielectric layer 130 on the cell region CR. The recessed top surface 130RUa of the second underlying dielectric layer 130 on the boundary region BR may be at a height lower than the height of the top surface 140U of the lower electrode contact 140.

[0034] The lower electrode contact 140 may include at least one of the following: a doped semiconductor material (e.g., doped silicon), a metal (e.g., one or more of tungsten, titanium, and tantalum), a metal-semiconductor compound (e.g., a metal silicide), and a conductive metal nitride (e.g., one or more of titanium nitride, tantalum nitride, and tungsten nitride).

[0035] Each of the data storage patterns DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE stacked (e.g., sequentially stacked) in a third direction D3 on the second lower dielectric layer 130. The magnetic tunnel junction pattern MTJ may be disposed between the bottom electrode BE and the top electrode TE. The lower electrode contact 140 may be correspondingly connected to the bottom electrode BE of the data storage pattern DS. The bottom electrode BE of each of the data storage patterns DS may contact the top surface 140U of one of the lower electrode contacts 140 and the uppermost surface 130U1 of the second lower dielectric layer 130 on the cell region CR.

[0036] The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP disposed between the first magnetic pattern MP1 and the second magnetic pattern MP2. The first magnetic pattern MP1 may be disposed between the bottom electrode BE and the tunnel barrier pattern TBP, and the second magnetic pattern MP2 may be disposed between the top electrode TE and the tunnel barrier pattern TBP. The bottom electrode BE may include, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The top electrode TE may include one or more of the following: a metal (e.g., Ta, W, Ru, or Ir) and a conductive metal nitride (e.g., TiN).

[0037] Reference Figure 4A and Figure 4B , the first magnetic pattern MP1 may be a reference layer having a magnetization direction MD1 fixed in one direction, and the second magnetic pattern MP2 may be a free layer having a magnetization direction MD2 that can be changed to be parallel or antiparallel to the magnetization direction MD1 of the first magnetic pattern MP1. Figure 4A and Figure 4B and show an example in which the second magnetic pattern MP2 is a free layer, but the present disclosure is not limited thereto. For example, the first magnetic pattern MP1 may be a free layer, and the second magnetic pattern MP2 may be a reference layer.

[0038] Reference Figure 4A, for example, the magnetization directions MD1 and MD2 of the first magnetic pattern MP1 and the second magnetic pattern MP2 can be perpendicular to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2 (for example, it can be perpendicular magnetization). In other words, the magnetic patterns MP1 and MP2 have perpendicular magnetic anisotropy. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 can include one or more of the following: intrinsic perpendicular magnetic materials and non-intrinsic perpendicular magnetic materials. Intrinsic perpendicular magnetic materials can include materials that have perpendicular magnetization properties even without external factors. Intrinsic perpendicular magnetic materials can include at least one of the following: perpendicular magnetic materials (e.g., CoFeTb, CoFeGd, CoFeDy), perpendicular magnetic materials with an L10 structure, CoPt with a hexagonal close-packed (HCP) lattice structure, and perpendicular magnetic structures. Perpendicular magnetic materials with an L10 structure can include one or more of the following: FePt with an L10 structure, FePd with an L10 structure, CoPd with an L10 structure, and CoPt with an L10 structure. Perpendicular magnetic structures can include alternately and repeatedly stacked magnetic layers and non-magnetic layers. For example, perpendicular magnetic structures can include one or more of the following: (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, and (CoCr / Pd)n (where n is the number of stacked layers). Non-intrinsic perpendicular magnetic materials can include materials that have inherent in-plane magnetization properties or perpendicular magnetization properties caused by external factors. For example, non-intrinsic perpendicular magnetic materials can have perpendicular magnetization properties caused by the magnetic anisotropy induced by the junction between the tunnel barrier pattern TBP and the first magnetic pattern MP1 (or the second magnetic pattern MP2). Non-intrinsic perpendicular magnetic materials can include, for example, CoFeB.

[0039] Referring to Figure 4B , for another example, the magnetization direction MD1 of the first magnetic pattern MP1 and the magnetization direction MD2 of the second magnetic pattern MP2 can be parallel to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 can include ferromagnetic materials. The first magnetic pattern MP1 can also include an antiferromagnetic material that is used to fix the magnetization direction of the ferromagnetic material in the first magnetic pattern MP1.

[0040] Each of the first and second magnetic patterns MP1 and MP2 may include a Heusler alloy including Co. The tunnel barrier pattern TBP may include one or more of a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium zinc (MgZn) oxide layer, and a magnesium boron (MgB) oxide layer.

[0041] Return to reference Figure 2 , Figure 3A and Figure 3B , the capping dielectric layer 150 may be disposed on the second lower dielectric layer 130 on the cell region CR. The capping dielectric layer 150 may conformally cover the side surface of each of the data storage patterns DS on the cell region CR and the recessed top surface 130RU of the second lower dielectric layer 130. The capping dielectric layer 150 may have a top surface that is recessed toward the substrate 100 between the data storage patterns DS. When viewed in a plan view, the capping dielectric layer 150 may surround the side surface of each of the data storage patterns DS. The capping dielectric layer 150 may extend onto the second lower dielectric layer 130 on the boundary region BR and may conformally cover the recessed top surface 130RUa of the second lower dielectric layer 130 on the boundary region BR.

[0042] The capping dielectric layer 150 may conformally cover the side surfaces of the bottom electrode BE, the magnetic tunnel junction pattern MTJ, and the top electrode TE. When viewed in a plane, the capping dielectric layer 150 may surround the side surfaces of the bottom electrode BE, the magnetic tunnel junction pattern MTJ, and the top electrode TE. The capping dielectric layer 150 may include a nitride (e.g., silicon nitride).

[0043] The magnetic shielding layer MSL may be formed on the cell region CR. The magnetic shielding layer MSL may extend from the cell region CR to the boundary region BR, and one end MSL_br of the magnetic shielding layer MSL may be located on the boundary region BR. The magnetic shielding layer MSL may not extend onto the peripheral region PR.

[0044] The data storage patterns DS two-dimensionally spaced apart from each other in the first direction D1 and the second direction D2 may penetrate the magnetic shielding layer MSL. The magnetic shielding layer MSL may surround the side surfaces of the data storage patterns DS and the sidewalls of the capping dielectric layer 150. For example, the magnetic shielding layer MSL may have an overall plate shape having a through hole penetrated by the data storage pattern DS (e.g., the data storage pattern DS extends through the through hole).

[0045] The magnetic shielding layer MSL may include a material exhibiting ferromagnetism. For example, the magnetic shielding layer MSL may include one or more of the following: cobalt (Co), iron (Fe), nickel (Ni), and rare earth metals. The magnetic shielding layer MSL may be a ferromagnetic material including a ferromagnetic material, and when a magnetic field is formed outside the semiconductor device, it may allow most of the magnetic flux caused by the external magnetic field to pass through the magnetic shielding layer MSL. Therefore, due to the external magnetic field, the magnetic flux passing through the data storage pattern DS may be reduced, and the magnetic tunnel junction pattern MTJ may be less affected by the external magnetic field.

[0046] Referring to Figure 2 , Figure 3A and Figure 5 , the magnetic shielding layer MSL has a top surface MSL_U that is recessed toward the substrate 100 between the data storage patterns DS. For example, the recessed top surface MSL_U may include a first portion MSL_U1 that contacts the sidewall of the capping dielectric layer 150, and the first portion MSL_U1 may be at the maximum level on the recessed top surface MSL_U. In addition, the recessed top surface MSL_U may include a second portion MSL_U2 that is spaced apart from the capping dielectric layer 150 and is located at the center of the recessed top surface MSL_U, and the second portion MSL_U2 may be at a level lower than that of the first portion MSL_U1. For example, the second portion MSL_U2 of the recessed top surface MSL_U of the magnetic shielding layer MSL may be at a height that is at least about 10 nm higher than the height of the top surface TBP_U of the tunnel barrier pattern TBP (or, R1≥10 nm). In this configuration, the first portion MSL_U1 of the recessed top surface MSL_U of the magnetic shielding layer MSL may be at a height that is at least about 5 nm lower than the height of the bottom surface 170L of the upper dielectric layer 170 (or, D1≥5 nm). Therefore, the second portion MSL_U2 may be at a height that is about 5 nm lower than the height of the bottom surface 170L of the upper dielectric layer 170 (or, D2>5 nm). The recessed top surface MSL_U of the magnetic shielding layer MSL may be at a level that decreases in the direction from the cell region CR toward the peripheral region PR.

[0047] Between data storage patterns DS adjacent to each other along a first direction D1 or a second direction D2, a top surface MSL_U of a recess of a magnetic shielding layer MSL may be at a level higher than a level of a top surface MTJ_U of a magnetic tunnel junction pattern MTJ included in the data storage pattern DS. Additionally, a bottom surface MSL_L of the magnetic shielding layer MSL may be at a level lower than a level of a bottom surface MTJ_L of the magnetic tunnel junction pattern MTJ. Accordingly, between adjacent magnetic tunnel junction patterns MTJ, the magnetic shielding layer MSL may be formed to have a volume larger than a volume of the magnetic tunnel junction pattern MTJ. Further, the magnetic shielding layer MSL may surround a side surface of the magnetic tunnel junction pattern MTJ and may be a ferromagnetic material having a magnetism stronger than that of the magnetic tunnel junction pattern MTJ, thereby allowing magnetic flux caused by an external magnetic field to pass through.

[0048] The top surface MSL_U of the recess of the magnetic shielding layer MSL may be at a level lower than a level of a bottom surface 192L of a first unit conductive line 192 to be discussed below. For example, the magnetic shielding layer MSL may be spaced apart from the first unit conductive line 192 and may not be electrically connected to any one of the first unit conductive line 192, a conductive contact 194 located on the first unit conductive line 192, and a second unit conductive line 196 to be discussed below.

[0049] Return reference Figure 2 and Figure 3A Referring back, a cell dielectric layer 160 may be disposed on a second lower dielectric layer 130 in a cell region CR and may cover the data storage pattern DS and the magnetic shielding layer MSL. The cell dielectric layer 160 may fill a space between the data storage patterns DS. A capping dielectric layer 150 may be interposed between the cell dielectric layer 160 and side surfaces of each of the data storage patterns DS and may extend between a top surface 130RU of a recess of the second lower dielectric layer 130 in the cell region CR and the cell dielectric layer 160. The cell dielectric layer 160 may extend onto the second lower dielectric layer 130 in a boundary region BR. The capping dielectric layer 150 may extend between the cell dielectric layer 160 in the boundary region BR and a top surface 130RUa of the recess of the second lower dielectric layer 130. The cell dielectric layer 160 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0050] An upper dielectric layer 170 may be disposed on the cell dielectric layer 160 in the cell region CR. The upper dielectric layer 170 may extend onto the cell dielectric layer 160 in the boundary region BR. The upper dielectric layer 170 may include a material different from a material of the cell dielectric layer 160. For example, the cell dielectric layer 160 may include silicon oxide, and the upper dielectric layer 170 may include silicon carbonitride (e.g., SiCN).

[0051] The peripheral dielectric layer 180 may be disposed on the second lower dielectric layer 130 on the peripheral region PR. The peripheral dielectric layer 180 may be in contact with the top surface of the first lower dielectric layer 120 on the peripheral region PR. The peripheral dielectric layer 180 may be in contact with the side surface 160S of the cell dielectric layer 160 and the side surface 170S of the upper dielectric layer 170. The peripheral dielectric layer 180 may be in contact with the side surface of the capping dielectric layer 150.

[0052] The top surface 180U of the peripheral dielectric layer 180 may be at the same height as the top surface 170U of the upper dielectric layer 170. The top surface 180U of the peripheral dielectric layer 180 may be coplanar with the top surface 170U of the upper dielectric layer 170.

[0053] For example, the peripheral dielectric layer 180 may include a material that is the same as or similar to the material of the cell dielectric layer 160. For another example, the peripheral dielectric layer 180 may include a material different from the material of the cell dielectric layer 160 and may include a dielectric material having a dielectric constant (k) less than that of the cell dielectric layer 160.

[0054] In the cell region CR, the bit lines 190 (see Figure 1 BL in

[0055] The first cell conductive lines 192 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. Each of the first cell conductive lines 192 may have a linear shape extending in the second direction D2. Each of the first cell conductive lines 192 may be electrically connected to a corresponding data storage pattern DS spaced apart from each other in the second direction D2. The data storage patterns DS spaced apart from each other in the first direction D1 may be electrically connected to corresponding first cell conductive lines 192.

[0056] Each of the first cell conductive lines 192 may penetrate the upper dielectric layer 170 and may also penetrate the upper portion of the cell dielectric layer 160 to be connected to a corresponding data storage pattern DS. The bottom surface 192L of each of the first cell conductive lines 192 may be in contact with the top electrode TE of the corresponding data storage pattern DS. The top surface 192U of the first cell conductive line 192 may be at the same height as the top surface 170U of the upper dielectric layer 170 and may be coplanar with the top surface 170U of the upper dielectric layer 170. The first cell conductive line 192 may include a conductive material such as a metal (e.g., copper).

[0057] The peripheral conductive line portion 210 may be disposed in the peripheral dielectric layer 180 and on the first lower dielectric layer 120 located on the peripheral region PR. The peripheral dielectric layer 180 may cover the peripheral conductive line portion 210. The peripheral conductive line portion 210 may have an exposed top surface 210U that is not covered by the peripheral dielectric layer 180. The top surface 210U of the peripheral conductive line portion 210 may be at the same height as the top surface 180U of the peripheral dielectric layer 180 and may be coplanar with the top surface 180U of the peripheral dielectric layer 180. The top surface 210U of the peripheral conductive line portion 210 may be coplanar with the top surface 180U of the peripheral dielectric layer 180, the top surface 192U of the first unit conductive line 192, and the top surface 170U of the upper dielectric layer 170, or may be at the same height as the top surface 180U of the peripheral dielectric layer 180, the top surface 192U of the first unit conductive line 192, and the top surface 170U of the upper dielectric layer 170.

[0058] Peripheral wiring patterns (e.g., the peripheral conductive line portion 210 and the peripheral conductive contact portion 220) may be disposed on the peripheral region PR. Each of the peripheral wiring patterns may include the peripheral conductive line portion 210 and the peripheral conductive contact portion 220 disposed below the peripheral conductive line portion 210. The peripheral conductive contact portion 220 may be electrically connected to the peripheral conductive line portion 210. The peripheral conductive contact portion 220 and its corresponding peripheral conductive line portion 210 may be in contact with each other without a boundary therebetween. Each of the peripheral conductive contact portion 220 and its corresponding peripheral conductive line portion 210 may be connected to each other as a single integral piece. Each of the peripheral conductive contact portions 220 may penetrate the lower portion of the peripheral dielectric layer 180. Each of the peripheral conductive contact portions 220 may penetrate the first lower dielectric layer 120 on the peripheral region PR and may be electrically connected to a corresponding one of the uppermost wiring lines 102. Each of the peripheral conductive line portions 210 may be electrically connected to a terminal (e.g., a source terminal, a drain terminal, or a gate terminal) of a corresponding peripheral transistor through a corresponding peripheral conductive contact portion 220 and a corresponding uppermost wiring line 102.

[0059] The peripheral conductive line portion 210 and the peripheral conductive contact portion 220 may include a conductive material such as a metal (e.g., copper). The first unit conductive line 192, the peripheral conductive line portion 210, and the peripheral conductive contact portion 220 may include the same material.

[0060] The upper interlayer dielectric layer 200 may be disposed on the cell region CR, the boundary region BR, and the peripheral region PR, and may cover the top surface 170U of the upper dielectric layer 170, the top surface 192U of the first cell conductive line 192, the top surface 180U of the peripheral dielectric layer 180, and the top surface 210U of the peripheral conductive line portion 210. The upper interlayer dielectric layer 200 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0061] The second cell conductive line 196 may be disposed in the upper interlayer dielectric layer 200 on the cell region CR. The second cell conductive line 196 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The second cell conductive line 196 may accordingly overlap vertically with the first cell conductive line 192 (e.g., overlap in the third direction D3). The conductive contact 194 may be disposed in the upper interlayer dielectric layer 200 on the cell region CR and may be placed between the first cell conductive line 192 and the second cell conductive line 196. Each of the first cell conductive lines 192 may be electrically connected to one of the second cell conductive lines 196 through a corresponding one of the conductive contacts 194. The conductive contact 194 and the second cell conductive line 196 may include a conductive material such as a metal (e.g., copper).

[0062] Figures 6 to 14 A cross-sectional view taken along line I-I' is shown, illustrating an example of a method of manufacturing a semiconductor device. For the sake of brevity of description, omissions will be made to avoid repetitive explanations of the semiconductor device referred to Figure 2 、 Figures 1 to 3A 、 Figure 4A 、 Figure 4B and Figure 5 .

[0063] Referring to Figure 2 and Figure 6 , the substrate 100 includes a cell region CR, a peripheral region PR, and a boundary region BR located between the cell region CR and the peripheral region PR. Selective elements (see SE in Figure 1 ) and peripheral transistors may be formed on the substrate 100, and a wiring structure (e.g., wiring lines 102 and wiring contacts 104) may be formed on the selective elements and the peripheral transistors. The wiring structure may include wiring lines 102 spaced vertically (e.g., in the third direction D3) from the substrate 100 and wiring contacts 104 connected to the wiring lines 102. Each of the wiring lines 102 may be electrically connected to a corresponding selective element or a terminal (e.g., a source terminal, a drain terminal, or a gate terminal) of a corresponding peripheral transistor through a corresponding one of the wiring contacts 104.

[0064] A wiring dielectric layer 110 may be formed on the substrate 100. The wiring dielectric layer 110 may expose the top surface of the topmost wiring line in the wiring lines 102. The wiring dielectric layer 110 may be located on the cell region CR, the boundary region BR, and the peripheral region PR.

[0065] A first lower dielectric layer 120 extending from the cell region CR to the boundary region BR and the peripheral region PR may be stacked on the wiring dielectric layer 110. The first lower dielectric layer 120 may cover the exposed top surface of the topmost wiring line 102.

[0066] A second lower dielectric layer 130 may be stacked on the first lower dielectric layer 120. The second lower dielectric layer 130 may extend from the cell region CR to the boundary region BR and the peripheral region PR.

[0067] Lower electrode contacts 140 may be formed in the second lower dielectric layer 130 on the cell region CR. Each of the lower electrode contacts 140 may penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130 on the cell region CR and may be electrically connected to one of the topmost wiring lines 102. The formation of the lower electrode contacts 140 may include, for example, forming lower contact holes penetrating the first lower dielectric layer 120 and the second lower dielectric layer 130 on the cell region CR, forming a lower contact layer filling the lower contact holes on the second lower dielectric layer 130, and planarizing the lower contact layer until the top surface of the second lower dielectric layer 130 is exposed. In the planarization process, the lower electrode contacts 140 may be locally formed in the corresponding lower contact holes.

[0068] A lower electrode layer BEL and a magnetic tunnel junction layer MTJL may be sequentially stacked on the second lower dielectric layer 130. The lower electrode layer BEL and the magnetic tunnel junction layer MTJL may be formed on the second lower dielectric layer 130 on the cell region CR, and the lower electrode layer BEL and the magnetic tunnel junction layer MTJL may extend to the second lower dielectric layer 130 on the boundary region BR and the peripheral region PR. The magnetic tunnel junction layer MTJL may include a first magnetic layer ML1, a tunnel barrier layer TBL, and a second magnetic layer ML2 sequentially stacked on the lower electrode layer BEL. The lower electrode layer BEL and the magnetic tunnel junction layer MTJL may be formed by, for example, sputtering, chemical vapor deposition, or atomic layer deposition.

[0069] A conductive mask pattern CM may be formed on the magnetic tunnel junction layer MTJL on the cell region CR. The conductive mask pattern CM may define a region on which a magnetic tunnel junction pattern MTJ as described below will be formed. The conductive mask patterns CM may be spaced apart from each other in a first direction D1 and a second direction D2 and may include one or more of a metal (e.g., Ta, W, Ru, or Ir) or a conductive metal nitride (e.g., TiN).

[0070] A blocking mask pattern BM can be formed on the magnetic tunnel junction layer MTJL in the peripheral region PR. The blocking mask pattern BM can cover the magnetic tunnel junction layer MTJL in the peripheral region PR and can expose the magnetic tunnel junction layer MTJL in the boundary region BR. The blocking mask pattern BM can include, for example, one or more of silicon nitride and metal nitride.

[0071] Referring to Figure 2 and Figure 7 , a data storage pattern DS includes a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked on the second lower dielectric layer 130. For example, a conductive mask pattern CM can be used as an etch mask to perform a first etching process for etching the magnetic tunnel junction layer MTJL and the lower electrode layer BEL. The first etching process can be, for example, an ion beam etching process using an ion beam. The ion beam can include inert ions. In the first etching process, the magnetic tunnel junction layer MTJL and the lower electrode layer BEL can be etched to form the magnetic tunnel junction pattern MTJ and the bottom electrode BE, respectively.

[0072] Etching the magnetic tunnel junction layer MTJL can include sequentially etching the second magnetic layer ML2, the tunnel barrier layer TBL, and the first magnetic layer ML1. The second magnetic layer ML2, the tunnel barrier layer TBL, and the first magnetic layer ML1 can be etched to form a second magnetic pattern MP2, a tunnel barrier pattern TBP, and a first magnetic pattern MP1, respectively. After the first etching process, the conductive mask pattern CM can remain on the magnetic tunnel junction pattern MTJ, and the remaining portion of the conductive mask pattern CM can be defined as the top electrode TE. The bottom electrode BE, the magnetic tunnel junction pattern MTJ, and the top electrode TE can be referred to as the data storage pattern DS. A plurality of data storage patterns DS can be correspondingly formed on the lower electrode contact 140, and the plurality of data storage patterns DS can be spaced apart from each other in a first direction D1 and a second direction D2.

[0073] The first etching process can cause the upper portion of the second lower dielectric layer 130 located between the plurality of data storage patterns DS to be recessed. Thus, the second lower dielectric layer 130 in the cell region CR can have a top surface 130RU that is recessed toward the substrate 100. The recessed top surface 130RU of the second lower dielectric layer 130 in the cell region CR can be located at a height lower than the height of the top surface 140U of the lower electrode contact 140 and the height of the uppermost surface 130U1 of the second lower dielectric layer 130 in the cell region CR.

[0074] The blocking mask pattern BM can be removed during the first etching process, and the magnetic tunnel junction layer MTJL and the lower electrode layer BEl on the boundary region BR and the peripheral region PR can also be removed during the first etching process. In addition, the first etching process can cause the upper portion of the second lower dielectric layer 130 on the boundary region BR to be recessed.

[0075] The top surface 130U2 of the second lower dielectric layer 130 on the peripheral region PR can be located at a height lower than the height of the uppermost surface 130U1 of the second lower dielectric layer 130 on the cell region CR. The thickness of the blocking mask pattern BM (e.g., the thickness in the third direction D3) can be adjusted such that the top surface 130U2 of the second lower dielectric layer 130 on the peripheral region PR can be located at a height higher or lower than the height of the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR.

[0076] The second lower dielectric layer 130 on the boundary region BR can have a recessed top surface 130RUa, which is located at a height lower than the height of the uppermost surface 130U1 of the second lower dielectric layer 130 on the cell region CR. The blocking mask pattern BM can not be provided on the boundary region BR.

[0077] Referring to Figure 2 and Figure 8 As shown in FIGS. and, the capping dielectric layer 150 extends from the second lower dielectric layer 130 on the cell region CR toward the second lower dielectric layer 130 on the boundary region BR. The capping dielectric layer 150 can cover the top surface and the side surfaces of the data storage pattern DS. On the cell region CR, the capping dielectric layer 150 can conformally cover the top surface and the side surfaces of each of the data storage patterns DS. The capping dielectric layer 150 can conformally cover the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR. The capping dielectric layer 150 can extend onto the second lower dielectric layer 130 on the boundary region BR and can conformally cover the recessed top surface 130RUa of the second lower dielectric layer 130 on the boundary region BR. The capping dielectric layer 150 can extend onto the second lower dielectric layer 130 on the peripheral region PR and can cover the top surface 130U2 of the second lower dielectric layer 130 on the peripheral region PR. The capping dielectric layer 150 can have a top surface that is recessed toward the substrate 100 between the data storage patterns DS.

[0078] A metal seed layer MSL' can be formed on the capping dielectric layer 150 to conformally cover the top surface of the capping dielectric layer 150. The metal seed layer MSL' can cover the recessed top surface of the capping dielectric layer 150. The metal seed layer MSL' can extend from the capping dielectric layer 150 on the cell region CR to the capping dielectric layer 150 on the boundary region BR and the peripheral region PR. For example, the metal seed layer MSL' can be formed by a deposition process. The metal seed layer MSL' can include at least one of, for example, cobalt (Co), iron (Fe), nickel (Ni), and rare earth metals.

[0079] Referring Figure 2 and Figure 9 , a metal layer ML can be deposited on the metal seed layer MSL'. The metal layer ML can conformally cover the top surface of the metal seed layer MSL'. For example, the metal layer ML can be formed by performing an electroplating process in which the metal seed layer MSL' is used as an electrode. As another example, chemical vapor deposition (CVD) can be used to deposit the metal layer ML on the metal seed layer MSL'. The metal layer ML can include the same or similar materials as the metal seed layer MSL'. The metal layer ML can include a magnetic material, such as at least one of: cobalt (Co), iron (Fe), nickel (Ni), and rare earth metals.

[0080] The metal layer ML can be deposited to a thickness equal to or greater than half the distance between adjacent data storage patterns DS. Thus, the metal layer ML can fill the space between the data storage patterns DS, and the metal layer ML can have a top surface with its lowest level ML_U1 higher than the top surface level of the data storage patterns DS.

[0081] The metal layer ML can have a convex top surface on the cell region CR and the boundary region BR, and a flat top surface on the peripheral region PR. The lowest level ML_U1 of the top surface of the metal layer ML on the cell region CR can be higher than the level ML_U2 of the top surface of the metal layer ML on the peripheral region PR.

[0082] Referring Figure 2 and Figure 10 , a part of the metal layer ML can be wet-etched to form a magnetic shielding layer MSL having a top surface MSL_U that is recessed toward the substrate 100 between the data storage patterns DS. The etchant for the wet-etching process can have a higher etching selectivity with respect to the metal layer ML and the metal seed layer MSL' than with respect to the capping dielectric layer 150.

[0083] A magnetic shielding layer MSL can be formed on the cell region CR and the border region BR by a wet etching process without a separate patterning process for the metal layer ML, and no metal material can be left on the peripheral region PR. The magnetic shielding layer MSL can have a top surface MSL_U that is recessed toward the substrate 100 between the data storage patterns DS. The recessed top surface MSL_U of the magnetic shielding layer MSL can be located at a level lower than the level of the top surface of the data storage pattern DS. The level of the recessed top surface MSL_U of the magnetic shielding layer MSL can decrease in the direction from the cell region CR toward the peripheral region PR. In addition, the magnetic shielding layer MSL can be integrally formed to extend from the cell region CR onto the border region BR. The magnetic shielding layer MSL can have an end MSL_br located on the border region BR.

[0084] For example, when the magnetic shielding layer MSL is formed by performing an anisotropic etching process using plasma without performing a wet etching process, it may not be possible to satisfactorily remove the metal seed layer MSL' including ferromagnetic material and the metal layer ML on the peripheral region PR. Therefore, the remaining metal material may cause electrical interference with the wiring pattern on the peripheral region PR. Alternatively, in order to form the magnetic shielding layer MSL by performing a chemical mechanical polishing (CMP) process without using a wet etching process, it may be difficult to separately form a dielectric layer on the capping dielectric layer 150 having a height highly similar to that of the data storage pattern DS on the peripheral region PR. As a result, forming the metal seed layer MSL' and the metal layer ML may complicate the manufacturing process.

[0085] In contrast, in the present disclosure, the capping dielectric layer 150 can be formed on the cell region CR and the peripheral region PR, and then, without forming a separate dielectric layer, the metal seed layer MSL' and the metal layer ML can be formed on the cell region CR and the peripheral region PR. In addition, without separately performing a patterning process on the metal layer ML, an etching process can be performed to completely remove the metal material on the peripheral region PR. The magnetic shielding layer MSL can be formed on the cell region CR simultaneously with the etching process. Therefore, the manufacturing process can be simplified.

[0086] Referring to Figure 2 and Figure 11 , the cell dielectric layer 160 can be formed on the capping dielectric layer 150. The cell dielectric layer 160 can be formed on the capping dielectric layer 150 in the cell region CR to cover the data storage pattern DS and fill the space between the data storage patterns DS. The cell dielectric layer 160 can extend onto the capping dielectric layer 150 in the border region BR and the peripheral region PR. The cell dielectric layer 160 can be formed by using, for example, a high density plasma chemical vapor deposition (HDP CVD) process.

[0087] An upper dielectric layer 170 may be formed on the cell dielectric layer 160. The upper dielectric layer 170 may be formed on the cell dielectric layer 160 in the cell region CR, and the upper dielectric layer 170 may extend onto the cell dielectric layer 160 in the border region BR and the peripheral region PR.

[0088] Referring Figure 2 and Figure 12 , a peripheral opening OP may be formed in the peripheral region PR. In the border region BR, the peripheral opening OP may expose the side surface 170S of the upper dielectric layer 170, the side surface 160S of the cell dielectric layer 160, and the side surface of the capping dielectric layer 150.

[0089] The formation of the peripheral opening OP may include performing a second etching process on the peripheral region PR to remove the upper dielectric layer 170, the cell dielectric layer 160, and the capping dielectric layer 150. For example, the formation of the peripheral opening OP may include forming a cell mask pattern on the upper dielectric layer 170 in the cell region CR and using the cell mask pattern as an etching mask to perform the second etching process. The cell mask pattern may be, for example, a photoresist pattern. Since the second etching process removes the upper dielectric layer 170, the cell dielectric layer 160, and the capping dielectric layer 150 in the peripheral region PR, the top surface of the first lower dielectric layer 120 in the peripheral region PR, the side surface 170S of the upper dielectric layer 170 in the border region BR, the side surface 160S of the cell dielectric layer 160, and the side surface of the capping dielectric layer 150 may be exposed.

[0090] Referring Figure 2 and Figure 13 , a peripheral dielectric layer 180 may be formed to fill the peripheral opening OP. The peripheral dielectric layer 180 may contact the top surface of the first lower dielectric layer 120 in the peripheral region PR, the side surface of the capping dielectric layer 150 in the border region BR, the side surface 160S of the cell dielectric layer 160, and the side surface 170S of the upper dielectric layer 170. The formation of the peripheral dielectric layer 180 may include, for example, forming a dielectric layer to fill the peripheral opening OP and planarizing the dielectric layer until the top surface of the upper dielectric layer 170 is exposed. The dielectric layer may be formed by using, for example, a chemical vapor deposition process. The planarization process may be performed by using, for example, at least one selected from an etch-back process and a chemical mechanical polishing process.

[0091] Referring Figure 2 and Figure 14, a first cell trench 192T may be formed on the cell region CR. The first cell trenches 192T may be spaced apart from each other in the first direction D1 and may extend in the second direction D2. Each of the first cell trenches 192T may have a linear shape extending in the second direction D2 and may expose corresponding data storage patterns DS spaced apart from each other in the second direction D2. Each of the first cell trenches 192T may penetrate the upper dielectric layer 170 and the upper portion of the cell dielectric layer 160. Each of the first cell trenches 192T may expose the top electrode TE of each of the corresponding data storage patterns DS.

[0092] Peripheral trenches 210T may be formed on the peripheral region PR and in the peripheral dielectric layer 180. Each of the peripheral trenches 210T may penetrate the upper portion of the peripheral dielectric layer 180. Peripheral holes 220H may extend from the bottom surface of the peripheral trenches 210T toward the substrate 100. Each of the peripheral holes 220H may penetrate the lower portion of the peripheral dielectric layer 180 and may penetrate the first lower dielectric layer 120 on the peripheral region PR. Each of the peripheral holes 220H may expose the top surface of a corresponding one of the uppermost wiring lines 102.

[0093] Referring again to Figure 2 and Figure 3A , a first cell wire 192 may be formed in a corresponding first cell trench 192T. A peripheral wire portion 210 may be formed in a corresponding peripheral trench 210T, and a peripheral conductive contact portion 220 may be formed in a corresponding peripheral hole 220H. The formation of the first cell wire 192, the peripheral wire portion 210, and the peripheral conductive contact portion 220 may include, for example, forming a conductive layer on the upper dielectric layer 170 and the peripheral dielectric layer 180 to fill the first cell trenches 192T, the peripheral trenches 210T, and the peripheral holes 220H, and planarizing the conductive layer until the top surface 170U of the upper dielectric layer 170 and the top surface 180U of the peripheral dielectric layer 180 are exposed. The planarization process may cause the upper dielectric layer 170, the peripheral dielectric layer 180, and the peripheral wire portion 210 to have top surfaces 170U, 180U, and 210U located at the same height, respectively.

[0094] An upper interlayer dielectric layer 200 may be formed on the cell region CR, the boundary region BR, and the peripheral region PR, and the upper interlayer dielectric layer 200 may cover the top surface 170U of the upper dielectric layer 170, the top surface 192U of the first cell wire 192, the top surface 180U of the peripheral dielectric layer 180, and the top surface 210U of the peripheral wire portion 210.

[0095] A second unit conductive line 196 and a conductive contact 194 may be formed in the upper interlayer dielectric layer 200. The formation of the second unit conductive line 196 and the conductive contact 194 may include, for example, forming a second unit trench penetrating the upper portion of the upper interlayer dielectric layer 200, forming a contact hole penetrating the bottom surface of the second unit trench through the lower portion of the upper interlayer dielectric layer 200, forming a conductive layer on the upper interlayer dielectric layer 200 to fill the second unit trench and the contact hole, and planarizing the conductive layer until the top surface of the upper interlayer dielectric layer 200 is exposed.

[0096] In some embodiments, the side surfaces of the data storage pattern may be surrounded by a magnetic shielding layer exhibiting ferromagnetism. When a magnetic field is formed outside the semiconductor device, most of the magnetic flux caused by the external magnetic field may pass through the magnetic shielding layer, and thus the magnetic flux passing through the data storage pattern may be reduced. Therefore, the data storage pattern may be less affected by the external magnetic field.

[0097] In addition, a wet etching process may be employed to form the magnetic shielding layer. Thus, no magnetic material may be left on the peripheral region, and the manufacturing process may be simplified.

[0098] Although this disclosure contains many specific implementation details, these should not be construed as limitations on the scope that may be claimed. The specific features described in this disclosure in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Moreover, although the features may be described above as acting in a specific combination, in some cases, one or more features of the combination may be excised from the combination, and the combination may be directed to a sub-combination or a variant of the sub-combination.

Claims

1. A semiconductor device comprising: a substrate including a cell region and a peripheral region; a plurality of data storage patterns on the cell region, each of the plurality of data storage patterns comprising a stacked bottom electrode, a magnetic tunnel junction pattern, and a top electrode; as well as a magnetic shielding layer on the cell region and between the plurality of data storage patterns, wherein the magnetic shielding layer surrounds the side surfaces of the plurality of data storage patterns, and The magnetic shielding layer has a top surface that is recessed toward the substrate between the plurality of data storage patterns.

2. The semiconductor device according to claim 1, wherein The plurality of data storage patterns are two-dimensionally arranged along a first direction and a second direction intersecting each other, and Wherein, each of the plurality of data storage patterns extends through the magnetic shielding layer.

3. The semiconductor device according to claim 1, wherein The substrate includes a boundary region between the cell region and the peripheral region, and Wherein, the magnetic shielding layer is on the unit area and the boundary area.

4. The semiconductor device according to claim 3, wherein: An end of the magnetic shielding layer is on the boundary region.

5. The semiconductor device according to claim 1, wherein The magnetic shielding layer surrounds a side surface of the magnetic tunnel junction pattern included in each of the plurality of data storage patterns.

6. The semiconductor device according to claim 1, wherein A top surface of the magnetic shield layer is located at a level higher than a level of a top surface of the magnetic tunnel junction pattern included in each of the plurality of data storage patterns in a vertical direction perpendicular to the top surface, and wherein a bottom surface of the magnetic shielding layer is located at a level lower than a level of a bottom surface of the magnetic tunnel junction pattern included in each of the plurality of data storage patterns along the vertical direction.

7. The semiconductor device according to claim 1 , further comprising a plurality of first cell conductive lines on the plurality of data storage patterns on the cell region, in, A top surface of the magnetic shield layer is located at a level lower than that of bottom surfaces of the plurality of first unit conductive lines in a vertical direction perpendicular to the top surface. 8 . The semiconductor device of claim 1 , further comprising a capping dielectric layer covering a bottom surface of the magnetic shield layer and located between side surfaces of the plurality of data storage patterns and side surfaces of the magnetic shield layer.

9. The semiconductor device according to claim 1, wherein: The magnetic shielding layer includes at least one of cobalt (Co), iron (Fe), nickel (Ni), and a rare earth metal.

10. The semiconductor device according to claim 1, further comprising: a plurality of wiring lines, the plurality of wiring lines being on the substrate; a wiring dielectric layer covering the plurality of wiring lines; as well as A plurality of lower electrode contacts extend through the wiring dielectric layer and connect the plurality of wiring lines to the plurality of data storage patterns.

11. A semiconductor device comprising: a substrate comprising a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; a first lower dielectric layer on the substrate; a second lower dielectric layer located on the first lower dielectric layer at the cell region and the boundary region; a plurality of data storage patterns located on the second lower dielectric layer at the cell region, the plurality of data storage patterns comprising a bottom electrode, a magnetic tunnel junction pattern, and a top electrode stacked sequentially; a capping dielectric layer at the second lower dielectric layer, the capping dielectric layer surrounding side surfaces of the plurality of data storage patterns; a magnetic shielding layer at the capping dielectric layer, the magnetic shielding layer surrounding side surfaces of the plurality of data storage patterns; a unit dielectric layer located at the unit region and the boundary region, the unit dielectric layer covering the plurality of data storage patterns and the magnetic shielding layer; a peripheral dielectric layer located at the first lower dielectric layer at the peripheral region; as well as a plurality of peripheral wiring patterns in the peripheral dielectric layer, the plurality of peripheral wiring patterns extending through the first lower dielectric layer at the peripheral region, The magnetic shielding layer has a top surface recessed toward the substrate between the plurality of data storage patterns.

12. The semiconductor device according to claim 11, wherein A top surface of the magnetic shield layer is located at a level higher than a level of a top surface of the magnetic tunnel junction pattern included in each of the plurality of data storage patterns in a vertical direction perpendicular to the top surface, and wherein a bottom surface of the magnetic shielding layer is located at a level lower than a level of a bottom surface of the magnetic tunnel junction pattern included in each of the plurality of data storage patterns along the vertical direction.

13. The semiconductor device according to claim 11 , further comprising a plurality of first unit conductive lines, the plurality of first unit conductive lines being located on the plurality of data storage patterns on the unit region, in, A top surface of the magnetic shield layer is located at a level lower than that of bottom surfaces of the plurality of first unit conductive lines in a vertical direction perpendicular to the top surface.

14. The semiconductor device according to claim 11, wherein The top surface of the magnetic shielding layer comprises: a first portion in contact with the capping dielectric layer; and a second portion, which is spaced apart from the capping dielectric layer and is located on the center of the top surface, wherein the first portion is located at a level higher than that of the second portion.

15. The semiconductor device according to claim 11, wherein The peripheral dielectric layer and the plurality of peripheral wiring patterns are horizontally spaced apart from the magnetic shield layer.

16. The semiconductor device according to claim 11, wherein A side surface of the peripheral dielectric layer contacts a side surface of the unit dielectric layer and a side surface of the capping dielectric layer.

17. The semiconductor device according to claim 11, further comprising: a plurality of wiring lines, the plurality of wiring lines being on the substrate; a wiring dielectric layer covering the plurality of wiring lines; as well as A plurality of lower electrode contacts extend through the wiring dielectric layer and connect the plurality of wiring lines to the plurality of data storage patterns.

18. A method for manufacturing a semiconductor device, comprising: Providing a substrate, the substrate comprising a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region; forming a wiring dielectric layer and a plurality of wiring structures extending through the wiring dielectric layer on the substrate; sequentially stacking a first lower dielectric layer and a second lower dielectric layer extending from the cell region to the boundary region and the peripheral region on the wiring dielectric layer; forming a plurality of data storage patterns on the cell region, each of the plurality of data storage patterns comprising a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked on the second lower dielectric layer; forming a capping dielectric layer at the second lower dielectric layer located at the cell region and the boundary region, wherein the capping dielectric layer covers top surfaces and side surfaces of the plurality of data storage patterns; depositing a metal layer conformally covering a top surface of the capping dielectric layer; and A portion of the metal layer is wet-etched to form a magnetic shielding layer having a top surface recessed toward the substrate between the plurality of data storage patterns.

19. The method according to claim 18, wherein: Forming the magnetic shielding layer includes removing the metal layer to expose the capping dielectric layer at the peripheral region.

20. The method according to claim 18, wherein: The magnetic shielding layer is on the cell region and the boundary region, and wherein a top surface of the magnetic shielding layer is located at a level lower than that of top surfaces of the plurality of data storage patterns along a vertical direction perpendicular to the top surface of the magnetic shielding layer.

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