LDMOS (Laterally Diffused Metal Oxide Semiconductor) with asymmetric groove structure and manufacturing method
By adopting asymmetric trench structure with high aspect ratio and U-shaped drift zone design in LDMOS devices, the contradiction between breakdown voltage and specific on-resistance of traditional LDMOS devices is solved, and higher integrated density and comprehensive performance are achieved, and production costs are reduced.
Patent Information
- Application Number
- CN202510237279.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-02
- Publication Date
- 2025-06-20
AI Technical Summary
There is a contradiction between increasing the breakdown voltage and reducing the specific on-resistance, and it is difficult to simultaneously improve the forward conduction and blocking voltage resistance of the device. The planar gate and field plate design limit the device's integration and size optimization, and the radiation resistance is weak.
Using an LDMOS device with an asymmetric trench structure, a gate and field plate structure of planar LDMOS are fused to achieve a doping concentration gradient from the source side to the drain side in the drift region, and a multi-layer variable doping is achieved through a photocoat.
Under the condition of maintaining the same level of voltage resistance, the device size is reduced, the integration density is increased, the specific on-resistance is reduced, the device's comprehensive performance is improved, the radiation resistance and surface trace interference resistance are enhanced, and the production cost is reduced.
Smart Images
Figure CN120187068A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology, and relates to an LDMOS with an asymmetric trench structure and a manufacturing method thereof. Background Art
[0002] The laterally diffused metal oxide semiconductor transistor (LDMOS) has received wide attention in the fields of industrial control, radio frequency communication, automotive electronics, etc. due to its good breakdown voltage performance, high process compatibility, and easy integration. In the field of integrated power semiconductor devices, LDMOS has been widely studied for its mature process, easy integration, high voltage resistance, low power consumption, etc., and commercial devices have been successfully developed.
[0003] As Figure 1 shown, taking a traditional N-type LDMOS device as an example, its structure consists of:
[0004] A silicon substrate, which is composed of a P-type epitaxial substrate 100, on which there are an N-type well 101 and a P-type well 102.
[0005] A gate structure, which is composed of a gate polysilicon layer 103, a gate oxide layer 106, and a silicon nitride sidewall 107. The gate structure covers a part of the N-type drift region 101 and the P-type well 102.
[0006] A body region, which is composed of a P-type heavily doped region 104 on the surface of the P-type well 102;
[0007] A source region, which is composed of an N-type heavily doped region 105a on the surface of the P-type well 102;
[0008] A drain region, which is composed of an N-type heavily doped region 105b on the surface of the N-type drift region 101.
[0009] There is a contradictory relationship between improving the breakdown voltage and reducing the specific on-resistance of the LDMOS device, that is, the "silicon limit" relationship. When the LDMOS device conducts forward, only one type of carrier participates in conduction. The on-state loss of the device is mainly determined by the resistance of the drift region, and the blocking voltage withstand performance of the device is mainly determined by the length and doping concentration of the drift region. In order to obtain better blocking voltage withstand performance, the length of the device drift region can be extended or the doping concentration of the device drift region can be reduced, but this measure will lead to a reduction in the forward conduction performance of the device (the resistance increases). Increasing the breakdown voltage may lead to an increase in the specific on-resistance, while reducing the specific on-resistance may reduce the breakdown voltage. This contradiction limits the performance improvement of the LDMOS. Therefore, breaking through the "silicon limit" relationship of the LDMOS and improving the forward conduction and blocking voltage withstand capabilities of the device are particularly important.
[0010] In order to break through the silicon limit relationship of LDMOS, improve the forward conduction and blocking voltage withstand capabilities of the device, and increase the on-state breakdown voltage of the device, traditional LDMOS structures usually incorporate field plate technology and variable doping technology in the drift region.
[0011] As Figure 2 shown, taking an N-type LDMOS device with a field plate and a variable doping drift region as an example, its structure consists of:
[0012] A silicon substrate, composed of a P-type epitaxial substrate 200, on which there are N-type wells 201, 202 with different concentrations and a P-type well 203.
[0013] A field plate structure, forming a shallow trench isolation oxide 204 on the surface of the silicon substrate, which plays a role in expanding the surface electric field of the device and improving the voltage withstand of the device.
[0014] A gate structure, which consists of a gate polysilicon layer 205, a gate oxide layer 208, and a silicon nitride sidewall 209. The gate structure covers part of the N-type drift region 201, the P-type well 203, and the shallow trench isolation oxide 204.
[0015] A variable doping drift region, which consists of N-type wells 201, 202 with different concentrations. The doping concentration of N-type well 201 is less than that of N-type well 202. Among them, N-type well 202 provides additional positive charges during the on-state of the device, compensating for the large amount of negative electron charges injected into the drift region due to the large drain current, increasing the on-state breakdown voltage of the device, and improving the SOA of the device.
[0016] A body region, which consists of a P-type heavily doped region 206 on the surface of the P-type well 203;
[0017] A source region, which consists of an N-type heavily doped region 207a on the surface of the P-type well 203;
[0018] A drain region, which consists of an N-type heavily doped region 207b on the surface of the N-type drift region 201.
[0019] The structure of the LDMOS device with a field plate and a variable doping drift region is simple. However, with the enrichment of application scenarios, the design of the planar gate and the field plate limits the integration and size optimization of the device. Its ability to reconcile the contradiction between the breakdown voltage and the specific on-resistance is limited. Therefore, the power efficiency and comprehensive performance of this device are not high. In addition, the drift region design located on the surface of the device is easily interfered by surface traces, and its radiation resistance ability is weak, affecting the stability of the device in harsh environments. Finally, the use of a variable doping drift region design helps to improve the breakdown voltage. However, in order to achieve the multi-layer doping gradient of the drift region from near the source region to near the drain region, photomasks with different process windows are required, which not only increases the complexity of the production process but also significantly increases the manufacturing cost. Summary of the Invention
[0020] In view of the deficiencies of the prior art, the present invention provides an LDMOS with an asymmetric trench structure and a manufacturing method therefor.
[0021] In a first aspect, the present invention provides an LDMOS device with an asymmetric trench structure, comprising:
[0022] A silicon substrate, composed of a P-type epitaxial substrate, on which there are N-type wells and P-type wells with different concentrations;
[0023] An asymmetric trench structure, composed of oxide and polysilicon. The trench side close to the source is a gate structure, composed of a gate polysilicon layer and a thin gate oxide layer. The trench side close to the drain is a field plate structure, composed of a thick oxide;
[0024] A variable doping drift region, composed of N-type wells with different concentrations. The doping concentration of the N-type well on the side close to the drain is greater than that of the N-type well on the side close to the source;
[0025] A body region, composed of a P-type heavily doped region on the surface of the P-type well;
[0026] A source region, composed of an N-type heavily doped region on the surface of the P-type well;
[0027] A drain region, composed of an N-type heavily doped region on the surface of the N-type drift region.
[0028] Preferably, the aspect ratio of the asymmetric trench structure is greater than 2:1.
[0029] Preferably, the doping concentration of the N-type wells in the variable doping drift region increases in a gradient on the side close to the drain, providing additional positive charge compensation when the device is in the on state.
[0030] Preferably, the thickness of the field plate oxide of the trench structure is much greater than the thickness of the gate oxide, more than 15 times the thickness of the gate oxide.
[0031] Preferably, the longitudinal part of the U-shaped drift region realizes multi-layer variable doping through multiple implantations with a single mask.
[0032] In a second aspect, the present invention provides a method for manufacturing an LDMOS device with an asymmetric trench structure, comprising the following steps:
[0033] Provide an N-type epitaxial substrate, isolate through DTI on the substrate, and define the LDMOS active region;
[0034] Etch the trench, deposit oxide and planarize, etch to retain the bottom oxide, grow a sacrificial layer and then remove it and grow a gate oxide layer, deposit polysilicon, anisotropically cut off the polysilicon at the bottom of the trench, fill with oxide and planarize, selectively etch and remove the polysilicon on the right side of the trench, fill with oxide and planarize to form an asymmetric trench structure;
[0035] Using the same photomask, N-type ions with different energies and doses are implanted on the right side of the trench to form a variably doped N-type buffer region;
[0036] N-type ions and P-type ions are implanted in large doses respectively to form the source region, drain region and body region.
[0037] Preferably, in the trench etching step, the depth of the trench is 1 / 3 to 1 / 2 of the length of the drift region.
[0038] Preferably, in the step of forming the variably doped drift region, the doping concentration gradient from the side close to the source to the side close to the drain is achieved by adjusting the implantation energy and dose.
[0039] Preferably, in the step of forming the asymmetric trench structure, the oxide thickness at the bottom of the trench is greater than the gate oxide thickness and less than the field plate oxide thickness, so as to achieve a gradual increase in the oxide thickness on the silicon surface from the source end to the drain end.
[0040] Preferably, in the step of forming the source region and the drain region, a heavily doped region with low resistivity is achieved by high-dose implantation to reduce the on-resistance of the device.
[0041] Advantages of the present invention:
[0042] 1) The present invention uses an asymmetric trench structure with a high aspect ratio to integrate the gate and field plate structures of the planar LDMOS, making full use of the longitudinal space of the device. Compared with the planar LDMOS, the present invention can reduce the device size, increase the integration density, reduce the specific on-resistance of the device, and achieve better comprehensive performance under the condition of maintaining the same horizontal breakdown voltage.
[0043] 2) The present invention transfers the channel and drift region of the LDMOS from the near surface to the body through the trench structure, improving the radiation resistance and anti-surface routing interference ability of the device.
[0044] 3) The U-shaped drift region structure proposed by the present invention can achieve multi-layer drift region variable doping through multiple implantations of different energies and doses with one photomask. The gradually varying drift region is beneficial to improving the on-state breakdown voltage and SOA of the device. Compared with the planar LDMOS with multi-layer drift region variable doping, the present invention can save photomasks, reduce production costs, and be more economically viable. Description of the Drawings
[0045] Figure 1 is a schematic structural diagram of a conventional N-type LDMOS device;
[0046] Figure 2 is a schematic structural diagram of an N-type LDMOS device with a field plate and a variably doped drift region;
[0047] Figure 3Schematic diagram of the N-type LDMOS device structure with an asymmetric trench structure;
[0048] Figure 4 Are the current paths and electron accumulation regions of two N-type LDMOS devices under the turn-on condition;
[0049] Figure 5 Is the implantation process for forming the graded-doping drift regions of two LDMOSs;
[0050] Figure 6 Is the manufacturing process of the LDMOS device with an asymmetric trench structure;
[0051] Figure 7 Is the manufacturing process of the asymmetric trench structure. Specific implementation mode
[0052] The present invention will be further described below in conjunction with the drawings and embodiments.
[0053] The LDMOS device structure with an asymmetric trench structure proposed in this application is as Figure 3 shown, and includes a substrate, an asymmetric trench structure (the gate structure is on the source-side, and the field plate structure is on the drain-side), a graded-doping drift region, a body region, a source region, and a drain region.
[0054] The silicon substrate is composed of a P-type epitaxial substrate 300, on which there are N-type wells 301, 302 with different concentrations and a P-type well 303.
[0055] The asymmetric trench structure: It is composed of an oxide 304 and polysilicon 305. The trench on the source-side / left side is the gate structure (composed of a gate polysilicon layer 305 and a thin gate oxide 304a), and the trench on the drain-side / right side is the field plate structure (composed of a thick oxide 304b).
[0056] The graded-doping drift region is composed of N-type wells 301, 302 with different concentrations, and the doping concentration of the N-type well 301 is less than that of the N-type well 302.
[0057] The body region is composed of a P-type heavily doped region 306 on the surface of the P-type well 303.
[0058] The source region is composed of an N-type heavily doped region 307a on the surface of the P-type well 303.
[0059] The drain region is composed of an N-type heavily doped region 307b on the surface of the N-type drift region 301.
[0060] The working principle of the LDMOS device with an asymmetric trench structure proposed in this application is as follows:
[0061] As Figure 4As shown in Fig. (b), on the left side of the asymmetric trench structure are the gate oxide and gate polysilicon. Applying a positive bias voltage to the electrode connected to the gate can promote the formation of an inversion layer (longitudinal channel region, as shown by the dashed box in Figure 4 ), thereby controlling the turn-on of the device. Applying a 0 bias voltage controls the device to turn off. On the right side of the asymmetric trench structure is the field plate oxide, whose dielectric constant is lower than that of silicon, which can weaken the peak electric field in the silicon material, expand the electric field on the silicon surface, and make its electric field distribution more uniform so that it is not easily broken down (the function of improving the device breakdown voltage). If a positive potential is applied to the gate, the electric field can be transmitted to the silicon surface through the field plate, causing an electron accumulation region (as shown by the negative charge icon in Figure 4 ), reducing the on-state conduction resistance of the device. Figure 4 The black arrowed line in Figure 4 Fig. (a) shows the current path when the device is turned on. It can be seen that the asymmetric trench structure with a high aspect ratio combines the gate and field plate structures of the planar LDMOS, making full use of the longitudinal space of the device. Compared with the planar LDMOS with a field plate and a variable doping drift region (as shown in
[0062] Fig. (a)), the present invention can reduce the lateral size of the device without changing the length, area, and doping concentration of the drift region (the breakdown voltage remains unchanged), thereby reducing the specific on-resistance of the device (the specific on-resistance is the resistance value per unit area when the device is operating normally), achieving a better trade-off relationship between the breakdown voltage and the specific on-resistance of the device, and enabling the device to have better comprehensive performance. Figure 4 In Figure 4 Fig. (a), the channel region and the drift region of the planar LDMOS device are horizontal and located on the device surface, while the channel region of the trench structure LDMOS is longitudinal, the drift region is U-shaped, and both are far from the device surface, with stronger anti-interference capabilities against external irradiation and surface traces.
[0063] As shown in Figure 5As shown in the figure, in order to improve the on-state breakdown voltage and SOA of the device, the drift region of the device needs to be variably doped from the source side to the drain side (the N-type doping concentration gradually increases). The denser drift region near the drain side can provide additional positive charges when the device is in the on state, compensating for the large amount of negative electron charges injected into the drift region due to the large drain current, thereby increasing the on-state breakdown voltage of the device and improving the SOA of the device. Since the planar LDMOS device has a lateral drift region, multiple implantations are required to achieve variably doped multi-layer drift regions (the process window sizes of the photomasks used for each implantation are different). However, for the LDMOS with an asymmetric trench structure, since it has a U-shaped drift region and the drift region near the drain side has a longitudinal direction, variably doped multi-layer drift regions can be achieved through multiple implantations with different energies and doses using a single photomask (the process window is fixed), saving production costs and being more cost-effective.
[0064] This application also provides a manufacturing method for an LDMOS device with an asymmetric trench structure. The manufacturing process is as Figure 6 shown, where step 602 is the manufacturing process for the asymmetric trench structure. For details, see Figure 7 , and this method at least includes:
[0065] Step 601: Provide an N-type epitaxial substrate, and define the LDMOS active region through DTI isolation on the substrate.
[0066] Step 602: Etch trench 701, deposit oxide and planarize 702, etch to retain the bottom oxide 703, grow a sacrificial layer, remove it, and grow a gate oxide layer 704, deposit polysilicon 705, anisotropically etch the polysilicon at the bottom of the trench 706, fill with oxide and planarize 707, selectively etch and remove the polysilicon on the right side of the trench (near the drain side) 708, fill with oxide and planarize 709 to form an asymmetric trench structure (including a gate structure and a field plate structure).
[0067] Step 603: Use the same photomask to implant N-type ions with different energies and doses on the right side of the trench (near the drain side) to form a variably doped N-type buffer region.
[0068] Step 604: Implant N-type ions and P-type ions at high doses respectively to form the source region, drain region, and body region.
[0069] In summary, this application aims to further break through the silicon limit relationship of LDMOS through innovative structural designs (asymmetric trench structure with high aspect ratio and U-shaped drift region), improve the forward conduction and blocking voltage withstand capabilities of the device, increase the on-state breakdown voltage of the device, reduce the process costs required for variably doped designs, and improve the stability and reliability of the device in complex environments. It solves the performance bottlenecks and manufacturing difficulties in the prior art and promotes the further development of LDMOS device technology.
[0070] Specifically, by introducing an asymmetric trench structure with a high aspect ratio, the device of the present application reduces the size and improves the integration while maintaining excellent breakdown voltage performance, thereby reducing the specific on-resistance and enhancing the power efficiency. In addition, by transferring the drift region from near the surface to the body, the radiation resistance and anti-interference ability of the device are enhanced, ensuring the stability and reliability of the device in a complex environment. Finally, through the design of the U-shaped drift region and the use of a graded doping profile with multiple doping steps, the number of masks is reduced, the production cost is lowered, and at the same time, the on-state breakdown voltage and SOA of the device are improved.
[0071] The present invention is not limited to the above embodiments. Any equivalent changes and modifications made within the scope of the present invention application shall fall within the scope of the present invention.
Claims
1. An LDMOS device having an asymmetric trench structure, characterized in that: include: A silicon substrate, consisting of a P-type epitaxial substrate with N-type wells and P-type wells of different concentrations; An asymmetric trench structure, which is composed of oxide and polysilicon. The trench near the source side is a gate structure, which is composed of a gate polysilicon layer and a thin layer of gate oxide. The trench near the drain side is a field plate structure, which is composed of thick oxide. The variable doping drift region is composed of N-type wells with different concentrations, and the doping concentration of the N-type well near the drain side is greater than that of the N-type well near the source side; The body region consists of a heavily P-doped region on the surface of the P-well; The source region consists of an N-type heavily doped region on the surface of the P-type well; The drain region is composed of an N-type heavily doped region on the surface of the N-type drift region.
2. The LDMOS device with an asymmetric trench structure according to claim 1, characterized in that: The depth-to-width ratio of the asymmetric trench structure is greater than 2:
1.
3. The LDMOS device with an asymmetric trench structure according to claim 1 or 2, characterized in that: The N-type well doping concentration of the variable doping drift region increases in a gradient manner on the side close to the drain, providing additional positive charge compensation when the device is in an on state.
4. The LDMOS device with an asymmetric trench structure according to claim 1 or 2, characterized in that: The field plate oxide thickness of the trench structure is much greater than the gate oxide thickness, which is more than 15 times the gate oxide thickness.
5. The LDMOS device with an asymmetric trench structure according to claim 1, characterized in that: The longitudinal part of the U-shaped drift region is implanted multiple times through one mask to achieve multi-layer variable doping.
6. A method for manufacturing an LDMOS device having an asymmetric trench structure, characterized in that: The following steps are involved: Providing an N-type epitaxial substrate, isolating the substrate through DTI, and defining the LDMOS active area; Etching the trench, depositing oxide and planarizing it, etching to retain the bottom oxide, growing a sacrificial layer and then removing it and growing a gate oxide layer, depositing polysilicon, anisotropically cutting the polysilicon at the bottom of the trench, filling oxide and planarizing it, selectively etching to remove the polysilicon on the right side of the trench, filling oxide and planarizing it, and forming an asymmetric trench structure; Using the same photomask, N-type ions with different energies and doses are distributed and implanted on the right side of the trench to form a variable doped N-type buffer zone. N-type ions and P-type ions are implanted in large doses to form source, drain and body regions.
7. The method for manufacturing an LDMOS device having an asymmetric trench structure according to claim 6, characterized in that: In the trench etching step, the depth of the trench is 1 / 3 to 1 / 2 of the length of the drift region.
8. The method for manufacturing an LDMOS device having an asymmetric trench structure according to claim 6, characterized in that: In the step of forming the variable doping drift region, the doping concentration gradient from the side close to the source to the side close to the drain is achieved by adjusting the implantation energy and the dose.
9. The method for manufacturing an LDMOS device having an asymmetric trench structure according to claim 6 or 8, characterized in that: In the step of forming the asymmetric trench structure, the oxide thickness at the bottom of the trench is greater than the gate oxide thickness and less than the field plate oxide thickness, so as to achieve a gradual increase in the oxide thickness on the silicon surface from the source end to the drain end.
10. The method for manufacturing an LDMOS device having an asymmetric trench structure according to claim 9, characterized in that: In the step of forming the source region and the drain region, a heavily doped region with low resistivity is achieved by high-dose implantation to reduce the on-resistance of the device.