MOSFET device and manufacturing method

Abstract

The present invention relates to the field of MOS semiconductor technology and discloses a MOSFET device and a manufacturing method. The MOSFET device comprises a plurality of mutually parallel MOS cells, wherein each MOS cell includes a drain, a source, a gate, a dielectric layer, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a load P+ layer, a P well layer, and an N well layer. The P well layer includes a P well layer 1 and a P well layer 2, and the cross-sectional profiles of the P well layer 1 and the P well layer 2 are both L-shaped. A conductive dielectric is provided between the P well layer 1 and the P well layer 2, and the gate further includes a U-shaped gate, wherein the opening of the U-shaped gate faces downward and the opening of the U-shaped gate is filled with a high-k dielectric. By filling the U-shaped gate structure with a high-k dielectric, the present invention increases the control area of ​​the gate over the channel, significantly reduces leakage current, while maintaining high gate capacitance, and improving the switching speed and energy efficiency of the device.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a MOSFET device and a manufacturing method thereof. Background Art

[0002] As semiconductor device sizes continue to shrink, traditional SiO2 gate dielectrics in MOSFETs face severe leakage and power consumption issues, leading to reduced device performance. High-k dielectric materials, due to their higher dielectric constant, can provide thicker physical layer thicknesses at the same equivalent oxide thickness (EOT), significantly suppressing gate leakage. However, the integration of high-k materials in existing technologies is often accompanied by problems such as increased interface state density and reduced carrier mobility. Therefore, an innovative device structure and manufacturing method are urgently needed to address these technical bottlenecks by optimizing the coordinated design of the high-k dielectric with the well and drift regions.

[0003] An existing patent discloses a high-performance SGT MOSFET device (CN216597598U). The key technical features of this device are: a MOSFET body virtually divided into a cell region and a ring region; an N+ substrate layer disposed at the bottom of the MOSFET body; an epi1 layer disposed above the N+ substrate layer; and an epi2 layer disposed above the epi1 layer. The technology disclosed in this patent fails to balance the requirements of low on-resistance and high breakdown voltage in the design of the MOSFET's well and drift regions, limiting the device's performance in high-power and high-frequency applications. Summary of the Invention

[0004] The present invention provides a MOSFET device and a manufacturing method to solve the existing technical problems, and solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a MOSFET device is provided, comprising a plurality of mutually parallel MOS cells, wherein a single MOS cell includes a drain, a source, a gate, a dielectric layer, and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a load P+ layer, a P well layer, and an N well layer, wherein the P well layer includes a P well layer 1 and a P well layer 2, and the cross-sectional profiles of the P well layer 1 and the P well layer 2 are both in an "L" shape; and a conductive medium is provided between the P well layer 1 and the P well layer 2.

[0006] Furthermore, the grid also includes a U-shaped grid, wherein the opening of the U-shaped grid faces downward.

[0007] Furthermore, the opening of the U-shaped gate is filled with a high-K dielectric.

[0008] Furthermore, the load P+ layer further includes a bottle-shaped P+ layer, the cross-sectional profile of the bottle-shaped P+ layer is in the shape of a thin top and a round middle, and the bottom end of the bottle-shaped P+ layer contacts the N substrate layer.

[0009] Furthermore, a wide-mouth N heavily doped layer is formed in the middle of the N drift layer by ion implantation, the bottom of the wide-mouth N heavily doped layer contacts the N substrate layer, and the top of the wide-mouth N heavily doped layer extends to the bottom of the gate.

[0010] Furthermore, a beam-mouth N heavily doped layer is formed in the middle of the N drift layer by ion implantation, the cross-sectional width of the beam-mouth N heavily doped layer does not exceed one layer of the P well, and the bottom end of the beam-mouth N heavily doped layer contacts the N substrate layer.

[0011] A method for manufacturing a MOSFET device includes:

[0012] S1. Providing an N-type semiconductor substrate layer as the basic structure of the device;

[0013] S2, epitaxially growing an N drift layer on the N substrate layer to form a low-doped drift region;

[0014] S3. Forming a P-well layer and a P-well layer with an L-shaped cross-section in the N-drift layer through ion implantation and annealing processes, and filling a conductive medium between the P-well layers;

[0015] S4. Forming a load P+ layer and a bottle-shaped P+ layer by ion implantation, wherein the bottle-shaped P+ layer has a cross-sectional shape with a thin top and a round middle, and is in contact with the N substrate layer;

[0016] S5. High-concentration N-type impurities are injected into the middle region of the N drift layer to form a wide-mouth N heavily doped layer and a narrow-mouth N heavily doped layer, which are in contact with the N substrate layer and extend to the bottom of the gate respectively;

[0017] S6, etching to form a U-shaped gate structure with an opening downward, and filling the U-shaped gate opening with a high-K dielectric;

[0018] S7. Metal contacts for the drain, source, and gate are formed respectively through photolithography, deposition, and etching processes.

[0019] Furthermore, in step S6, the filled high-K dielectric includes hafnium dioxide or aluminum oxide.

[0020] Furthermore, in step S7, the MOSFET device with the drain, source and gate formed thereon is subjected to high-temperature annealing to activate the doped ions, and a passivation layer is deposited to protect the device surface.

[0021] The present invention provides a MOSFET device and a manufacturing method. Compared with the prior art, the present method has the following effects:

[0022] 1. The present invention increases the control area of ​​the gate over the channel by filling the high-k dielectric through the U-shaped gate structure, significantly reduces the leakage current, and at the same time maintains a high gate capacitance, thereby improving the switching speed and energy efficiency of the device.

[0023] 2. The present invention adopts a P-well layer with an "L"-shaped cross-section and an intermediate conductive medium, which improves the electric field distribution, reduces the on-resistance, and enhances the carrier migration efficiency, thereby improving the current driving capability.

[0024] 3. The present invention optimizes the contact resistance with the substrate through the cross-sectional design of the bottle-shaped P+ layer with a thin top and a round middle, reduces the conduction loss, and improves the current carrying capacity.

[0025] 4. The present invention uses the wide-mouth and bundle-mouth N heavily doped layer step-by-step injection technology to accurately control the conductivity and electric field distribution of the drift region, taking into account both low on-state voltage drop and high breakdown voltage.

[0026] 5. The present invention reduces parasitic capacitance and process errors through the coordinated optimization of ion implantation and annealing processes, enhances device stability and reliability, and is suitable for high-performance, low-power semiconductor application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of Example 1 of the present invention;

[0028] Figure 2 This is a schematic diagram of Example 2 of the present invention;

[0029] Figure 3 This is a schematic diagram of Example 3 of the present invention;

[0030] Figure 4 This is a schematic diagram of Example 4 of the present invention;

[0031] Figure 5 This is a schematic diagram of Example 5 of the present invention;

[0032] Figure 6 This is a schematic diagram of Example 6 of the present invention;

[0033] Figure 7 A comparison diagram of drain current between Example 1 of the present invention and a conventional structure;

[0034] Figure 8 This is a comparison diagram of the breakdown voltage between Example 1 of the present invention and the traditional structure.

[0035] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Dielectric layer; 5. N substrate layer; 6. N drift layer; 7. Load P+ layer; 8. P well layer 1; 9. P well layer 2; 10. N well layer; 11. Conductive dielectric; 12. High-K dielectric; 13. Wide-mouth N heavily doped layer; 14. Beam-mouth N heavily doped layer; 31. U-shaped gate; 71. Bottle-shaped P+ layer. DETAILED DESCRIPTION

[0036] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] like Figure 1-6 As shown, a method for manufacturing a MOSFET device includes:

[0038] Step 1: providing an N-type semiconductor substrate layer 5 as the basic structure of the device;

[0039] Step 2: epitaxially growing an N drift layer 6 on the N substrate layer 5 to form a low-doped drift region;

[0040] Step 3: Through ion implantation and annealing processes, a P-well layer 8 and a P-well layer 9 with an "L"-shaped cross-section are formed in the N-drift layer 6, and a conductive medium 11 is filled between the P-well layers. The L-shaped P-well layer design and the conductive medium filling simplify the process complexity and improve the structural stability of the well area.

[0041] Step 4: Form a load P+ layer 7 and a bottle-shaped P+ layer 71 through ion implantation, wherein the bottle-shaped P+ layer 71 has a cross-sectional shape with a thin top and a round middle, and is in contact with the N substrate layer 5; the special cross-sectional shape of the bottle-shaped P+ layer 71 is achieved through ion implantation, which accurately controls the doping distribution and reduces process errors.

[0042] Step 5: High-concentration N-type impurities are injected into the middle region of the N-drift layer 6 to form a wide-mouth N-heavily doped layer 13 and a narrow-mouth N-heavily doped layer 14, which are in contact with the N substrate layer 5 and extend to the bottom of the gate. The step-by-step injection of the wide-mouth and narrow-mouth N-heavily doped layers optimizes the conductivity and electric field distribution of the drift region, thereby improving the breakdown performance.

[0043] Step 6: Etch to form a U-shaped gate 31 with a downward opening. Fill the U-shaped gate opening with a high-k dielectric 12. The U-shaped gate 31 structure combined with the high-k dielectric 12 significantly improves gate 3 control efficiency and reduces leakage current, making it suitable for high-performance, low-power scenarios. The high-k dielectric 12 filled in this step can be hafnium dioxide or aluminum oxide.

[0044] Step 7: Through photolithography, deposition and etching processes, metal contacts for the drain 1, source 2 and gate 3 are formed respectively. In this step, the MOSFET device with the drain 1, source 2 and gate 3 formed is subjected to high-temperature annealing to activate the doped ions, and a passivation layer is deposited to protect the device surface.

[0045] Example 1

[0046] like Figure 1 、 7 As shown in Figure 8, according to one aspect of the present invention, a MOSFET device is provided, comprising a plurality of mutually parallel MOS cells. A single MOS cell includes a drain 1, a source 2, a gate 3, a dielectric layer 4, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes an N substrate layer 5, an N drift layer 6, a load P+ layer 7, a P well layer, and an N well layer 10. The P well layer includes a P well layer 1 8 and a P well layer 2 9, and the cross-sectional profiles of the P well layer 1 8 and the P well layer 2 9 are both L-shaped. A conductive dielectric 11 is provided between the P well layer 1 8 and the P well layer 2 9. A unique well region structure is formed by the L-shaped cross-section of the P well layer 1 8 and the P well layer 2 9 and the conductive dielectric 11 in between, thereby optimizing the well region electric field distribution, reducing the on-resistance, enhancing the carrier migration efficiency, and improving the current driving capability of the device.

[0047] Example 2

[0048] like Figure 2 As shown, the P-well layer includes a first P-well layer 8 and a second P-well layer 9, each of which has an L-shaped cross-sectional profile. A conductive dielectric 11 is disposed between the first P-well layer 8 and the second P-well layer 9. Gate 3 also includes a U-shaped gate 31 with its opening facing downward. By introducing the downward-facing U-shaped gate 31, the gate's control area over the channel is increased, improving gate control capability, lowering the threshold voltage, and increasing switching speed.

[0049] Example 3

[0050] like Figure 3 As shown, the P-well layer includes a first P-well layer 8 and a second P-well layer 9, each of which has an L-shaped cross-sectional profile. A conductive dielectric 11 is disposed between the first P-well layer 8 and the second P-well layer 9. Gate 3 also includes a U-shaped gate 31, with its opening facing downward and filled with a high-k dielectric 12. Filling the U-shaped gate opening with high-k dielectric 12 (such as hafnium dioxide or aluminum oxide) leverages the dielectric constant advantage of the high-k material to significantly reduce gate leakage current, maintain a high gate capacitance, and enhance device energy efficiency.

[0051] In the preparation of MOSFET devices, high-K dielectric refers to an insulating material with a dielectric constant (dielectric constant is also known as K value) greater than that of traditional silicon dioxide, and is used to increase the breakdown resistance of traditional silicon dioxide when used as the dielectric layer 4.

[0052] Example 4

[0053] like Figure 4 As shown, the P-well layer includes a first P-well layer 8 and a second P-well layer 9, both of which have an L-shaped cross-section. A conductive medium 11 is disposed between the first P-well layer 8 and the second P-well layer 9. The load P+ layer 7 also includes a bottle-shaped P+ layer 71, which has a thin top and a rounded middle cross-section. The bottom of the bottle-shaped P+ layer 71 contacts the N-substrate layer 5. By designing the bottle-shaped P+ layer 71 with a thin top and a rounded middle cross-section and contacting the N-substrate layer 5, the contact resistance between the P+ layer and the substrate is optimized, reducing overall conduction losses, improving carrier injection efficiency, and enhancing the current-carrying capacity of the device.

[0054] Example 5

[0055] like Figure 5 As shown, the P-well layer includes a first P-well layer 8 and a second P-well layer 9, each of which has an L-shaped cross-sectional profile. A conductive medium 11 is provided between the first P-well layer 8 and the second P-well layer 9. A wide-mouth N-heavily doped layer 13 is formed in the middle of the N-drift layer 6 through ion implantation. The bottom of the wide-mouth N-heavily doped layer 13 contacts the N-substrate layer 5, and the top of the wide-mouth N-heavily doped layer 13 extends to the bottom of the gate 3. By forming the wide-mouth N-heavily doped layer 13 in the middle of the N-drift layer 6 and extending it to the bottom of the gate, the conductivity of the drift region is enhanced, the on-state voltage drop is reduced, and the heavily doped layer expands the electric field distribution, thereby increasing the breakdown voltage.

[0056] Example 6

[0057] like Figure 6 As shown, the P-well layer includes a first P-well layer 8 and a second P-well layer 9, both of which have an L-shaped cross-section. A conductive dielectric 11 is disposed between the first P-well layer 8 and the second P-well layer 9. The load P+ layer 7 also includes a bottle-shaped P+ layer 71, which has a narrow top and a rounded center. The bottom of the bottle-shaped P+ layer 71 contacts the N substrate layer 5. A beam-mouth N-heavily doped layer 14 is formed in the center of the N-drift layer 6 through ion implantation. The beam-mouth N-heavily doped layer 14 has a cross-sectional width that does not exceed that of the first P-well layer 8, and the bottom of the beam-mouth N-heavily doped layer 14 contacts the N substrate layer 5. By combining the bottle-shaped P+ layer 71 with the beam-mouth N-heavily doped layer 14, whose width does not exceed that of the first P-well layer 8, the beam-mouth design precisely controls the doping region, reduces parasitic capacitance, and synergistically optimizes the P+ and N-heavily doped layers, further reducing dynamic losses and improving reliability.

[0058] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A MOSFET device, comprising a plurality of mutually parallel MOS cells, wherein each MOS cell comprises a drain (1), a source (2), a gate (3), a dielectric layer (4) and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer (5), an N drift layer (6), a load P+ layer (7), a P well layer and an N well layer (10), characterized in that: The P-well layer comprises a first P-well layer (8) and a second P-well layer (9), and the cross-sectional profiles of the first P-well layer (8) and the second P-well layer (9) are both in an "L" shape; a conductive medium (11) is provided between the first P-well layer (8) and the second P-well layer (9); The gate (3) further comprises a U-shaped gate (31), wherein the opening of the U-shaped gate (31) faces downward; The opening of the U-shaped gate (31) is filled with a high-K medium (12).

2. A MOSFET device, comprising a plurality of mutually parallel MOS cells, wherein each of the MOS cells comprises a drain (1), a source (2), a gate (3), a dielectric layer (4), and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer (5), an N drift layer (6), a load P+ layer (7), a P well layer, and an N well layer (10), characterized in that: The P-well layer comprises a P-well layer (8) and a P-well layer (9), and the cross-sectional profiles of the P-well layer (8) and the P-well layer (9) are both in an "L" shape; A conductive medium (11) is provided between the P-well layer (8) and the P-well layer (9); The load P+ layer (7) further includes a bottle-shaped P+ layer (71), the cross-sectional profile of the bottle-shaped P+ layer (71) being in the shape of a thin top and a round middle, and the bottom end of the bottle-shaped P+ layer (71) is in contact with the N substrate layer (5).

3. The MOSFET device according to claim 2, wherein: A wide-mouth N heavily doped layer (13) is formed in the middle of the N drift layer (6) by ion implantation, the bottom of the wide-mouth N heavily doped layer (13) is in contact with the N substrate layer (5), and the top of the wide-mouth N heavily doped layer (13) extends to the bottom of the gate (3); The wide-mouth N heavily doped layer (13) is in a wide-mouth shape that is wide at the bottom and narrow at the top.

4. The MOSFET device according to claim 2, wherein: A beam-mouth N heavily doped layer (14) is formed in the middle of the N drift layer (6) by ion implantation, wherein the cross section of the beam-mouth N heavily doped layer (14) does not exceed the width of the region between two P well layers (8) in the MOS cell; and the bottom end of the beam-mouth N heavily doped layer (14) is in contact with the N substrate layer (5); The beam-mouth N heavily doped layer (14) is in a beam-mouth shape that gradually narrows from top to bottom.

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