Table-top transistor and manufacturing method thereof

Abstract

The embodiment of the invention provides a mesa transistor and a manufacturing method thereof, and relates to the technical field of semiconductor manufacturing. The mesa transistor comprises a single crystal substrate, a first doped region, a mesa groove, an isolation oxide layer, a semi-insulating polycrystalline silicon layer and a floating field plate. The isolation oxide layer is located between the single-crystal substrate and the semi-insulating polycrystalline layer, an ohmic current path between the single-crystal substrate and the semi-insulating polycrystalline layer in a high-temperature environment can be effectively blocked, the leakage current of the mesa transistor is greatly reduced, the reliability of the mesa transistor is improved, and the working temperature range of the mesa transistor is widened. And the floating field plate penetrates through the semi-insulating polycrystalline silicon layer and the isolation oxide layer and is in contact with the single crystal substrate and the semi-insulating polycrystalline silicon layer, and the floating field plate has no lead and is equipotential with the cathode, so that the voltage is applied to the semi-insulating polycrystalline silicon layer when the device is reversely biased, and the electrical isolation failure of the device is avoided. Meanwhile, the floating field plate can also optimize the electric field distribution on the surface of the single crystal substrate, reduce the peak electric field intensity and effectively improve the breakdown voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more particularly, to a mesa transistor and a method for manufacturing the same. Background Art

[0002] As an important power electronic device, the mesa transistor plays a key role in high-voltage and high-current application scenarios. However, there are some problems in the existing mesa transistors, such as large leakage current in high-temperature environments and limited improvement in breakdown voltage. These problems limit the application of mesa transistors in higher-voltage and higher-temperature environments. Therefore, how to improve the performance of mesa transistors, reduce leakage current, and increase breakdown voltage has become an urgent problem for those skilled in the art. Summary of the Invention

[0003] In order to at least overcome the above deficiencies in the prior art, the purpose of this application is to provide a mesa transistor and a method for manufacturing the same.

[0004] In a first aspect, an embodiment of this application provides a mesa transistor, which includes:

[0005] A single-crystal substrate, the single-crystal substrate includes a first surface;

[0006] A first doping region, the first doping region is located on the first surface;

[0007] A mesa trench, the mesa trench is located on the first surface, and the mesa trench is adjacent to the first doping region;

[0008] An isolation oxide layer, the isolation oxide layer covers the surface of the mesa trench and the first surface;

[0009] A semi-insulating polysilicon layer, the semi-insulating polysilicon layer is located on the side of the isolation oxide layer away from the single-crystal substrate;

[0010] A floating field plate, at least part of the floating field plate is located on the side of the semi-insulating polysilicon layer away from the single-crystal substrate and surrounds the periphery of the mesa trench. The floating field plate penetrates through the semi-insulating polysilicon layer and the isolation oxide layer and contacts the single-crystal substrate and the semi-insulating polysilicon layer.

[0011] In a possible implementation, the mesa transistor further includes a glass passivation layer and a protective layer. The glass passivation layer is filled in the mesa trench, and the protective layer is located on the side of the isolation oxide layer and the glass passivation layer away from the single-crystal substrate.

[0012] In a possible implementation, the mesa transistor further includes via holes that are disposed around the mesa trench and penetrate through the protective layer, the semi-insulating polysilicon layer, and the isolation oxide layer;

[0013] The floating field plate is located inside the via holes and on the side of the semi-insulating polysilicon layer away from the single-crystal substrate, and the floating field plate is in contact with the single-crystal substrate and the semi-insulating polysilicon layer.

[0014] In a possible implementation, in the direction perpendicular to the plane where the single-crystal substrate is located, the radius of the mesa trench gradually increases.

[0015] In a possible implementation, the single-crystal substrate further includes a second surface opposite to the first surface, and the mesa transistor further includes a first electrode and a second electrode;

[0016] The first electrode is located on the first surface, the first electrode penetrates through the protective layer, the semi-insulating polysilicon layer, and the isolation oxide layer, and the orthographic projection of the mesa trench on the single-crystal substrate surrounds the orthographic projection of the first electrode on the single-crystal substrate;

[0017] The second electrode is located on the second surface.

[0018] In a second aspect, an embodiment of the present application further provides a method for manufacturing a mesa transistor, the method including:

[0019] Providing a single-crystal substrate, the single-crystal substrate including a first surface;

[0020] Doping the single-crystal substrate to form a first doped region, and forming a mesa trench on the first surface, wherein the mesa trench is adjacent to the first doped region;

[0021] Fabricating an isolation oxide layer covering the surface of the mesa trench and the first surface, and fabricating a semi-insulating polysilicon layer on the side of the isolation oxide layer away from the single-crystal substrate;

[0022] Fabricating a floating field plate that penetrates through the semi-insulating polysilicon layer and the isolation oxide layer, wherein the floating field plate is at least partially located on the side of the semi-insulating polysilicon layer away from the single-crystal substrate and surrounds the periphery of the mesa trench, and is in contact with the single-crystal substrate and the semi-insulating polysilicon layer.

[0023] In a possible implementation, before the step of fabricating the floating field plate that penetrates through the semi-insulating polysilicon layer and the isolation oxide layer, the method further includes:

[0024] Apply glass powder in the mesa trench, and sinter the mesa trench coated with glass powder to form a glass passivation layer;

[0025] Fabricate a protective layer on the side of the glass passivation layer and the isolation oxide layer away from the single crystal substrate.

[0026] In a possible implementation manner, the step of fabricating the floating field plate penetrating the semi-insulating polysilicon layer and the isolation oxide layer includes:

[0027] Perform patterning on the protective layer, the semi-insulating polysilicon layer and the isolation oxide layer to form lead holes and routing holes penetrating the protective layer, the semi-insulating polysilicon layer and the isolation oxide layer. The lead holes surround the mesa trench, and the orthographic projection of the mesa trench on the single crystal substrate surrounds the orthographic projection of the routing hole on the single crystal substrate;

[0028] Perform metal deposition on the single crystal substrate after forming the lead holes and the routing holes to form a floating field plate located in the lead holes and on the side of the semi-insulating polysilicon layer away from the single crystal substrate, and a first electrode at least partially located in the routing holes. Among them, the floating field plate is in contact with the single crystal substrate and the semi-insulating polysilicon layer.

[0029] In a possible implementation manner, the single crystal substrate includes a second surface opposite to the first surface. After the step of fabricating the floating field plate penetrating the semi-insulating polysilicon layer and the isolation oxide layer, the method further includes:

[0030] Perform metal deposition on the single crystal substrate to form a second electrode on the second surface.

[0031] In a possible implementation manner, the step of doping the single crystal substrate to form a first doping region and forming a mesa trench surrounding the first doping region on the first surface includes:

[0032] Form at least one annular masking layer on the first surface, and dope the single crystal substrate based on the masking layer to form a first doping region located on the first surface. The first doping region forms a doped region with a slope in the region covered by the masking layer;

[0033] Fabricate a photoresist layer on the first surface, expose and develop the photoresist layer to obtain a photoresist layer that at least exposes part of the first surface;

[0034] Etch the first surface region exposed by the photoresist layer to obtain a mesa trench surrounding the first doping region. Among them, in the direction perpendicular to the plane where the single crystal substrate is located, the radius of the mesa trench gradually increases.

[0035] Based on any of the above aspects, the mesa transistor and its manufacturing method provided by the embodiments of the present application include a single-crystal substrate, a first doped region, a mesa trench, an isolation oxide layer, a semi-insulating polysilicon layer, and a floating field plate. The isolation oxide layer is located between the single-crystal substrate and the semi-insulating polysilicon layer. The floating field plate penetrates through the semi-insulating polysilicon layer and the isolation oxide layer and contacts the single-crystal substrate and the semi-insulating polysilicon layer. In the above structure, by adding an isolation oxide layer between the single-crystal substrate and the semi-insulating polysilicon layer, the ohmic current path between the single-crystal substrate and the semi-insulating polysilicon layer in a high-temperature environment can be effectively blocked, the leakage current of the mesa transistor can be greatly reduced, and the reliability and operating temperature range of the mesa transistor can be improved. In addition, a floating field plate that contacts the single-crystal substrate and the semi-insulating polysilicon layer is provided. The floating field plate has no lead and is equipotential with the cathode, so that when the device is reverse-biased, the voltage is applied to the semi-insulating polysilicon layer to avoid electrical isolation failure. At the same time, the floating field plate can also optimize the surface electric field distribution of the single-crystal substrate, reduce the peak electric field intensity, and effectively improve the breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be referred to in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 is a schematic structural diagram of a mesa transistor in the related art;

[0038] Figure 2 is a schematic structural diagram of the mesa transistor provided by the embodiments of the present application Figure 1 ;

[0039] Figure 3 is a schematic structural diagram of the mesa transistor provided by the embodiments of the present application Figure 2 ;

[0040] Figure 4 is a schematic flow chart of the manufacturing method of the mesa transistor provided by the embodiments of the present application;

[0041] Figure 5 is Figure 4 the corresponding process chart. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are some, but not all, of the embodiments of this application. The components of the embodiments of this application generally described and illustrated in the accompanying drawings here can be arranged and designed in a variety of different configurations.

[0043] Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of this application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of this application without creative efforts fall within the scope of protection of this application.

[0044] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings.

[0045] In the description of this application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship in which the product of this application is customarily placed during use. This is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of this application. In addition, terms such as "first", "second", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0046] In the description of this application, it should also be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "coupled", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] It should be noted that, without conflict, the different features in the embodiments of this application can be combined with each other.

[0048] Such as Figure 1As shown, the inventors have found that mesa transistors 10 generally adopt a design of a semi-insulating polysilicon layer 140 (i.e., a SIPOS layer) combined with a glass passivation layer 160. The surface electric field distribution is optimized through the electric field modulation function of the semi-insulating polysilicon to increase the breakdown voltage. However, since the single-crystal substrate 110 is in direct contact with the semi-insulating polysilicon layer 140, this may form an ohmic current path between the two, resulting in a sharp increase in the leakage current as the temperature rises, greatly limiting the operating temperature range and reliability of the device.

[0049] Some related technologies usually increase the breakdown voltage of mesa transistors by increasing the chip resistivity, junction depth, or terminal area, etc., in order not to affect the high-temperature parameters of the device. However, the inventors have found in practice that the correlation between these methods and the breakdown voltage is insufficient. In the mesa terminal structure, the electric field strength is highly concentrated at the position where the PN junction intersects the mesa trench (i.e., Figure 1 the P point shown). Simulation examples show that the field strength at the edge here is more than two orders of magnitude greater than that in the internal region. In other words, reducing the electric field strength at P is the key to increasing the breakdown voltage. Although methods such as increasing the resistivity or junction depth can optimize the electric field distribution to a certain extent, these methods are not only costly but also have limited effects and cannot fundamentally solve the problem.

[0050] Some other related technologies may optimize the device performance by adjusting the parameters of the glass passivation layer 160, such as adjusting the type of glass powder, coating times, or sintering temperature, etc. However, the above methods still have significant limitations. Exemplarily, if the coating times of the glass powder are increased to increase the thickness of the glass passivation layer 160, although the breakdown voltage of the mesa transistor can be increased, the high-temperature leakage current will also increase; while if the coating times of the glass powder are reduced, although the high-temperature leakage current can be reduced, the thinning of the thickness of the glass passivation layer 160 may limit the improvement effect of the breakdown voltage of the mesa transistor, and in production, it is easy to have the situation of photoresist falling off due to the height difference between the glass passivation layer 160 and the surface, resulting in the problem of via hole etching.

[0051] To solve the problems in the prior art, please refer to Figure 2 , an embodiment of the present application provides a mesa transistor 10, which includes a single-crystal substrate 110, a first doping region 120, a mesa trench, an isolation oxide layer 130, a semi-insulating polysilicon layer 140, and a floating field plate 150. Among them, the single-crystal substrate 110 may include an N-type single-crystal substrate 110 or a P-type single-crystal substrate 110. Exemplarily, the single-crystal substrate 110 is an N-type single-crystal substrate.

[0052] The single-crystal substrate 110 may include a first surface, a first doped region 120 and mesa trenches are located on the first surface, and the mesa trenches are adjacent to the first doped region 120. Among them, the doping type of the first doped region 120 is different from that of the single-crystal substrate 110, and a PN junction is formed between the edge of the first doped region 120 and the single-crystal substrate 110.

[0053] The isolation oxide layer 130 covers the surface of the mesa trenches and the first surface, and a semi-insulating polycrystalline layer is located on the side of the isolation oxide layer 130 away from the single-crystal substrate 110. Among them, the isolation oxide layer 130 may include a silicon nitride layer and a thin oxide layer. By adding the isolation oxide layer 130 between the single-crystal substrate 110 and the semi-insulating polycrystalline layer, the ohmic current path between the single-crystal substrate 110 and the semi-insulating polycrystalline layer in a high-temperature environment can be effectively blocked, the leakage current of the mesa transistor 10 can be greatly reduced, and the reliability and operating temperature range of the mesa transistor 10 can be improved.

[0054] The floating field plate 150 is at least partially located on the side of the semi-insulating polysilicon layer 140 away from the single-crystal substrate 110 and surrounds the periphery of the mesa trenches. The floating field plate 150 penetrates through the semi-insulating polysilicon layer 140 and the isolation oxide layer 130 and contacts the single-crystal substrate 110 and the semi-insulating polysilicon layer 140. The floating field plate 150 has no lead and is equipotential with the cathode, so that the voltage when the device is reverse-biased can be applied to the semi-insulating polysilicon layer 140 to avoid its electrical isolation failure. At the same time, the floating field plate 150 can also optimize the surface electric field distribution of the single-crystal substrate 110, reduce the peak electric field intensity, and effectively improve the breakdown voltage. Specifically, under the action of the floating field plate 150, there is a certain potential difference between the semi-insulating polycrystalline layer and the source region metal, and this potential difference can effectively optimize the surface electric field distribution, make the electric field more evenly distributed on the surface of the device, reduce the peak electric field intensity, and improve the breakdown voltage.

[0055] In this embodiment, by adding the isolation oxide layer 130 between the single-crystal substrate 110 and the semi-insulating polycrystalline layer, the ohmic current path between the single-crystal substrate 110 and the semi-insulating polycrystalline layer in a high-temperature environment can be effectively blocked, the leakage current of the mesa transistor 10 can be greatly reduced, and the reliability and operating temperature range of the mesa transistor 10 can be improved. In addition, by providing the floating field plate 150 in contact with the single-crystal substrate 110 and the semi-insulating polysilicon layer 140, the floating field plate 150 has no lead and is equipotential with the cathode, so that the voltage when the device is reverse-biased can be applied to the semi-insulating polysilicon layer 140 to avoid its electrical isolation failure, and at the same time, it can also optimize the surface electric field distribution of the single-crystal substrate 110, reduce the peak electric field intensity, and effectively improve the breakdown voltage.

[0056] In some possible embodiments, please refer to again Figure 2, the mesa transistor 10 further includes a glass passivation layer 160 and a protective layer 170. The glass passivation layer 160 is filled in the mesa trench, and the protective layer 170 is located on the side of the isolation oxide layer 130 and the glass passivation layer 160 away from the single crystal substrate 110. Among them, in the direction perpendicular to the plane where the single crystal substrate 110 is located, the radius of the mesa trench gradually increases, and the depth of the mesa trench is greater than the depth of the first doping region 120. The glass passivation layer 160 can not only effectively improve the surface defects of the sidewall of the mesa trench, but also prevent external contaminants (such as moisture, dust, and chemical impurities, etc.) from invading the device interior through the sidewall of the mesa trench, reducing the influence of the environment on the device performance, while the protective layer 170 can protect the glass passivation layer 160 from external damage. Exemplarily, the protective layer 170 may include an LPCVD oxide layer.

[0057] Furthermore, the mesa transistor 10 further includes via holes, which are arranged around the mesa trench and penetrate through the protective layer 170, the semi-insulating polysilicon layer 140, and the isolation oxide layer 130. The floating field plate 150 is located in the via holes and on the side of the semi-insulating polysilicon layer 140 away from the single crystal substrate 110, and the floating field plate 150 is in contact with the single crystal substrate 110 and the semi-insulating polysilicon layer 140, so that the single crystal substrate 110 and the semi-insulating polysilicon layer 140 are in an equipotential state, that is, the potential difference between the two is zero, thus avoiding the generation of a significant ohmic current between the two in a high-temperature environment, thereby achieving the purpose of reducing the leakage current.

[0058] Furthermore, please refer to Figure 3 , the mesa transistor 10 further includes a first electrode A and a second electrode K. The first electrode A is located on the first surface, and the first electrode A penetrates through the protective layer 170, the semi-insulating polysilicon layer 140, and the isolation oxide layer 130, and the positive projection of the mesa trench on the single crystal substrate surrounds the positive projection of the first electrode A on the single crystal substrate, that is, the mesa trench is arranged around the first electrode A. The second electrode T2 is located on the second surface of the single crystal substrate 110 opposite to the first surface, where the first electrode A can be an anode and the second electrode K can be a cathode.

[0059] In the above structure, the first electrode A can be fabricated synchronously with the floating field plate 150. Specifically, via holes and routing holes penetrating through the protective layer 170, the semi-insulating polysilicon layer 140, and the isolation oxide layer 130 can be fabricated synchronously, and then metal deposition is performed on the single crystal substrate 110 with the fabricated via holes and routing holes to form at least part of the floating field plate 150 located in the via holes and at least part of the first electrode A located in the routing holes. In this way, the cost of fabricating the floating field plate 150 can be effectively reduced, and the production efficiency can be improved.

[0060] Based on the same inventive concept, the present application also provides a method for fabricating a mesa transistor 10. Specifically, please refer to Figure 4 andFigure 5 , Figure 4 is a schematic flow chart of a method for fabricating a mesa transistor 10, Figure 5 and Figure 4 is the corresponding process flow chart. The following will describe each step of the method for fabricating the mesa transistor 10 in detail with reference to Figure 4 and Figure 5 .

[0061] Step S110: Provide a single crystal substrate.

[0062] In this step, the single crystal substrate 110 includes a first surface. The single crystal substrate 110 may include an N-type single crystal substrate 110 or a P-type single crystal substrate 110. Exemplarily, the single crystal substrate 110 is an N-type single crystal substrate.

[0063] Step S120: Dope the single crystal substrate to form a first doped region and form a mesa trench on the first surface.

[0064] In this step, a first doped region 120 may be formed on the first surface first. The doping type of the first doped region 120 is different from that of the single crystal substrate 110. The edge of the first doped region 120 forms a PN junction with the single crystal substrate 110. Exemplarily, when the single crystal substrate is an N-type single crystal substrate, the first doped region 120 is a P-type doped region.

[0065] Next, a photoresist layer is fabricated on the first surface, exposed and developed, and a photoresist layer that exposes at least a part of the first surface is obtained. Finally, the first surface region exposed by the photoresist layer is etched to obtain a mesa trench adjacent to the first doped region 120. Among them, in the direction perpendicular to the plane where the single crystal substrate 110 is located, the radius of the mesa trench gradually increases, and the depth of the mesa trench is greater than the depth of the first doped region 120.

[0066] Step S130: Fabricate an isolation oxide layer covering the surface of the mesa trench and the first surface, and fabricate a semi-insulating polysilicon layer on the side of the isolation oxide layer away from the single crystal substrate.

[0067] In this step, the single crystal substrate 110 on which the mesa trench is formed may be deposited to sequentially form an isolation oxide layer 130 and a semi-insulating polysilicon layer 140. The isolation oxide layer 130 may include a silicon nitride layer and a thin oxide layer.

[0068] After this step, glass powder can also be coated in the mesa trench first, and the mesa trench coated with glass powder is sintered to form a glass passivation layer 160. The glass passivation layer 160 not only improves the surface defects of the mesa trench sidewall, but also can prevent external contaminants (such as moisture, dust, and chemical impurities, etc.) from invading the device interior through the mesa trench sidewall, reducing the influence of the environment on the device performance. Then, a protective layer 170 is fabricated on the side of the glass passivation layer 160 and the isolation oxide layer 130 away from the single crystal substrate 110 to protect the glass passivation layer 160 from external damage. Exemplarily, the protective layer 170 can include an LPCVD oxide layer.

[0069] Step S140: Fabricate a floating field plate 150 that penetrates the semi-insulating polysilicon layer and the isolation oxide layer.

[0070] In this step, the floating field plate 150 has no lead and is at the same potential as the cathode, so that the voltage during device reverse bias can be applied to the semi-insulating polysilicon layer 140 to avoid its electrical isolation failure. At the same time, the floating field plate 150 can also optimize the surface electric field distribution of the single crystal substrate 110, reduce the peak electric field intensity, and effectively improve the breakdown voltage. Specifically, under the action of the floating field plate 150, there is a certain potential difference between the semi-insulating polysilicon layer and the source region metal, and this potential difference can effectively optimize the surface electric field distribution, making the electric field more evenly distributed on the device surface, reducing the peak electric field intensity, and increasing the breakdown voltage.

[0071] In this embodiment, by adding an isolation oxide layer 130 between the single crystal substrate 110 and the semi-insulating polysilicon layer 140, the ohmic current path between the single crystal substrate 110 and the semi-insulating polysilicon layer 140 in a high-temperature environment can be effectively blocked, greatly reducing the leakage current of the mesa transistor 10 and improving the reliability and operating temperature range of the mesa transistor 10. In addition, a floating field plate 150 in contact with the single crystal substrate 110 and the semi-insulating polysilicon layer 140 is provided. The floating field plate 150 has no lead and is at the same potential as the second electrode K (i.e., the cathode), so that the voltage during device reverse bias can be applied to the semi-insulating polysilicon layer 140 to avoid its electrical isolation failure. At the same time, the floating field plate 150 can also optimize the surface electric field distribution of the single crystal substrate 110, reduce the peak electric field intensity, and effectively improve the breakdown voltage.

[0072] Further, in step S150, the protective layer 170, semi-insulating polysilicon layer 140, and isolation oxide layer 130 located outside the mesa trench can be patterned first to form lead holes and routing holes. The lead holes and routing holes penetrate through the protective layer 170, semi-insulating polysilicon layer 140, and isolation oxide layer 130. The positive projection of the mesa trench on the single-crystal substrate 110 surrounds the positive projection of the routing hole on the single-crystal substrate 110, that is, the mesa trench is arranged around the routing hole, and the lead holes are arranged around the mesa trench. Then, metal deposition is performed on the single-crystal substrate 110 with the lead holes fabricated to form a floating field plate 150 located inside the lead holes and on the side of the semi-insulating polysilicon layer 140 away from the single-crystal substrate 110, and a first electrode A at least partially located inside the routing hole. The floating field plate 150 is in contact with the single-crystal substrate 110 and the semi-insulating polysilicon layer 140, and the first electrode A can be an anode. In this way, the cost of fabricating the floating field plate 150 can be effectively reduced, and the production efficiency can be improved.

[0073] After step S140, metal deposition can also be performed on the single-crystal substrate 110 to form a nickel-titanium-silver alloy layer, and the nickel-titanium-silver alloy layer is polished to form a second electrode K on the second surface, where the second electrode K can be an anode.

[0074] In summary, the embodiment of the present application provides a mesa transistor and a manufacturing method thereof. The mesa transistor includes a single-crystal substrate, a first doping region, a mesa trench, an isolation oxide layer, a semi-insulating polysilicon layer, and a floating field plate. The isolation oxide layer is located between the single-crystal substrate and the semi-insulating polysilicon layer. The floating field plate is at least partially located on the side of the semi-insulating polysilicon layer away from the single-crystal substrate and surrounds the periphery of the mesa trench. The floating field plate penetrates through the semi-insulating polysilicon layer and the isolation oxide layer and is in contact with the single-crystal substrate and the semi-insulating polysilicon layer. In the above structure, by adding an isolation oxide layer between the single-crystal substrate and the semi-insulating polysilicon layer, the ohmic current path between the single-crystal substrate and the semi-insulating polysilicon layer in a high-temperature environment can be effectively blocked, the leakage current of the mesa transistor can be greatly reduced, and the reliability and operating temperature range of the mesa transistor can be improved. In addition, a floating field plate in contact with the single-crystal substrate and the semi-insulating polysilicon layer is provided. The floating field plate has no leads and is equipotential with the cathode, so that when the device is reverse-biased, the voltage is applied to the semi-insulating polysilicon layer, avoiding the electrical isolation failure. At the same time, the floating field plate can also optimize the surface electric field distribution of the single-crystal substrate, reduce the peak electric field intensity, and effectively improve the breakdown voltage.

[0075] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A mesa transistor, characterized in that: include: A single crystal substrate, the single crystal substrate comprising a first surface; a first doped region, the first doped region being located on the first surface; A mesa groove, wherein the mesa groove is located on the first surface and is adjacent to the first doped region; an isolation oxide layer, the isolation oxide layer covering the surface of the mesa groove and the first surface; a semi-insulating polysilicon layer, wherein the semi-insulating polysilicon layer is located on a side of the isolation oxide layer away from the single crystal substrate; A floating field plate, wherein the floating field plate is at least partially located on a side of the semi-insulating polysilicon layer away from the single crystal substrate and surrounds the periphery of the mesa groove, the floating field plate penetrates the semi-insulating polysilicon layer and the isolation oxide layer, and contacts the single crystal substrate and the semi-insulating polysilicon layer.

2. The mesa transistor according to claim 1, characterized in that The mesa transistor further comprises a glass passivation layer and a protection layer. The glass passivation layer is filled in the mesa groove, and the protection layer is located on a side of the isolation oxide layer and the glass passivation layer away from the single crystal substrate.

3. The mesa transistor according to claim 2, characterized in that: The mesa transistor further comprises a lead hole, the lead hole is arranged around the mesa groove, and the lead hole penetrates the protection layer, the semi-insulating polysilicon layer and the isolation oxide layer; The floating field plate is located in the lead hole and on a side of the semi-insulating polysilicon layer away from the single crystal substrate, and the floating field plate is in contact with the single crystal substrate and the semi-insulating polysilicon layer.

4. The mesa transistor according to claim 1, characterized in that: In a direction perpendicular to the surface of the single crystal substrate, the radius of the mesa groove gradually increases.

5. The mesa transistor according to claim 2, characterized in that: The single crystal substrate further includes a second surface opposite to the first surface, and the mesa transistor further includes a first electrode and a second electrode; The first electrode is located on the first surface, the first electrode penetrates the protection layer, the semi-insulating polysilicon layer and the isolation oxide layer, and the orthographic projection of the mesa groove on the single crystal substrate surrounds the orthographic projection of the first electrode on the single crystal substrate; The second electrode is located on the second surface.

6. A method for manufacturing a mesa transistor, characterized in that: The method comprises: Providing a single crystal substrate, the single crystal substrate comprising a first surface; Doping the single crystal substrate to form a first doping region, and forming a mesa groove on the first surface, wherein the mesa groove is adjacent to the first doping region; Fabricating an isolation oxide layer covering the surface of the mesa groove and the first surface, and fabricating a semi-insulating polysilicon layer on a side of the isolation oxide layer away from the single crystal substrate; A floating field plate is manufactured to penetrate the semi-insulating polysilicon layer and the isolation oxide layer, wherein the floating field plate is at least partially located on a side of the semi-insulating polysilicon layer away from the single crystal substrate and surrounds the periphery of the mesa groove and is in contact with the single crystal substrate and the semi-insulating polysilicon layer.

7. The method for manufacturing a mesa transistor according to claim 6, characterized in that: Before the step of manufacturing a floating field plate penetrating the semi-insulating polysilicon layer and the isolation oxide layer, the method further includes: Applying glass powder in the mesa groove, and sintering the mesa groove coated with the glass powder to form a glass passivation layer; A protective layer is formed on the side of the glass passivation layer and the isolation oxide layer away from the single crystal substrate.

8. The method for manufacturing a mesa transistor according to claim 7, characterized in that: The step of manufacturing a floating field plate penetrating the semi-insulating polysilicon layer and the isolation oxide layer comprises: The protective layer, the semi-insulating polysilicon layer and the isolation oxide layer are patterned to form lead holes and routing holes penetrating the protective layer, the semi-insulating polysilicon layer and the isolation oxide layer, wherein the lead holes surround the mesa grooves, and the orthographic projection of the mesa grooves on the single crystal substrate surrounds the orthographic projection of the routing holes on the single crystal substrate; Metal deposition is performed on the single crystal substrate on which the lead hole and the routing hole are made to form a floating field plate located in the lead hole and on the side of the semi-insulating polycrystalline silicon layer away from the single crystal substrate, and a first electrode at least partially located in the routing hole, wherein the floating field plate is in contact with the single crystal substrate and the semi-insulating polycrystalline silicon layer.

9. The method for manufacturing a mesa transistor according to claim 8, characterized in that: The single crystal substrate includes a second surface opposite to the first surface. After the step of manufacturing a floating field plate penetrating the semi-insulating polysilicon layer and the isolation oxide layer, the method further includes: Metal deposition is performed on the single crystal substrate to form a second electrode on the second surface.

10. The method for manufacturing a mesa transistor according to claim 7, characterized in that: The step of doping the single crystal substrate to form a first doping region, and forming a mesa groove surrounding the first doping region on the first surface includes: At least one annular masking layer is formed on the first surface, and the single crystal substrate is doped based on the masking layer to form a first doping region located on the first surface, wherein the first doping region forms a doping region with a slope in the area covered by the masking layer; Forming a photoresist layer on the first surface, exposing and developing the photoresist layer to obtain a photoresist layer that exposes at least a portion of the first surface; The first surface area exposed by the photoresist layer is etched to obtain a mesa groove surrounding the first doped region, wherein the radius of the mesa groove gradually increases in a direction perpendicular to the surface of the single crystal substrate.

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