Method for manufacturing electronic device and electronic device

Abstract

The invention discloses a method for manufacturing an electronic device and the electronic device, and generally relates to the technical field of semiconductor manufacturing. The method comprises the following steps: depositing a stress layer with a negative Poisson's ratio material in a manufacturing area of a wafer; annealing is carried out on the wafer; and removing the stress layer in the manufacturing area of the wafer. According to the method for manufacturing the electronic device disclosed by the invention, the negative Poisson's ratio material is used as the stress layer in the stress memory technology, so that the stress layer crystal can be simultaneously kept in a stretching state in the transverse direction and the longitudinal direction due to deformation caused by thermal expansion of the gate electrode layer, and the mobility of carriers in a channel is improved.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor manufacturing technology. More specifically, the present invention relates to a method for manufacturing an electronic device and an electronic device. Background Art

[0002] Stress Memorization Technique (SMT) is an important method for enhancing the carrier mobility in N-channel Metal-Oxide-Semiconductor Field-Effect Transistors (N-MOSFETs).

[0003] In the prior art, stress memorization technology usually uses silicon nitride (SiN) as the stress layer material. In the spike annealing process, silicon nitride and the polysilicon in the gate electrode layer expand according to their own thermal expansion coefficients. Since the thermal expansion coefficient of polysilicon is larger than that of silicon nitride, the expansion degree of the gate electrode layer is also larger, thereby generating an outward tension on the material wrapping the gate electrode layer. The SiN layer is stretched after being subjected to the tension of the gate electrode layer, and thus deforms. The deformation of the SiN crystal introduces tensile stress to the semiconductor field effect transistor, and the tensile stress transmitted to the channel can significantly accelerate the carrier mobility. However, as the size of semiconductor products decreases, the effect of enhancing the carrier mobility in the channel by the stress memorization technology based on the SiN stress layer can no longer meet the production requirements. How to further improve the degree of enhancing the carrier mobility in the channel by the stress memorization technology has become a technical problem.

[0004] In view of this, there is an urgent need to provide a solution for manufacturing an electronic device to facilitate improving the carrier mobility in the channel of the electronic device. Summary of the Invention

[0005] In order to at least solve one or more of the technical problems described in the above background art section, the present invention proposes the following technical solutions and multiple embodiments thereof.

[0006] In a first aspect, the present invention discloses a method for manufacturing an electronic device, including: depositing a stress layer with a material having a negative Poisson's ratio in a manufacturing area of a wafer; annealing the wafer; and removing the stress layer in the manufacturing area of the wafer.

[0007] In a second aspect, the present invention also discloses an electronic device manufactured according to the method described in the first aspect.

[0008] According to the method for manufacturing an electronic device disclosed in the present invention, by using a negative Poisson's ratio material as a stress layer in the stress memory technology, the deformation of the stress layer crystal caused by the thermal expansion of the gate electrode layer can maintain a tensile state both laterally and longitudinally, thereby improving the carrier mobility in the channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present invention will become readily understood. In the drawings, several embodiments of the present invention are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein: Figure 1 FIG. shows an exemplary schematic diagram of manufacturing an N-MOSFET based on the stress memory technology in some embodiments of the present invention.

[0010] Figure 2 FIG. shows an exemplary schematic diagram of the deformation of a SiN crystal due to tension in some embodiments of the present invention.

[0011] Figure 3 FIG. shows an exemplary schematic diagram of manufacturing a CMOS based on the stress memory technology in some embodiments of the present invention.

[0012] Figure 4 FIG. shows an exemplary flowchart of the method for manufacturing an electronic device in some embodiments of the present invention.

[0013] Figure 5 FIG. shows an exemplary schematic diagram of the method for manufacturing an electronic device in some embodiments of the present invention.

[0014] Figure 6 FIG. shows an exemplary schematic diagram of the deformation of positive and negative Poisson's ratio materials in some embodiments of the present invention.

[0015] Figure 7 FIG. shows an exemplary schematic diagram of manufacturing a CMOS using SMT based on a negative Poisson's ratio material in some embodiments of the present invention. DETAILED DESCRIPTION

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0017] It should be understood that the terms "comprising" and "including" as used in the specification and claims of the present invention indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0018] It should also be understood that the terms used in the specification of the present invention are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used in the specification and claims of the present invention, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should be further understood that the term "and / or" as used in the specification and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0019] As used in this specification and the claims, the term "if" can be interpreted, depending on the context, as "when...", "once", "in response to determining", or "in response to detecting". Similarly, the phrase "if determined" or "if [the described condition or event] is detected" can be interpreted, depending on the context, as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]".

[0020] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0021] The stress memory technique is an important method for enhancing the carrier mobility in N-channel metal-oxide-semiconductor field-effect transistors. Figure 1 An exemplary schematic diagram of manufacturing an N-MOSFET based on the stress memory technique in some embodiments of the present invention is shown, as Figure 1As shown, the production of N-MOSFET based on stress memory technology involves multiple process steps. The gate stack process is used to stack a gate dielectric layer and a gate electrode layer on a silicon substrate; among them, the gate dielectric layer generally uses silicon dioxide (SiO2) or high-k materials, and its main function is to form an insulating barrier between the gate electrode and the silicon substrate, and at the same time regulate the carrier concentration and movement in the channel through the electric field effect; the commonly used material for the gate electrode layer is polysilicon, which is responsible for applying voltage to control the on and off of the channel. The extension region implantation process is mainly to implant N-type impurities such as phosphorus (P) and arsenic (As) into the regions near the source and drain to form extension regions near the source and drain, shortening the channel length. The sidewall formation process is mainly to form an insulating sidewall structure on both sides of the gate to achieve precise control of the source and drain implantation regions. The source / drain implantation process is mainly to introduce N-type impurities into the source region and the drain region through ion implantation technology. The silicon nitride deposition process is mainly to grow a layer of silicon nitride thin film on the surface of the semiconductor wafer. Spike annealing is a rapid thermal processing technology that can heat the wafer to a high temperature (such as 1035 °C) in an extremely short time and then quickly cool it. The silicidation process forms metal silicides on the silicon surface through the chemical reaction of metal and silicon, thereby improving the current conduction efficiency.

[0022] In the spike annealing process, the silicon nitride and the polysilicon in the gate electrode layer will expand according to their own thermal expansion coefficients. Since the thermal expansion coefficient of polysilicon is larger than that of silicon nitride, the expansion degree of the gate electrode layer is also larger, thus generating an outward tension on the material wrapping the gate electrode layer. The SiN layer is stretched after being subjected to the tension of the gate electrode layer, thus deforming. Figure 2 Shows an exemplary schematic diagram of the deformation of the SiN crystal due to stretching in some embodiments of the present invention. As Figure 2 shown, since the Poisson's ratio of SiN is 0.24, its 100 crystal orientation is stretched, while the 010 crystal orientation is compressed. The deformation of the SiN crystal introduces tensile stress to the N-MOSFET, and the tensile stress transmitted to the channel can significantly accelerate the electron mobility of the N-MOSFET, thereby increasing the drive current of the N-MOSFET.

[0023] One feature of SMT is that the tensile stress introduced by the cap-shaped stress layer can improve the performance of N-MOSFETs, but has an adverse effect of reducing the performance of P-channel Metal-Oxide-Semiconductor Field-Effect Transistors (P-MOSFETs). Complementary Metal-Oxide-Semiconductor (CMOS) is an integrated circuit electronic device formed by connecting P-MOSFETs and N-MOSFETs in a complementary symmetric form. It utilizes the complementary characteristics of the two field-effect transistors to achieve specific circuit functions and is widely used in fields such as digital circuits and analog circuits. In order to introduce SMT during the production of CMOS and improve the performance of N-MOSFETs without damaging the performance of P-MOSFETs, the general approach is to deposit a silicon nitride film layer and then remove the silicon nitride film layer in the PMOS region through photolithography and etching, followed by rapid annealing.

[0024] Figure 3 An exemplary schematic diagram of manufacturing CMOS based on stress memory technology in some embodiments of the present invention is shown. As Figure 3 shown, Shallow Trench Isolation (STI) is a physical isolation structure created on a substrate to separate different MOSFETs from each other. Regarding the well implantation process, it can be understood that: taking a silicon wafer as the substrate, N-type impurities can be doped into the substrate to form an N-type well (N Well), and P-MOSFETs can be fabricated based on the N-type well; or P-type impurities can be doped into the substrate to form a P-type well (P Well), and N-MOSFETs can be fabricated based on the P-type well. After depositing the SiN film layer, in order to remove the SiN material on the surface of the P-MOSFET, photoresist needs to be covered on the surface of the N-MOSFET, and then the SiN material on the upper surface of the P-MOSFET is etched. After the SiN material on the upper surface of the P-MOSFET is removed, spike annealing can be performed on the entire device, causing the SiN crystals covered on the upper surface of the N-MOSFET to deform, thereby introducing tensile stress into the channel in the N-MOSFET to improve the electron mobility. It can be understood that the process steps of gate stack, extension region implantation, spacer formation, source / drain implantation, SiN deposition, SiN removal, and silicidation introduced in the previous text for manufacturing N-MOSFETs based on SMT are also applicable to the method of manufacturing CMOS based on SMT and will not be elaborated here.

[0025] At present, the stress memory technology based on the SiN stress layer has become the standard technology for improving the carrier mobility in the 90nm and below processes. However, with the reduction of the semiconductor product size, the stress memory technology based on the SiN capping layer can no longer meet the production requirements for improving the carrier mobility in the channel. How to further improve the degree of improvement of the stress memory technology on the carrier mobility in the channel has become a technical problem. In view of this, the present invention proposes a method for manufacturing an electronic device to improve the improvement effect of the stress memory technology on the carrier mobility in the channel.

[0026] Figure 4 FIG. shows an exemplary flowchart of a method for manufacturing an electronic device in some embodiments of the present invention. As Figure 4 shown, the method includes: Step 401, depositing a stress layer of a material with a negative Poisson's ratio in the manufacturing area of the wafer; Step 402, annealing the wafer; and Step 403, removing the stress layer in the manufacturing area of the wafer.

[0027] It can be understood that the method proposed by the present invention can be used to manufacture electronic devices, including but not limited to semiconductor field effect transistors, such as N-MOSFETs, CMOSs, and complex circuits obtained by combining N-MOSFETs and / or CMOSs. The present invention does not limit this. For ease of understanding, Figure 5 FIG. shows an exemplary schematic diagram of a method for manufacturing an electronic device in some embodiments of the present invention. The following will be combined with Figure 5 to explain Steps 401-403.

[0028] For Step 401, it can be understood that a semiconductor field effect transistor can be manufactured with a silicon wafer as the substrate. Among them, the wafer includes an edge area and a manufacturing area, and the manufacturing area is the area used for manufacturing semiconductor field effect transistors or complex circuits. A prototype device of an N-MOSFET or CMOS can be prepared in the manufacturing area through a process including process steps such as gate stack, extension region implantation, sidewall formation, source / drain implantation, etc. In some embodiments, after the source / drain implantation process is completed and the source and drain of the N-MOSFET or CMOS are formed on the wafer, a stress layer of a material with a negative Poisson's ratio is deposited in the manufacturing area of the wafer. The material with a negative Poisson's ratio is a material with a negative Poisson's ratio value. Among them, the Poisson's ratio (υ) refers to the ratio of the transverse normal strain ε x to the longitudinal normal strain ε y , υ = -ε x / ε y .

[0029] For step 402, it can be understood that spike annealing can be performed on the wafer. During the annealing process, the gate electrode layer of the semiconductor field-effect transistor in the prototype state will undergo thermal expansion, which will cause the negative Poisson's ratio material in the stress layer to deform. The deformation of the stress layer will transfer stress to the channel in the semiconductor field-effect transistor, thereby improving the carrier mobility in the channel. Figure 6 FIG. shows an exemplary schematic diagram of the deformation of positive and negative Poisson's ratio materials in some embodiments of the present invention. As Figure 6 shown, for the positive Poisson's ratio material, while the material produces elongation deformation along the load direction, it will produce shortening deformation in the direction perpendicular to the load; for the negative Poisson's ratio material, while the material produces elongation deformation along the load direction, it will also produce elongation deformation in the direction perpendicular to the load. According to Figure 6 it can be known that since SiN is a positive Poisson's ratio material, in the stress memory technology based on the SiN covering layer, when the deformation of the SiN crystal due to the thermal expansion of the gate electrode layer is tensile in the <100> crystal direction, it will generate tensile stress in the same direction on the channel. That is to say, the channel maintains a tensile stress state in the <100> crystal direction, which helps to improve the carrier mobility in the <100> crystal direction. In the method disclosed in the present invention, the stress layer has a negative Poisson's ratio material, and the deformation of the stress layer crystal due to the thermal expansion of the gate electrode layer can maintain a tensile state in both the <100> and <010> crystal directions simultaneously, so as to generate a greater strain in the <110> crystal direction, thereby further improving the carrier mobility in the channel.

[0030] For step 403, it can be understood that the stress transferred from the stress layer to the channel will be memorized in the channel region. Even after removing the stress layer, the channel will still maintain a certain tensile stress state, thereby improving the carrier mobility.

[0031] It can be understood that according to the method for manufacturing an electronic device disclosed in the present invention, by using a negative Poisson's ratio material as the stress layer in the stress memory technology, the deformation of the stress layer crystal due to the thermal expansion of the gate electrode layer can maintain a tensile state both laterally and longitudinally, thereby improving the carrier mobility in the channel.

[0032] In some embodiments, the negative Poisson's ratio material includes: SiS2.

[0033] It can be understood that the Poisson's ratio value of SiS2 is -0.13, which can be used in the stress memory technology based on the negative Poisson's ratio material disclosed in the present invention. Since pyrite crystal, α-cristobalite, and hexafluorographene have negative Poisson's ratio characteristics, in some embodiments, pyrite, α-cristobalite, or hexafluorographene can be selected as the negative Poisson's ratio material.

[0034] In some embodiments, the method for fabricating an electronic device disclosed in the present invention further includes: in a sealed silica tube, controlling the reaction of silicon and sulfur under a first reaction condition to prepare SiS2.

[0035] In some embodiments, the first reaction condition includes: the reaction temperature is in the range of [773K, 1073K] and / or the reaction ratio of silicon and sulfur is: 1:2.2.

[0036] It can be understood that silicon dioxide (SiO2) has good high-temperature resistance and chemical stability, and the sealed silica tube provides a relatively stable environment for the reaction of silicon and sulfur. High-purity silicon and sulfur react in a sealed silica tube at a temperature of 773 - 1073K in a ratio of 1:2.2 to obtain NP-phase SiS2.

[0037] In some embodiments, the method for fabricating an electronic device disclosed in the present invention further includes: in a boron nitride crucible, controlling the reaction of silicon and sulfur under a second reaction condition to prepare SiS2.

[0038] In some embodiments, the second reaction condition includes: the reaction pressure is 2.8 GPa and / or the reaction temperature is 1473K.

[0039] In some embodiments, under the conditions of 2.8 GPa and 1473K, controlling the reaction of silicon and sulfur in a boron nitride (BN) crucible in a cylindrical graphite heater for 15 minutes, and then reducing the pressure after quenching to room temperature, HP1 SiS2 can be obtained.

[0040] In some embodiments, in the case of fabricating a CMOS, after depositing a stress layer of a material with a negative Poisson's ratio in the manufacturing area of the wafer, it includes: forming a photoresist protection layer on the surface of the N-MOSFET; etching the material with a negative Poisson's ratio on the upper surface of the P-MOSFET gate.

[0041] It can be understood that the stress memory technology will reduce the performance of the P-MOSFET. Since the CMOS is a device composed of P-MOSFET and N-MOSFET, when fabricating a CMOS based on the stress memory technology, it is necessary to protect the P-MOSFET from performance degradation.

[0042] In some embodiments, forming a photoresist protective layer on the surface of an N-MOSFET includes: uniformly coating a positive photoresist on the wafer surface; exposing regions of the wafer other than the N-MOSFET; and developing the wafer with a developer. In these embodiments, after the developing process, the photoresist covering the N-MOSFET is retained because it is not exposed, thereby forming a photoresist protective layer on the surface of the N-MOSFET. For regions other than the N-MOSFET, they are no longer covered by the photoresist because they are exposed.

[0043] In some embodiments, etching the auxetic material on the upper surface of a P-MOSFET gate includes: using plasma etching technology to etch the auxetic material on the upper surface of the P-MOSFET gate.

[0044] In some embodiments, after etching the auxetic material on the upper surface of the P-MOSFET gate, it includes: removing the etching impurities on the surface of the P-MOSFET.

[0045] It can be understood that after etching the auxetic material on the upper surface of the P-MOSFET gate, impurities such as etching products will remain on the surface of the wafer manufacturing area and the surface of the wafer edge area, and chemical cleaning methods can be used to remove these impurities.

[0046] In some embodiments, after etching the auxetic material on the upper surface of the P-MOSFET gate, it includes: removing the photoresist protective layer on the surface of the N-MOSFET.

[0047] It can be understood that the photoresist protective layer on the surface of the N-MOSFET can be removed using an alkaline solution or an organic solvent, or the photoresist protective layer on the surface of the N-MOSFET can also be removed using a reactive ion etching method.

[0048] Figure 7 Shows an exemplary schematic diagram of using SMT based on auxetic materials to produce CMOS in some embodiments of the present invention. As Figure 7 shown in sub-figure (a) therein, a buffer oxide layer is deposited on the surfaces of the P-MOSFET and the N-MOSFET, and the material of the buffer oxide layer can be SiO2. It can be understood that by depositing a buffer oxide layer between the stress layer and the wafer manufacturing area, it can play a role in buffering stress, reducing the adverse effects of the stress layer on the wafer substrate and the device structures in the manufacturing area, and protecting the integrity and performance stability of the devices. As Figure 7 shown in sub-figure (b) therein, a stress layer with an auxetic material is deposited in the manufacturing area of the wafer, and the selected auxetic material can be SiS2. As Figure 7As shown in sub - figure (c) therein, the negative Poisson's ratio material on the upper surface of the gate electrode layer of the P - MOSFET is removed through photolithography and etching processes. Among them, the photolithography process is used to form a photoresist protection layer on the surface of the N - MOSFET, and then the negative Poisson's ratio material on the upper surface of the gate electrode layer of the P - MOSFET is etched. As Figure 7 As shown in sub - figure (d) therein, after the etching is completed, the etching impurities generated in the etching process are removed and the photoresist protection layer on the surface of the N - MOSFET is removed. As Figure 7 As shown in sub - figure (e) therein, the wafer is annealed to facilitate the introduction of tensile stress to the N - MOSFET.

[0049] Furthermore, the present invention discloses an electronic device, which is fabricated according to the methods described in the foregoing embodiments of the present invention.

[0050] In summary, the specific functions achieved by the electronic device provided in the embodiments of this specification can be explained in contrast to the foregoing embodiments in this specification, and can achieve the technical effects of the foregoing embodiments, which will not be elaborated here.

[0051] It should be noted that, for the purpose of simplicity, the present invention describes some methods and their embodiments as a series of actions and combinations. However, those skilled in the art can understand that the solutions of the present invention are not limited by the order of the described actions. Therefore, based on the disclosure or teachings of the present invention, those skilled in the art can understand that some of the steps can be executed in other orders or simultaneously. Further, those skilled in the art can understand that the embodiments described in the present invention can be regarded as optional embodiments, that is, the actions or modules involved are not necessarily required for the implementation of certain or some solutions of the present invention. In addition, according to the differences in the solutions, the present invention also focuses on the descriptions of some embodiments. In view of this, those skilled in the art can understand the parts not detailed in a certain embodiment of the present invention by referring to the relevant descriptions of other embodiments.

Claims

1. A method for manufacturing an electronic device, characterized in that, Comprising: Depositing a stress layer with a negative Poisson's ratio material in the manufacturing area of the wafer; Annealing the wafer; And Removing the stress layer in the manufacturing area of the wafer.

2. The method according to claim 1, characterized in that, The negative Poisson's ratio material includes: SiS2.

3. The method according to claim 2, characterized in that, Further comprising: Controlling the reaction of silicon and sulfur under a first reaction condition in a sealed silica tube to prepare the SiS2.

4. The method according to claim 3, characterized in that, The first reaction condition includes: the reaction temperature is in the range [773K, 1073K] and / or the reaction ratio of silicon and sulfur is: 1:2.

2.

5. The method according to claim 2, characterized in that, Further comprising: Controlling the reaction of silicon and sulfur under a second reaction condition in a boron nitride crucible to prepare the SiS2.

6. The method according to claim 5, characterized in that, The second reaction condition includes: the reaction pressure is 2.8 GPa and / or the reaction temperature is 1473K.

7. The method according to claim 1, characterized in that, In the case of manufacturing a CMOS, after depositing a stress layer with a negative Poisson's ratio material in the manufacturing area of the wafer, it includes: Forming a photoresist protection layer on the surface of the N-MOSFET; Etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate.

8. The method according to claim 7, characterized in that, After etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate, it includes: Removing the etching impurities on the surface of the P-MOSFET.

9. The method according to claim 7, characterized in that, After etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate, it includes: Removing the photoresist protection layer on the surface of the N-MOSFET.

10. An electronic device, characterized in that, The electronic device is manufactured by the method according to any one of claims 1-9.

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