Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a solar cell and a preparation method thereof, and a photovoltaic module, and the solar cell comprises a semiconductor substrate; the intrinsic amorphous silicon layers are positioned on the front surface, the back surface and the side surfaces of the semiconductor substrate; the doping layer is positioned on the intrinsic amorphous silicon layer; the doping layer is located on the front side and the back side of the semiconductor substrate, the transparent conducting layer is located on the doping layer, the transparent conducting layer at least covers the front side and the back side of the semiconductor substrate, and the transparent conducting layer located on the front side of the semiconductor substrate and the transparent conducting layer located on the back side of the semiconductor substrate are disconnected.

Description

Technical Field

[0001] The present disclosure relates to the field of solar cells, and in particular, to a solar cell, a preparation method thereof, and a photovoltaic module. Background Art

[0002] At present, crystalline silicon solar cells are obtained by cleaning and texturing a silicon wafer, depositing amorphous silicon thin films on both sides of the silicon wafer, depositing TCO on both sides thereof, and finally performing screen printing metallization. However, problems arising during the preparation are as follows: ① The side film layers are formed by overplating when depositing amorphous silicon thin films and TCO on both sides of the silicon substrate, rather than planar deposition. Therefore, it is easy to form discontinuous film layers, and / or the unevenly deposited film layers are electrically connected to each other, resulting in leakage, so that the conversion efficiency of the battery is reduced; ② Impurities may be adsorbed on the surface of ITO, forming oxides or generating other pollutants, all of which will increase the contact resistance at the interface, hinder the transmission and collection of charges, and thus reduce the efficiency of the battery; ③ Moreover, the pollutants and oxides will affect the light transmittance of ITO, resulting in an increase in light loss and a reduction in the light absorption efficiency of the battery. Summary of the Invention

[0003] The present disclosure provides a solar cell, a preparation method thereof, and a photovoltaic module to at least solve the above technical problems existing in the prior art.

[0004] According to a first aspect of the present disclosure, there is provided a solar cell, including:

[0005] A semiconductor substrate;

[0006] An intrinsic amorphous silicon layer located on the front, back, and side surfaces of the semiconductor substrate;

[0007] A doped layer located on the intrinsic amorphous silicon layer;

[0008] A transparent conductive layer located on the doped layer, the transparent conductive layer covering at least the front and back surfaces of the semiconductor substrate, wherein the transparent conductive layer on the front surface of the semiconductor substrate and the transparent conductive layer on the back surface of the semiconductor substrate are disconnected.

[0009] In an implementable embodiment, the transparent conductive layer further covers a part of the side surface of the semiconductor substrate.

[0010] In an implementable embodiment, the part of the transparent conductive layer covering the front surface of the semiconductor substrate is a first transparent conductive layer, the part covering the back surface of the semiconductor substrate is a second transparent conductive layer, and the part covering a part of the side surface of the semiconductor is a third transparent conductive layer; wherein,

[0011] The third transparent conductive layer is connected to the first transparent conductive layer, and / or, the third transparent conductive layer is connected to the second transparent conductive layer.

[0012] In an implementable embodiment, the transparent conductive layer includes a halogen element.

[0013] In an implementable embodiment, the content of the halogen element in the transparent conductive layer is 100 ppb to 10 ppm.

[0014] According to a second aspect of the present disclosure, there is provided a method for manufacturing a solar cell, the method including:

[0015] Providing a semiconductor substrate;

[0016] Forming an intrinsic amorphous silicon layer on the front, back, and side surfaces of the semiconductor substrate;

[0017] Forming a doped layer on the intrinsic amorphous silicon layer;

[0018] Forming a transparent conductive layer on the doped layer;

[0019] Performing several pickling treatments on the transparent conductive layer such that the transparent conductive layer after the pickling treatments covers at least the front and back surfaces of the semiconductor substrate, wherein the transparent conductive layer on the front surface of the semiconductor substrate and the transparent conductive layer on the back surface of the semiconductor substrate are disconnected.

[0020] In an implementable embodiment, the performing several pickling treatments on the transparent conductive layer includes:

[0021] The several pickling treatments remove a part of the transparent conductive layer covering the side surface of the semiconductor substrate such that the transparent conductive layer after the pickling treatments also covers a part of the side surface of the semiconductor substrate.

[0022] In an implementable embodiment, the performing several pickling treatments on the transparent conductive layer includes:

[0023] The solution concentrations of the several pickling treatments decrease in sequence, and / or, the times of the several pickling treatments increase in sequence.

[0024] In an implementable embodiment, the performing several pickling treatments on the transparent conductive layer includes:

[0025] Performing a first pickling on the transparent conductive layer, wherein the solution concentration range of the first pickling is 0.5 - 1.5 mol / L;

[0026] Performing a second pickling on the transparent conductive layer, wherein the solution concentration range of the second pickling is 0.1 - 0.5 mol / L;

[0027] The third pickling of the transparent conductive layer is carried out, and the solution concentration range of the third pickling is 0.01 - 0.1 mol / L.

[0028] In one implementable manner, the method further includes:

[0029] After the first pickling, the first water washing of the transparent conductive layer is carried out;

[0030] After the second pickling, the second water washing of the transparent conductive layer is carried out;

[0031] After the third pickling, the third water washing of the transparent conductive layer is carried out.

[0032] In one implementable manner, the part of the transparent conductive layer covering the front surface of the semiconductor substrate is the first transparent conductive layer, the part covering the back surface of the semiconductor substrate is the second transparent conductive layer, and the part covering the side surface of the semiconductor part is the third transparent conductive layer; wherein,

[0033] The third transparent conductive layer is connected to the first transparent conductive layer, and / or the third transparent conductive layer is connected to the second transparent conductive layer.

[0034] In one implementable manner, the method further includes:

[0035] After the several pickling treatments, a first metal electrode is formed on the first transparent conductive layer, and a second metal electrode is formed on the second transparent conductive layer.

[0036] In one implementable manner, the solution of the several pickling treatments includes one or more of HNO3, HCl, HBr, H2SO4, and HF.

[0037] According to the third aspect of the present disclosure, a photovoltaic module is provided, including the solar cell as described in any one of the above embodiments.

[0038] For the solar cell, its preparation method, and the photovoltaic module of the present disclosure, the transparent conductive layer on the front surface of the semiconductor substrate is disconnected from the transparent conductive layer on the back surface of the semiconductor substrate, avoiding front-back conduction and reducing battery leakage.

[0039] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understandable through the following description. Description of the Drawings

[0040] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown by way of illustration and not limitation, wherein:

[0041] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0042] Figure 1 It is a schematic structural diagram of a solar cell provided by an embodiment of the present disclosure;

[0043] Figures 2a to 2c It is a schematic structural diagram of a solar cell provided by other embodiments of the present disclosure;

[0044] Figure 3 It is a flowchart of a solar cell provided by an embodiment of the present disclosure;

[0045] Figures 4a to 4f It is a schematic diagram of a solar cell provided by an embodiment of the present disclosure during the manufacturing process;

[0046] Figure 5 It is a diagram of the cell cross-sectional film layer before several pickling processes;

[0047] Figure 6 It is a diagram of the cell cross-sectional film layer after several pickling processes.

[0048] Reference numerals in the drawings:

[0049] 10. Semiconductor substrate; 101. Front side; 102. Back side; 103. Side; 20. Intrinsic amorphous silicon layer; 30. Doped layer; 31. First doped layer; 32. Second doped layer; 40. Transparent conductive layer; 41. First transparent conductive layer; 42. Second transparent conductive layer; 43. Third transparent conductive layer; 51. First metal electrode; 52. Second metal electrode. Detailed implementation manners

[0050] To make the objects, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present disclosure.

[0051] An embodiment of the present disclosure provides a solar cell, as Figure 1 shown, the solar cell includes:

[0052] A semiconductor substrate 10. The semiconductor substrate 10 can be a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (such as a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a polysilicon substrate, etc. In a preferred embodiment, the semiconductor substrate 10 can be crystalline silicon, and the crystalline silicon can be P-type single-crystalline silicon or N-type single-crystalline silicon. Preferably, it can be N-type single-crystalline silicon.

[0053] As Figure 1 shown, the surface of the semiconductor substrate 10 is formed into a pyramid texture structure.

[0054] The solar cell further includes: an intrinsic amorphous silicon layer 20, which is located on the front surface 101, the back surface 102, and the side surface 103 of the semiconductor substrate 10.

[0055] In one embodiment, the intrinsic amorphous silicon layer 20 is a passivation layer. The passivation layer has a good passivation effect on the surface of the semiconductor substrate. Excellent surface passivation ability is an important condition for obtaining a higher battery efficiency, and it can greatly improve the minority carrier lifetime of the battery.

[0056] The solar cell further includes: a doping layer 30, which is located on the intrinsic amorphous silicon layer 20.

[0057] In one embodiment, the doping layer 30 can include a first doping layer 31 located on the front surface of the semiconductor substrate 10 and a second doping layer 32 located on the back surface of the semiconductor substrate 10. The first doping layer 31 can be an N-type doping layer, and the second doping layer 32 can be a P-type doping layer.

[0058] The first doping layer 31 and the second doping layer 32 can be microcrystalline silicon doping layers or amorphous silicon doping layers.

[0059] The first doping layer 31 and the second doping layer 32 form the PN junction and the back surface field of the heterojunction solar cell.

[0060] The solar cell further includes: a transparent conductive layer 40, which is located on the doping layer 30. The transparent conductive layer 40 at least covers the front surface 101 and the back surface 102 of the semiconductor substrate 10. Among them, the transparent conductive layer 40 located on the front surface 101 of the semiconductor substrate 10 is disconnected from the transparent conductive layer 40 located on the back surface 102 of the semiconductor substrate 10.

[0061] The transparent conductive layer 40 selects a transparent conductive oxide. The transparent conductive oxide can be a single-layer or stacked structure of materials such as indium tin oxide, aluminum-doped zinc oxide, or tungsten-doped indium oxide; the transparent conductive layer 40 can effectively increase the collection of carriers and reduce the reflection of light.

[0062] The thickness range of the transparent conductive layer 40 is 10 to 100 nm.

[0063] In some embodiments, as Figure 1 shown, the transparent conductive layer 40 also covers a part of the side surface 103 of the semiconductor substrate 10.

[0064] In other embodiments, as Figure 2c shown, the transparent conductive layer 40 only covers the front surface 101 and the back surface 102 of the semiconductor substrate 10.

[0065] In one embodiment, the part of the transparent conductive layer 40 covering the front surface 101 of the semiconductor substrate 10 is the first transparent conductive layer 41, the part covering the back surface 102 of the semiconductor substrate 10 is the second transparent conductive layer 42, and the part covering the side surface 103 of the semiconductor part 10 is the third transparent conductive layer 43; wherein,

[0066] The third transparent conductive layer 43 is connected to the first transparent conductive layer 41, and / or the third transparent conductive layer 43 is connected to the second transparent conductive layer 42.

[0067] Specifically, in some embodiments, as Figure 1 shown, the third transparent conductive layers 43 on all side surfaces of the semiconductor substrate 10 are all connected to the first transparent conductive layer 41.

[0068] In other embodiments, as Figure 2a shown, the third transparent conductive layers 43 on all side surfaces of the semiconductor substrate 10 are all connected to the second transparent conductive layer 42.

[0069] In other embodiments, as Figure 2b shown, the third transparent conductive layer 43 on a part of the side surfaces of the semiconductor substrate 10 is connected to the first transparent conductive layer 41, and the third transparent conductive layer 43 on another part of the side surfaces is connected to the second transparent conductive layer 42.

[0070] In the embodiments of the present disclosure, the transparent conductive layer only covers a part of the side surface of the semiconductor substrate. In this way, the transparent conductive layer on the front surface of the semiconductor substrate is disconnected from the transparent conductive layer on the back surface of the semiconductor substrate, avoiding conduction between the front and back surfaces and reducing battery leakage.

[0071] In one embodiment, the transparent conductive layer includes a halogen element. The content of the halogen element in the transparent conductive layer is 100 ppb to 10 ppm.

[0072] Therefore, the transparent conductive layer in the embodiments of the present disclosure is obtained after pickling treatment. During the pickling process, solutions containing halogen elements such as HCl, HBr, and HF can be used for pickling, and the halogen elements can increase the work function of the transparent conductive layer. For example, if HCl is selected for pickling, Cl- ions enter the surface of the ITO film through the treatment and fill the oxygen vacancies therein, thereby increasing the work function of the Cl-ITO surface.

[0073] The solar cell further includes: a first metal electrode 51 located on the first transparent conductive layer 41; and a second metal electrode 52 located on the second transparent conductive layer 42.

[0074] The first metal electrode 51 and the second metal electrode 52 are used to form the positive and negative electrodes of the battery and effectively collect photo-generated carriers. The materials thereof can be silver, silver-coated copper grid, or copper. The first metal electrode 51 is disposed on the first transparent conductive layer 41, and the second metal electrode 52 is disposed on the second transparent conductive layer 41, realizing direct contact between the metal electrode and the transparent conductive layer and ensuring good ohmic contact.

[0075] The embodiments of the present disclosure also provide a method for manufacturing a solar cell. Figure 3 This is a flowchart of the solar cell provided by the embodiments of the present disclosure, as Figure 3 shown. The manufacturing method includes:

[0076] Step 301: Provide a semiconductor substrate;

[0077] Step 302: Form an intrinsic amorphous silicon layer on the front, back, and side surfaces of the semiconductor substrate;

[0078] Step 303: Form a doped layer on the intrinsic amorphous silicon layer;

[0079] Step 304: Form a transparent conductive layer on the doped layer;

[0080] Step 305: Perform pickling treatment on the transparent conductive layer several times so that the pickled transparent conductive layer covers at least the front and back surfaces of the semiconductor substrate, wherein the transparent conductive layer on the front surface of the semiconductor substrate and the transparent conductive layer on the back surface of the semiconductor substrate are disconnected.

[0081] The following further elaborates in detail on the method for manufacturing the solar cell provided by the embodiments of the present disclosure with reference to specific embodiments. Figures 4a to 4f This is a schematic diagram of the solar cell provided by the embodiments of the present disclosure during the manufacturing process.

[0082] First, referring to Figure 4a , perform Step 301 to provide a semiconductor substrate 10.

[0083] The semiconductor substrate 10 can be a single-element semiconductor material substrate (such as a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (such as a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a polysilicon substrate, etc. In a preferred embodiment, the semiconductor substrate 10 can be crystalline silicon, and the crystalline silicon can be P-type single-crystalline silicon or N-type single-crystalline silicon. Preferably, it can be N-type single-crystalline silicon.

[0084] Next, the method further includes: pre-cleaning the semiconductor substrate 10 and performing gettering on the semiconductor substrate 10.

[0085] Next, referring to Figure 4b , the semiconductor substrate 10 is subjected to a texturing process to form a pyramid-textured surface structure on the surface of the semiconductor substrate 10.

[0086] In actual operation, the texturing process includes: placing the semiconductor substrate 10 in a KOH solution with a concentration of 0.5%-10%, reacting at 50-85°C for 1 min - 20 min. Under these conditions, the best textured surface structure can be obtained, which can reduce reflection and absorb more light sources. This embodiment mainly utilizes the anisotropic etching characteristics of silicon in a low-concentration alkali solution. Silicon undergoes a series of chemical reactions with the alkali solution to form a pyramid-textured surface on the silicon wafer surface.

[0087] Next, referring to Figure 4c , step 302 is performed to form an intrinsic amorphous silicon layer 20 on the front surface 101, the back surface 102, and the side surface 103 of the semiconductor substrate 10.

[0088] In actual operation, the intrinsic amorphous silicon layer 20 can be deposited by a chemical vapor deposition method (Chemical Vapor Deposition, CVD).

[0089] In one embodiment, the intrinsic amorphous silicon layer 20 is a passivation layer. The passivation layer has a good passivation effect on the semiconductor substrate surface. Excellent surface passivation ability is an important condition for obtaining a high battery efficiency, and it can greatly improve the minority carrier lifetime of the battery.

[0090] Next, continuing to refer to Figure 4c , step 303 is performed to form a doped layer 30 on the intrinsic amorphous silicon layer 20.

[0091] In actual operation, the doped layer 30 can be deposited by a chemical vapor deposition method (Chemical Vapor Deposition, CVD).

[0092] In one embodiment, the doping layer 30 may include a first doping layer 31 located on the front surface of the semiconductor substrate 10 and a second doping layer 32 located on the back surface of the semiconductor substrate 10. The first doping layer 31 may be an N-type doping layer, and the second doping layer 32 may be a P-type doping layer.

[0093] The first doping layer 31 and the second doping layer 32 may be microcrystalline silicon doping layers or amorphous silicon doping layers.

[0094] The first doping layer 31 and the second doping layer 32 form the PN junction and the back surface field of the heterojunction solar cell.

[0095] Next, referring to Figure 4d , perform step 304 to form a transparent conductive layer 40 on the doping layer 30.

[0096] In actual operation, the transparent conductive layer 40 may be deposited by a physical vapor deposition process (Physical Vapor Deposition, PVD).

[0097] The transparent conductive layer 40 selects a transparent conductive oxide. The transparent conductive oxide may be a single-layer or multi-layer structure of materials such as indium tin oxide, aluminum-doped zinc oxide, or indium oxide doped with tungsten; the transparent conductive layer 40 can effectively increase the collection of carriers and reduce the reflection of light.

[0098] The thickness range of the transparent conductive layer 40 is 10 - 100 nm.

[0099] As Figure 4d shown, after the transparent conductive layer 40 is formed, there will be impurities, contaminants, and discontinuous films on the transparent conductive layer 40 located on the side surface of the semiconductor substrate 10. Therefore, it is necessary to etch the coating film around the side of the battery, and this step is the key to reducing the leakage phenomenon.

[0100] Currently, the etching technology used in the manufacture of solar cells is mainly dry etching. However, this technology has some disadvantages when processing the textured silicon wafers. The dry etching process may require special equipment and gases, and the mentioned laser etching and other dry etching technologies may require precise control and adjustment, which will increase the cost of the production line and the technical complexity of laser use. Pyramidal structures are formed on the surface of the textured silicon wafers, and the concave areas between these structures are difficult to be completely processed by dry etching, resulting in incomplete etching, which may cause side leakage problems. In addition, the crystalline silicon surface of the HJT (heterojunction) solar cell is covered with a layer of amorphous silicon passivation layer, and this film layer is crucial for the performance of the battery. When using dry etching, the bombardment of gas or laser may damage this passivation layer, thereby reducing the overall efficiency of the battery. It should be noted that laser etching may cause irreversible damage to the crystalline silicon.

[0101] Therefore, the embodiments of the present disclosure use a wet etching process to etch the coating layer.

[0102] Next, referring to Figure 4e , perform step 305 to perform several pickling treatments on the transparent conductive layer 40 so that the pickled transparent conductive layer 40 covers at least the front surface 101 and the back surface 102 of the semiconductor substrate 10, wherein the transparent conductive layer 40 on the front surface 101 of the semiconductor substrate 10 is disconnected from the transparent conductive layer 40 on the back surface 102 of the semiconductor substrate 10.

[0103] In one embodiment, as Figure 4e shown, performing several pickling treatments on the transparent conductive layer 40 includes:

[0104] Several pickling treatments remove a part of the transparent conductive layer 40 covering the side surface 103 of the semiconductor substrate 10 so that the pickled transparent conductive layer 40 also covers a part of the side surface 103 of the semiconductor substrate 10.

[0105] In other embodiments, as Figure 2c shown, several pickling treatments remove all of the transparent conductive layer 40 covering the side surface 103 of the semiconductor substrate 10 so that the transparent conductive layer 40 only covers the front surface 101 and the back surface 102 of the semiconductor substrate 10.

[0106] In one embodiment, performing several pickling treatments on the transparent conductive layer 40 includes:

[0107] The solution concentration of several pickling treatments decreases in sequence, and / or the time of several pickling treatments increases in sequence.

[0108] In one embodiment, performing several pickling treatments on the transparent conductive layer 40 includes:

[0109] Perform a first pickling on the transparent conductive layer 40, and the solution concentration range of the first pickling is 0.5 - 1.5 mol / L; perform a second pickling on the transparent conductive layer 40, and the solution concentration range of the second pickling is 0.1 - 0.5 mol / L; perform a third pickling on the transparent conductive layer 40, and the solution concentration range of the third pickling is 0.01 - 0.1 mol / L.

[0110] In one embodiment, the solution of several pickling treatments includes one or more of HNO3, HCl, HBr, H2SO4, and HF.

[0111] Specifically, the solution for wet etching includes an acid solution (one or more of HNO3, HCl, HBr, H2SO4, HF). The method of multi-step pickling is adopted: for the first pickling, soak in a solution with a concentration of 0.5 - 1.5 mol / L for 5 - 10 s, then perform the first water wash, and the time for the first water wash is 60 s; for the second pickling, soak in a solution with a concentration of 0.1 - 0.5 mol / L for 10 - 30 s, then perform the second water wash; for the third pickling, soak in a solution with a concentration of 0.01 - 0.1 mol / L for 30 - 60 s, then perform the third water wash; after the third water wash is completed, perform slow lifting, the temperature for slow lifting is 60 °C, and the time is 60 s to ensure that the acidic solution is cleaned thoroughly, then perform drying, the drying temperature is 80 °C, and the time is 900 s.

[0112] In the embodiments of the present disclosure, during the first pickling, dust and impurities on the surface of the transparent conductive layer are removed, during the second pickling, the adsorbed oxide layer on the surface is etched, and during the third pickling, smaller grains are etched away, and the remaining grain size is about 27 - 29 nm; the multi-step pickling process can better control the roughness and flatness of the metal surface, reduce local corrosion and over-pickling phenomena, thereby improving the appearance and corrosion resistance of the final product.

[0113] In the embodiments of the present disclosure, three pickling steps are selected because if the number of pickling times is too many, it will damage the ITO film. For example, the acid will corrode the surface of the ITO film so that the ITO film layer peels off, and excessive acid will cause deformation of the ITO film structure or damage to the crystal lattice. In addition, other impurities may be introduced, affecting the transmittance of the ITO film.

[0114] In the present disclosure, multiple pickling steps will not damage the ITO films on the front and back because the thicknesses of the ITO films on the front and back both reach 70 - 80 nm. The ITO film on the side is only the film layer that is deposited by bypassing during the deposition of the front and back film layers, and the film layer is intermittent and uneven. Therefore, pickling will not damage the film layers on the front and back while removing the film layer on the side.

[0115] The method of the embodiments of the present disclosure can effectively reduce the battery leakage phenomenon, fully collect photo-generated electrons and holes, and thus improve the efficiency, which is mainly divided into the following points:

[0116] 1. Pickling can remove pollutants and defects in the edge bypass coating film layer of the battery, improve the uniformity and compactness of the film layer, reduce the leakage phenomenon, lower the resistance, and enhance the stability and reliability of the battery.

[0117] 2. Wet cleaning removes dust and impurity particles on the surface of the film layer after coating, enables better contact with the electrode, reduces the contact resistance, increases the FF (Fill Factor), and ensures that the battery can maximize its light conversion efficiency.

[0118] 3. Pickling can remove contaminants and oxides on the ITO surface, improve the light transmittance of ITO, enable more light to enter the battery interior, be absorbed by silicon and converted into electrical energy, thereby improving the conversion efficiency of the battery.

[0119] 4. Pickling can clean the ITO surface, reduce the capture of carriers, increase the carrier concentration and mobility, enhance the electrical performance of the battery, and improve the short-circuit current and fill factor.

[0120] 5. Pickling can adjust the surface chemical state of ITO. During the pickling process, solutions containing halogen elements such as HCl, HBr, and HF can be used for pickling. The halogen elements in the acid solution enter the ITO film, increasing the work function of the ITO film. For example, the Cl ions in HCl will supplement the oxygen vacancies in ITO, adjusting the work function of ITO to better match silicon, reducing the resistance of charge transport, increasing the open-circuit voltage and fill factor of the battery, and thus improving the overall performance of the battery.

[0121] 6. Pickling can make the ITO surface smoother, which helps for better contact between ITO and other layers. When preparing the metal electrode subsequently, the grid lines are not likely to fall off.

[0122] 7. After pickling, the side insulation treatment of the battery can also meet the requirements of battery encapsulation to ensure that the battery still maintains good insulation performance after encapsulation.

[0123] Figure 5 is the cross-sectional film layer diagram of the battery before several pickling processes, Figure 6 is the cross-sectional film layer diagram of the battery after several pickling processes. As Figure 5 and Figure 6 shown, after pickling using the process of this method, the coating layer around the cross-section of the battery is cleaned, and the front and back sides are not electrically connected.

[0124] In one embodiment, the part of the transparent conductive layer 40 covering the front surface 101 of the semiconductor substrate 10 is the first transparent conductive layer 41, the part covering the back surface 102 of the semiconductor substrate 10 is the second transparent conductive layer 42, and the part covering the side surface 103 of the semiconductor part 10 is the third transparent conductive layer 43; wherein,

[0125] The third transparent conductive layer 43 is connected to the first transparent conductive layer 41, and / or, the third transparent conductive layer 43 is connected to the second transparent conductive layer 42.

[0126] Specifically, in some embodiments, as Figure 4e shown, the third transparent conductive layer 43 on all side surfaces of the semiconductor substrate 10 is connected to the first transparent conductive layer 41.

[0127] In other embodiments, asFigure 2a As shown, the third transparent conductive layer 43 on all sides of the semiconductor substrate 10 is connected to the second transparent conductive layer 42.

[0128] In some other embodiments, as Figure 2b shown, the third transparent conductive layer 43 on some sides of the semiconductor substrate 10 is connected to the first transparent conductive layer 41, and the third transparent conductive layer 43 on the other sides is connected to the second transparent conductive layer 42.

[0129] In the embodiments of the present disclosure, the transparent conductive layer only covers some sides of the semiconductor substrate. In this way, the transparent conductive layer on the front side of the semiconductor substrate is disconnected from the transparent conductive layer on the back side of the semiconductor substrate, avoiding conduction between the front and back sides and reducing battery leakage.

[0130] Next, referring to Figure 4f , the method further includes: after several pickling treatments, forming a first metal electrode 51 on the first transparent conductive layer 41 and forming a second metal electrode 52 on the second transparent conductive layer 42.

[0131] In actual operation, the process of forming the first metal electrode 51 and the second metal electrode 52 includes but is not limited to screen printing process.

[0132] The first metal electrode 51 and the second metal electrode 52 are used to form the positive and negative electrodes of the battery, effectively collecting photo-generated carriers. Their materials can be silver, silver-coated copper grid or copper. The first metal electrode 51 is disposed on the first transparent conductive layer 41, and the second metal electrode 52 is disposed on the second transparent conductive layer 41, realizing direct contact between the metal electrode and the transparent conductive layer and ensuring good ohmic contact.

[0133] In the present disclosure, after forming the transparent conductive layer, by performing several pickling operations on the transparent conductive layer, several pickling operations can more effectively remove the oxide layer and impurities on the metal surface, can contact the electrode better, reduce the contact resistance, increase the FF, and ensure that the battery can maximize its light conversion efficiency; several pickling operations can better control the roughness and flatness of the metal surface, reduce local corrosion and over-pickling phenomena, thereby improving the appearance and corrosion resistance of the final product.

[0134] The embodiments of the present disclosure further provide a photovoltaic module, including the solar cell as described in any one of the above embodiments.

[0135] It should be understood that various forms of the processes shown above can be used, reordering, adding or deleting steps. For example, the steps described in the present disclosure can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved. This is not limited herein.

[0136] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality of" means two or more unless otherwise specifically defined.

[0137] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily conceive of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A solar cell, characterized in that: The solar cell comprises: Semiconductor substrate; An intrinsic amorphous silicon layer is located on the front side, the back side and the side surface of the semiconductor substrate; a doping layer, located on the intrinsic amorphous silicon layer; A transparent conductive layer is located on the doped layer, and the transparent conductive layer at least covers the front side and the back side of the semiconductor substrate, wherein the transparent conductive layer located on the front side of the semiconductor substrate is disconnected from the transparent conductive layer located on the back side of the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that The transparent conductive layer also covers a portion of the side surface of the semiconductor substrate.

3. The solar cell according to claim 2, characterized in that: The portion of the transparent conductive layer covering the front side of the semiconductor substrate is the first transparent conductive layer, the portion covering the back side of the semiconductor substrate is the second transparent conductive layer, and the portion covering the side of the semiconductor portion is the third transparent conductive layer; wherein, The third transparent conductive layer is connected to the first transparent conductive layer, and / or the third transparent conductive layer is connected to the second transparent conductive layer.

4. The solar cell according to claim 1, characterized in that The transparent conductive layer includes halogen elements.

5. The solar cell according to claim 4, characterized in that: The content of halogen elements in the transparent conductive layer is 100 ppb to 10 ppm.

6. A method for preparing a solar cell, characterized in that: The method comprises: providing a semiconductor substrate; forming an intrinsic amorphous silicon layer on the front side, the back side and the side surface of the semiconductor substrate; forming a doping layer on the intrinsic amorphous silicon layer; forming a transparent conductive layer on the doped layer; The transparent conductive layer is subjected to acid washing treatment for several times, so that the transparent conductive layer after the acid washing treatment covers at least the front and back sides of the semiconductor substrate, wherein the transparent conductive layer on the front side of the semiconductor substrate is disconnected from the transparent conductive layer on the back side of the semiconductor substrate.

7. The method according to claim 6, characterized in that The transparent conductive layer is subjected to several acid washing processes, including: The several acid wash treatments remove a portion of the transparent conductive layer covering the side surface of the semiconductor substrate, so that the transparent conductive layer after the acid wash treatment still covers a portion of the side surface of the semiconductor substrate.

8. The method according to claim 6, characterized in that The transparent conductive layer is subjected to several acid washing processes, including: The solution concentrations of the several pickling treatments are successively reduced, and / or the time of the several pickling treatments is successively increased.

9. The method according to claim 6, characterized in that The transparent conductive layer is subjected to several acid washing processes, including: Performing a first acid wash on the transparent conductive layer, wherein the concentration of the first acid wash solution is in the range of 0.5-1.5 mol / L; Performing a second acid wash on the transparent conductive layer, wherein the concentration of the second acid wash solution is in the range of 0.1-0.5 mol / L; The transparent conductive layer is subjected to a third acid wash, wherein the concentration of the third acid wash solution is in the range of 0.01-0.1 mol / L.

10. The method according to claim 9, characterized in that The method further comprises: After the first acid washing, the transparent conductive layer is washed with water for the first time; After the second acid washing, washing the transparent conductive layer with water for the second time; After the third acid washing, the transparent conductive layer is washed with water for the third time.

11. The method according to claim 7, characterized in that The portion of the transparent conductive layer covering the front side of the semiconductor substrate is the first transparent conductive layer, the portion covering the back side of the semiconductor substrate is the second transparent conductive layer, and the portion covering the side of the semiconductor portion is the third transparent conductive layer; wherein, The third transparent conductive layer is connected to the first transparent conductive layer, and / or the third transparent conductive layer is connected to the second transparent conductive layer.

12. The method according to claim 11, characterized in that The method further comprises: After the acid washing processes are performed several times, a first metal electrode is formed on the first transparent conductive layer, and a second metal electrode is formed on the second transparent conductive layer.

13. The method according to claim 6, characterized in that The solutions of the several pickling treatments include one or more of HNO3, HCl, HBr, H2SO4, and HF.

14. A photovoltaic module, characterized in that: The invention comprises the solar cell according to any one of claims 1 to 5.

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