Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, the solar cell comprises a silicon substrate, the silicon substrate comprises a first surface and a second surface which are oppositely arranged, a diffusion layer is formed on the first surface of the silicon substrate, the first surface comprises a first region and a second region which are distributed at an interval, and the first region and the second region are oppositely arranged. The second surface comprises a third region and a fourth region which are distributed at an interval, the first region is provided with a first tunneling passivation structure and a first electrode, and the third region is provided with a second tunneling passivation structure and a second electrode. The front surface and the back surface of the solar cell are provided with local tunneling passivation structures, so that passivation contact of a front surface metal region is ensured, parasitic absorption of a front surface non-metal region is reduced, and the cell efficiency can be greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and particularly relates to a solar cell and a preparation method thereof. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and international photovoltaic markets are also continuously increasing, and industry manufacturers have focused on the research and development of high-efficiency cells. TOPCon (Tunnel Oxide Passivated Contact) cells can improve the surface passivation performance of the cells, reduce the metal contact recombination current, and effectively improve the open-circuit voltage and short-circuit current of the cells by sequentially preparing an ultra-thin tunneling oxide layer and a doped polysilicon layer on the back of the cell.

[0003] The existing TOPCon cells are usually of a single-sided TOPCon structure. The emitter is usually prepared by boron diffusion process on the front side. Due to the low diffusion doping concentration, the contact resistance with the metal electrode is high. At the same time, the metal directly contacts the silicon substrate, and the recombination in the metal region is still relatively high, resulting in a large reverse saturation current, which limits the improvement of the cell efficiency.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a solar cell and a preparation method thereof. Summary of the Invention

[0005] The purpose of the present invention is to provide a solar cell and a preparation method thereof to improve the cell efficiency and optimize the preparation process.

[0006] To achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0007] A solar cell, the solar cell includes a silicon substrate, the silicon substrate includes a first surface and a second surface which are oppositely arranged, a diffusion layer is formed on the first surface of the silicon substrate, the first surface includes a first region and a second region which are spaced apart, the second surface includes a third region and a fourth region which are spaced apart, the first region is provided with a first tunneling passivation structure and a first electrode, and the third region is provided with a second tunneling passivation structure and a second electrode.

[0008] In one embodiment, the first surface of the silicon substrate is recessed relative to the first region in the second region; and / or,

[0009] The second surface of the silicon substrate is recessed relative to the third region in the fourth region.

[0010] In one embodiment, the recessed depth of the first surface of the silicon substrate in the second region is 1 μm to 6 μm; and / or,

[0011] The second surface of the silicon substrate has a depression depth of 1 μm to 6 μm in the fourth region.

[0012] In one embodiment, the height difference between the surface of the first tunneling passivation structure facing away from the silicon substrate and the first surface of the silicon substrate in the second region is 0.1 μm to 6 μm; and / or,

[0013] The height difference between the surface of the second tunneling passivation structure facing away from the silicon substrate and the second surface of the silicon substrate in the fourth region is 0.1 μm to 6 μm.

[0014] In one embodiment, the diffusion layer includes a first diffusion layer located in the first region and a second diffusion layer located in the second region.

[0015] In one embodiment, the doping concentration of the second diffusion layer is greater than that of the first diffusion layer; and / or,

[0016] The doping concentration of the second diffusion layer is 1E18 cm -3 ~5E19 cm -3 ; and / or,

[0017] The doping concentration of the first diffusion layer is 1E17 cm -3 ~5E19 cm -3 .

[0018] In one embodiment, the first tunneling passivation structure includes a first tunneling layer and a first doping layer stacked in sequence in the first region, the second tunneling passivation structure includes a second tunneling layer and a second doping layer stacked in sequence in the third region, the first electrode is in electrical contact with the first doping layer, the second electrode is in electrical contact with the second doping layer, the doping type of the first doping layer is the same as that of the diffusion layer, and the doping type of the second doping layer is opposite to that of the first doping layer.

[0019] In one embodiment, the diffusion layer includes a first diffusion layer located in the first region, and the doping concentration of the first diffusion layer is less than that of the first doping layer.

[0020] In one embodiment, the first tunneling layer is any one or a combination of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0021] The thickness of the first tunneling layer is 1.5 nm to 2.5 nm or 1.8 nm to 2.2 nm; and / or,

[0022] The first doping layer is a doped polysilicon layer with a thickness of 80 nm to 400 nm or 200 nm to 300 nm;

[0023] The doping concentration of the first doping layer is 1E19 cm-3 ~1E20 cm -3 ; and / or,

[0024] The second tunneling layer is any one or a combination of multiple ones of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0025] The thickness of the second tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 1.8 nm; and / or,

[0026] The second doping layer is a doped polysilicon layer, and the thickness is 50 nm to 150 nm or 90 nm to 130 nm; and / or,

[0027] The silicon substrate is an N-type silicon substrate, the diffusion layer is a P-type diffusion layer, the first doping layer is a P-type doping layer, and the second doping layer is an N-type doping layer.

[0028] In one embodiment, a first passivation layer covering the first tunneling passivation structure and the second region of the silicon substrate is provided on the first surface of the silicon substrate, and a second passivation layer covering the second tunneling passivation structure and the fourth region of the silicon substrate is provided on the second surface of the silicon substrate.

[0029] In one embodiment, the height difference between the surface of the first passivation layer facing away from the silicon substrate in the first region and the second region is 0.1 μm to 6 μm; and / or,

[0030] The height difference between the surface of the second passivation layer facing away from the silicon substrate in the third region and the fourth region is 0.1 μm to 6 μm.

[0031] In one embodiment, the first passivation layer includes one or a combination of multiple layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer; and / or,

[0032] The second passivation layer includes one or a combination of multiple layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0033] In one embodiment, the first passivation layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3 nm to 6 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm; and / or,

[0034] The second passivation layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3 nm to 6 nm, and the thickness of the silicon nitride layer is 60 nm to 100 nm.

[0035] In one embodiment, the first region in the first surface of the silicon substrate is a matte surface with a pyramid structure or a polished surface with a tower base, and the second region in the first surface of the silicon substrate is a matte surface with a pyramid structure.

[0036] In one embodiment, the bottom width of the pyramid structure in the first region is 0.5 μm to 1.5 μm, and the height is 0.3 μm to 1 μm; or, the base width of the pyramid in the first region is 1 μm to 5 μm, and the base height is 0.1 μm to 0.4 μm; and / or,

[0037] the bottom width of the pyramid structure in the second region is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm.

[0038] In one embodiment, both the third region and the fourth region in the second surface of the silicon substrate are polished surfaces.

[0039] In one embodiment, the width of the first region is 20 μm to 200 μm or 80 μm to 100 μm; and / or,

[0040] the width of the third region is 20 μm to 200 μm or 80 μm to 100 μm.

[0041] The technical solution provided by another embodiment of the present invention is as follows:

[0042] A method for manufacturing a solar cell, the manufacturing method comprising the following steps:

[0043] Provide a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the first surface comprising a first region and a second region distributed at intervals, and the second surface comprising a third region and a fourth region distributed at intervals;

[0044] Prepare a first tunneling passivation structure in the first region of the first surface, and then form a diffusion layer below the first surface of the silicon substrate;

[0045] Prepare a second tunneling passivation structure in the third region of the second surface;

[0046] Prepare a first electrode in the first region of the first surface, and a second electrode in the third region of the second surface.

[0047] In one embodiment, preparing the first tunneling passivation structure in the first region of the first surface includes:

[0048] Prepare a first tunneling layer, a first intrinsic layer, and a first mask layer on the first surface;

[0049] Use a laser process to pattern and open the first mask layer in the second region, exposing the first intrinsic layer in the second region;

[0050] Use a wet etching process to remove the first intrinsic layer and the first tunneling layer in the second region, exposing the silicon substrate in the second region;

[0051] Remove the first mask layer in the first region to expose the first intrinsic layer in the first region;

[0052] Convert the first intrinsic layer into a first doped layer by a diffusion process.

[0053] In one embodiment, the preparation method further includes:

[0054] Use a wet etching process to remove the first intrinsic layer and the first tunneling layer in the second region, and etch a part of the silicon substrate in the second region.

[0055] In one embodiment, the first intrinsic layer is an intrinsic polysilicon layer, the first tunneling layer is any one or a combination of a silicon oxide layer and a silicon oxynitride layer, and the etching solution in the wet etching process is an alkaline solution; and / or,

[0056] The first mask layer is any one or a combination of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer, and the first mask layer is removed using an acid solution; and / or,

[0057] The thickness of the first mask layer is 20 nm to 80 nm.

[0058] In one embodiment, the preparation method further includes:

[0059] Before preparing the first tunneling layer, the first intrinsic layer, and the first mask layer on the first surface, prepare a textured surface with a pyramid structure on the first surface of the silicon substrate by an alkaline texturing process, the bottom width of the pyramid structure is 0.5 μm to 1.5 μm, and the height is 0.3 μm to 1 μm; or, prepare a polished surface with a tower base on the first surface of the silicon substrate by an alkaline texturing process and an alkaline polishing process, the tower base width is 1 μm to 5 μm, and the tower base height is 0.1 μm to 0.4 μm;

[0060] After using a wet etching process to remove the first intrinsic layer and the first tunneling layer in the second region, prepare a textured surface with a pyramid structure on the second region on the first surface of the silicon substrate by an alkaline texturing process, the bottom width of the pyramid structure is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm.

[0061] In one embodiment, use a one-step diffusion process to convert the first intrinsic layer into a first doped layer, and simultaneously form a first diffusion layer and a second diffusion layer in the first region and the second region on the first surface of the silicon substrate, respectively.

[0062] In one embodiment, the doping concentration of the first diffusion layer is less than the doping concentration of the first doped layer, and the doping concentration of the second diffusion layer is greater than the doping concentration of the first diffusion layer.

[0063] In one embodiment, the preparation method further includes:

[0064] An acid solution is used to remove the diffusion bypass layer generated on the second surface of the silicon substrate during the diffusion process;

[0065] An alkaline solution is used to etch the second surface of the silicon substrate.

[0066] In one embodiment, preparing a second tunneling passivation structure in a third region of the second surface includes:

[0067] Preparing a second tunneling layer, a second doping layer, and a second mask layer on the second surface;

[0068] A laser process is used to pattern and open the second mask layer in a fourth region, exposing the second doping layer in the fourth region;

[0069] A wet etching process is used to remove the second doping layer and the second tunneling layer in the fourth region, exposing the silicon substrate in the fourth region;

[0070] The second mask layer in the third region is removed, exposing the second doping layer in the third region.

[0071] In one embodiment, the preparation method further includes:

[0072] A wet etching process is used to remove the second doping layer and the second tunneling layer in the fourth region, and a part of the silicon substrate in the fourth region is etched.

[0073] In one embodiment, the second doping layer is a doped polysilicon layer, the second tunneling layer is any one or a combination of a silicon oxide layer and a silicon oxynitride layer, and the etching solution in the wet etching process is an alkaline solution; and / or,

[0074] The second mask layer is any one or a combination of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer, and the second mask layer is removed using an acid solution; and / or,

[0075] The thickness of the second mask layer is 15 nm to 25 nm.

[0076] In one embodiment, the preparation method further includes:

[0077] After using a wet etching process to remove the second doping layer and the second tunneling layer in the fourth region, an alkaline polishing process is performed on the silicon substrate in the fourth region.

[0078] In one embodiment, the preparation method further includes:

[0079] A first passivation layer is prepared on the first surface of the silicon substrate, and a first electrode that penetrates the first passivation layer and is in electrical contact with the first tunneling passivation structure is prepared in a first region of the first surface. The first passivation layer includes one or a combination of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer; and / or,

[0080] A second passivation layer is prepared on the second surface of the silicon substrate, and a second electrode that penetrates the second passivation layer and is in electrical contact with the second tunneling passivation structure is prepared in a third region of the second surface. The second passivation layer includes one or a combination of multiple layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0081] Compared with the prior art, the present invention has the following beneficial effects:

[0082] The solar cell of the present invention is a double-sided TOPCon cell, and both the front and back surfaces have local tunneling passivation structures, which ensure the passivated contact of the front metal region and reduce the parasitic absorption of the front non-metal region at the same time, and can greatly improve the cell efficiency. Description of the Drawings

[0083] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0084] Figure 1 It is a schematic structural diagram of the solar cell in Embodiment 1 of the present invention;

[0085] Figure 2 is Figure 1 a partial enlarged structural diagram of part A in

[0086] Figure 3 is Figure 1 a partial enlarged structural diagram of part B in

[0087] Figures 4a to 4k It is a process flow chart of the preparation of the solar cell in Embodiment 1 of the present invention;

[0088] Figure 5 It is a schematic structural diagram of the solar cell in Embodiment 3 of the present invention;

[0089] Figure 6 It is a schematic structural diagram of the solar cell in Embodiment 4 of the present invention.

[0090] Main reference numeral description:

[0091] 10 - Substrate, 11 - Diffusion layer, 111 - First diffusion layer, 112 - Second diffusion layer, 21 - First tunneling layer, 22 - Second tunneling layer, 31 - First doping layer, 31’ - First intrinsic layer, 32 - Second doping layer, 41 - First electrode, 42 - Second electrode, 51 - First passivation layer, 52 - Second passivation layer, 511 - First alumina layer, 512 - First silicon nitride layer, 521 - Second alumina layer, 522 - Second silicon nitride layer, 61 - First mask layer, 62 - Second mask layer, S1 - First surface, S11 - First region, S12 - Second region, S2 - Second surface, S21 - Third region, S22 - Fourth region. Detailed implementation manners

[0092] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0093] In the present invention, unless otherwise clearly defined and limited, the first feature being “on” or “under” the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being “above”, “over” and “on” the second feature may be that the first feature is directly above or obliquely above the second feature, or simply means that the first feature has a higher horizontal height than the second feature. The first feature being “under”, “beneath” and “under” the second feature may be that the first feature is directly below or obliquely below the second feature, or simply means that the first feature has a lower horizontal height than the second feature.

[0094] The present invention discloses a solar cell, including a silicon substrate. The silicon substrate includes a first surface and a second surface which are oppositely arranged. A diffusion layer is formed at the first surface of the silicon substrate. The first surface includes a first region and a second region which are spaced apart. The second surface includes a third region and a fourth region which are spaced apart. The first region is provided with a first tunneling passivation structure and a first electrode, and the third region is provided with a second tunneling passivation structure and a second electrode.

[0095] The present invention also discloses a method for manufacturing a solar cell, including the following steps:

[0096] Provide a silicon substrate. The silicon substrate includes a first surface and a second surface which are oppositely arranged. The first surface includes a first region and a second region which are spaced apart. The second surface includes a third region and a fourth region which are spaced apart;

[0097] A first tunneling passivation structure is prepared in a first region of the first surface, and then a diffusion layer is formed below the first surface of the silicon substrate;

[0098] A second tunneling passivation structure is prepared in a third region of the second surface;

[0099] A first electrode is prepared in the first region of the first surface, and a second electrode is prepared in the third region of the second surface.

[0100] The solar cell of the present invention is a double-sided TOPCon cell, and both the front and back surfaces have local tunneling passivation structures, which ensure the passivated contact of the front metal region and reduce the parasitic absorption of the front non-metal region at the same time. Compared with the single-sided TOPCon cell in the prior art, the cell efficiency can be greatly improved.

[0101] The present invention will be further described below in conjunction with specific embodiments.

[0102] Embodiment 1:

[0103] Refer Figure 1 And Figure 2 、 Figure 3 As shown, in this embodiment, the solar cell is a double-sided TOPCon cell, including a silicon substrate 10. The silicon substrate 10 includes a first surface S1 and a second surface S2 arranged opposite to each other. The first surface S1 includes a first region S11 and a second region S12 distributed at intervals, and the second surface S2 includes a third region S21 and a fourth region S22 distributed at intervals. The first surface S1 is the front surface (i.e., the main light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10. The first region S11 is the front metal region, the second region S12 is the front non-metal region, the third region S21 is the back metal region, and the fourth region S22 is the back non-metal region. Of course, in other embodiments, the first surface S1 can also be the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10, and the second surface S2 is the front surface (i.e., the main light-receiving surface) of the silicon substrate 10.

[0104] In the double-sided TOPCon cell of this embodiment, first tunneling passivation structures are arranged at intervals on the first surface S1, and second tunneling passivation structures are arranged at intervals on the second surface S2. A diffusion layer 11 is formed at the entire first surface S1 through a diffusion process. Specifically, the first tunneling passivation structure includes a first tunneling layer 21 and a first doping layer 31 stacked in sequence on the first region S11, and the second tunneling passivation structure includes a second tunneling layer 22 and a second doping layer 32 stacked in sequence on the third region S21.

[0105] In addition, a first electrode 41 is provided on a first region S11 of the first surface S1. The first electrode 41 is in electrical contact with a first doping layer 31 below it. A second electrode 42 is provided on a third region S21 of the second surface S2. The second electrode 42 is in electrical contact with a second doping layer 32 below it. In this embodiment, the first doping layer 31 has the same doping type as the diffusion layer 11, and the second doping layer 32 has a doping type opposite to that of the first doping layer 31.

[0106] Further, in this embodiment, a first passivation layer 51 covering the first tunneling passivation structure and the second region S12 of the silicon substrate 10 is provided on the first surface S1 of the silicon substrate 10, and a second passivation layer 52 covering the second tunneling passivation structure and the fourth region S22 of the silicon substrate 10 is provided on the second surface S2 of the silicon substrate 10.

[0107] The materials, thicknesses, doping types, etc. of each layer in the solar cell of this embodiment will be described in detail below.

[0108] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm. Preferably, a light trapping structure is formed on the first surface S1 of the silicon substrate 10 in this embodiment. For example, a pyramidal texture can be formed by alkaline texturing, or a polished surface with a tower base can be formed by alkaline texturing and alkaline polishing; the entire second surface S2 of the silicon substrate 10 is a polished surface with a reflectivity of 45% to 55%.

[0109] The first tunneling layer 21 in this embodiment is any one or a combination of an oxide layer, a silicon oxynitride layer, etc., with a thickness of 1.5 nm to 2.5 nm, preferably 1.8 nm to 2.2 nm; the second tunneling layer 22 is any one or a combination of an oxide layer, a silicon oxynitride layer, etc., with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 1.8 nm.

[0110] Both the first doping layer 31 and the second doping layer 32 in this embodiment can be a single-layer doped polysilicon layer or a multi-layer doped polysilicon layer with a gradually increasing doping concentration from the inside to the outside (i.e., in the direction away from the silicon substrate). The thickness of the first doping layer 31 is 80 nm to 400 nm, preferably 200 nm to 300 nm; the thickness of the second doping layer 32 is 50 nm to 150 nm, preferably 90 nm to 130 nm. The first doping layer 31 is a P-type doped polysilicon layer, such as boron doping; the second doping layer 32 is an N-type doped polysilicon layer, such as phosphorus doping.

[0111] In addition, the silicon substrate in this embodiment is an N-type silicon substrate, and the diffusion layer 11 is a P-type diffusion layer. For example, a boron diffusion process is used to form a boron diffusion layer below the first surface S1 (i.e., inside the silicon substrate), thereby forming a PN junction. Electron-hole pairs are generated after illumination. The diffusion layer in the second region S12 can ensure a better photovoltaic effect, thereby increasing the current and improving the battery efficiency. Exemplarily, the doping concentration of the diffusion layer 11 is 1E19 cm -3 ~1E20 cm -3 .

[0112] Furthermore, the first doping layer 31 in this embodiment is a P-type doped polysilicon layer formed by a diffusion process. For example, an intrinsic polysilicon layer is first deposited on the first tunneling layer 21, and then the intrinsic polysilicon layer is converted into a boron-doped polysilicon layer by a boron diffusion process. Preferably, the first doping layer 31 and the diffusion layer 11 are prepared by a one-step diffusion process.

[0113] Combined Figure 2 As shown, the diffusion layer 11 in this embodiment includes a first diffusion layer 111 located in the first region S11 and a second diffusion layer 112 located in the second region S12. Exemplarily, the doping concentration of the second diffusion layer 112 is 1E18 cm -3 ~5E19 cm -3 , and the doping concentration of the first diffusion layer 111 is 1E17 cm -3 ~5E19 cm -3 .

[0114] Referring Figure 1 and combined Figure 2 As shown, on the first surface S1 of the silicon substrate 10 in this embodiment, a first tunneling passivation structure is only provided in the first region S11, while there is no first tunneling passivation structure in the second region S12, and the second region S12 is recessed relative to the first region S11. The height of the surface of the first doping layer 31 facing away from the silicon substrate in the first region S11 is higher than the height of the first surface S1 of the silicon substrate 10 in the second region S12. The height difference H1 between the two is the sum of the thickness of the first tunneling layer 21, the thickness of the first doping layer 31, and the recessed depth of the second region S12. The height difference H1 in this embodiment is 0.1 μm to 6 μm. Preferably, the recessed depth is 1 μm to 6 μm. The size of the height difference H1 is affected by the process and is usually at least 1 μm. The larger the height difference H1, the larger the light-receiving area on the front surface, thereby further improving the battery efficiency.

[0115] In addition, since the width of the second region S12 in the first surface S1 is larger and the width of the first region S11 is smaller, in order to ensure that the first surface S11 has a better light trapping effect, a suede surface with a better light trapping effect needs to be formed on the second region S12, while a suede surface with a poor light trapping effect can be formed on the first region S11. The larger the size of the pyramid structure, the better the light trapping effect.

[0116] Exemplarily, in this embodiment, the first region S11 in the first surface S1 is a suede surface with a pyramid structure, the bottom width of the pyramid structure is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm; while the second region S12 in the first surface S1 is a suede surface with a pyramid structure, the bottom width of the pyramid structure is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm. Among them, after the alkali texturing process on the silicon substrate surface, a suede surface with a pyramid structure will be formed. The bottom shape of the pyramid structure can be triangular, quadrilateral, etc. Define the bottom width of the pyramid structure as the average value of the widths of the bottom shapes of the pyramid structure. Taking the bottom shape as a square as an example, the bottom width is the side length of the square.

[0117] Refer Figure 1 And in combination with Figure 3 As shown, on the second surface S2 of the silicon substrate 10 in this embodiment, a second tunneling passivation structure is only provided in the third region S21, while there is no second tunneling passivation structure in the fourth region S22, and the fourth region S22 is recessed relative to the third region S21. The height of the surface of the second doped layer 32 facing away from the silicon substrate in the third region S21 is higher than the height of the second surface S2 of the silicon substrate 10 in the fourth region S22. The height difference H2 between the two is the sum of the thickness of the second tunneling layer 22, the thickness of the second doped layer 32, and the recessed depth of the fourth region S22. The height difference H2 in this embodiment is 0.1 μm to 6 μm. Preferably, the recessed depth is 1 μm to 6 μm.

[0118] In addition, a first passivation layer 51 and a second passivation layer 52 are respectively stacked on the first surface S1 and the second surface S2 of the silicon substrate in this embodiment.

[0119] Specifically, the first passivation layer 51 covers the first tunneling passivation structure and the second region S12 of the silicon substrate 10, and the second passivation layer 52 covers the second tunneling passivation structure and the fourth region S22 of the silicon substrate 10. The first passivation layer 51 and the second passivation layer 52 can be one or a combination of multiple layers of silicon oxide (SiO X ), aluminum oxide (AlO X ), silicon nitride (SiN X ), and silicon oxynitride (SiN X O Y ).

[0120] Exemplarily, the first passivation layer 51 in this embodiment includes a first aluminum oxide layer 511 and a first silicon nitride layer 512 stacked in sequence, and the second passivation layer 52 includes a second aluminum oxide layer 521 and a second silicon nitride layer 522 stacked in sequence. The first aluminum oxide layer 511 is in direct electrical contact with the surface of the silicon substrate in the second region S12, and the second aluminum oxide layer 521 is in direct electrical contact with the surface of the silicon substrate in the fourth region S22, which can ensure the passivation effect of the non-metal regions on the front and back surfaces. Preferably, the thicknesses of both the first aluminum oxide layer 511 and the second aluminum oxide layer 521 are 3 nm to 6 nm, and the thicknesses of both the first silicon nitride layer 512 and the second silicon nitride layer 522 are 60 nm to 100 nm.

[0121] As shown Figure 2 in the figure, the thickness of the first passivation layer 51 in the first region S11 and the second region S12 in this embodiment is equal. Therefore, there is a height difference H3 between the surfaces of the first passivation layer 51 facing away from the silicon substrate 10 in the first region S11 and the second region S12, and the height difference H3 is equal to the height difference H1, which is 0.1 μm to 6 μm.

[0122] As shown Figure 3 in the figure, the thickness of the second passivation layer 52 in the third region S21 and the fourth region S22 in this embodiment is equal. Therefore, there is a height difference H4 between the surfaces of the second passivation layer 52 facing away from the silicon substrate 10 in the third region S21 and the fourth region S22, and the height difference H4 is equal to the height difference H2, which is 0.1 μm to 6 μm.

[0123] In this embodiment, the first electrode 41 on the first surface S1 is in electrical contact with the first doping layer 31, but the bottommost first tunneling layer 21 cannot be damaged to ensure the tunneling effect of the first tunneling layer 21. The second electrode 42 on the second surface S2 is in electrical contact with the second doping layer 32, but the bottommost second tunneling layer 22 cannot be damaged to ensure the tunneling effect of the second tunneling layer 22.

[0124] As shown Figure 2 again in the figure, the first electrode 41 in this embodiment is distributed directly above the first region S11, and the projection of the first electrode 41 on the first surface S1 is within the first region S11. Taking the gate line electrode as an example, the gate line electrode may include multiple main gate lines and multiple sub-gate lines (or called fine gate lines) vertically distributed. The main gate lines are usually prepared using non-burn-through type pastes. The first electrode 41 in the present invention is described by taking the sub-gate line as an example. The width of the sub-gate line can be 5 μm to 40 μm. The first region S11 includes multiple linearly distributed regions spaced apart from each other. The width of the first region S11 is 20 μm to 200 μm, preferably 80 μm to 100 μm.

[0125] Taking the 210 TOPCon cell as an example, the cell size is 203.396 ± 15 mm, the number of fine grid lines is 230, the width is 15 μm to 100 μm, and the spacing between adjacent fine grid lines is 0.907 ± 0.015 mm. The spacing between adjacent first regions S11 is equal to the spacing between adjacent fine grid lines. Each first region S11 is distributed with one fine grid line, and the width of the first region S11 is greater than the width of the fine grid line. For example, the width of the fine grid line is 40 μm, and the width of the first region S11 is 80 μm.

[0126] The above description takes the first electrode 41 and the first region S11 on the first surface S1 of the silicon substrate 10 as examples. The second electrode 42 and the third region S21 on the second surface S2 of the silicon substrate 10 are basically the same as those on the first surface S1, and will not be elaborated here.

[0127] The preparation method of the solar cell in this embodiment specifically includes the following steps:

[0128] 1. Double-sided polishing

[0129] Refer Figure 4a As shown, a silicon substrate 10 is provided. The silicon substrate 10 includes a first surface S1 and a second surface S2 that are oppositely arranged. The first surface S1 includes a first region S11 and a second region S12 that are spaced apart. The second surface S2 includes a third region S21 and a fourth region S22 that are spaced apart. The first surface S1 is the front surface (i.e., the main light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10. The first region S11 is the front metal region, the second region S12 is the front non-metal region, the third region S21 is the back metal region, and the fourth region S22 is the back non-metal region. Of course, in other embodiments, the first surface S1 can also be the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10, and the second surface S2 is the front surface (i.e., the main light-receiving surface) of the silicon substrate 10.

[0130] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm. The first surface S1 and the second surface S2 of the silicon substrate 10 are polished by an alkaline polishing process to form a polished surface with a reflectivity of 45% to 55%. The alkaline polishing solution can contain NaOH, KOH, TMAH, etc.

[0131] Preferably, a textured surface with a pyramid structure is prepared on the first surface S1 and the second surface S2 of the silicon substrate through an alkaline texturing process. The bottom width of the pyramid structure is 0.5 μm to 1.5 μm, and the height is 0.3 μm to 1 μm.

[0132] 2. Prepare the first tunneling passivation structure

[0133] Prepare a first tunneling layer 21 and a first doping layer 31 that are sequentially stacked in a first region S11 of the first surface S1. Specifically, the following steps are included:

[0134] First, refer Figure 4b As shown, deposit the first tunneling layer 21 and the first intrinsic layer 31' over the entire surface of the first surface S1.

[0135] Exemplarily, in this embodiment, the LPCVD (Low Pressure Chemical Vapor Deposition) process is used for deposition; the first tunneling layer 21 is any one or a combination of an oxide layer, a silicon oxynitride layer, etc., with a thickness of 1.5 nm to 2.5 nm, preferably 1.8 nm to 2.2 nm, and the first intrinsic layer 31' is an intrinsic polysilicon layer with a thickness of 80 nm to 400 nm, preferably 200 nm to 300 nm. Compared with the PECVD process, the LPCVD process deposits a better-quality intrinsic polysilicon layer thin film.

[0136] Then, refer Figure 4c As shown, deposit a first mask layer 61 on the first intrinsic layer 31'.

[0137] Exemplarily, the first mask layer 61 is deposited using the PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and the first mask layer 61 is an inorganic mask, such as a silicon oxide (SiO X ) mask, with a thickness of 20 nm to 80 nm, preferably 30 nm to 40 nm.

[0138] Subsequently, refer Figure 4d As shown, use a laser process to pattern-open the first mask layer 61 in the second region S12, exposing the first intrinsic layer 31' in the second region S12.

[0139] Use a laser process to pattern-open the film. According to the number of gate line electrodes and the width of the first region S11, remove the first mask layer 61 in the second region S12, and only retain the first mask layer 61 in the first region S11. For example, in this embodiment, the width of the first region S11 is 20 μm to 200 μm, preferably 80 μm to 100 μm.

[0140] Finally, refer Figure 4e As shown, use a wet etching process to remove the first intrinsic layer 31' and the first tunneling layer 21 in the second region S12, exposing the silicon substrate 10 in the second region S12, and remove the first mask layer 61 in the first region S11, exposing the first intrinsic layer 31' in the first region S11.

[0141] The wet etching process includes the following steps:

[0142] First, use an alkaline etching process to remove the first intrinsic layer 31' and the first tunneling layer 21 in the second region S12, and etch a part of the silicon substrate in the second region S12 to form a groove in the second region S12 of the first surface S1. Due to the blocking of the first mask layer 61 in the first region S11, the first intrinsic layer 31' below it will not be etched;

[0143] Then, use an alkaline texturing process to texture the second region S12 on the first surface S1 to prepare a textured surface with a pyramid structure in the second region S12. For example, in this embodiment, the bottom width of the pyramid structure in the second region S12 is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm, while the first region S11 is the original textured surface with a pyramid structure, the bottom width of the pyramid structure is 0.5 μm to 1.5 μm, and the height is 0.3 μm to 1 μm

[0144] Finally, use an acid solution to remove the first mask layer 61 and simultaneously remove the silicon oxide formed on the surface during the deposition process.

[0145] 3. Front surface diffusion process

[0146] Refer Figure 4f As shown, use a diffusion process to diffuse the first surface S1 of the silicon substrate 10 and the first intrinsic layer 31' to form a diffusion layer 11 and a first doped layer 31.

[0147] Specifically, a P-type doped diffusion layer 11 (i.e., P+ emitter) is formed by a boron diffusion process at the first surface S1 of the silicon substrate 10, and the diffusion temperature is 920 °C to 980 °C.

[0148] In the second region S12, since there is no blocking of the first tunneling layer 21 above, boron atoms directly diffuse downward from the first surface S1 of the silicon substrate, thereby forming a second diffusion layer 112; while in the first region S11, boron atoms first diffuse into the intrinsic layer and then diffuse downward through the first tunneling layer 21, thereby forming a first diffusion layer 111 in the first region S11; in addition, the first intrinsic layer 31' can be simultaneously boron-doped during the diffusion process to form a boron-doped polysilicon layer. Preferably, the doping concentration of the second diffusion layer 112 is 1E18 cm -3 ~5E19 cm -3 , the doping concentration of the first diffusion layer 111 is 1E17 cm -3 ~5E19 cm -3 , the doping concentration of the first doped layer 31 is 1E19 cm -3 ~1E20 cm -3 . During the boron diffusion process, BSG (boron silicate glass) is formed on the second surface S2 of the silicon substrate.

[0149] In this embodiment, an intrinsic polysilicon layer is first prepared, and then a boron diffusion layer and a boron-doped polysilicon layer are simultaneously prepared by a one-step diffusion process, which can optimize the process and improve the battery efficiency. If the first surface S1 of the silicon substrate 10 is first subjected to boron diffusion, and then the first tunneling layer and the boron-doped polysilicon layer are sequentially deposited, during the subsequent wet etching process of the second region S12, the boron diffusion layer formed in the second region S12 will be etched away, reducing the built-in electric field of the front PN junction and affecting the photovoltaic effect, thereby reducing the battery efficiency.

[0150] 4. Backside de-spreading and backside etching

[0151] Through a chain machine, an acid solution (such as an HF solution) is used to remove the sputtered layer generated on the second surface S2 of the silicon substrate 10 during the diffusion process. Taking the boron diffusion process as an example, the sputtered layer is boron silicate glass (BSG);

[0152] Through a tank machine, an alkaline solution is used to etch the second surface S2 of the silicon substrate 10 to remove the P+ junction sputtered on the backside during the diffusion process.

[0153] 5. Preparation of the second tunneling passivation structure

[0154] On the third region S21 of the second surface S1, a second tunneling layer 22 and a second doping layer 32 are sequentially stacked. Specifically, the following steps are included:

[0155] First, refer Figure 4g As shown, the second tunneling layer 22, the second doping layer 32, and the second mask layer 62 are deposited over the entire surface of the second surface S1.

[0156] Exemplarily, in this embodiment, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process is used for deposition; the second tunneling layer 22 is any one or a combination of an oxide layer, a silicon oxynitride layer, etc., with a thickness of 0.5 nm to 3 nm, preferably 1.5 nm to 1.8 nm, the second doping layer 32 is a doped polysilicon layer, with a thickness of 50 nm to 150 nm, preferably 90 nm to 130 nm, and the second mask layer 62 is an inorganic mask, such as a silicon oxide (SiO X ) mask, with a thickness of 15 nm to 25 nm.

[0157] Subsequently, refer Figure 4h As shown, a laser process is used to pattern and open the second mask layer 62 in the fourth region S22, exposing the second doping layer 32 in the fourth region S22.

[0158] Use a laser process to perform pattern opening and film removal. According to the number of grid line electrodes and the width of the third region S21, remove the second mask layer 62 of the fourth region S22, and only retain the second mask layer 62 of the third region S21. For example, in this embodiment, the width of the third region S21 is 20 μm to 200 μm, preferably 80 μm to 100 μm.

[0159] Finally, refer Figure 4i As shown, use a wet etching process to remove the second doped layer 32 and the second tunneling layer 22 of the fourth region S22, expose the silicon substrate 10 of the fourth region S22, and remove the second mask layer 62 of the third region S21 to expose the second doped layer 32 of the first region S11.

[0160] The wet etching process includes the following steps:

[0161] First, use an alkaline etching process to remove the second doped layer 32 and the second tunneling layer 22 of the fourth region S22, and etch a part of the silicon substrate of the fourth region S22 to form a groove in the fourth region S22 of the second surface S2. Due to the blocking of the second mask layer 62, the second doped layer 32 below the third region S21 will not be etched; the alkaline etching process can simultaneously remove the polysilicon deposited on the front side.

[0162] Then, use an alkaline polishing process to polish the fourth region S22 on the second surface S2.

[0163] Finally, use an acid solution to remove the second mask layer 62 and simultaneously remove the silicon oxide formed on the surface during the deposition process.

[0164] 6. Double-sided passivation

[0165] Refer Figure 4j As shown, prepare a passivation layer on the first surface S1 and the second surface S2.

[0166] Specifically, in this embodiment, use the ALD (Atomic Layer Deposition) process to prepare the first passivation layer 51 and the second passivation layer 52 on the first surface S1 and the second surface S2 respectively. Among them, the first passivation layer 51 includes a first aluminum oxide layer 511 and a first silicon nitride layer 512 stacked in sequence, the second passivation layer 52 includes a second aluminum oxide layer 521 and a second silicon nitride layer 522 stacked in sequence, the thicknesses of the first aluminum oxide layer 511 and the second aluminum oxide layer 521 are both 3 nm to 6 nm, and the thicknesses of the first silicon nitride layer 512 and the second silicon nitride layer 522 are both 60 nm to 100 nm.

[0167] 7. Prepare metal electrodes

[0168] Refer Figure 4kAs shown, a first electrode 41 in contact with the silicon substrate with a 10-ohm contact is prepared in a first region S11 on the first surface S1, and a second electrode 42 in contact with the silicon substrate with a 10-ohm contact is prepared on the second surface S2.

[0169] Specifically, in this embodiment, a screen printing process is used to print metal layers in the first region S11 on the first surface S1 and the third region S21 on the second surface S2 respectively, forming the first electrode 41 and the second electrode 42 in contact with the silicon substrate with a 10-ohm contact. Preferably, the first electrode 41 and the second electrode 42 in this embodiment are both silver grid line electrodes.

[0170] 8. LIF Process

[0171] The LIF (Laser Induced Firing) process is used to sinter the electrodes, which can increase the contact between the electrodes and the doped layer and significantly reduce the contact resistance between the metal and the doped layer.

[0172] Example 2:

[0173] The structure and preparation method of the solar cell in this embodiment are substantially the same as those in Example 1. The difference is that in this embodiment, a tower base with poor light trapping effect is formed in the first region S11 on the first surface S1, and a suede surface with better light trapping effect is formed in the second region S12. Compared with the tower base of the same size, the pyramid structure has a better light trapping effect.

[0174] Exemplarily, in this embodiment, the first region S11 on the first surface S1 is a polished surface with a tower base, the width of the tower base is 1 μm to 5 μm, and the height of the tower base is 0.1 μm to 0.4 μm; while the second region S12 on the first surface S1 is a suede surface with a pyramid structure, the bottom width of the pyramid structure is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm. Among them, after the alkali texturing process on the surface of the silicon substrate, a suede surface with a pyramid structure will be formed, and after the alkali polishing process, the pyramid structure is polished to form a tower base. The tower base is the base left after the suede surface of the pyramid structure is polished. The bottom of the pyramid structure and the bottom of the tower base can be triangular, quadrilateral, etc. The bottom width of the pyramid structure is defined as the average value of the widths of the bottom shapes of the pyramid structure, and the bottom width of the tower base is the average value of the widths of the bottom shapes of the tower base. Taking the bottom shape as a square as an example, the bottom width is the side length of the square.

[0175] Example 3:

[0176] Refer Figure 5As shown, the structure and preparation method of the solar cell in this embodiment are substantially the same as those in Embodiment 1. The difference is that in this embodiment, the first surface S1 of the silicon substrate is flush in the first region S11 and the second region S12. In the wet etching process step, the parameters of the alkaline etching process are controlled, and the etching is stopped after etching away the first intrinsic layer 31' and the first tunneling layer 21 in the second region S12.

[0177] Compared with Embodiment 1, the surface of the second region in this embodiment is relatively smooth, so that the first passivation layer subsequently deposited on the silicon substrate has better uniformity and better passivation performance, thus improving the recombination defect problem of the solar cell.

[0178] Embodiment 4:

[0179] Refer Figure 6 As shown, the structure and preparation method of the solar cell in this embodiment are substantially the same as those in Embodiment 1. The difference is that in this embodiment, the second surface S2 of the silicon substrate is flush in the third region S21 and the fourth region S22. In the wet etching process step, the parameters of the alkaline etching process are controlled, and the etching is stopped after etching away the second doped layer 32 and the second tunneling layer 22 in the fourth region S22.

[0180] Compared with Embodiment 1, the surface of the fourth region in this embodiment is relatively smooth, so that the second passivation layer subsequently deposited on the silicon substrate has better uniformity and better passivation performance, thus improving the recombination defect problem of the solar cell.

[0181] For the double-sided TOPCon cells in the above embodiments, the front and back sides both adopt a Poly-finger structure with local tunneling passivation contact, which ensures the contact passivation of the first region on the front side and the third region on the back side, and at the same time reduces the parasitic absorption in the second region on the front side. Compared with the single-sided TOPCon cells in the prior art, the cell efficiency can be greatly improved, and the preparation process is simple and suitable for mass production.

[0182] The metal regions on both the front and back sides of the cell adopt a polysilicon (poly) process, which minimizes the recombination in the metal regions, effectively reduces the reverse saturation current, and can significantly improve the cell efficiency.

[0183] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

[0184] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized in that: The solar cell includes a silicon substrate, the silicon substrate includes a first surface and a second surface arranged opposite to each other, a diffusion layer is formed on the first surface of the silicon substrate, the first surface includes a first region and a second region distributed at intervals, the second surface includes a third region and a fourth region distributed at intervals, the first region is provided with a first tunneling passivation structure and a first electrode, and the third region is provided with a second tunneling passivation structure and a second electrode.

2. The solar cell according to claim 1, characterized in that: The first surface of the silicon substrate is arranged to be recessed in the second region relative to the first region; and / or, The second surface of the silicon substrate is recessed relative to the third region in a fourth region.

3. The solar cell according to claim 1 or 2, characterized in that: The first surface of the silicon substrate has a recessed depth in the second region of 1 μm to 6 μm; and / or, The second surface of the silicon substrate is recessed in the fourth region to a depth of 1 μm to 6 μm.

4. The solar cell according to claim 1 or 2, characterized in that: A height difference between a surface of the first tunnel passivation structure facing away from the silicon substrate and the first surface of the silicon substrate in the second region is 0.1 μm to 6 μm; and / or, A height difference between a surface of the second tunnel passivation structure facing away from the silicon substrate and the second surface of the silicon substrate in the fourth region is 0.1 μm to 6 μm.

5. The solar cell according to claim 1, characterized in that: The diffusion layer includes a first diffusion layer located in the first region and a second diffusion layer located in the second region.

6. The solar cell according to claim 5, characterized in that: The doping concentration of the second diffusion layer is greater than the doping concentration of the first diffusion layer; and / or, The doping concentration of the second diffusion layer is 1E18cm -3 ~5E19cm -3 and / or, The doping concentration of the first diffusion layer is 1E17cm -3 ~5E19cm -3 .

7. The solar cell according to claim 1, characterized in that The first tunneling passivation structure includes a first tunneling layer and a first doped layer stacked sequentially in the first region, the second tunneling passivation structure includes a second tunneling layer and a second doped layer stacked sequentially in the third region, the first electrode is electrically in contact with the first doped layer, the second electrode is electrically in contact with the second doped layer, the first doped layer and the diffusion layer have the same doping type, and the second doped layer and the first doped layer have a doping type opposite.

8. The solar cell according to claim 7, characterized in that: The diffusion layer includes a first diffusion layer located in the first region, and a doping concentration of the first diffusion layer is lower than a doping concentration of the first doping layer.

9. The solar cell according to claim 7, characterized in that: The first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or, The thickness of the first tunneling layer is 1.5 nm to 2.5 nm or 1.8 nm to 2.2 nm; and / or, The first doped layer is a doped polysilicon layer with a thickness of 80nm to 400nm or 200nm to 300nm; The doping concentration of the first doping layer is 1E19cm -3 ~1E20cm -3 and / or, The second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or, The thickness of the second tunneling layer is 0.5 nm to 3 nm or 1.5 nm to 1.8 nm; and / or, The second doped layer is a doped polysilicon layer with a thickness of 50nm to 150nm or 90nm to 130nm; and / or, The silicon substrate is an N-type silicon substrate, the diffusion layer is a P-type diffusion layer, the first doping layer is a P-type doping layer, and the second doping layer is an N-type doping layer.

10. The solar cell according to claim 1, characterized in that: A first passivation layer covering the first tunnel passivation structure and the second region of the silicon substrate is disposed on the first surface of the silicon substrate, and a second passivation layer covering the second tunnel passivation structure and the fourth region of the silicon substrate is disposed on the second surface of the silicon substrate.

11. The solar cell according to claim 10, characterized in that The height difference between the first region and the second region of the first passivation layer facing away from the silicon substrate is 0.1 μm to 6 μm; and / or, The height difference between the third region and the fourth region of the surface of the second passivation layer on the side facing away from the silicon substrate is 0.1 μm to 6 μm.

12. The solar cell according to claim 10, characterized in that: The first passivation layer includes a combination of one or more layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer and a silicon oxynitride layer; and / or, The second passivation layer includes one or more layers selected from the group consisting of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer and a silicon oxynitride layer.

13. The solar cell according to claim 10, characterized in that: The first passivation layer comprises an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3nm to 6nm, and the thickness of the silicon nitride layer is 60nm to 100nm; and / or, The second passivation layer includes an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the thickness of the aluminum oxide layer is 3nm to 6nm, and the thickness of the silicon nitride layer is 60nm to 100nm.

14. The solar cell according to claim 1, characterized in that The first area in the first surface of the silicon substrate is a suede surface with a pyramid structure or a polished surface with a pyramid base, and the second area in the first surface of the silicon substrate is a suede surface with a pyramid structure.

15. The solar cell according to claim 14, characterized in that: The bottom width of the pyramid structure in the first region is 0.5 μm to 1.5 μm, and the height is 0.3 μm to 1 μm; or, the base width of the pyramid structure in the first region is 1 μm to 5 μm, and the base height is 0.1 μm to 0.4 μm; and / or, The bottom width of the pyramid structure in the second region is 1.5 μm to 2.2 μm, and the height is 1 μm to 1.3 μm.

16. The solar cell according to claim 1, characterized in that The third region and the fourth region in the second surface of the silicon substrate are both polished surfaces.

17. The solar cell according to claim 1, characterized in that The width of the first region is 20 μm to 200 μm or 80 μm to 100 μm; and / or, The width of the third region is 20 μm to 200 μm or 80 μm to 100 μm.

18. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the first surface comprising a first region and a second region distributed at intervals, and the second surface comprising a third region and a fourth region distributed at intervals; Preparing a first tunnel passivation structure in a first region of the first surface, and then forming a diffusion layer below the first surface of the silicon substrate; preparing a second tunnel passivation structure in a third region of the second surface; A first electrode is formed on a first region of the first surface, and a second electrode is formed on a third region of the second surface.

19. The preparation method according to claim 18, characterized in that: Preparing a first tunnel passivation structure in a first region of the first surface includes: Preparing a first tunneling layer, a first intrinsic layer and a first mask layer on the first surface; Using a laser process to pattern and open the first mask layer in the second area to expose the first intrinsic layer in the second area; Using a wet etching process to remove the first intrinsic layer and the first tunneling layer in the second region to expose the silicon substrate in the second region; removing the first mask layer in the first region to expose the first intrinsic layer in the first region; The first intrinsic layer is transformed into a first doped layer by a diffusion process.

20. The preparation method according to claim 19, characterized in that: The preparation method further comprises: The first intrinsic layer and the first tunneling layer in the second region are removed by a wet etching process, and a portion of the silicon substrate in the second region is etched.

21. The preparation method according to claim 19, characterized in that: The first intrinsic layer is an intrinsic polysilicon layer, the first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer, and the etching solution in the wet etching process is an alkaline solution; and / or, The first mask layer is any one or more combinations of a silicon oxide layer, a silicon oxynitride layer and a silicon nitride layer, and the first mask layer is removed by using an acid solution; and / or, The thickness of the first mask layer is 20 nm to 80 nm.

22. The preparation method according to claim 19, characterized in that: The preparation method further comprises: Before preparing the first tunneling layer, the first intrinsic layer and the first mask layer on the first surface, a velvet surface with a pyramid structure is prepared on the first surface of the silicon substrate by an alkali texturing process, wherein the bottom width of the pyramid structure is 0.5 μm to 1.5 μm and the height is 0.3 μm to 1 μm; or, a polished surface with a tower base is prepared on the first surface of the silicon substrate by an alkali texturing process and an alkali polishing process, wherein the tower base width is 1 μm to 5 μm and the tower base height is 0.1 μm to 0.4 μm; After removing the first intrinsic layer and the first tunneling layer of the second area by a wet etching process, the second area on the first surface of the silicon substrate is prepared with a velvet surface having a pyramid structure by an alkali velvet process. The bottom width of the pyramid structure is 1.5μm to 2.2μm, and the height is 1μm to 1.3μm.

23. The preparation method according to claim 19, characterized in that: The first intrinsic layer is transformed into a first doped layer by a one-step diffusion process, and a first diffusion layer and a second diffusion layer are formed in a first area and a second area of ​​the first surface of the silicon substrate, respectively.

24. The preparation method according to claim 23, characterized in that: The doping concentration of the first diffusion layer is lower than the doping concentration of the first doping layer, and the doping concentration of the second diffusion layer is higher than the doping concentration of the first diffusion layer.

25. The preparation method according to claim 19, characterized in that: The preparation method further comprises: Using an acid solution to remove the wrap-around layer produced on the second surface of the silicon substrate during the diffusion process; The second surface of the silicon substrate is etched using an alkaline solution.

26. The preparation method according to claim 18, characterized in that: Preparing a second tunnel passivation structure in the third region of the second surface includes: Preparing a second tunneling layer, a second doping layer and a second mask layer on the second surface; The second mask layer in the fourth region is patterned and opened by a laser process to expose the second doping layer in the fourth region; Using a wet etching process to remove the second doping layer and the second tunneling layer in the fourth region to expose the silicon substrate in the fourth region; The second mask layer in the third region is removed to expose the second doping layer in the third region.

27. The preparation method according to claim 26, characterized in that: The preparation method further comprises: The second doping layer and the second tunneling layer in the fourth region are removed by a wet etching process, and a portion of the silicon substrate in the fourth region is etched.

28. The preparation method according to claim 26, characterized in that: The second doped layer is a doped polysilicon layer, the second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer, and the etching solution in the wet etching process is an alkaline solution; and / or, The second mask layer is any one or more combinations of a silicon oxide layer, a silicon oxynitride layer and a silicon nitride layer, and the second mask layer is removed by using an acid solution; and / or, The thickness of the second mask layer is 15 nm to 25 nm.

29. The preparation method according to claim 26, characterized in that: The preparation method further comprises: After the second doping layer and the second tunneling layer in the fourth region are removed by a wet etching process, an alkali polishing process is performed on the silicon substrate in the fourth region.

30. The preparation method according to claim 18, characterized in that: The preparation method further comprises: A first passivation layer is formed on the first surface of the silicon substrate, and a first electrode is formed in a first region of the first surface, the first passivation layer penetrates the first passivation layer and is in electrical contact with the first tunnel passivation structure, wherein the first passivation layer comprises a combination of one or more layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer; and / or, A second passivation layer is prepared on the second surface of the silicon substrate, and a second electrode is prepared in a third area of ​​the second surface, penetrating the second passivation layer and electrically contacting the second tunneling passivation structure, wherein the second passivation layer includes a combination of one or more layers of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

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